SRAM-based in-memory computing method and apparatus in digital domain

Abstract

The application provides an SRAM-based digital domain in-memory computing method and device. First, input data and bit high-low order of the input data are acquired, and SRAM in-memory computing arrays corresponding to the input data respectively are determined according to the bit high-low order of the input data. Different preset approximate adder trees are included in different SRAM in-memory computing arrays, the different preset approximate adder trees include preset approximate full adders with different calculation accuracies, and the structure of the adder tree is a Wallace tree structure. Finally, the input data are subjected to approximate operation through the preset approximate adder tree, and a data approximate operation result is obtained. Through the above method, in combination with the application of the preset approximate full adder and the Wallace tree structure, the preset approximate adder tree with different accuracies can be selected to perform data calculation according to the bit high-low order of the input data while reducing the area and power consumption of the adder tree, and the calculation accuracy is improved.

Description

Technical Field

[0001] This application relates to the field of neural network technology, and in particular to a digital domain in-memory computing method and apparatus based on SRAM. Background Technology

[0002] With the continuous development of neural network technology, the scale of network parameters is gradually increasing. However, with the gradual slowdown of Moore's Law, the development speed of hardware lags far behind that of networks. Therefore, to address the ever-increasing bandwidth demands, in-memory computing technology has emerged. As an emerging computing architecture, in-memory computing integrates computation and storage, enabling computation to be completed within memory units. In parallel processing of large numbers of matrix-vector multiplication operations, in-memory computing has significant advantages due to its inherent high parallelism and high energy efficiency.

[0003] In-memory computing can be broadly divided into digital domain in-memory computing and analog domain in-memory computing. In the current digital domain in-memory computing architecture based on SRAM, an adder tree constructed from multiple precise adders is typically used to accumulate the multiplication results of the SRAM (Static Random-Access Memory) array to complete the data calculation. Although this method can achieve high-precision data operation, the structure of the precise adder tree is relatively complex, causing the entire adder tree structure to occupy a large area and consume a lot of power in the entire CIM (Computing-In-Memory) macro, which to some extent reduces the advantages brought by digital domain in-memory computing.

[0004] In existing technologies, OR gates are typically used directly in the adder tree to replace the precise full adder. While this method reduces the area and power consumption of the adder tree, its logic is too simple compared to the traditional precise full adder, and the direct replacement results in poor accuracy in data computation. Therefore, when using this method, the obtained data computation results often have significant computational errors.

[0005] Therefore, how to ensure the accuracy of in-memory computation in the data domain without occupying a large area and power consumption has become a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0006] To address the aforementioned issues and ensure the accuracy of in-memory computation in the data domain without consuming excessive area and power in the adder tree, this application provides a method and apparatus for in-memory computation in the digital domain based on SRAM.

[0007] The embodiments of this application disclose the following technical solutions:

[0008] In a first aspect, this application discloses a digital domain in-memory computation method based on SRAM, including:

[0009] Obtain the input data and sort the bits of the input data from high to low order;

[0010] Based on the high and low order of the bits in the input data, the SRAM in-memory computation array corresponding to each bit in the input data is determined; different SRAM in-memory computation arrays include different preset approximate adder trees, and the different preset approximate adder trees include preset approximate full adders with different computational accuracies; the structure of the preset approximate adder tree is a Wallace tree structure;

[0011] The input data is approximated using the different preset approximation adder trees to obtain the data approximation result.

[0012] Optionally, after obtaining the input data, the process further includes:

[0013] The input data is divided according to a preset data partitioning rule to obtain a first dataset and a second dataset.

[0014] Optionally, the preset approximate adder tree includes: OR gates and conventional full adders;

[0015] The OR gate is used to compress the first input dataset to obtain compressed data, and then sends the compressed data to the conventional full adder.

[0016] The preset approximate full adder is used to perform approximate operations on the second input dataset to obtain approximate operation data, and then sends the approximate operation data to the conventional full adder;

[0017] The conventional full adder is used to generate the approximate calculation result of the data based on the compressed data and the approximate calculation data.

[0018] Optionally, the preset approximate full adder includes at least: a first preset approximate full adder and a second preset approximate full adder; the gate-level circuit of the first preset approximate full adder includes: an XOR gate, an AND gate, and a first OR gate;

[0019] The first input terminal of the AND gate is the addend input terminal, the second input terminal is the augend input terminal, and the output terminal of the AND gate is connected to the first input terminal of the first OR gate;

[0020] The second input terminal of the first OR gate is the low-order carry input terminal, and the output terminal is the high-order carry output terminal of the gate circuit.

[0021] The first input terminal of the XOR gate is the addend input terminal, the second input terminal is the augend input terminal, and the output terminal is the sum output terminal of the gate circuit.

[0022] Optionally, the gate-level circuit of the second preset full adder includes: a second OR gate;

[0023] The first input terminal of the second OR gate is the addend input terminal, the second input terminal is the augend input terminal, and the output terminal of the second OR gate is the sum output terminal of the gate-level circuit of the second preset adder.

[0024] Optionally, the step of determining the SRAM in-memory computing array corresponding to each different bit position in the input data based on the high and low bit order of the input data specifically includes:

[0025] In the input data, data whose bit order is higher than a preset threshold are processed using an SRAM in-memory computing array including the first preset approximate full adder;

[0026] In the input data, data whose bit order is lower than the preset threshold are processed using an SRAM in-memory computation array including the second preset approximate full adder.

[0027] Secondly, this application discloses an SRAM-based digital domain in-memory computing device, comprising:

[0028] The acquisition module is used to acquire input data and sort the bits of the input data from high to low.

[0029] The adder tree determination module is used to determine the SRAM in-memory computation array corresponding to each bit of the input data according to the high-low order of the bits of the input data; different SRAM in-memory computation arrays include different preset approximate adder trees, and the different preset approximate adder trees include preset approximate full adders with different computational accuracies; the structure of the preset approximate adder tree is a Wallace tree structure;

[0030] The data approximation operation module is used to perform approximation operations on the input data through the different preset approximation adder trees to obtain the data approximation operation result.

[0031] Optionally, the digital domain in-memory computing device further includes:

[0032] The data partitioning module is used to partition the input data according to a preset data partitioning rule to obtain a first dataset and a second dataset.

[0033] Optionally, the preset approximate adder tree includes: OR gates and conventional full adders;

[0034] The OR gate is used to compress the first input dataset to obtain compressed data, and then sends the compressed data to the conventional full adder.

[0035] The preset approximate full adder is used to perform approximate operations on the second input dataset to obtain approximate operation data, and then sends the approximate operation data to the conventional full adder;

[0036] The conventional full adder is used to generate the approximate calculation result of the data based on the compressed data and the approximate calculation data.

[0037] Optionally, the preset approximate full adder includes at least: a first preset approximate full adder and a second preset approximate full adder; the gate-level circuit of the first preset approximate full adder includes: an XOR gate, an AND gate, and a first OR gate;

[0038] The first input terminal of the AND gate is the addend input terminal, the second input terminal is the augend input terminal, and the output terminal of the AND gate is connected to the first input terminal of the first OR gate;

[0039] The second input terminal of the first OR gate is the low-order carry input terminal, and the output terminal is the high-order carry output terminal of the gate circuit.

[0040] The first input terminal of the XOR gate is the addend input terminal, the second input terminal is the augend input terminal, and the output terminal is the sum output terminal of the gate circuit.

[0041] Compared to existing technologies, this application offers the following advantages: This application provides a digital domain in-memory computation method and apparatus based on SRAM. First, it acquires input data and its bit order (high to low). Then, based on the bit order, it determines the corresponding SRAM in-memory computation array. Different SRAM in-memory computation arrays include different preset approximate adder trees, each containing preset approximate full adders with different computational accuracies. The adder tree structure is a Wallace tree structure. Finally, the input data is approximated using the preset approximate adder trees to obtain the approximate computation result. By combining the application of preset approximate full adders and the Wallace tree structure, the area and power consumption of the adder tree are reduced. Furthermore, the method selects preset approximate adder trees with different accuracies based on the bit order of the input data for computation, thereby improving computational accuracy without significantly increasing the area and power consumption of the adder trees. Attached Figure Description

[0042] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0043] Figure 1 A flowchart illustrating an SRAM-based digital domain in-memory computation method provided in this application embodiment;

[0044] Figure 2 This is a schematic diagram of the structure of a preset approximate adder tree provided in an embodiment of this application;

[0045] Figure 3 A schematic diagram of the gate-level circuit of a conventional precise full adder provided in the embodiments of this application;

[0046] Figure 4 A schematic diagram of the gate-level circuit of the first preset approximate full adder provided in the embodiments of this application;

[0047] Figure 5 This is a schematic diagram of the gate-level circuit of the second preset approximate full adder provided in an embodiment of this application;

[0048] Figure 6 This is a schematic diagram of the structure of an SRAM-based digital domain in-memory computing device provided in an embodiment of this application. Detailed Implementation

[0049] As described above, in current SRAM-based digital domain in-memory computing architectures, an adder tree constructed from multiple precise adders is typically used to accumulate the multiplication results in the computer to complete the data calculation. Although this method can achieve high-precision data operations, the structure of the precise adder tree is relatively complex, causing the entire adder tree structure to occupy a large area and consume a lot of power in the entire CIM macro, which to some extent reduces the advantages brought by digital domain in-memory computing.

[0050] In existing technologies, precise full adders are typically replaced by directly connecting them to the adder tree using OR gates. While this method reduces the area and power consumption of the adder tree, its logic is too simple compared to traditional precise full adders, and the direct replacement results in poor accuracy in data computation. Therefore, when using this method, the obtained data computation results often have significant computational errors.

[0051] Through research, the inventors have developed a digital domain in-memory computation method and apparatus based on SRAM. First, they acquire the input data and its bit order (high to low). Based on this bit order, they determine the corresponding SRAM in-memory computation array. Different SRAM in-memory computation arrays include different preset approximate adder trees, each containing preset approximate full adders with different computational accuracies. The adder tree structure is a Wallace tree structure. Finally, the input data is approximated using the preset approximate adder trees to obtain the approximate computation result. By combining the application of preset approximate full adders and the Wallace tree structure, this method reduces the adder tree area and power consumption while selecting preset approximate adder trees with different accuracies based on the bit order of the input data. This improves computational accuracy without requiring excessive area or power consumption from the adder trees.

[0052] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present application.

[0053] Method Implementation Examples

[0054] Figure 2 This is a schematic diagram of the structure of the preset approximate adder tree provided in the embodiments of this application. The technical solution of this application can be further understood in conjunction with this diagram.

[0055] See Figure 1 The figure is a flowchart illustrating a digital domain memory computation method based on SRAM provided in this application, specifically including the following:

[0056] S101: Obtain the input data and sort the bits of the input data from high to low.

[0057] First, the input data and its bit order are obtained. When mapping multi-bit input data to an SRAM in-memory computing array, bit-parallel mapping is often used, meaning each bit of the input data is mapped to a different SRAM in-memory computing array. In practical applications, data with lower bit order (lower bit count) tends to have less impact on the result during subsequent calculations. Conversely, data with higher bit order (higher bit count) has a greater impact on the calculation result. By obtaining the bit order of the input data, the appropriate approximate adder tree can be selected based on the specific bit order when using a pre-defined approximate adder tree for subsequent calculations, thus achieving a balance between circuit overhead and computational accuracy.

[0058] S102: Based on the high and low order of the bits in the input data, determine the SRAM in-memory computation array corresponding to each bit in the input data; different SRAM in-memory computation arrays include different preset approximate adder trees, and the different preset approximate adder trees include preset approximate full adders with different computational accuracies; the structure of the preset approximate adder tree is a Wallace tree structure.

[0059] After obtaining the input data and sorting the bits of the input data from high to low, the SRAM in-memory computing array corresponding to each bit of the input data is determined according to the specific bit sorting of the input data, thereby selecting the corresponding preset approximate adder tree to perform data calculation.

[0060] Specifically, in this application, for data with different bit positions, preset approximate adder trees with different computational accuracies are often used to complete subsequent data calculations. By sorting the input data by bit position (high to low), the influence of different data on the calculation result can be determined from the data at different bit positions, thus selecting the corresponding SRAM in-memory computation array to complete the subsequent data calculations. For input data with higher bit position ranking, a preset approximate adder tree with higher computational accuracy can be selected; for input data with lower bit position ranking, a preset approximate adder tree with lower computational accuracy can be selected.

[0061] While different preset approximate adder trees contain preset approximate full adders with varying computational accuracies, each preset approximate adder tree is structured as a Wallace tree. The inclusion of the Wallace tree structure fully leverages the 3-2 compression characteristic of full adders, enabling timely parallel computation of input data and intermediate results.

[0062] S103: By using the different preset approximation adder trees, approximate operations are performed on the input data to obtain the data approximation operation result.

[0063] After determining the SRAM in-memory computation array corresponding to each bit in the input data, the input data is processed by the preset approximate adder tree in the different SRAM in-memory computation arrays to obtain the approximate computation result of the data.

[0064] Figure 2 This is a schematic diagram of the structure of the preset approximate adder tree provided in the embodiments of this application. The technical solution of this application can be further understood in conjunction with this diagram.

[0065] Among them, WT10-WT1 15 This represents the 16 sub-adder trees in the first level of the adder tree, L0_IN0-L0_IN 127 This represents 128 input data points. AFA represents the preset approximate full adder in this application, FA represents the traditional full adder, DOUT represents the output data, and L1_S0-L1_S2 represent the three data points after being compressed by an OR gate and processed by the approximate full adder.

[0066] Optionally, as an alternative implementation, after step S103, the following step is further included:

[0067] Step 1: Divide the input data according to the preset data partitioning rules to obtain the first dataset and the second dataset.

[0068] After receiving the input data, it can be partitioned into a first data set and a second data set according to a preset data partitioning rule. The first data set is mainly received by the OR gate in the preset approximate adder tree, while the second data set is mainly received by the preset approximate full adders in the adder tree. The preset data partitioning rule divides the input data into a subset received by the OR gate and a subset received by the approximate full adders. For example, after receiving the input data, if the preset approximate adder tree receives eight 1-bit input data, the preset data partitioning rule can divide these eight input data into a (2,3,3) form. The first two input data are used as the first dataset, which is compressed by the OR gate in the adder tree. The last six input data are used as the second dataset, which is connected to the two preset approximate full adders respectively. By effectively partitioning the input data, the adder tree can efficiently send the datasets to the OR gate and the approximate full adders in an orderly manner, thereby indirectly improving the efficiency of subsequent data computation.

[0069] As an optional implementation, the preset approximate adder tree in this embodiment includes at least: OR gates and conventional full adders;

[0070] In this preset approximate adder tree, the OR gate is used to compress the first input dataset to obtain compressed data, and the compressed data is sent to the conventional full adder;

[0071] In the preset approximate adder tree, an OR gate is used to compress the first dataset. By using the OR gate to compress a portion of the data, three half-adders are saved compared to existing technologies, and the output result is reduced from 4 bits to 3 bits. Taking an 8-bit input as an example, the OR gate compression results in a 7-bit output from the adder tree. Simultaneously, due to the sparsity of parameters in the neural network model, the higher-order bits of the adder tree structure are removed in this embodiment, reducing the maximum required 8-bit output to 5 bits. However, since the preset approximate adder tree in this application uses a preset approximate full adder instead of an exact full adder, the approximate full adder may lead to a larger error result, causing the accumulated result to overflow. Therefore, in this embodiment, a 6-bit output is ultimately retained.

[0072] The preset approximate full adder is used to perform approximate operations on the second input dataset to obtain approximate operation data, and then sends the approximate operation data to the conventional full adder;

[0073] In this application, preset approximate full adders with different computational accuracies are provided for input data with different bit order. This application primarily provides two preset approximate full adders to replace the traditional precise full adder by simplifying the addition logic. The first and second preset approximate full adders are described below:

[0074] First, we will introduce the first preset approximate full adder. Figure 3 This is a schematic diagram of the gate-level circuit of a precise full adder in the prior art. Figure 4 This is a schematic diagram of the gate-level circuit of the first preset approximate full adder. For a more detailed understanding, please refer to the comparison between the two.

[0075] The gate-level circuit of the first preset approximate full adder includes: an XOR gate, an AND gate, and a first OR gate;

[0076] Wherein, the first input terminal of the AND gate is the addend input terminal, the second input terminal is the augend input terminal, and the output terminal of the AND gate is connected to the first input terminal of the first OR gate; the second input terminal of the first OR gate is the low-order carry input terminal, and the output terminal is the high-order carry output terminal of the gate circuit.

[0077] In a traditional precise full adder, the output sum (S) and carry (Co) are calculated based on three input values ​​(A, B, Ci in the figure). The structure of a traditional precise full adder consists of three AND gates, one OR gate, and two XOR gates, making its overall structure quite complex. Although this type of precise full adder can ensure the accuracy of the calculation, it occupies a large area and consumes a lot of power in the entire adder tree structure, which to some extent reduces the advantages brought by in-memory computation in the digital domain.

[0078] The first preset approximate full adder proposed in this application internally includes only an XOR gate, an AND gate, and a first OR gate. In this first preset approximate full adder, by simplifying the generation logic of Co and S, the output sum (S) requires only one XOR gate, and the carry (Co) output requires only one AND gate and one OR gate. Compared to traditional precise full adders, the carry and output sum generation logic in this first preset approximate full adder is simpler and clearer, ensuring a certain level of accuracy without occupying excessive area or power consumption.

[0079] The second preset approximate full adder will be introduced below. Figure 5 The diagram shows the gate-level circuit of the second preset approximate full adder. The gate-level circuit of the second preset approximate full adder includes: a second OR gate; wherein, the first input terminal of the second OR gate is the addend input terminal, the second input terminal is the augend input terminal, and the output terminal of the second OR gate is the sum output terminal of the gate-level circuit of the second preset adder.

[0080] The second preset approximate full adder is obtained on the same principle as the first preset approximate full adder, both based on the reduction of addition logic to obtain a new approximate full adder. In obtaining the second preset approximate full adder, the logic is further reduced based on the first preset approximate full adder, thereby further simplifying the generation logic of Co and S. In the second preset approximate full adder, Ci is used as the carry (Co), and the output sum (S) is calculated through only one OR gate.

[0081] In practical applications, for input data with high bit order, the data has a relatively high impact on the calculation process. In this case, an SRAM in-memory computing array containing a first preset approximate full adder with high calculation accuracy is used to store and process the input data.

[0082] For input data with lower bit order, the impact of the data on the calculation process is relatively low. In this case, an SRAM in-memory calculation array containing a second preset approximate full adder with lower calculation accuracy will be used to store and process the input data.

[0083] By sorting the input data bits by high and low, an SRAM in-memory computing array containing preset approximate full adders with different computational accuracies is selected to store and compute the input data. Through the flexible application of the above two types of approximate full adders, a balance is achieved between reducing circuit overhead and computational accuracy in the digital domain memory. This ensures the accuracy of data computation while reducing the area and power consumption occupied by the adder tree.

[0084] The conventional full adder is used to generate the approximate calculation result of the data based on the compressed data and the approximate calculation data.

[0085] Optionally, as another alternative implementation, step S102 can be achieved through the following two steps, specifically including:

[0086] Step 1: In the input data, data whose bit order is higher than a preset threshold are processed using an SRAM in-memory computation array including the first preset approximate full adder;

[0087] Step 2: In the input data, data whose bit order is lower than the preset threshold are processed using an SRAM in-memory computation array including the second preset approximate full adder.

[0088] This application provides a digital domain in-memory computation method and apparatus based on SRAM. First, input data and its bit order are obtained. Then, based on the bit order, a corresponding SRAM in-memory computation array is determined. Different SRAM in-memory computation arrays include different preset approximate adder trees, each containing preset approximate full adders with different computational accuracies. The adder tree structure is a Wallace tree structure. Finally, the input data is approximated using the preset approximate adder trees to obtain the approximate computation result. By combining the application of preset approximate full adders and the Wallace tree structure, the area and power consumption of the adder trees are reduced. Furthermore, the method selects preset approximate adder trees with different accuracies based on the bit order of the input data for computation, thereby improving computational accuracy without significantly increasing the area and power consumption of the adder trees.

[0089] The following describes a digital domain in-memory computing method based on SRAM provided in the embodiments of this application. The digital domain in-memory computing device based on SRAM described below can be referred to in correspondence with the digital domain in-memory computing method based on SRAM described above.

[0090] Device Examples

[0091] Reference Figure 6The figure is a schematic diagram of the structure of a digital domain memory computing device based on SRAM provided in an embodiment of this application, which specifically includes the following modules:

[0092] The acquisition module 100 is used to acquire input data and sort the bits of the input data from high to low.

[0093] The adder tree determination module 200 is used to determine the SRAM in-memory computation array corresponding to each bit of the input data according to the high and low order of the bits of the input data; different SRAM in-memory computation arrays include different preset approximate adder trees, and the different preset approximate adder trees include preset approximate full adders with different computational accuracies; the structure of the preset approximate adder tree is a Wallace tree structure;

[0094] The data approximation operation module 300 is used to perform approximation operations on the input data through the different preset approximation adder trees to obtain the data approximation operation result.

[0095] Optionally, the digital domain in-memory computing device further includes:

[0096] The data partitioning module is used to partition the input data according to a preset data partitioning rule to obtain a first dataset and a second dataset.

[0097] Optionally, the preset approximate adder tree includes: OR gates and conventional full adders;

[0098] The OR gate is used to compress the first input dataset to obtain compressed data, and then sends the compressed data to the conventional full adder.

[0099] The preset approximate full adder is used to perform approximate operations on the second input dataset to obtain approximate operation data, and then sends the approximate operation data to the conventional full adder;

[0100] The conventional full adder is used to generate the approximate calculation result of the data based on the compressed data and the approximate calculation data.

[0101] Optionally, the preset approximate full adder includes at least: a first preset approximate full adder and a second preset approximate full adder; the gate-level circuit of the first preset approximate full adder includes: an XOR gate, an AND gate, and a first OR gate;

[0102] The first input terminal of the AND gate is the addend input terminal, the second input terminal is the augend input terminal, and the output terminal of the AND gate is connected to the first input terminal of the first OR gate;

[0103] The second input terminal of the first OR gate is the low-order carry input terminal, and the output terminal is the high-order carry output terminal of the gate circuit.

[0104] The first input terminal of the XOR gate is the addend input terminal, the second input terminal is the augend input terminal, and the output terminal is the sum output terminal of the gate circuit.

[0105] Optionally, the preset approximate full adder includes at least: a first preset approximate full adder and a second preset approximate full adder; the gate-level circuit of the first preset approximate full adder includes: an XOR gate, an AND gate, and a first OR gate;

[0106] The first input terminal of the AND gate is the addend input terminal, the second input terminal is the augend input terminal, and the output terminal of the AND gate is connected to the first input terminal of the first OR gate;

[0107] The second input terminal of the first OR gate is the low-order carry input terminal, and the output terminal is the high-order carry output terminal of the gate circuit.

[0108] The first input terminal of the XOR gate is the addend input terminal, the second input terminal is the augend input terminal, and the output terminal is the sum output terminal of the gate circuit.

[0109] Optionally, the gate-level circuit of the second preset full adder includes: a second OR gate;

[0110] The first input terminal of the second OR gate is the addend input terminal, the second input terminal is the augend input terminal, and the output terminal of the second OR gate is the sum output terminal of the gate-level circuit of the second preset adder.

[0111] Optionally, the adder tree determination module is specifically used for:

[0112] In the input data, data whose bit order is higher than a preset threshold are processed using an SRAM in-memory computing array including the first preset approximate full adder;

[0113] In the input data, data whose bit order is lower than the preset threshold are processed using an SRAM in-memory computation array including the second preset approximate full adder.

[0114] It should be noted that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, for the method and apparatus embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the description of the method embodiments. The method and apparatus embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components indicated as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of the solution in this embodiment according to actual needs. Those skilled in the art can understand and implement this without creative effort.

[0115] The above description is merely one specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A digital domain in-memory computation method based on SRAM, characterized in that, include: Obtain the input data and sort the bits of the input data from high to low order; Based on the high and low order of the bits in the input data, the SRAM in-memory computation array corresponding to each bit in the input data is determined; different SRAM in-memory computation arrays include different preset approximate adder trees, and the different preset approximate adder trees include preset approximate full adders with different computational accuracies; the structure of the preset approximate adder tree is a Wallace tree structure; By using the different preset approximation adder trees, approximate operations are performed on the input data to obtain the data approximation operation results; After obtaining the input data, the process also includes: The input data is divided according to a preset data partitioning rule to obtain a first dataset and a second dataset; The preset approximate adder tree includes: OR gates and conventional full adders; The OR gate is used to compress the first dataset to obtain compressed data, and then sends the compressed data to the conventional full adder; The preset approximate full adder is used to perform approximate operations on the second dataset to obtain approximate operation data, and then sends the approximate operation data to the conventional full adder; The conventional full adder is used to generate the approximate calculation result of the data based on the compressed data and the approximate calculation data.

2. The method according to claim 1, characterized in that, The preset approximate full adder includes at least: a first preset approximate full adder and a second preset approximate full adder; the gate-level circuit of the first preset approximate full adder includes: an XOR gate, an AND gate, and a first OR gate; The first input terminal of the AND gate is the addend input terminal, the second input terminal is the augend input terminal, and the output terminal of the AND gate is connected to the first input terminal of the first OR gate; The second input terminal of the first OR gate is the low-order carry input terminal, and the output terminal is the high-order carry output terminal of the gate circuit. The first input terminal of the XOR gate is the addend input terminal, the second input terminal is the augend input terminal, and the output terminal is the sum output terminal of the gate circuit.

3. The method according to claim 2, characterized in that, The gate-level circuit of the second preset approximate full adder includes: a second OR gate; The first input terminal of the second OR gate is the addend input terminal, the second input terminal is the augend input terminal, and the output terminal of the second OR gate is the sum output terminal of the gate-level circuit of the second preset approximate full adder.

4. The method according to claim 2, characterized in that, The step of sorting the input data by bit height and determining the SRAM in-memory computing array corresponding to different bit positions in the input data specifically includes: In the input data, data whose bit order is higher than a preset threshold are processed using an SRAM in-memory computing array including the first preset approximate full adder; In the input data, data whose bit order is lower than the preset threshold are processed using an SRAM in-memory computation array including the second preset approximate full adder.

5. A digital domain in-memory computing device based on SRAM, characterized in that, include: The acquisition module is used to acquire input data and sort the bits of the input data from high to low. The adder tree determination module is used to determine the SRAM in-memory computation array corresponding to each bit of the input data according to the high-low order of the bits of the input data; different SRAM in-memory computation arrays include different preset approximate adder trees, and the different preset approximate adder trees include preset approximate full adders with different computational accuracies; the structure of the preset approximate adder tree is a Wallace tree structure; The data approximation operation module is used to perform approximate operations on the input data through the different preset approximation adder trees to obtain the data approximation operation result; the device further includes: a data partitioning module, used to partition the input data according to preset data partitioning rules to obtain a first dataset and a second dataset; The preset approximate adder tree includes: OR gates and conventional full adders; The OR gate is used to compress the first dataset to obtain compressed data, and then sends the compressed data to the conventional full adder; The preset approximate full adder is used to perform approximate operations on the second dataset to obtain approximate operation data, and then sends the approximate operation data to the conventional full adder; The conventional full adder is used to generate the approximate calculation result of the data based on the compressed data and the approximate calculation data.

6. The apparatus according to claim 5, characterized in that, The preset approximate full adder includes at least: a first preset approximate full adder and a second preset approximate full adder; the gate-level circuit of the first preset approximate full adder includes: an XOR gate, an AND gate, and a first OR gate; The first input terminal of the AND gate is the addend input terminal, the second input terminal is the augend input terminal, and the output terminal of the AND gate is connected to the first input terminal of the first OR gate; The second input terminal of the first OR gate is the low-order carry input terminal, and the output terminal is the high-order carry output terminal of the gate circuit. The first input terminal of the XOR gate is the addend input terminal, the second input terminal is the augend input terminal, and the output terminal is the sum output terminal of the gate circuit.

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