Display device and driving method thereof

Abstract

Disclosed are a display apparatus and a driving method thereof. The display apparatus includes a display panel configured to display an image, a driver configured to drive the display panel, a controller configured to control the driver, and a duty cycle controller configured to define an unknown area and a known area within one frame when a driving frequency of the display panel is changed, and to change a duty cycle for driving the known area, wherein vertical resolution information is unknown in the unknown area and the vertical resolution information is known in the known area.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10-2021-0191865, filed on December 29, 2021, which is incorporated herein by reference as if fully set forth herein. Technical Field

[0003] This invention relates to a display device and its driving method. Background Technology

[0004] With the development of information technology, the market for display devices, which serve as a connection medium between users and information, is growing. Consequently, the use of display devices such as micro-LED displays, light-emitting displays, quantum dot displays, and liquid crystal displays is increasing.

[0005] The aforementioned display device includes: a display panel comprising a plurality of sub-pixels; a driver that outputs drive signals for driving the display panel; and a power supply that generates power for the display panel or the driver; etc.

[0006] In the aforementioned display device, when a driving signal (e.g., a scan signal and a data signal) is provided to the sub-pixels formed in the display panel, the selected sub-pixels transmit light or emit light directly to display an image. Summary of the Invention

[0007] One object of the present invention is to achieve uniform brightness of the display panel by re-driving the display panel with a recalculated duty cycle even if the driving frequency changes. Furthermore, another object of the present invention is to reduce brightness deviations between frames caused by driving frequency variations and flicker that can occur throughout the entire display surface by dividing the display panel into at least two display areas and using a frame memory to simultaneously scan the structure of the display areas.

[0008] To achieve these objectives and other advantages, according to the intent of the invention, as embodied and broadly described herein, a display device includes: a display panel configured to display an image; a driver configured to drive the display panel; a controller configured to control the driver; and a duty cycle controller configured to define an unknown region and a known region within a frame when the driving frequency of the display panel changes, and to change the duty cycle for driving the known region, wherein vertical resolution information is unknown in the unknown region and known in the known region.

[0009] After the vertical resolution information is known, the duty cycle of the known region can be changed according to the length of the remaining regions within the frame.

[0010] The duty cycle of the unknown region can be fixed to the set duty cycle of the duty cycle controller.

[0011] The duty cycle controller can define the unknown region and the known region by recalculating the duty cycle during the vertical blanking period that occurs after the drive frequency changes, and change the duty cycle of the known region according to the length of the remaining regions in the frame after the vertical resolution information is known.

[0012] The driver can divide the display panel into at least two display areas and scan the at least two display areas simultaneously.

[0013] The timing controller can store the data signal of the current frame in a memory and output the data signal of the previous frame stored in the memory to display the image.

[0014] The duty cycle controller may include: a resolution information detector for analyzing input data signals to detect resolution information for each frame; a signal generator for monitoring the drive frequency and generating a control signal based on whether the drive frequency changes; and a control signal output unit for recalculating the duty cycle based on the resolution information transmitted from the resolution information detector and the control signal transmitted from the signal generator to change the duty cycle of the known region, and controlling a first gate control signal and a second gate control signal based on the recalculated duty cycle.

[0015] The duty cycle of the display panel's light-emitting time and non-light-emitting time can be controlled by the first gate control signal and the second gate control signal.

[0016] In another aspect of the invention, a method for driving a display device includes: detecting resolution information for each frame by analyzing a data signal input for displaying an image on a display panel; monitoring a driving frequency for driving the display panel and generating a control signal based on whether the driving frequency changes; and, when the driving frequency of the display panel changes, defining an unknown region and a known region within a frame based on the resolution information and the control signal, and changing the duty cycle of the known region, wherein vertical resolution information is unknown in the unknown region and known in the known region.

[0017] Changing the duty cycle of the known region may include: defining the unknown region and the known region by recalculating the duty cycle during the vertical blanking period that occurs after the drive frequency change, and changing the duty cycle of the known region according to the length of the remaining regions in the frame after the vertical resolution information is known.

[0018] Once the vertical resolution information is known, the duty cycle of the known region can be changed based on the length of the remaining regions within the frame.

[0019] The duty cycle of the unknown region can be fixed to the set duty cycle of the duty cycle controller.

[0020] Changing the duty cycle of the known area may include: recalculating the duty cycle and generating a first gate control signal and a second gate control signal based on the recalculated duty cycle. The duty cycle of the display panel's light-emitting time and non-light-emitting time can be divided and controlled by the first gate control signal and the second gate control signal.

[0021] Even when the driving frequency changes, this invention can achieve uniform brightness of the display panel by recalculating the duty cycle to reflect frame information to a certain extent and re-driving the remaining driving areas based on the recalculated duty cycle. Furthermore, this invention can reduce brightness deviations between frames caused by driving frequency changes and flicker that can occur throughout the entire display surface by dividing the display panel into at least two display areas and using a frame memory to simultaneously scan the structure of the display areas. Attached Figure Description

[0022] Figure 1 This is a block diagram schematically showing a display device. Figure 2 It is shown schematically. Figure 1 The diagram shows the structure of the display panel.

[0023] Figure 3 and Figure 4 This is a diagram used to briefly describe the pixel configuration and duty cycle driving method. Figure 5 This is a diagram used to describe the advantages of driving based on the pixel's duty cycle.

[0024] Figure 6 and Figure 7 It is a diagram used to describe the scanning method of a display device and the structure of the device.

[0025] Figures 8 to 11 This diagram is used to describe considerations when driving a display device based on a structure employing a frame memory.

[0026] Figure 12This is a diagram used to illustrate the adaptive duty cycle changing method according to an embodiment of the present invention. Figure 13 and Figure 14 This is an example diagram of adaptive duty cycle variation according to an embodiment of the present invention. Figure 15 This is a diagram used to illustrate the advantages of embodiments of the present invention. Figure 16 This is an exemplary construction diagram of a timing controller for adaptive duty cycle changes according to an embodiment of the present invention. Detailed Implementation

[0027] The advantages, features, and implementation methods of the present invention will become clear from the following detailed description of the embodiments in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but can be implemented in many different forms. These exemplary embodiments are provided to make the disclosure of the present invention thorough and complete, and to fully convey the scope of the invention to those skilled in the art. Therefore, the scope of the present invention should be defined by the claims.

[0028] In the accompanying drawings, which illustrate exemplary embodiments of the present invention, shapes, dimensions, ratios, angles, and quantities are given by way of example and are therefore not limited to the disclosure of the present invention. Throughout the application, the same reference numerals refer to the same constituent elements. Furthermore, in the following description of the present invention, detailed descriptions of known functions and constructions involved herein will be omitted if such detailed descriptions would obscure the subject matter of the invention. The terms “comprising,” “including,” and / or “having” as used in this specification do not exclude the presence or addition of other elements unless used with the term “only.”

[0029] In the following description of the embodiments, the terms "first" and "second" are used to describe the components, but these components are not limited by these terms. These terms are used to distinguish one component from another. Therefore, the first component mentioned in the following description can be the second component within the technical spirit of the present invention.

[0030] The corresponding features of the various embodiments of the present invention can be partially or wholly combined and integrated with each other, and various technical links and drives are possible. These various embodiments can be implemented independently of each other or can be implemented in conjunction with each other.

[0031] The display device according to the present invention can be implemented as a television set, video player, personal computer (PC), home theater, vehicle electronic device, smartphone, etc., but is not limited thereto. The display device according to the present invention can achieve the desired effect when applied to a microLED display device capable of displaying images based on microlight-emitting diodes (LEDs). However, this is merely an example, and the constructions or methods described below can be used to solve problems caused by display devices other than microLED display devices.

[0032] Figure 1 This is a block diagram schematically showing a display device. Figure 2 It is shown schematically. Figure 1 The diagram shows the structure of the display panel.

[0033] like Figure 1 and 2 As shown, the display device may include an image provider 110, a timing controller 120, a gate driver 130, a data driver 140, a display panel 150, a power supply 180, etc.

[0034] The image provider (set or host system) 110 can output image data signals provided from an external source or image data signals stored in internal memory, as well as various drive signals. The image provider 110 can provide data signals and various drive signals to the timing controller 120.

[0035] The timing controller 120 can output a gate timing control signal GDC for controlling the operating timing of the gate driver 130, a data timing control signal DDC for controlling the operating timing of the data driver 140, and various synchronization signals (vertical synchronization signal Vsync and horizontal synchronization signal Hsync). The timing controller 120 can provide the data driver 140 with the data signal DATA and the data timing control signal DDC provided from the image provider 110. The timing controller 120 can be implemented as an integrated circuit (IC) and can be mounted on a printed circuit board, but is not limited thereto.

[0036] Gate driver 130 can output a gate signal (or scan signal) in response to a gate timing control signal GDC provided from timing controller 120. Gate driver 130 can provide the gate signal to pixels included in display panel 150 via gate lines GL1 to GLm. Gate driver 130 can be implemented as an IC and mounted on a printed circuit board, or it can be formed directly on display panel 150 according to the in-panel gate structure.

[0037] In response to the data timing control signal DDC provided from the timing controller 120, the data driver 140 samples and latches the data signal DATA, converts the digital data signal into an analog data voltage based on a gamma reference voltage, and outputs the analog data voltage. The data driver 140 can provide data voltages to the pixels included in the display panel 150 via data lines DL1 to DLn. The data driver 140 can be implemented as an IC and mounted on the display panel 150, or it can be mounted on a printed circuit board.

[0038] The power supply 180 can generate a first voltage with a high potential and a second voltage with a low potential based on an external input voltage provided from the outside, and can output the first voltage and the second voltage via a first power line EVDD and a second power line EVSS, respectively.

[0039] Display panel 150 can display images based on pixel PIXs, including micro light-emitting diodes (LEDs) that emit light in response to gate signals and data voltages. A pixel PIX may include multiple microLEDs. These multiple microLEDs may include a red microLED LR, a green microLED LG, and a blue microLED LB. Meanwhile, although... Figure 2 An example is shown that includes multiple red microLEDs LR, green microLEDs LG, and blue microLEDs LB arranged vertically in the same manner in a single pixel PIX, but the invention is not limited thereto.

[0040] Figure 3 and Figure 4 This is a diagram used to briefly describe the pixel configuration and duty cycle driving method. Figure 5 This is a diagram used to describe the advantages of driving based on the pixel's duty cycle.

[0041] like Figure 3 and Figure 4 As shown, a pixel (PIX) can emit light based on at least one microLED (mLED), a driving transistor (DT), a control transistor (ET), etc. However, since various circuit configurations and methods exist for driving the microLED (mLED), please note that only the microLED (mLED), driving transistor (DT), and control transistor (ET) relevant to this invention are illustrated and described.

[0042] The driving transistor DT can generate a driving current for driving the microLED mLED based on a scan signal applied via a scan signal line GAL included in the first gate line GL1. The control transistor ET can control the timing of the driving current being delivered to the microLED mLED based on a light emission control signal applied via a light emission control line EML included in the first gate line GL1. That is, the control transistor ET can be used to control the driving current applied to the microLED mLED and the light emission time.

[0043] Figure 4 The left side shows a current-driven method that only controls the drive current. Figure 4 The right side illustrates a duty cycle driving method that controls both the drive current and drive time. By controlling the on-time (On) and off-time (Off) of the control transistor ET, the drive current applied to the microLED (mLED) and the emission time can be controlled. Therefore, the duty cycle driving method can be considered suitable for driving microLEDs (mLEDs) that require high current operation. Meanwhile, Figure 4The two methods shown can display the same brightness. This is because, in the duty cycle driving method shown on the right, although the light emission time is reduced, the driving current can be increased, thus the display panel has the same display area as in the case of the current driving method shown on the left.

[0044] like Figure 5 As shown, the Type 1 current-driven method (with low current density) has low luminous efficiency, making it difficult to achieve the desired brightness using microLEDs. The Type 2 current-driven method (with high current density) improves luminous efficiency, thus enabling the achievement of the desired brightness using microLEDs, but power consumption may increase. The Type 3 duty cycle-driven method reduces the emission time rather than increasing the current density, thereby enabling the achievement of the desired brightness using microLEDs while reducing power consumption.

[0045] Therefore, the duty cycle driving method has become a highlight because it can achieve the desired brightness and reduce power consumption when applied to microLED display devices based on microLEDs.

[0046] Figure 6 and Figure 7 It is a diagram used to describe the scanning method of a display device and the structure of the device.

[0047] like Figure 6 and Figure 7 As shown, in the display device, the display panel 150 can be divided into at least two display areas 150A and 150B by drivers such as a gate driver and a data driver, and can be scanned simultaneously. When the upper display area 150A and the lower display area 150B are scanned simultaneously in this manner, the physical time required to define a horizontal time 1H can be reduced compared to the method of driving one display area at a time sequentially.

[0048] To implement the above scanning method, the timing controller 120 can be configured as a framememory application structure, wherein the data signal DATA of the current frame is stored in the memory 160, and the data signal DATA of the previous frame stored in the memory 160 is output to the data driver 140.

[0049] Figures 8 to 11 This is a diagram used to describe considerations when driving a display device based on a frame memory application structure.

[0050] like Figure 7 , Figure 8 and Figure 9As shown, when the display device is driven based on the same driving frequency (e.g., 144Hz), the externally applied input vertical synchronization signal In_Vsync and the input active signal In_Active can be output from the timing controller 120 after the same delay time. This can be known by referring to the output vertical synchronization signal Out_Vsync and the output active signal Out_Active output from the timing controller 120. Figure 8 In this context, Vblank represents the vertical blank period that exists between vertical synchronization signals to distinguish between frames.

[0051] Due to the aforementioned driving characteristics, an image with an equal delay for each frame can be displayed on the display panel. This can be determined by referring to the A data signal DA of the output active signal Out_Active, which is output after a delay of one frame.

[0052] In duty cycle-driven methods, the duty cycle can be calculated based on the vertical resolution of the image to be displayed. In frame buffer architectures, as long as the driving frequency remains uniform (e.g., at 144Hz), the vertical resolution remains constant. Therefore, the time point A for transmitting image resolution information and the time point a for requiring image resolution information can be the same. In this case, even if the synchronization signals are mismatched, the refresh rate will not change, and the duty cycle driving information is constant. Thus, small differences between time point A and time point a do not need to be considered.

[0053] Therefore, the display panel can maintain the same duty cycle (6:4) corresponding to the image while presenting the same brightness (e.g., 150 nits) during the period from the first frame to the Nth frame (1F to NF) driven at the same driving frequency at a fixed refresh rate. Thus, the frame memory application structure can be applied to a fixed refresh rate driving method that maintains the same driving frequency.

[0054] like Figure 7 , Figure 10 and Figure 11 As shown, when the display device is driven based on different driving frequencies (e.g., 144Hz → 40Hz), the externally applied input vertical synchronization signal In_Vsync can be output from the timing controller 120 after different delay times. This can be known by referring to the output vertical synchronization signal Out_Vsync and the output active signal Out_Active output from the timing controller 120.

[0055] Due to the aforementioned driving characteristics, images with equal delay for each frame can be displayed on the display panel, but a difference may occur between the input vertical sync signal In_Vsync and the output vertical sync signal Out_Vsync. This can be determined by the difference between the time it takes for the driving frequency of the input vertical sync signal In_Vsync to change from a high frequency (144Hz) to a low frequency (40Hz) and the time it takes for the driving frequency of the output vertical sync signal Out_Vsync to change from a high frequency (144Hz) to a low frequency (40Hz). The lower driving frequency is also referred to as the refresh drive.

[0056] The duty cycle in the duty cycle driving method can be calculated based on the vertical resolution of the image to be displayed. In the case of a frame memory application structure, when the driving frequency changes from a high frequency to a low frequency (e.g., 144Hz → 40Hz), the vertical resolution also changes, so the time point B for transmitting the image resolution information can be delayed from the time point b when the image resolution information is needed.

[0057] Therefore, the display panel may exhibit undesirable brightness (e.g., 40 nits) during a period of time (?:?) between the first frame 1F and the third frame 3F, driven at a variable refresh rate with a variable drive frequency, while having a duty cycle (?:?) that does not correspond to the image. Here, "?" indicates an unknown duty cycle. Therefore, the potential brightness deviation needs to be considered when using a frame memory application structure for a variable refresh rate driving method with a variable drive frequency.

[0058] Meanwhile, in the above description, the duty cycle of 6:4 is an example under the condition that the vertical resolution (V Total) = 2205 (144Hz) / 8122 (40Hz). In the case of a duty cycle of 6:4, 6 corresponds to the turn-on duty ratio when the light-emitting element is emitting light, and 4 corresponds to the turn-off duty ratio when the light-emitting element is not emitting light. The concepts of turn-on ratio and turn-off ratio will be understood in more detail in the following description.

[0059] Figure 12 This is a diagram used to illustrate the adaptive duty cycle changing method according to an embodiment of the present invention. Figure 13 and Figure 14 This is an example diagram of adaptive duty cycle variation according to an embodiment of the present invention. Figure 15 This is a diagram used to illustrate the advantages of embodiments of the present invention. Figure 16 This is an exemplary construction diagram of a timing controller for adaptive duty cycle changes according to an embodiment of the present invention.

[0060] The adaptive duty-varying method according to embodiments of the present invention is a driving method capable of solving the brightness deviation problem that can occur when performing variable refresh rate driving in a display device with a frame memory application structure. Furthermore, since it can solve the brightness deviation problem between frames, the adaptive duty-varying method according to embodiments of the present invention can reduce flicker that may be seen across the entire display surface.

[0061] like Figures 12 to 16 As shown, when the display device is driven based on different driving frequencies (e.g., 144Hz → 40Hz), the externally applied input vertical synchronization signal In_Vsync can be output from the timing controller 120 after different delay times. This can be known by referring to the output vertical synchronization signal Out_Vsync and the output active signal Out_Active output from the timing controller 120.

[0062] Due to the aforementioned driving characteristics, images with equal delay for each frame can be displayed on the display panel, but a difference may occur between the input vertical sync signal In_Vsync and the output vertical sync signal Out_Vsync. This can be determined by the difference between the time it takes for the driving frequency of the input vertical sync signal In_Vsync to change from a high frequency (144Hz) to a low frequency (40Hz) and the time it takes for the driving frequency of the output vertical sync signal Out_Vsync to change from a high frequency (144Hz) to a low frequency (40Hz).

[0063] The duty cycle in the duty cycle driving method can be calculated based on the vertical resolution of the image to be displayed. In the case of a frame memory application structure, when the driving frequency changes from a high frequency to a low frequency (e.g., 144Hz → 40Hz), the vertical resolution also changes, so the time point B for transmitting the image resolution information can be delayed from the time point b where the resolution information is needed.

[0064] Since it is difficult to know what duty cycle to use to drive the region where the time point B transmitting image resolution information is delayed from the time point b where image resolution information is needed, such as the second frame F2, this region can be defined as the vertical resolution unknown region VUKA. On the other hand, the duty cycle used to drive the region where the time point A transmitting image resolution information is the same as the time point a where image resolution information is needed, such as the first frame F1, will be known, and therefore this region can be defined as the vertical resolution information known region VKA.

[0065] In frame memory application architectures, when using a variable refresh rate driving method with a variable drive frequency, brightness deviations can occur through the region VUKA where vertical resolution information is unknown. Therefore, in embodiments of the present invention, the region VUKA where vertical resolution information is unknown and the region VKA where vertical resolution information is known are distinguished and driven based on whether the vertical resolution information is known. This will be described below.

[0066] (1) When a region VUKA with unknown vertical resolution information is generated due to changes in the driving frequency, the display device drives for a predetermined time using the duty cycle (default value) set in the region VUKA with unknown vertical resolution information. That is, the duty cycle of the region VUKA with unknown vertical resolution information can be fixed. The predetermined time for driving the display device using the duty cycle set in the region VUKA with unknown vertical resolution information can be the period up to the time before the region VKA with known vertical resolution information is acquired.

[0067] (2) At the point in time after the known vertical resolution information region VKA is obtained following the region with unknown vertical resolution information VUKA, the remaining driving regions are checked, and the display device is driven with a duty cycle that has been recalculated to be applicable to the remaining driving regions. That is, the duty cycle of the region with known vertical resolution information VKA can be variable, but this can be affected by the remaining driving regions.

[0068] By recalculating the duty cycle during the vertical blanking period Vblank that occurs after the drive frequency of the input vertical synchronization signal In_Vsync changes from a high frequency (144Hz) to a low frequency (40Hz), the known vertical resolution information region VKA can be determined. By recalculating the duty cycle, the remaining drive region after the unknown vertical resolution information region VUKA can be examined. Furthermore, since re-driving (normal driving) is performed with the recalculated duty cycle and the duty cycle can be known, the remaining drive region can be included within the known vertical resolution information region VKA.

[0069] Therefore, if the duty cycle is recalculated based on the embodiments of the present invention and re-driving is performed with this duty cycle, the second frame F2 can be divided into regions driven when the vertical resolution information is unknown and regions driven when the vertical resolution information is known.

[0070] As a result, a frame, such as the second frame F2, is divided into a region VUKA with unknown vertical resolution information driven by a first duty cycle (e.g., 10H) and a region VKA with known vertical resolution information driven by a second duty cycle (e.g., 8H). Here, the first duty cycle of 10H may include a 6H on-period and a 4H off-period, and the second duty cycle of 8H may include a 4.8H on-period and a 3.2H off-period.

[0071] As described above, if the duty cycle is recalculated based on the embodiments of the present invention and re-driving is performed using this duty cycle, the duty cycle can vary according to the length (number of lines) of the known region VKA with the remaining vertical resolution information within a frame, such as... Figure 13 The first example and Figure 14 The second example illustrates this. That is, once the vertical resolution information is known, the duty cycle of the known region can be changed based on the length of the remaining regions within a frame.

[0072] Figure 13 The first example corresponds to the case where the duty cycle (8H) of the region VKA with known vertical resolution information is less than the duty cycle (10H) of the region VUKA with unknown vertical resolution information. In other words, in the second frame, the number of rows occupied by the region VUKA with unknown vertical resolution information is greater than the number of rows occupied by the region VKA with known vertical resolution information.

[0073] In the case of the first example, the 2-1 frame F2-1, which is the region VUKA with unknown vertical resolution information, can be driven according to the first duty cycle (10H) set therein to maintain the duty cycle (6:4); and the 2-2 frame F2-2, which is the region VKA with known vertical resolution information, can be driven according to the recalculated second duty cycle (8H) to maintain the duty cycle (6:4).

[0074] Figure 14 The second example corresponds to the case where the duty cycle (14H) of the region VKA with known vertical resolution information is greater than the duty cycle (10H) of the region VUKA with unknown vertical resolution information. In other words, in the second frame, the number of rows occupied by the region VKA with known vertical resolution information is greater than the number of rows occupied by the region VUKA with unknown vertical resolution information.

[0075] In the second example, frame F2-1, which is the region VUKA with unknown vertical resolution information, can be driven according to the first duty cycle (10H) set therein to maintain the duty cycle (6:4); and frame F2-2, which is the region VKA with known vertical resolution information, can be driven according to the recalculated third duty cycle (14H) to maintain the duty cycle (6:4).

[0076] Furthermore, embodiments of the present invention can employ a duty cycle division driving method, wherein within a frame based on the duty cycle, the emission time and non-emission time of the light-emitting element are divided into multiple time periods. In this case, the emission time of the light-emitting element can correspond to the on-state percentage (or on-time) On, and the non-emission time of the light-emitting element can correspond to the off-state percentage (or off-time) Off. Therefore, Figure 3 The control transistor ET shown can be in the on state when the on ratio is On, and in the off state when the off ratio is Off.

[0077] Also, note that a 6:4 duty cycle was illustrated in the description above. Furthermore, although the description above illustrates driving with the duty cycle of the region VUKA where the vertical resolution information is unknown, driving can be performed with the duty cycle of the region VKA where the vertical resolution information is known before changing the driving frequency.

[0078] from Figure 15 It can be seen that, according to the embodiments of the present invention, the region VKA with known vertical resolution information can be driven according to the recalculated duty cycle, thereby achieving uniform brightness (e.g., 150 nits) even if the driving frequency changes to a high frequency (144Hz), a low frequency (40Hz), and then back to a high frequency (144Hz). Furthermore, since the second frame 2F is driven at a lower frequency than other frames 1F, 3F, etc., brightness non-uniformity may occur in some areas. However, according to the embodiments of the present invention, since the remaining driving regions are redriven according to the recalculated duty cycle, brightness approximately equal to or equal to that of other frames can be presented throughout the entire frame, thereby achieving uniform brightness.

[0079] In embodiments of the present invention, the timing controller 120 may be as follows: Figure 16 The system is configured to recalculate the duty cycle and then perform a re-drive using the recalculated duty cycle. According to an embodiment of the invention, the timing controller 120 may include a resolution information detector 125a, a signal generator 125b, a data signal processor 126, a control signal output unit (or circuit) 127, etc.

[0080] The resolution information detector 125a can be used to analyze the input data signal DATA to detect resolution information for each frame. The resolution information detector 125a can transmit the resolution information RI obtained by analyzing the input data signal DATA to the control signal output unit 127.

[0081] Signal generator 125b can be used to generate a control signal VC for controlling the display device based on the input data signal DATA. Signal generator 125b can monitor the drive frequency, generate the control signal VC for controlling the display device according to whether the drive frequency changes, and transmit the control signal VC to the control signal output unit 127.

[0082] The data signal processor 126 can be used to output an input data signal DATA after image processing, etc. The data signal processor 126 can perform image processing based on an algorithm configured therein to output a data signal suitable for a display panel.

[0083] The control signal output unit 127 can be used to generate a first gate control signal GCS and a second gate control signal ECS based on the resolution information RI transmitted from the resolution information detector 125a, the control signal VC transmitted from the signal generator 125b, and the data signal DATA transmitted from the data signal processor 126. The first gate control signal GCS can be a signal used to control the scan signal applied via the scan signal line, and the second gate control signal ECS can be a signal used to control the light emission control signal applied via the light emission control line.

[0084] The control signal output unit 127 can recalculate the duty cycle based on the resolution information RI, the control signal VC, and the data signal DATA to change the duty cycle of the known region, and control (change) the first gate control signal GCS and the second gate control signal ECS based on the recalculated duty cycle. The control signal output unit 127 can recalculate the duty cycle during the vertical blanking period generated after the drive frequency changes, or after the drive frequency changes from a high frequency to a low frequency, or from a low frequency to a high frequency.

[0085] When the duty cycle is divided or the duty cycle is changed, the control signal output unit 127 can select an appropriate period within a set period range. For this purpose, the control signal output unit 127 can refer to a lookup table (test value) for selecting a preferred duty cycle for each remaining drive region, which stores the set period range.

[0086] Meanwhile, the resolution information detector 125a, signal generator 125b, and control signal output unit 127, which are used to recalculate the duty cycle and generate control signals based on the recalculated duty cycle, can be collectively referred to as the duty cycle controller. The duty cycle controller can be built into the timing controller 120 or set separately from the timing controller 120.

[0087] As described above, the adaptive duty cycle changing method according to embodiments of the present invention can be applied to other display devices that have problems due to dividing the display panel into at least two display areas and using a frame memory to scan the display areas simultaneously.

[0088] As described above, according to the present invention, even when the driving frequency changes, uniform brightness of the display panel can be achieved by recalculating the duty cycle to reflect frame information to a certain extent, and then re-driving the remaining driving areas with the recalculated duty cycle. Furthermore, the present invention can minimize brightness deviations between frames caused by driving frequency variations and flicker that can occur throughout the entire display surface by dividing the display panel into at least two display areas and using a frame memory to simultaneously scan the structure of the display areas.

Claims

1. A display device, comprising: A display panel configured to display images; A driver configured to drive the display panel; A controller configured to control the driver; as well as A duty cycle controller is configured to define an unknown region and a known region within a frame when the driving frequency of the display panel changes, and to change the duty cycle used to drive the known region, wherein the vertical resolution information is unknown in the unknown region and the vertical resolution information is known in the known region.

2. The display device according to claim 1, wherein after the vertical resolution information is known, the duty cycle of the known region changes according to the length of the remaining regions within the frame.

3. The display device according to claim 1, wherein the duty cycle of the unknown region is fixed to the set duty cycle of the duty cycle controller.

4. The display device of claim 1, wherein the duty cycle controller defines the unknown region and the known region by recalculating the duty cycle during the vertical blanking period that occurs after the drive frequency change, and changes the duty cycle of the known region according to the length of the remaining regions in the frame after the vertical resolution information is known.

5. The display device according to claim 1, wherein the driver divides the display panel into at least two display areas and scans the at least two display areas simultaneously.

6. The display device according to claim 1, wherein the controller stores the data signal of the current frame in a memory and outputs the data signal of the previous frame stored in the memory to display the image.

7. The display device according to claim 1, wherein the duty cycle controller comprises: A resolution information detector, which analyzes the input data signal to detect resolution information for each frame; A signal generator, the signal generator being used to monitor the drive frequency and generate a control signal based on whether the drive frequency changes; as well as A control signal output circuit is provided for recalculating the duty cycle based on the resolution information transmitted from the resolution information detector and the control signal transmitted from the signal generator, so as to change the duty cycle of the known region, and controlling the first gate control signal and the second gate control signal based on the recalculated duty cycle.

8. The display device according to claim 7, wherein the duty cycle of the light-emitting time and the non-light-emitting time of the display panel is divided and controlled by the first gate control signal and the second gate control signal.

9. The display device according to claim 1, wherein the duty cycle controller maintains the same duty cycle in the unknown region and the known region.

10. The display device of claim 7, wherein the duty cycle controller further comprises a data signal processor for outputting a data signal suitable for the display panel.

11. The display device of claim 10, wherein the control signal output circuit is configured to generate the first gate control signal and the second gate control signal based on resolution information transmitted from the resolution information detector, a control signal transmitted from the signal generator, and a data signal transmitted from the data signal processor.

12. The display device according to claim 7, wherein the control signal output circuit includes a lookup table storing a set duty cycle range.

13. A method for driving a display device, comprising: Resolution information is detected for each frame by analyzing the data signal input used to display images on the display panel; Monitor the driving frequency used to drive the display panel and generate control signals based on whether the driving frequency changes; as well as When the driving frequency of the display panel changes, the duty cycle controller defines an unknown region and a known region within a frame based on the resolution information and the control signal, and changes the duty cycle of the known region. In the unknown region, the vertical resolution information is unknown, and in the known region, the vertical resolution information is known.

14. The method of claim 13, wherein varying the duty cycle of the known regions comprises: The unknown region and the known region are defined by recalculating the duty cycle during the vertical blanking period that occurs after the driving frequency change, and the duty cycle of the known region is changed according to the length of the remaining regions in the frame after the vertical resolution information is known.

15. The method of claim 13, wherein after the vertical resolution information is known, the duty cycle of the known region is changed according to the length of the remaining region within the frame.

16. The method of claim 13, wherein the duty cycle of the unknown region is fixed to the set duty cycle of the duty cycle controller.

17. The method of claim 14, wherein varying the duty cycle of the known regions comprises: The duty cycle is recalculated, and a first gate control signal and a second gate control signal are generated based on the recalculated duty cycle. The duty cycle of the display panel's light-emitting time and non-light-emitting time is divided and controlled by the first gate control signal and the second gate control signal.

18. The method of claim 13, wherein the duty cycle controller maintains the same duty cycle in the unknown region and the known region.

19. The method of claim 13, wherein detecting resolution information for each frame comprises: The display panel is divided into at least two display areas by a driver and the at least two display areas are scanned simultaneously.

Images