A test circuit and method for radiation-resistant FPGA embedded PCI Express IP core

Abstract

The invention provides a test circuit and method for an anti-radiation FPGA embedded PCI Express IP core. The circuit comprises: a test input port TDI, connected to the test input ports TI of N tested PCI Express IP cores; a test output pin TDO, connected to the test output port TO of one of the tested PCI Express IP cores; all the test output ports TO of the tested PCI Express IP cores are connected to a comparison module; the comparison module sets a Result signal to be 1 when N is 1; when N is greater than 1, the test output ports TO of the N tested PCI Express IP cores are compared bit by bit, if the test output ports TO of the N tested PCI Express IP cores are different, the output Result signal is 0, otherwise, the output Result signal is 1; a test machine ATE, inputs different test vectors into the test input pin TDI twice to perform testing, if the data output by the N test output pins TDO in the two tests are consistent with expectations, and the comparison module outputs the Result signal 1, it is considered that the test is passed.

Description

Technical Field

[0001] The invention relates to a test circuit and method for a radiation-resistant FPGA embedded PCI Express IP core, belonging to the field of integrated circuits. Background Art

[0002] The PCI Express IP core is a high-speed communication interface circuit that is widely integrated on integrated circuit devices to meet users' high bandwidth and high transmission rate requirements. Usually, one or more identical PCI Express IP cores are embedded in a programmable logic device (PLD) represented by a field programmable gate array (FPGA).

[0003] The PCI Express IP core embedded in FPGA is complex in function and huge in scale, and is an important part of FPGA. In order to ensure the normal function of the device as a whole and avoid the delivery of defective products to users, it is necessary to conduct fast and high-coverage mass production tests on the PCI Express IP core to ensure its correct function, while reducing test time and test costs.

[0004] Different from the general PCIExpress IP core, the PCIExpress IP core embedded in FPGA has programmable features, and the ports are divided into configuration ports and user ports. First, the PCIExpress IP core embedded in FPGA adds a large number of configuration ports. The user defines the PCIExpress IP core function, generates a bitstream file containing the PCIExpress IP core function information, configures the FPGA through the bitstream, stores the bitstream information in the configuration storage unit such as SRAM, and the PCIExpress IP core embedded in FPGA reads the configuration storage unit information such as SRAM through a special configuration interface, thereby realizing the programmable function. Secondly, the user port of the PCIExpress IP core embedded in FPGA is connected to the interconnection resources of FPGA. The user-controllable input and output ports of one or more PCIExpress IP cores embedded in FPGA are connected to the programmable FPGA interconnection resources. The user can connect the user port of the PCIExpress IP core to other FPGA resources or FPGA pins by configuring the interconnection resources.

[0005] Based on the above characteristics, traditional test circuits such as DFT and BIST circuits are difficult to meet the test requirements of PCI Express IP cores embedded in FPGAs. The scan chain test method using traditional testability design (i.e. DFT) is difficult to implement the test of the configuration port-related logic of the PCI Express IP core, resulting in reduced test coverage. At the same time, the test time increases when multiple PCI Express IP cores are embedded in the FPGA. The traditional built-in self-test (BIST) method has low test coverage, many test vectors, and complex design and development, resulting in long test time and high test costs.

[0006] The Chinese patent publication number CN 112597009 A, published on April 2, 2021, is titled "A mass production test method for FPGA embedded PCIExpress IP core based on coverage ranking". It discloses a method for sorting the test vector set of FPGA embedded PCIExpress IP core, which reduces the number of test vectors and maintains a certain test coverage, but does not define the test vector set generation process. Summary of the invention

[0007] The technical problem solved by the present invention is: to overcome the shortcomings of the prior art, to provide a test circuit and method for a radiation-resistant FPGA embedded with a PCIExpress IP core, to form a small number of high-coverage test vectors, and to achieve fast, high-coverage mass production testing of one or more identical PCIExpress IP cores embedded in the FPGA, thereby meeting the requirements for fast, accurate and comprehensive device testing.

[0008] The technical solution of the present invention is: a test circuit of a radiation-resistant FPGA embedded with a PCIExpress IP core, wherein the radiation-resistant FPGA embeds N PCIExpress IP cores to be tested, where N is greater than or equal to 1, and the test circuit comprises a test input pin TDI, a test output pin TDO, and a comparison module;

[0009] The test input port TDI is connected to the test input ports TI of N PCI Express IP cores under test through FPGA interconnection resources;

[0010] The test output pin TDO is connected to the test output ports TO of N PCIExpress IP cores under test through FPGA interconnection resources;

[0011] The comparison module sets the test output indication signal Result to be 1 when N is 1; when N is greater than 1, compares the test output ports TO of the N tested PCIExpress IP cores bit by bit. If the test output ports TO of any tested PCIExpress IP core are different, the output Result signal is 0; otherwise, the test output port TO of the tested PCIExpress IP core is 1.

[0012] The test machine ATE inputs different test vectors into the test input pin TDI twice for testing. If the data output by the test output port TO of the N tested PCIExpress IP cores meets expectations in the two tests, and the comparison module outputs the Result signal as 1, the test is considered to have passed; otherwise, the test is considered to have failed.

[0013] Preferably, the PCI Express IP core further comprises a CI port for connecting to a configuration SRAM, and the configuration SRAM is used to store an initial value of the CI port for configuring the PCI Express IP core.

[0014] Preferably, the test input port of the PCIExpress IP core under test includes a test reset signal RESET, a test clock TCLK[num_clk-1:0], a test mode signal SCANMODE, a test enable signal SCANEABLE, and a test chain input signal SCANIN[numsacnin-1:0];

[0015] num_clk is the number of clock bits; numsacnin is the number of scan chains.

[0016] Preferably, the test output port of the PCI Express IP core under test comprises a test chain output signal SCANOUT[numsacnin-1:0], where numsacnout is the number of output bits.

[0017] Preferably, the comparison module is designed and implemented using a BIST method.

[0018] Another technical solution of the present invention is: a method for testing a radiation-resistant FPGA embedded PCI Express IP core, the method comprising the following steps:

[0019] S1. Establish the test circuit as claimed in claim 1, and set the configuration storage unit SRAM corresponding to the PCIExpress IP core configuration interface in the test circuit to all 1s;

[0020] S2, based on the test circuit established in step S1, generate a test configuration code stream A for the entire FPGA;

[0021] S3, based on the PCIExpress IP core gate-level netlist Netlist under test and the PCIExpress IP core port settings corresponding to the test configuration code stream A, generate a test vector a;

[0022] S4, load the test configuration code stream A into the PCIExpress IP core, and input the test vector a to the test input pin TDI according to the preset timing, extract the first Result signal, and determine whether the data output by the test output port TO of the N tested PCIExpress IP cores meets expectations;

[0023] S5, based on the test circuit established in step S1, setting the configuration storage unit SRAM corresponding to the PCIExpress IP core configuration interface to all 0s;

[0024] S6. Based on the test circuit established in step S1, generate a test configuration code stream B for the entire FPGA;

[0025] S7, based on the PCI Express IP core gate-level netlist Netlist under test and the PCI Express IP core port settings corresponding to the test code stream B, generate a test vector b;

[0026] S8, load the test configuration code stream B into the PCIExpress IP core, and input the test vector b to the test input pin TDI according to the preset timing, extract the second Result signal, and determine whether the data output by the test output port TO of the N tested PCIExpress IP cores meets expectations;

[0027] S9. If the first Result signal and the second Result signal are both high levels, and the data output by the test output ports TO of the N tested PCIExpress IP cores are all in line with expectations, then the test of the radiation-resistant FPGA embedded PCIExpress IP core is considered to have passed; otherwise, the test of the radiation-resistant FPGA embedded PCIExpress IP core is considered to have failed.

[0028] Preferably, the test input port of the PCIExpress IP core under test includes a test reset signal RESET, a test clock TCLK[num_clk-1:0], a test mode signal SCANMODE, a test enable signal SCANEABLE, and a test chain input signal SCANIN[numsacnin-1:0];

[0029] num_clk is the number of clock bits; numsacnin is the number of scan chains.

[0030] Preferably, the test output port of the PCI Express IP core under test comprises a test chain output signal SCANOUT[numsacnin-1:0], where numsacnout is the number of output bits.

[0031] Preferably, the test vector a and the test vector b are generated using an ATPG method.

[0032] Preferably, the PCI Express IP core under test is a PCI Express IP core designed through DFT.

[0033] The advantages of the present invention compared with the prior art are:

[0034] (1) The present invention aims at the programmable characteristics of the PCI Express IP core embedded in the FPGA, sets two test environments for the configuration port of the PCI Express IP core: all 1 and all 0, and generates test vectors respectively through the ATPG method, thereby improving the test coverage and greatly reducing the number of test vectors;

[0035] (2) The present invention designs a test output port circuit by using the BIST method for the situation where multiple PCI Express IP cores are embedded in FPGA, thereby realizing simultaneous testing of multiple PCI Express IP cores, shortening the test time, and reducing the test cost;

[0036] (3) The PCIE core of the present invention adopts DFT scan test chain testing, and the peripheral circuit is BIST testing. A hybrid test method based on scan chain testing and BIST is adopted, which reduces the difficulty of test vector development and shortens the vector development time compared with the BIST method of traditional FPGA. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 It is a schematic diagram of a test circuit of a radiation-resistant FPGA embedded with a PCIExpress IP core according to an embodiment of the present invention;

[0038] Figure 2 It is a schematic diagram of the test method flow of an embodiment of the present invention;

[0039] Figure 3 This is a flow chart of a peripheral test circuit designed using a BIST method according to an embodiment of the present invention;

[0040] Figure 4 This is a comparison module circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0041] The present invention is described in detail below with reference to the accompanying drawings and embodiments.

[0042] like Figure 1 As shown, the present invention provides a test circuit of a radiation-resistant FPGA embedded with a PCIExpress IP core, wherein the radiation-resistant FPGA embeds N PCIExpress IP cores to be tested, where N is greater than or equal to 1, and the test circuit includes a test input pin TDI108, a test output pin TDO106, and a comparison module 105;

[0043] A test input port TDI108 is connected to the test input ports TI of N PCI Express IP cores under test through FPGA interconnection resources;

[0044] The test output pin TDO106 is connected to the test output port TO of one of the tested PCI Express IP cores through the FPGA interconnection resources, and the test output ports TO of all the tested PCI Express IP cores are connected to the comparison module (105);

[0045] The comparison module 105 sets the test output indication signal Result to 1 when N is 1; when N is greater than 1, compares the test output ports TO of the N tested PCI Express IP cores bit by bit. If the outputs of the test output ports TO of the N tested PCI Express IP cores are different, the test output indication signal Result is 0, otherwise, the test output indication signal Result is 1; the test machine ATE inputs different test vectors to the test input pin TDI108 twice for testing. If the data output by the test output pin TDO (106) meets the expectation in the two tests and the comparison module outputs the Result signal as 1, it is considered that the test has passed, otherwise, it is considered that the test has failed.

[0046] Preferably, the PCI Express IP core further comprises a CI port for connecting to the configuration SRAM 103, and the configuration SRAM 103 is used to store the initial value of the CI port for configuring the PCI Express IP core.

[0047] Preferably, the test input port of the PCIExpress IP core under test includes a test reset signal RESET, a test clock TCLK[num_clk-1:0], a test mode signal SCANMODE, a test enable signal SCANEABLE, and a test chain input signal SCANIN[numsacnin-1:0];

[0048] num_clk is the number of clock bits; numsacnin is the number of scan chains.

[0049] The test reset signal RESET is used to reset the test triggers of all tested PCIExpress IP cores;

[0050] Test clock TCLK, providing clock for the test trigger of the PCIExpress IP core under test;

[0051] Test mode signal SCANMODE, when this signal is valid, the PCIExpress IP core under test enters the test mode, the clock and reset are reset using the test clock, and the internal state machine of the PCIExpress IP core under test is switched to the test mode;

[0052] The test enable signal SCANEABLE, when valid, selects the test selection terminal S of all the PCIExpress IP core test triggers under test, and the test triggers form multiple test chains;

[0053] The test chain input signal SCANIN[numsacnin-1:0] is the input of the scan test chain and enters the first trigger of the test chain. numsacnin is the number of scan chains.

[0054] Preferably, the test output port of the PCIExpress IP core under test includes a test chain output signal SCANOUT[numsacnin-1:0], where numsacnout is the number of output bits;

[0055] Test chain output signal SCANOUT[numsacnin-1:0]: It is the output signal of the PCIExpress IP core scan test chain under test, connected to the output of the last trigger of the PCIExpress IP core scan test chain under test, including the test chain output signal SCANOUT[numsacnin-1:0], numsacnout is the number of output bits;

[0056] Preferably, the comparison module 105 is designed and implemented using a BIST method. BIST (Built-in Self Test) is a testability design implementation technology.

[0057] like Figure 2 and Figure 3 As shown, based on the above test circuit, the present invention also provides a test method for a radiation-resistant FPGA embedded PCI Express IP core, the method comprising the following steps:

[0058] S1. Establish the test circuit as claimed in claim 1, and set the configuration storage unit SRAM corresponding to the PCIExpress IP core configuration interface in the test circuit to all 1s;

[0059] S2, based on the test circuit established in step S1, generate a test configuration code stream A for the entire FPGA;

[0060] S3, based on the PCIExpress IP core gate-level netlist Netlist under test and the PCIExpress IP core port settings corresponding to the test configuration code stream A, the test vector a is generated using the ATPG method;

[0061] S4, load the test configuration code stream A into the PCI Express IP core, input the test vector a to the test input pin TDI108 according to the preset timing, extract the first Result signal, and determine whether the data output by the test output pin TDO (106) meets expectations;

[0062] S5, based on the test circuit established in step S1, setting the configuration storage unit SRAM corresponding to the PCIExpress IP core configuration interface to all 0s;

[0063] S6. Based on the test circuit established in step S1, generate a test configuration code stream B for the entire FPGA;

[0064] S7, based on the PCI Express IP core gate-level netlist Netlist under test and the PCI Express IP core port settings corresponding to the test code stream B, the test vector b is generated by using the ATPG method;

[0065] S8. Load the test configuration code stream B into the PCIExpress IP core, and input the test vector b to the test input pin TDI108 according to the preset timing, extract the second Result signal, and determine whether the data output by the test output pin TDO (106) meets the expectations; the running time of this step depends on the circuit scale. The larger the circuit scale, the greater the vector depth and the longer the time.

[0066] S9. If the first Result signal and the second Result signal are both at high levels, and the data output by the test output pin TDO (106) are consistent with expectations, it is considered that the radiation-resistant FPGA embedded PCI Express IP core test has passed; otherwise, it is considered that the radiation-resistant FPGA embedded PCI Express IP core test has failed.

[0067] The test vector a and the test vector b may be generated by using an ATPG method.

[0068] Example:

[0069] The test process of a radiation-resistant FPGA embedded with a PCI Express IP core is used to illustrate a mass production test method of an FPGA embedded with a PCI Express IP core of the present invention. The specific test steps are as follows:

[0070] S1. Obtain basic information of a PCIExpress IP core embedded in a certain FPGA: including the number of PCIExpress embedded in the FPGA N=3; the configuration port CI[3199:0] of a single PCIExpress IP core; the test input port TI[36:0]={RESET, TCLK[8:0], SCANMODE, SCANEABLE, SCANIN[24:0]} of a single PCIExpress IP core, where the specific signals include the test reset signal RESET, the test clock TCLK[8:0], the test mode signal SCANMODE, the test enable signal SCANEABLE, the test chain input signal SCANIN[24:0], the test output port TO[24:0]=SCANOUT[24:0] of a single PCIExpress IP core, and the gate-level netlist Netlist of a single PCIExpress IP core designed by DFT;

[0071] S2, based on the basic information obtained in step S1, a PCIExpress IP core test circuit is designed using a BIST method;

[0072] The specific steps are as follows:

[0073] S2-1: Complete the design of the device test input port. The specific steps are as follows:

[0074] S2-1-1, according to the test input port TI[36:0] of a single PCIExpress IP core, set the test input port TDI[36:0] of the FPGA as a whole device = {RESET, TCLK[8:0], SCANMODE, SCANEABLE, SCANIN[24:0]}, the width and specific signal allocation of TDI are consistent with TI, and TDI is constrained to the 37 available pins of the FPGA. Enter step S2-1-2;

[0075] S2-1-2, if the number of PCIExpress IPs embedded in the FPGA is N=1, go to step S2-1-3; if N≥2, jump to step S2-1-4. Here N=3, jump to step S2-1-4;

[0076] S2-1-3. DTI is directly connected to TI bit by bit through FPGA interconnection resources according to specific signal allocation, thus completing step S2-1.

[0077] S2-1-4, DTI uses FPGA interconnection resources to allocate bits according to specific signal allocation and connect to the test input port TI1[36:0] of the FPGA embedded PCIExpress IP core P1, the test input port TI2[36:0] of the FPGA embedded PCIExpress IP core P2, and the TI3[36:0] port of the FPGA embedded PCIExpress IP core P3, respectively, so that TDI can drive the TI1, TI2, and TI3 ​​ports at the same time, thus completing step S2-1.

[0078] S2-2: Complete the design of the device test output port. The specific steps are as follows:

[0079] S2-2-1, according to the test output port TO[24:0] of a single PCIExpress IP core, set the test output port DTO[24:0] of the FPGA device as a whole, make the width and specific signal allocation of TDO consistent with TO, and make TDO constrained to the 25 available pins of the FPGA. Enter step S2-2-2;

[0080] S2-2-2, if the number of PCIExpress IPs embedded in the FPGA is N=1, go to step S2-2-3; if N≥2, jump to step S2-2-5. Here N=3, jump to step S2-2-5;

[0081] S2-2-3, TDO is directly connected to TO bit by bit according to specific signal allocation through FPGA interconnection resources, and then proceeds to step S2-2-4.

[0082] S2-2-4, set the test output indication signal Result to be always 1, and constrain Result to the available pins of FPGA, thus completing step S2-2. This step is not performed in the embodiment;

[0083] S2-2-5, TDO is directly connected to the test input port TO of any FPGA embedded PCIExpress IP core according to the specific signal allocation bit by bit through the FPGA interconnection resources. In this step, TDO is connected to the test output terminal TO1[24:0] of the FPGA embedded PCIExpress IP core P1, and then enters step S2-2-6;

[0084] S2-2-6, compare the test output port TO1 of the FPGA embedded PCIExpress IP core P1, the test output port TO2 of the FPGA embedded PCIExpress IP core P2, ..., and TO3 of the FPGA embedded PCIExpress IP core PN bit by bit. If TO1, TO2, and TO3 are the same, set the test output indication signal Result to 1, and if they are not the same, set the output to 0. And constrain Result to the available pins of the FPGA, and step S2-2 is completed.

[0085] like Figure 3 As shown, it is a schematic diagram of the peripheral test circuit of this embodiment, where 101 is the FPGA to be tested. 102 is a PCIExpress IP core, which includes TI, TO and CI ports. There are 3 PCIExpress IP cores in this embodiment. 103 is a configuration SRAM. In normal working mode, the PCIExpress IP core function is configured through the CI port to realize programmable characteristics. In test mode, the configuration SRAM 103 is used to store the initial value of the CI port of the configuration PCIExpress IP core. 104 is an internal interconnection resource of the FPGA, and the PCIExpress IP core interface can be connected to the FPGA pin or other resources inside the FPGA through the interconnection resource. 105 realizes the comparison of TO1, TO2, and TO3, and outputs the Result signal. 107 is the Result signal. 106 is TDO, which is constrained to the FPGA pin and connected to TO1 through the interconnection resource. 108 is TDI, which is constrained to the FPGA pin and drives TI1, TI2, and TI3 ​​through the interconnection resource.

[0086] S3, generate test configuration code stream: based on the test circuit designed in step S2, design the 3200 configuration storage units SRAM corresponding to the PCIExpress IP core configuration interface to be all 1, and generate test configuration code stream A based on the above settings; based on the peripheral test circuit formed in step S2, design the 3200 configuration storage units SRAM corresponding to the PCIExpress IP core configuration interface to be all 0, and generate test configuration code stream B based on the above settings;

[0087] S4. Generate test vector set using ATPG method: Based on the gate-level netlist of the PCIExpress IP core under test and the PCIExpress IP core port settings corresponding to the test configuration code stream A, the ATPG method is used to generate test vector a; based on the gate-level netlist and the PCIExpress IP core port settings corresponding to the configuration test code stream B, the ATPG method is used to generate test vector b. The test coverage of test vectors a and b reaches 99.24%, achieving a high test coverage.

[0088] S5. Use the test machine to complete the test: configure test stream A and test vector a; configure test stream B and test vector b. If both test vectors a and b pass, and the Result signal is always high, the test passes, that is, the mass production test of the PCIExpressIP core is completed; otherwise, the test fails. In the example, both test vectors a and b pass, and the Result signal is always high, indicating that the test passes. The test takes 1200ms in total, which shortens the test time and reduces the test cost.

[0089] Figure 4 For a form of comparison and implementation of the module, K1 is an XOR gate, K2 is a NOR gate, and K3 is a NAND gate. Port A inputs the SCANOUT of one PCIe module, and port B inputs the SCANOUT of another PCIe module. If they are the same, Result = 1.

[0090] Although the present invention has been disclosed as above in the form of a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art may make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims

1. A test circuit for a radiation-resistant FPGA embedded with a PCI Express IP core, wherein the radiation-resistant FPGA embeds N PCI Express IP cores to be tested, where N is greater than or equal to 1, and wherein It includes a test input pin TDI (108), a test output pin TDO (106), and a comparison module (105); A test input port TDI (108) is connected to the test input ports TI of N PCI Express IP cores under test through FPGA interconnection resources; A test output pin TDO (106) is connected to a test output port TO of one of the PCI Express IP cores under test through FPGA interconnection resources, and all the test output ports TO of the PCI Express IP cores under test are connected to the comparison module (105); A comparison module (105), when N is 1, sets the test output indication signal Result to be always 1; when N is greater than 1, compares the test output ports TO of the N tested PCI Express IP cores bit by bit, if the outputs of the test output ports TO of the N tested PCI Express IP cores are different, the test output indication signal Result is 0, otherwise, the test output indication signal Result is 1; The test machine ATE inputs different test vectors into the test input pin TDI (108) twice for testing. If the data output by the test output pin TDO (106) meets expectations in the two tests and the comparison module outputs a Result signal of 1, the test is considered to have passed. Otherwise, the test is considered to have failed.

2. The test circuit of a radiation-resistant FPGA embedded with a PCI Express IP core according to claim 1, characterized in that The PCI Express IP core also includes a CI port for connecting to a configuration SRAM (103), and the configuration SRAM (103) is used to store an initial value of the CI port for configuring the PCI Express IP core.

3. The test circuit of a radiation-resistant FPGA embedded with a PCI Express IP core according to claim 1, characterized in that The test input port of the PCI Express IP core under test includes a test reset signal RESET, a test clock TCLK [num_clk-1:0], a test mode signal SCANMODE, a test enable signal SCANEABLE, and a test chain input signal SCANIN [numsacnin-1:0]; num_clk is the number of clock bits; numsacnin is the number of scan chains.

4. The test circuit of a radiation-resistant FPGA embedded with a PCI Express IP core according to claim 1, characterized in that The test output port of the PCI Express IP core under test includes a test chain output signal SCANOUT[numsacnin-1:0], where numsacnout is the number of output bits.

5. The test circuit of a radiation-resistant FPGA embedded with a PCI Express IP core according to claim 1, characterized in that The comparison module (105) is designed and implemented using the BIST method.

6. A method for testing a radiation-resistant FPGA embedded with a PCI Express IP core according to claim 1, characterized in that The steps include: S1. Establish the test circuit as claimed in claim 1, and set the configuration storage unit SRAM corresponding to the PCI Express IP core configuration interface in the test circuit to all 1s; S2, based on the test circuit established in step S1, generate a test configuration code stream A for the entire FPGA; S3, based on the PCI Express IP core gate-level netlist Netlist under test and the PCI Express IP core port settings corresponding to the test configuration code stream A, generate test vector a; S4, loading the test configuration code stream A into the PCI Express IP core, and inputting the test vector a into the test input pin TDI (108) according to the preset timing, extracting the first Result signal, and determining whether the data output by the test output pin TDO (106) meets expectations; S5, based on the test circuit established in step S1, setting the configuration storage unit SRAM corresponding to the PCI Express IP core configuration interface to all 0s; S6. Based on the test circuit established in step S1, generate a test configuration code stream B for the entire FPGA; S7, based on the PCI Express IP core gate-level netlist Netlist under test and the PCI Express IP core port settings corresponding to the test code stream B, generate a test vector b; S8, loading the test configuration code stream B into the PCI Express IP core, and inputting the test vector b into the test input pin TDI (108) according to the preset timing, extracting the second Result signal, and determining whether the data output by the test output pin TDO (106) meets expectations; S9. If the first Result signal and the second Result signal are both at high levels, and the data output by the test output pin TDO (106) are consistent with expectations, it is considered that the radiation-resistant FPGA embedded PCI Express IP core test has passed; otherwise, it is considered that the radiation-resistant FPGA embedded PCI Express IP core test has failed.

7. A method for testing a radiation-resistant FPGA embedded PCI Express IP core based on claim 6, characterized in that The test input port of the PCI Express IP core under test includes a test reset signal RESET, a test clock TCLK [num_clk-1:0], a test mode signal SCANMODE, a test enable signal SCANEABLE, and a test chain input signal SCANIN [numsacnin-1:0]; num_clk is the number of clock bits; numsacnin is the number of scan chains.

8. A method for testing a radiation-resistant FPGA embedded PCI Express IP core based on claim 6, characterized in that The test output port of the PCI Express IP core under test includes a test chain output signal SCANOUT[numsacnin-1:0], where numsacnout is the number of output bits.

9. A method for testing a radiation-resistant FPGA embedded PCI Express IP core based on claim 6, characterized in that The test vector a and the test vector b are generated by using the ATPG method.

10. A method for testing a radiation-resistant FPGA embedded PCI Express IP core based on claim 6, characterized in that The PCI Express IP core under test is a PCI Express IP core designed through DFT.

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