Device with digital / analog conversion circuit

Abstract

A device (1) having a DA conversion circuit is provided with at least: a processor (10P) that outputs a DA conversion target value; a pre-stage circuit (10FNT) that receives the DA conversion target value from the processor (10P), corrects the DA conversion target value in accordance with the correction data, and outputs the corrected DA conversion target value; a main body circuit (10BDY) that includes one or more DA converter elements to be corrected and that performs DA conversion on the corrected DA conversion value; and an AD converter (10AD). Here, the DA converter element to be corrected is a hybrid DA converter element that outputs, from an output terminal, an analog value obtained by adding an analog value output by a first-type circuit section (SEG1) responsible for an upper level and an analog value output by a second-type circuit section (SEG2) responsible for a lower level. Furthermore, as a calibration test for creating or updating calibration data, the processor (10P): A) acquires a plurality of test pairs, each of which is a pair of a test input value and a test result value having the following characteristics: (A1) the test input value is a value input to the main circuit in a corrected or uncorrected manner as a value to be subjected to DA conversion, and (A2) the test result value is a value input to the main circuit in a corrected or uncorrected manner as a value to be subjected to DA conversion; (A2) The test result value is a value obtained by AD-converting an analog value output by inputting the test input value to the main body circuit by means of an AD converter, and (B) the correction data is updated on the basis of the plurality of test pairs in (A). Here, the number of test pairs acquired during the calibration test is less than N power of 2, N being the number of bits indicating the resolution of the DA converter element to be calibrated.

Description

Technical Field

[0001] The present invention relates to a device having a digital / analog conversion circuit (hereinafter also referred to as a DA conversion circuit or a DA converter element), and for example, to a device having a DA conversion circuit capable of achieving high precision. Background Art

[0002] For example, Patent Document 1 describes a technology for providing a high-precision DA conversion circuit. Patent Document 1 describes a technology for achieving high-precision DA conversion circuits using R-2R resistor DAC (digital-to-analog converter) elements, interpolation DAC elements, and sigma-delta modulator elements. Furthermore, this document describes performing a calibration process (equivalent to a calibration test in the embodiments described below) to achieve high precision.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Laid-Open No. 2022-3830 Summary of the Invention

[0006] Problems to be solved by the invention

[0007] As a result of the present inventors' research, they found that the technology disclosed in Patent Document 1 has at least one of the following improvements.

[0008] The temperature (ambient temperature) of a device including a DA converter element (hereinafter referred to as a DA converter) dynamically changes, potentially causing changes in the DA converter's conversion characteristics. Consequently, repeated calibration tests are necessary. However, the technique disclosed in Patent Document 1 leaves room for improvement in the calibration test time.

[0009] The target device to which the analog value output from the DA converter is provided may require high voltage or high current. In such devices, it is difficult to directly provide the DA converter output to the target device. Typically, an amplifier circuit is connected between the DA converter and the target device. The input-output characteristics of the amplifier circuit, such as the amplification factor, vary with temperature (ambient temperature), and consequently, with the passage of time. As a result, the analog value provided to the target device also fluctuates over time. The technology described in Patent Document 1 has room for improvement in this regard.

[0010] An object of the present invention is to provide a device that solves one or more of the above-mentioned problems.

[0011] Other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0012] Means for solving problems

[0013] Hereinafter, an outline of a representative embodiment among the embodiments disclosed in this application will be briefly described.

[0014] Specifically, the apparatus of the embodiment includes at least: a processor that outputs a DA conversion target value; a preceding circuit that receives the DA conversion target value from the processor, corrects it according to calibration data, and outputs it; a main circuit that includes one or more calibration target DA converter elements that performs DA conversion on the corrected DA conversion target value; and an AD converter. The calibration target DA converter element is a hybrid DA converter element that outputs, from an output terminal, an analog value obtained by adding an analog value output by a first type circuit segment responsible for upper-level operations and an analog value output by a second type circuit segment responsible for lower-level operations. Furthermore, as a calibration test for generating or updating calibration data, the processor: (A) obtains a plurality of test pairs, each consisting of test input values ​​and test result values ​​having the following characteristics: (A1) the test input values ​​are values ​​input to the main circuit as DA conversion target values, with or without correction; and (A2) the test result values ​​are values ​​obtained by using the AD converter to convert analog values ​​output by the main circuit as a result of the test input values ​​being input to the main circuit; and (B) updates the calibration data based on the plurality of test pairs obtained in (A). Here, the number of test pairs acquired during the calibration test is less than 2 raised to the power of N, where N is the number of bits representing the resolution of the DA converter element to be calibrated.

[0015] In addition, a device in another embodiment includes at least: a main circuit including one or more DA converter elements that convert a main input bit string, which is a received bit string, into a main output analog value, which is an analog value, and outputs the converted value; a processor that outputs the processor output bit string; a front-stage circuit that receives the processor output bit string and outputs the main input bit string; and an AD converter. Here, the front-stage circuit corrects the processor output bit string based on calibration data and outputs the main input bit string, and the main circuit includes an amplifier circuit that amplifies the analog value output by the DA converter element and outputs it as the main output analog value. Here, the processor: (A) obtains multiple pairs of test bit strings and test result bit strings having the following characteristics: (A1) the test bit string is a processor output bit string or a main input bit string used for calibration testing, and (A2) the test result bit string is obtained by converting the main output analog value using the AD converter; and (B) updates the calibration data based on the multiple pairs in (A).

[0016] Effects of the Invention

[0017] In the invention disclosed in this application, the effects obtained by representative embodiments will be briefly described, and a device including a high-precision DA conversion circuit can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 This is a block diagram showing the configuration of a device including the DA converter according to the first embodiment.

[0019] Figure 2 This is a block diagram showing the configuration of a DA converter according to the first embodiment.

[0020] Figure 3 This is a circuit diagram showing the configuration of a DA converter according to the first embodiment.

[0021] Figure 4 This is a flowchart when the DA converter according to the first embodiment is operated.

[0022] Figure 5 This is a flowchart for explaining the calibration test of the first embodiment.

[0023] Figure 6 This is a diagram for explaining the calibration test in the first embodiment.

[0024] Figure 7 This is a diagram for explaining the correction amount in the first embodiment.

[0025] Figure 8 This is a block diagram showing the configuration of a bit string correction circuit according to the first embodiment.

[0026] Figure 9 This is a block diagram showing the configuration of a DA converter according to the second embodiment.

[0027] Figure 10 This is a diagram for explaining a bit string correction circuit according to the second embodiment.

[0028] Figure 11 This is a block diagram showing the configuration of a charged particle beam device according to a fourth embodiment.

[0029] Figure 12 It is a diagram showing formulas for explaining the embodiment.

[0030] Figure 13 This is a block diagram showing the configuration of a DA converter according to a modified example of the second embodiment. DETAILED DESCRIPTION

[0031] The embodiments will be described with reference to the accompanying drawings. The embodiments described below do not limit the invention to the scope of the claimed patents, and not all elements and combinations thereof described in the embodiments are necessarily essential to the solution provided by the invention.

[0032] (Implementation 1)

[0033] <Device Structure>

[0034] Figure 1 This is a block diagram showing the structure of the device according to Embodiment 1. Figure 1 In the figure, 1 represents a device. The device 1 includes a processor 10P, a front-stage circuit 10FNT, a main circuit 10BDY, and an analog / digital converter (hereinafter referred to as an AD converter) 10AD.

[0035] exist Figure 1 In the description, OBJ represents an object device, and an analog value is output from device 1 to object device OBJ. Here, the case where object device OBJ is provided outside device 1 is described, but of course object device OBJ can also be included in device 1. Object device OBJ is a device that performs actions by providing analog values ​​from device 1. An example of object device OBJ will be described later, but it is not limited to this. If understood broadly, object device OBJ can also be regarded as a control object device that controls its actions according to the analog value from device 1, and object device OBJ can also be understood as an amplifier circuit such as an operational amplifier. In addition, in this specification, a value represented in an analog manner (at least referring to a value represented by a physical quantity that continuously changes (or is caused to change) such as voltage or current) is called an analog value. In addition, the generation, output, input, transmission and reception of analog values ​​of physical existence (elements, circuits, devices) actually at least means the change of physical quantities such as current and voltage that continuously change (or are caused to change).

[0036] In the following description, sometimes Figure 1 The front-stage circuit 10FNT and the main body circuit 10BDY shown are collectively referred to as a DA conversion circuit.

[0037] <<Processor>>

[0038] The processor 10P is a processor that performs predetermined processing (in Figure 1 A device that generates and transmits a value (hereinafter sometimes referred to as a DA conversion target value) to be provided to an object device OBJ after DA conversion via a circuit described later, as a digital value (bit string). In the following description, the bit string generated and transmitted by the processor 10P as a result of the control processing is referred to as a processor output bit string, and is Figure 1 10BTP is shown in FIG.

[0039] The processor 10P is, for example, a device such as a CPU or a GPU that executes a predetermined process by executing a program. However, the processor 10P may be an FPGA or other IC as long as the processor 10P can generate the above-mentioned digital value (bit string) by performing the predetermined process. In addition, the processor 10P may be part of a component 10C such as a motherboard or a controller together with a volatile memory VOLMEM or a non-volatile memory NVMEM (for example, a flash memory or an HDD), but may also be a computer. In other words, the device 1 itself may be a computer. In addition, the program (group) for implementing the test process and the control process executed by the processor 10P is stored in the non-volatile memory NVMEM.

[0040] <<Main circuit and pre-stage circuit>>

[0041] The main circuit 10BDY includes one or more DA converters (calibration target DA converters) 10DAC that convert the main input bit string 10BTB into analog output values ​​10ANG(A) and output them. The value of the main input bit string 10BTB outputted based on the processor output bit string 10BTP having the DA conversion target value can also be said to have a "calibrated DA conversion target value."

[0042] The front-end circuit 10FNT is a circuit that receives the processor output bit string 10BTP and outputs the main body input bit string 10BTB. The front-end circuit 10FNT includes a bit string correction circuit 10BCT. The bit string correction circuit 10BCT corrects the bit string according to the correction data (in Figure 1 (D) Correction is performed on the processor output bit string 10BTP and the output main input bit string 10BTB. The correction data is stored in a memory (not shown) within the preceding circuit. This correction does not have to be performed constantly. For example, it can be performed after the calibration test described below.

[0043] AD Converter

[0044] AD converter 10AD is used in the calibration test described later. During the calibration test, AD converter 10AD converts analog output value 10ANG into bit string 10BTTR. In the following description, bit string 10BTTR will be referred to as test result bit string 10BTTR for ease of distinction. Furthermore, the calibration test may sometimes be referred to simply as "test." Of course, AD converter 10AD can also be used for purposes other than testing.

[0045] <<Test Purpose and Calibration Purpose>>

[0046] The processor 10P performs a calibration test to determine the conversion relationship (primarily the D / A conversion relationship) between the input and output of the main circuit 10BDY based on changes in the main circuit 10BDY's characteristics (e.g., due to environmental factors such as temperature). Based on the results of this test, calibration data is generated for use in the preceding circuit 10FNT. While the first embodiment focuses on the characteristic changes of the D / A converter 10DAC(A), characteristic changes of other components can also be considered. For example, characteristic changes of the amplifier circuit AMP, described later, can also be considered.

[0047] Furthermore, the typical purpose of calibration based on understanding this conversion relationship is to improve digital and analog linearity. This is explained using a 3-bit bit string (offset binary or unsigned binary) as an example. If the output current is 4 mA for the bit string (1, 0, 0) represented in the order of MSB, middle bit, and LSB, then a DA converter with high linearity would ideally output an analog value of 2 mA for the bit string (0, 1, 0) and 1 mA for the bit string (0, 0, 1), based on the meaning of each bit.

[0048] However, because the characteristics of the circuit responsible for the intermediate bits within the DA converter change significantly, the linearity described above degrades when only the bit string (0, 1, 0) outputs 3 mA and other outputs remain unchanged. The correction performed in the preceding circuit 10FNT improves the degraded linearity by changing the bit string actually input to the DA converter 10DAC. Furthermore, the target straight line for improvement does not need to be a straight line connecting the analog values ​​of the bit string (1, 0, 0) and the analog values ​​of the bit string (0, 0, 1). It can also be a straight line interpolated using the analog values ​​of the other two bit strings, or a straight line obtained using regression analysis.

[0049] In the first embodiment, during the calibration test of the processor 10P, a plurality of pairs (hereinafter also referred to as test pairs) of test bit strings (sometimes abstractly referred to as test input values) and test result bit strings (sometimes abstractly referred to as test result values) having the following characteristics (A1) and (A2) are acquired:

[0050] (A1) The test bit string is the processor output bit string or the main body input bit string used for calibration testing. Alternatively, the test bit string can be viewed from another perspective as a value input to the main body circuit, with or without correction, as the DA conversion target value.

[0051] (A2) The test result bit string is obtained by converting the analog value output by the main circuit using the AD converter. Alternatively, the test result bit string can be viewed as a value obtained by converting the analog signal output by the main circuit by the AD converter using the AD converter.

[0052] Here, the conversion relationship between the digital value (bit string) and the analog value of the DA converter 10DAC(A) is obtained by processing the set of the plurality of test pairs or the set.

[0053] The following describes a plurality of embodiments in which, in order to shorten the test processing time, the number of logarithms associated with the above-mentioned test is reduced by taking into account the internal structure of the DA converter 10DAC(A). More specifically, Figure 1 As shown, the DA converter 10DAC(A) considers the structure of a DA converter (hereinafter also referred to as a hybrid DA converter) that generates an analog value as a converter by adding the analog value output by the first circuit segment SEG1 and the analog value output by the second circuit segment SEG2, and reduces the number of test pairs.

[0054] In the case of a hybrid DA converter that supports multi-bit inputs with high precision while suppressing the circuit scale within the DA converter, a circuit segment designed for high precision (typically responsible for the MSB and a predetermined number of bits (groups) below the MSB) and a circuit segment designed for low circuit scale implementation (typically responsible for the LSB and a predetermined number of bits (groups) above the LSB) are used. Examples of such segments (first circuit segment SEG1, second circuit segment SEG2) include a thermometer type designed for high precision and a weighted binary type (ladder type) designed for low circuit scale implementation. Taking a 3-bit hybrid DA converter (offset binary format or unsigned binary format) as an example, the circuit segment designed for high precision (hereinafter sometimes referred to as the high-precision circuit segment) is responsible for the MSB, while the circuit segment designed for low circuit scale implementation (hereinafter sometimes referred to as the low circuit scale implementation circuit segment) is responsible for the LSB and intermediate bits. The above example is not intended to limit the technology of this specification to DA converters that process inputs in offset binary format or unsigned binary format. The technology of this specification can also be applied to other binary formats (for example, two's complement binary format).

[0055] Furthermore, in low-circuit-scale circuit segments, shared components are often used to output the analog value of a particular bit string and the analog value of another bit string. For a three-bit example, shared components are used within the low-circuit-scale circuit segment for both the bit string (x, 0, 1) and the bit string (x, 1, 1). Furthermore, the MSB is omitted as x, as it is a prerequisite for high-density packaging.

[0056] In the following embodiments, based on the relationship between each bit in the bit string and the components used in the circuit segment, one or more test pairs are obtained. This allows the test result bit strings of the other test pairs to be accurately estimated, and these "other test pairs" are omitted. As a result, the number of test pairs in a single calibration test is less than 2 raised to the power of "the number of bits in the test bit string." In other words, the number of test pairs obtained during the calibration test is less than 2 raised to the power of N (where N is the number of bits representing the resolution of the DA converter component being calibrated).

[0057] <<Main circuit options>>

[0058] The main body circuit 10BDY of the first embodiment may also have the following options.

[0059] <<<Amplifier Circuit AMP>>>

[0060] When the output (output current, output voltage) of the DA converter 10DAC(A) is insufficient to operate the target device OBJ, the amplifier circuit AMP amplifies the output of the DA converter 10DAC(A). Examples of such an amplifier circuit AMP include an operational amplifier, an amplifier circuit using an operational amplifier, or an amplifier circuit using transistors (including FETs). Furthermore, the amplifier circuit AMP may use circuit elements (e.g., resistors) that may be affected by the operating environment (e.g., temperature). To compensate for such amplifier circuit fluctuations, the output of the amplifier circuit AMP, 10ANG(B), may be used as the conversion target for the AD converter 10AD, instead of the main output analog circuit 10ANG(A). Furthermore, if the DA converter 10DAC(A) varies the current value and outputs it as an analog value, the amplifier circuit AMP can amplify either the current value or the voltage value. If the DA converter 10DAC(A) varies the voltage value and outputs it as an analog value, the amplifier circuit AMP can amplify either the voltage value or the current value.

[0061] <<<Attenuator>>>

[0062] The output of the DA converter 10DAC(A) or the output of the amplifier circuit AMP can also be input to the AD converter 10AD via an attenuator (not shown). The attenuator can limit the voltage or current input to the AD converter 10AD, thereby preventing damage to the AD converter 10AD due to high voltage or current values. Furthermore, even if the components constituting the attenuator are affected by the operating environment, fluctuations in the attenuator can be corrected.

[0063] DAC (B)

[0064] The main circuit 10BDY may also include an additional DA converter 10DAC(B). For example, DA converter 10DAC(B) is used to convert a number of bits exceeding the number of bits that can be input to DA converter 10DAC(A) into an analog value. The components required to add this DA converter 10DAC(B) include a splitter circuit 10SPT and a weighted addition circuit 10ADDW. Their respective functions will be described later. DA converter 10DAC(B) does not need to be a hybrid DA converter or may not be the subject of calibration testing. Conversely, DA converter 10DAC(B) may be a hybrid DA converter or may be the subject of calibration testing.

[0065] <<<Switch 10SW>>>

[0066] The switch 10SW switches whether the output of the DA converter 10DAC(A) is supplied to the object device OBJ side or the AD converter 10AD side. Figure 1 In the figure, the solid line indicates the state of switch 10SW during a test described later. In this state, the output of DA converter 10DAC(A) is supplied to AD converter 10AD. Switch 10SW is used when the main output analog value 10ANG is not favorable for target device OBJ during a test described later.

[0067] The front-stage circuit 10FNT may include the optional components described in connection with the main circuit 10BDY, instead of the main circuit 10BDY. For example, the front-stage circuit 10FNT may include the splitter circuit 10SPT(B) instead of the splitter circuit 10SPT(A) provided as an option for the main circuit 10BDY. Such an example arises when calibration, which is at least part of the function of the front-stage circuit 10FNT, is performed more closely in conjunction with the DA converter circuit.

[0068] Furthermore, addition is not limited to the DA converter 10DAC(A). Operational amplifiers and other components are not necessarily required for addition. For example, to add current values, the wiring from two current sources can be combined into a single line. To add voltage values, two voltage sources can be directly connected. In the following description, such a structure for addition will sometimes be referred to as an "adding circuit." In other words, an adding circuit may consist solely of wiring. Furthermore, a "circuit" may simply be wiring without any components.

[0069] In addition, the connection between the "wiring", the processor 10P, the front-stage circuit 10FNT, the main circuit 10BDY, and the AD converter 10AD can be a wiring formed on a substrate, or a cable such as a coaxial cable, an optical cable, a communication cable, or a wiring pattern within an IC chip, or a wiring virtually defined within an FPGA. For example, a communication cable (e.g., a network communication cable) can be used in part or all of the connection between the processor 10P and the front-stage circuit 10FNT. Therefore, the processor output bit string 10BTP can be sent in parallel through multiple wirings, or it can be serialized and sent as in a general communication method. The connection between the processor 10P, the front-stage circuit 10FNT, the main circuit 10BDY, and the AD converter 10AD is not necessarily directly connected only by wiring, but can also include some components in between. Examples of such components are photodiodes for optical communication, communication chips for communicating via network communication protocols (e.g., USB, PCI, Ethernet), timing adjustment and holding circuits (elements) commonly used in digital circuits and analog circuits, and bandpass filter circuits (elements). While this specification describes output, input, and transmission and reception of bit strings, it is sufficient that bit strings can be output, input, and transmitted and received, and it does not necessarily mean that "string" transmission must be maintained as in serial communication.

[0070] Furthermore, the components constituting the device 1 do not necessarily need to be unified into a single housing, device, or substrate. In other words, each component may be implemented by a different housing, device, or substrate.

[0071] <Configuration Example of DA Converter 10DAC(A)>

[0072] Figure 2 : is a block diagram showing the structure of the DA converter of embodiment 1. Figure 2 As shown, Figure 1 The DA converter 10DAC(A) shown in the figure includes a main DA converter M_DAC, a sub DA converter S_DAC, a weighted addition circuit MS_ADDW, holding circuits M_HL and S_HL, and a division circuit 10SPT(B). Here, an example in which the division circuit 10SPT(B) is included in the DA converter 10DAC(A) within the main circuit 10BDY is described, but Figure 1 As shown, the division circuit 10SPT(B) can also be included in the preceding stage circuit 10FNT. The following description uses a DA converter that processes inputs in offset binary or unsigned binary format as an example. However, the technology of this specification can also be applied to two's complement binary format (for example, a decoder circuit that performs binary conversion can be included within the DA converter 10DAC(A)).

[0073] exist Figure 2 FIGURE 1 shows a case where the number of bits in the processor output bit string (input bit string) 10BTP supplied from the processor 10P to the preceding circuit 10FNT and the main circuit 10BDY is N. The N-bit input bit string 10BTP is divided by the division circuit 10SPT(B) into an upper input bit string Inp_U and a lower input bit string Inp_L. Here, the relationship between the input bit string 10BTP, the upper input bit string Inp_U, and the lower input bit string Inp_L is as follows: the number of bits K of the upper input bit string Inp_U + the number of bits M of the lower input bit string Inp_L = the number of bits N of the input bit string 10BTP. Furthermore, the division circuit 10SPT(B) extracts M-1 bits from the least significant bit (LSB) of the input bit string 10BTP as the lower input bit string Inp_L. Furthermore, in the input bit string 10BTP, K bits from the M bits to the most significant bit MSB are extracted by the segmentation circuit 10SPT(B) as a higher-order input bit string Inp_U.

[0074] The upper input bit string Inp_U is held in a holding circuit M_HL corresponding to the main DA converter M_DAC and supplied to the input of the main DA converter M_DAC. The lower input bit string Inp_L is held in a holding circuit S_HL corresponding to the slave DA converter S_DAC and supplied to the input of the slave DA converter S_DAC. The upper input bit string Inp_U is converted to a corresponding analog value by the main DA converter M_DAC, and the lower input bit string Inp_L is converted to a corresponding analog value by the slave DA converter S_DAC. The analog values ​​obtained by the main DA converter M_DAC and the analog values ​​obtained by the slave DA converter S_DAC are added by the adding circuit MS_ADDW and output as an analog value 10ANG(A) corresponding to the input bit string 10BTP.

[0075] Since the upper input bit string Inp_U consists of bits on the MSB side of the most significant bit, the analog value output from the main DA converter M_DAC changes significantly (roughly) when the bits constituting the upper input bit string Inp_U change. In contrast, since the lower input bit string Inp_L consists of bits on the LSB side of the least significant bit, the analog value output from the sub DA converter S_DAC changes slightly (subtly) when the bits constituting the lower input bit string Inp_L change.

[0076] <<Configuration of DA converters M_DAC, S_DAC, and adding circuit MS_ADDW>>

[0077] Next, explain Figure 2The main DA converter M_DAC, the sub DA converter S_DAC, and the adding circuit MS_ADDW are shown as specific examples. Figure 3 This is a circuit diagram showing the configuration of a DA converter according to the first embodiment.

[0078] In the first embodiment, the main DA converter M_DAC is composed of a thermometer type DA converter (hereinafter referred to as M_DAC), and the sub DA converter S_DAC is composed of a weighted binary type DA converter (hereinafter referred to as S_DAC). The thermometer type DA converter M_DAC is equivalent to Figure 1 The first circuit segment SEG1 shown, and the weighted binary DA converter S_DAC correspond to the second circuit segment SEG2. Therefore, the DA converter 10DAC(A) is a segmented DA converter that combines the thermometer-type DA converter M_DAC (the first circuit segment) and the weighted binary DA converter S_DAC (the second circuit segment).

[0079] The input bit string from the segmentation circuit 10SPT (B) is provided to the control circuits (hereinafter also referred to as decoders) M_DEC and S_DEC. That is, the upper input bit string Inp_U from the segmentation circuit 10SPT (B) is provided to the decoder M_DEC. The decoder M_DEC outputs a plurality of complementary signals UI+ and UI- according to the code of the upper input bit string Inp_U provided. That is, the signal UI+ is set to a high level for a number corresponding to the number represented by the code of the upper input bit string Inp_U, and the remaining signal UI+ is set to a low level. In addition, the signal UI- is complementary (inverted) to the paired signal UI+, and becomes a low level when the paired signal UI+ is at a high level.

[0080] The lower-order input bit string Inp_L from the segmentation circuit 10SPT(B) is provided to the decoder S_DEC. The decoder S_DEC outputs complementary signals UB_0+, UB_0- to UB_M-1+, and UB_M-1- corresponding to the code of the provided lower-order input bit string Inp_L. The complementary signals UB_0+, UB_0- to UB_M-1+, and UB_M-1- correspond to bit 0 (the least significant bit, LSB) to bit M-1 of the lower-order input bit string Inp_L. For example, when bit 0 is a logical value of "1," the signal UB_0+ becomes high (UB_0- is low), and when bit 0 is a logical value of "0," the signal UB_0+ becomes low (UB_0- is high). Similarly, the remaining complementary signals UB_1+, UB_1- to UB_M-1+, and UB_M-1- become high or low depending on the logical value of the corresponding bit in the lower-order input bit string Inp_L.

[0081] <<<Weighted Binary DA Converter>>>

[0082] The weighted binary DA converter S_DAC includes a number of binary unit circuits (binary circuits, second-type circuits) UB_0 to UB_M-1, corresponding to the number M of bit strings comprising the lower-order input bit string Inp_L. Binary unit circuit UB_0 corresponds to the least significant bit (LSB) of the lower-order input bit string Inp_L, and binary unit circuits UB_1 to UB_M-1 correspond to bits 1 to M-1 in the lower-order input bit string Inp_L.

[0083] Each binary unit circuit UB_0 to UB_M-1 has a similar structure. Taking the binary unit circuit UB_0 corresponding to the least significant bit LSB as an example to illustrate the structure, the binary unit circuit UB_0 includes: transistors Q2 and Q3 whose drains are connected to the output lines Lo+ and Lo-; and a transistor Q4 connected between the common source of transistors Q2 and Q3 and the ground line Ls. Transistors Q2 and Q3 are turned on / off by the corresponding signals UB_0+ and UB_0- from the decoder S_DEC. A reference voltage Vref is supplied to the gate of transistor Q4. When the reference voltage Vref is supplied to transistor Q4, it generates a predetermined constant current 2 0 I lsb The constant current source functions. The transistor Q4 included in the binary unit circuit UB_0 is dimensioned, for example, so as to generate a constant current corresponding to the least significant bit (LSB). Therefore, when the signal UB_0+ is at a high level, for example, the transistor Q2 is turned on, and a predetermined constant current 2 flows from the output line Lo+ to the ground line Ls via the transistor Q2. 0 I lsb .

[0084] The difference between the binary unit circuits UB_1 to UB_M-1 and the binary unit circuit UB_0 is that the size of the transistor Q4 is set so that the value of the constant current formed becomes the value corresponding to bits 1 to M-1 of the lower input bit string Inp_L. For example, the transistor Q4 of the binary unit circuit UB_M-1 is set to flow a constant current 2 corresponding to bit M-1 of the lower input bit string Inp_L. M-1 I lsb .

[0085] Thus, in the weighted binary DA converter S_DAC, a constant current corresponding to each bit flows from the output line Lo+ to the ground line Ls via the binary unit circuit corresponding to the bit with a logical value of "1" in the lower-order input bit sequence Inp_L. As a result, the lower-order input bit sequence Inp_L is converted to the corresponding current value.

[0086] <<<Thermometer Type DA Converter>>>

[0087] The thermometer-type DA converter M_DAC includes thermal energy unit circuits (thermometer circuits, first-type circuits) UI corresponding to the number of bits K of the upper input bit string Inp_U. In other words, the thermometer-type DA converter M_DAC includes a power of 2 (2^ K ) The number of thermal energy unit circuits UI is . In addition, each thermal energy unit circuit UI is connected in parallel between the output lines Lo+, Lo- and the ground line Ls.

[0088] These thermal energy unit circuits UI have the same structure as each other. Figure 3 As shown, each thermal energy unit circuit UI includes a transistor Q1 to which a reference voltage Vref is supplied, and transistors Q2 and Q3 that operate complementarily to each other.

[0089] The transistor Q1 functions as a constant current source that generates a predetermined constant current by supplying a reference voltage Vref to the gate. The value of the generated constant current is the current 2 corresponding to the least significant bit M in the upper input bit string Inp_U. M I lsb .

[0090] In the thermometer-type DA converter M_DAC, transistors Q2 in the thermal energy unit circuit UI are turned on by the number of transistors indicated by the code of the upper input bit string Inp_U. Therefore, a current corresponding to the amount indicated by the upper input bit string Inp_U flows from the output line Lo+ to the ground line Ls. As a result, the upper input bit string Inp_U is also converted to a corresponding current value.

[0091] like Figure 3 As shown, the output lines Lo+ and Lo- are connected to the voltage Vd via the load resistor RL. That is, the load resistor RL is shared by the thermometer type DA converter M_DAC and the binary type DA converter S_DAC. Thus, the output of the thermometer type DA converter M_DAC is added to the output of the binary type DA converter S_DAC. That is, Figure 1 and Figure 2 The shown adding circuit MS_ADDW is implemented by common output lines Lo+ and Lo- and a load resistor RL.

[0092] <<<Handling various binary inputs>>>

[0093] The above is an explanation of the hybrid DA converter 10DAC (A) that assumes an offset binary form or an unsigned binary form. In the case of processing an input in a 2's complement binary form, a decoder circuit that converts the 2's complement binary form input inside the converter into an offset binary form can be configured between the segmentation circuit 10SPT (B) and the input terminal. In addition, other implementation examples are also considered. For example, the segmentation circuit 10SPT (B) can also input a bit string in a 2's complement binary form, split it into an upper input bit string Inp_U and a lower input bit string Inp_L in a 2's complement binary form, and output it. In this case, the decoder of each segment processes the 2's complement binary form. According to the above implementation example, the segmentation circuit can also be regarded as a circuit that outputs a K-bit internal upper bit string and an M-bit internal lower bit string based on the input value from the input terminal and the binary form assumed to be input by the element.

[0094] <DA Converter Calibration Test>

[0095] As a parameter related to the accuracy of the DA converter, there is linearity (INL) as described above. Figure 1 The linearity of the DA converter 10DAC(A) shown in FIG. 1 varies depending on, for example, changes in ambient temperature. In the first embodiment, in order to improve the accuracy of the DA converter 10DAC(A), a calibration test is performed before the DA converter 10DAC(A) actually performs a conversion operation. Based on the correction amount obtained by the calibration test, the linearity of the DA converter 10DAC(A) is adjusted by Figure 1 The front-stage circuit 10FNT shown corrects the input bit string of the DA converter 10DAC(A).

[0096] Figure 4 This is a flowchart for operating the DA converter 10DAC(A) of the first embodiment. In step S0, the DA converter 10DAC(A) starts operating. Thereafter, during the calibration period CAL, the processor 10P( Figure 1 ) Executes steps S0 to S3 to perform a calibration test on the DA converter 10DAC(A). Specifically, in step S1, the processor 10P reads a test bit string from the test data, inputs the read test bit string into the DA converter 10DAC(A) as an input bit string, and measures the output of the DA converter. In step S2, the processor 10P generates a correction value using the test bit string and the output of the DA converter 10DAC(A) measured in step S1. Thereafter, in step S3, the processor 10P determines whether the measurement of all test bit strings and the generation of correction values ​​have been completed. If it is determined in step S3 that the processing of all test bit strings has not yet been completed, the processor 10P returns to step S1. Specifically, during the calibration period CAL, the processor 10P repeatedly executes steps S1 to S3.

[0097] After the calibration test is completed, in step S4 , the DA converter 10 DAC(A) performs actual DA conversion operation.

[0098] To suppress fluctuations in the accuracy of the DA converter circuit caused by changes in ambient temperature and improve accuracy, one approach is to increase the frequency of calibration tests. However, a longer calibration period (CAL) reduces the frequency of actual DA conversion operations. If the calibration period (CAL) is long, one approach is to divide the calibration period into multiple parts and perform calibration tests in a distributed manner. However, this delays the completion of the final calibration, reducing accuracy until calibration is complete.

[0099] The test bit string has the same number of bits as the input bit string 10BTP actually input to the DA converter 10DAC(A). Generally, test bit strings corresponding to all code combinations of the input bit string 10BTP are prepared as test data. That is, as described above, in the case of an input bit string 10BTP with a bit number N (the number of bits of the upper input bit string: K bits + the number of bits of the lower input bit string: M bits), a power of 2 (2^ N ) test bit strings as test data. To achieve high resolution for the DA converter 10DAC(A), the number of bits in the input bit string needs to be increased, which results in a problem of lengthening the calibration period CAL.

[0100] Test data

[0101] In the first embodiment, in order to shorten the calibration period CAL, a test bit string is used that takes into account the structure of the DA converter 10DAC(A). Figure 2 and Figure 3 As described above, the case where the DA converter 10DAC(A) is composed of the thermometer type DA converter M_DAC and the weighted binary type DA converter S_DAC will be described as an example.

[0102] <<Test bit string for weighted binary DA converter>>

[0103] Input to Figure 3 The relationship between the lower input bit string Inp_L of the weighted binary DA converter S_DAC shown and the output of the DA converter is given by Figure 12 The formula (1) shown in FIG. In the formula (1), D0 to D M-1 Indicates the bits constituting the lower input bit string Inp_L. That is, bit D0 corresponds to the least significant bit LSB of the lower input bit string Inp_L, and D M-1 Corresponding to the most significant bit in the lower-order input bit string Inp_L. Figure 3The decoder S_DEC shown in FIG. 1 outputs signals UB_0+ and UB_0- according to the logic value of the bit D0. For example, when the logic value of the bit D0 is "1", the decoder S_DEC outputs a high-level signal UB_0+. M-1 Similar to the bit D0 , when the logic value of the bit is “1”, the decoder S_DEC sets the corresponding signals UB_1+ to UB_M−1+ to a high level.

[0104] In addition, in formula (1), W0~W M-1 Indicates the value of the constant current generated by the constant current source (transistor Q4) in the binary unit circuits UB_0 to UB_M-1. For example, the current value W0 indicates the value of the constant current generated by the transistor Q4 in the binary unit circuit UB_0.

[0105] As can be seen from formula (1), the current value S_DA output by the weighted binary DA converter S_DAC becomes the value of the constant current when the desired bit is the logic value "1" by setting the desired bit in the lower input bit string Inp_L to the logic value "1" and setting all other bits to the logic value "0". This means that, for example, if the logic value of bit D0 is set to "1" and bits D1 to D M-1 If all logical values ​​of are set to “0”, the value of the constant current corresponding to the bit D0 can be measured as the current value S_DA output from the weighted binary DA converter S_DAC.

[0106] Furthermore, when multiple bits in the lower input bit string Inp_L have a logic value of "1," by combining (adding) previously measured current values ​​S_DA for the bits that have a logic value of "1," it is possible to calculate the value of the constant current output from the DA converter S_DAC when multiple bits in the lower input bit string Inp_L have a logic value of "1." For example, when both bits D0 and D1 in the lower input bit string Inp_L have a logic value of "1," and all remaining bits have a logic value of "0," the current value S_DA output from the weighted binary DA converter S_DAC at this time can be calculated by adding the previously measured current value S_DA for bit D0 and the previously measured current value S_DA for bit D1.

[0107] That is, if the output of the weighted binary DA converter S_DAC is measured when only one bit in the lower input bit string Inp_L is the logical value "1", then the measured value can also be used to calculate the output of the weighted binary DA converter S_DAC when multiple bits in the lower input bit string Inp_L are simultaneously the logical value "1".

[0108] Considering the structure of the weighted binary DA converter, in the weighted binary DA converter S_DAC of the first embodiment, bits D0 to D1 are used as a test bit string corresponding to the lower input bit string Inp_L. M-1 Any one of the bits is a logic value "1", and all other bits are a logic value "0".

[0109] Furthermore, it is considered that the weighted binary DA converter S_DAC has a DC offset DC_Offset. Therefore, in the first embodiment, D0 to D M-1 Therefore, the number of test bit strings for the weighted binary DA converter S_DAC in the first embodiment is M+1.

[0110] <<Test bit string for thermometer-type DA converter>>

[0111] In the thermometer type DA converter M_DAC, the constant currents of the thermal energy unit circuits UI corresponding to the number indicated by the code of the input bit string are added together to form a current value output from the thermometer type DA converter M_DAC.

[0112] In the first embodiment, the same bit string as all codes that can be input to the thermometer type DA converter M_DAC is used as the test bit string. That is, the number of test bit strings for the thermometer type DA converter M_DAC is the power of 2 (2^ K ).

[0113] As a result, during the calibration period CAL, the DA converter 10DAC(A) ( Figure 2 The number of test bit strings for the weighted binary DA converter S_DAC is M+1, and the number of test bit strings for the thermometer DA converter M_DAC is 2^ K The sum (M+1+2^ K ), the number of test bit strings corresponding to all codes represented by the input bit string (2^ N For example, when the number of bits K of the upper input bit string Inp_U is set to 7, the number of bits M of the lower input bit string Inp_L is set to 7, and the number of bits N (=K+M) of the input bit string 10BTP is set to 14 (when the resolution is N bits), the number of test bit strings corresponding to all codes is 2^ 14 =16384. In contrast, according to the first embodiment, the number of test bit strings is 7+1+2^ 7= 136. That is, during the calibration period CAL, the test bit string is supplied to the DA converter 10DCA(A), and the number of times its output is measured can be significantly reduced to 136 times.

[0114] Before executing the calibration test, the test data for the thermometer type DA converter M_DAC and the test data for the weighted binary type DA converter S_DAC determined in this way are stored in Figure 1 The non-volatile memory NVMEM or the volatile memory VOLMEM is shown.

[0115] <Calibration test operation>

[0116] Figure 5 This is a flow chart for explaining the calibration test of embodiment 1. Figure 6 This is a diagram for explaining the calibration test of embodiment 1. Figure 1 、 Figure 2 、 Figure 5 as well as Figure 6 , explaining the actions of the calibration test.

[0117] exist Figure 5 In step SC0, processor 10P starts a calibration test. While this example describes an example in which a calibration test of thermometer-type DA converter M_DAC (hereinafter, also referred to as DA converter M_DAC) is performed before a weighted binary DA converter S_DAC (hereinafter, also referred to as DA converter S_DAC), the present invention is not limited to this example. Alternatively, a calibration test may be performed on DA converter S_DAC first.

[0118] In step SC1, the processor 10P reads a test bit string from the test data stored in the non-volatile memory NVMEM or the volatile memory VOLMEM, and inputs the test bit string as the upper input bit string Inp_U to the DA converter M_DAC constituting the DA converter 10DAC(A) via the front-stage circuit 10FNT. At this time, the processor 10P inputs a bit string (lower input bit string of a predetermined value) having all logic values ​​of "0" as the lower input bit string Inp_L to the DA converter S_DAC constituting the DA converter 10DAC(A). In addition, the processor 10P controls the switch 10SW( Figure 1 ) so that the output of the DA converter 10DAC(A) is provided to the AD converter 10AD.

[0119] Thus, the analog value corresponding to the test bit string converted by the DA converter M_DAC is supplied to the AD converter 10AD, and is converted by the AD converter 10AD into a digital string corresponding to the supplied analog value, and is output as the test result bit string 10BTTR ( Figure 1) is provided to processor 10P.

[0120] In step SC2, the processor 10P compares the test bit string supplied to the DA converter M_DAC in step SC1 with the supplied test result bit string, and generates input-output characteristics of the DA converter M_DAC based on the test bit string. Based on the generated input-output characteristics, the processor 10P generates a correction amount to make the test result bit string consistent with the test bit string, and uses this as correction data ( Figure 1 The correction value D) is stored in the memory of the preceding circuit 10FNT. At this time, the processor 10P stores the generated correction value in a pair with the supplied test bit string.

[0121] Next, in step SC3, processor 10P determines whether testing of DA converter M_DAC based on all test bit strings has completed. This is achieved, for example, by processor 10P determining whether all test data to be supplied to DA converter M_DAC has been read from non-volatile memory NVMEM or volatile memory VOLMEMTHM. If processor 10P determines that testing based on all test bit strings has not yet completed, processor 10P returns to step SC1, reads out the unread test bit strings, and repeats steps SC1 to SC3.

[0122] The output voltage range represented by the input bit string Input input to the DA converter 10DAC(A) is determined according to the code of the upper input bit string Inp_U input to the DA converter M_DAC, as shown in FIG. Figure 6 As shown in the table on the left, the 128-bit CMOS is divided into multiple blocks 1 to 128. The code of the upper input bit string Inp_U represents the unique base voltage value of each block, and the code of the lower input bit string Inp_L represents the voltage value common to all blocks. For example, if the upper input bit string Inp_U has a logical value of "0x8000", block 1 is identified, and the upper input bit string Inp_U represents the base voltage VB1B of block 1. If the upper input bit string Inp_U has a logical value of "0x0000", block 65 is identified, and the upper input bit string Inp_U represents the base voltage VB65B of block 65.

[0123] The analog value 10ANG(A) outputted from the DA converter 10DAC(A) after the input bit string is converted is represented by Figure 12The formula (2) shown is expressed. In formula (2), VB(i) represents the basic voltage represented by the upper input bit string Inp_U. According to formula (2), by adding the common voltage value represented by the code of the lower input bit string Inp_L to the basic voltage value determined by the code of the upper input bit string Inp_U, the analog value 10ANG(A) corresponding to the input bit string 10BTP is obtained. Therefore, in step SC1, by inputting a predetermined value (all logical values ​​are "0") as the lower input bit string Inp_L to the DA converter S_DAC, the upper input bit string Inp_U represents the basic voltage VB(i) of the block represented by the upper input bit string.

[0124] exist Figure 6 , the graph on the right shows the relationship between the block number and the base voltage. In the graph, the horizontal axis represents the block number and the vertical axis represents the base voltage. Although there is no particular limitation, it can be understood from the graph that the DA converter 10DAC(A) of embodiment 1 converts the input bit string 10BTP into the positive voltage side and the negative voltage side with the ground voltage (0V) as the reference. In addition, as the DC offset DC_Offset, the base voltage uses the value at block number 65 corresponding to the ground voltage (0(V)) at which the output noise becomes smaller. That is, the output value of the DA converter 10DAC(A) when the test bit string corresponding to the logical value "0x000" is provided to the DA converter 10DAC(A) becomes the DC offset DC_Offset. In other words, the lower input bit string Inp_L is set to a predetermined value (all logical values ​​are "0"), and the upper input bit string Inp_U is also set to a predetermined value (all logical values ​​are "0") to obtain the DC offset DC_Offset.

[0125] Next, a calibration test of the DA converter S_DAC will be described.

[0126] After step SC3, the processor 10P executes step SC4. In step SC4, the processor 10P reads a test bit string related to the DA converter S_DAC stored in the nonvolatile memory NVMEM or the volatile memory VOLMEM and inputs it to the DA converter S_DAC as the lower input bit string Inp_L. At this time, the processor 10P inputs a bit string with all logical values ​​of "0" (the upper input bit string of a predetermined value) as the upper input bit string Inp_U to the DA converter M_DAC. In addition, the processor 10P controls the switch 10SW so that the output of the DA converter 10DAC(A) is provided to the AD converter 10AD.

[0127] Thus, the analog value corresponding to the test bit string converted by DA converter S_DAC is provided to AD converter 10AD, converted by AD converter 10AD into a corresponding digital string, and provided to processor 10P as test result bit string 10BTTR.

[0128] In step SC5, the processor 10P compares the test bit string provided to the DA converter S_DAC in step SC3 with the provided test result bit string, and generates input-output characteristics of the DA converter S_DAC based on the test bit string. Based on the generated input-output characteristics, the processor 10P generates a correction amount to make the test result bit string consistent with the test bit string, and uses this as correction data ( Figure 1 The correction value D) is stored in the memory of the preceding circuit 10FNT. At this time, the processor 10P stores the generated correction value in a pair with the provided test bit string.

[0129] Next, in step SC6, processor 10P determines whether testing of DA converter S_DAC based on all test bit strings has been completed. This determination can be made, for example, using the same method as described in step SC3. If processor 10P determines in step SC6 that not all test bit strings have been read, processor 10P returns to step SC4, reads the remaining test bit strings, and repeats steps SC4 to SC6.

[0130] When step SC6 is completed, the processor 10P ends the calibration test in step SC7.

[0131] Figure 7 This is a diagram for explaining the correction amount in Embodiment 1. Figure 7 In the figure, the Figure 6 This is an example of a correction amount generated by the processor 10P according to the calibration test described in , and stored as correction data (correction data D) in the preceding stage circuit 10FNT.

[0132] exist Figure 7 In FIG, THM_D corresponds to the DA converter M_DAC and indicates an area storing a plurality of correction values ​​generated by executing steps SC1 to SC3, and BW_D corresponds to the DA converter S_DAC and indicates an area storing a plurality of correction values ​​generated by executing steps SC4 to SC6. Figure 7 As shown, the correction amount of the DC offset DC_Offset is stored in the area BW_D.

[0133] In the area THM_D, the column M_DAC_Code indicates an area where a test bit string corresponding to the upper input bit string Inp_U is stored, and the column THM_C indicates an area where a correction amount is stored. Figure 7In the THM_C area, the correction amount for the block number corresponding to the test bit string is stored. In the TMH_D area, the test bit string and the correction amount are stored in pairs. For example, the correction amount for block number 1 is stored in a pair with the test bit string "0x8000" representing block number 1.

[0134] In area BW_D, the S_DAC_Code column indicates the area for storing the test bit string corresponding to the lower-order input bit string Inp_L, and BW_C indicates the area for storing the correction value for the bit number corresponding to the test bit string. For example, the correction value for bit 1 is stored as a pair with the test bit string "0x0001," in which only bit 1 has a logical value of "1." Furthermore, a DC offset DC_Offset is stored as a pair as correction data corresponding to the test bit string "0x0000."

[0135] <Correction>

[0136] Next, correction performed in the preceding stage circuit 10FNT will be described using the drawings. Figure 8 This is a block diagram showing the configuration of a bit string correction circuit according to the first embodiment.

[0137] The bit string correction circuit 10BCT includes a table THM_T corresponding to the upper input bit string Inp_U, a table BW_T corresponding to the lower input bit string Inp_L, and adders ADD1 and ADD2.

[0138] The processor 10P stores the data in the area THM_D ( Figure 7 ) is sent to the table THM_T and the correction amount of the test bit string and block number stored in the area BW_D ( Figure 7 ) and the correction amount of the bit are sent to the table BW_T. Figure 8 As shown, in table THM_T, test bit strings corresponding to upper input bit strings Inp_U and corresponding correction amounts are registered in pairs, and in table BW_T, test bit strings corresponding to lower input bit strings Inp_L and corresponding correction amounts are registered in pairs.

[0139] The table THM_T is searched by the upper input bit string Inp_U of the input bit string 10BTP, and outputs the correction amount corresponding to the test bit string that matches the upper input bit string Inp_U. The output correction amount is supplied to the adder ADD1.

[0140] In addition, the table BW_T is searched using the lower input bit string Inp_L of the input bit string 10BTP. In this search, a test bit string with the same bit number as the bit number with the logical value of "1" is searched in the lower input bit string Inp_L. Through the search, the correction amount corresponding to the test bit string with the same bit number and the logical value of "1" is output from the table BW_T. In the lower input bit string Inp_L of the input bit string 10BTP, sometimes multiple bit numbers that are different from each other become the logical value "1" at the same time. In this case, multiple correction amounts are output from the table BW_T. To cope with this situation, the correction amounts output from the table BW_T are digitally summed. The summed correction amount is provided to the adder ADD1.

[0141] Adder ADD1 adds the correction amount from table THM_T and the correction amount from table BW_T (the sum of the correction amounts) and supplies it to adder ADD2. Adder ADD2 adds the input bit string 10BTP and the correction amount from adder ADD1 and supplies it to the input of DA converter 10DAC(A).

[0142] Thus, the main input bit string 10BTB supplied to the DA converter 10DAC(A) is corrected by the preceding circuit 10FNT based on the correction amount determined in the calibration test. In other words, the input bit string supplied to the DA converter 10DAC(A) is corrected based on the input / output characteristics of the DA converter 10DAC(A), thereby improving accuracy.

[0143] Since the number of test bit strings used during the calibration test can be reduced, the calibration period CAL can be shortened. Therefore, the execution interval of the calibration test can be shortened to cope with fluctuations in the ambient temperature.

[0144] Furthermore, the number of correction amounts corresponding to the lower-order input bit string Inp_L becomes the number M+1 of bits constituting the lower-order input bit string Inp_L, and thus it is possible to prevent the table BW_T and the area BW_D of the memory 100 from becoming larger.

[0145] In the first embodiment, the bit string correction circuit 10BCT of the preceding stage circuit 10FNT is as follows, for example. Figure 8 Although an adder is shown, it can be omitted. This can be achieved, for example, by registering not only the correction amount but also a value obtained by adding the correction amount to the value shown in the original processor output bit string 10BTP in the tables THM_T and BW_T, and outputting the value obtained by correcting the processor output bit string from the bit string correction circuit 10BCT.

[0146] Alternatively, the DA converter 10DAC(A) may be configured by a plurality of DA converters, a plurality of division circuits, and a plurality of weighted addition circuits.

[0147] In addition, Figure 4 as well as Figure 5 While the example of repeatedly measuring the test result bit string corresponding to the test bit string and generating the correction value is shown in FIG, the method of generating the correction value is not limited to this. For example, the correction value can be generated by creating a target DA conversion relationship using regression analysis (linear regression). In other words, all measurements can be performed and then the correction value generated.

[0148] While the first embodiment illustrates an example of generating calibration data through a calibration test, the present invention is not limited thereto. For example, already generated calibration data can also be updated through a calibration test. In this case, the preceding circuitry performs calibration based on the updated calibration data. In the following description, the term "updating calibration data" may sometimes encompass both the generation and updating of calibration data.

[0149] In the first embodiment, the updating of the calibration data or the generation of the test input value is performed based on the relationship between the bit group included in the bit string input to the DA converter 10DAC(A) and the first type circuit segment SEG1 and the second type circuit segment SEG2.

[0150] In addition, in the first embodiment, an example was described in which uncorrected values ​​were used as test pairs, ie, test input values. However, the present invention is not limited thereto. That is, for example, a calibration test may be performed using corrected values ​​as test input values.

[0151] like Figure 2 As shown, the segmentation circuit 10SPT (B) outputs the K-bit internal upper bits (Inp_U) to the first circuit segment (M_DAC) and the M-bit internal lower bits (Inp_L) to the second circuit segment (S_DAC). In addition, the calibration test includes a first-type test for understanding the DA conversion characteristics of the first circuit segment (M_DAC) and a second-type test for understanding the DA conversion characteristics of the second circuit segment (S_DAC). In this case, as Figure 5 As shown, the test input value for the first type used in the test for the first type is adjusted so that the internal lower bit string becomes the value of the second fixed bit string (predetermined value input of step SC1). Figure 5 As shown, the test input values ​​used in the second test are adjusted so that the internal high-order bit string becomes the first fixed bit string (the predetermined value input in step SC4). This reduces the influence of the second circuit segment in the first test and reduces the influence of the first circuit segment in the second test.

[0152] In addition, during calibration tests, e.g. Figure 6As shown in FIG, an offset measurement test is performed to obtain an analog value that does not depend on the values ​​of the internal upper bit string and the internal lower bit string. Figure 6 As shown, "0x0000" as the first fixed bit string and the second fixed bit string are input to the first type circuit segment (M_DAC) and the second type circuit segment (S_DAC).

[0153] The calibration test involved in the first embodiment can be regarded as not including the first reduction target test using the first reduction target test input value. Here, the internal high-order bit string of the first reduction target test input value is the first fixed bit string ( Figure 5 M_DAC: input a value other than a predetermined value), and the internal lower bit string is the second fixed bit string ( Figure 5 S_DAC: Enter a value other than the predetermined value).

[0154] Furthermore, the calibration test according to Embodiment 1 can be considered to include a first reduced test using the first reduced test input value. Here, the internal upper bit string of the first reduced test input value is a value other than the first fixed bit string, and the internal lower bit string is a value other than the second fixed bit string. The number of test pairs used in the first reduced test is 2 to the power of N - (2 to the power of K + 2 to the power of M + 1).

[0155] exist Figure 3 In the embodiment, the decoder M_DEC can be regarded as a selector for selecting a first type of circuit from a plurality of first type of circuits UI. In this case, the selector provides an activation signal (high level signal UI+) to the selected first type of circuit and provides an inactivation signal (high level signal UI-) to the unselected first type of circuit. Considering Figure 3 The activation / inactivation of the first circuit and the second circuit shown is based on the relationship between the bit group included in the bit string input to the DA converter 10DAC(A) and the activation / inactivation of the first circuit and the second circuit to update the correction data or generate the test input value.

[0156] In addition, the number of test pairs obtained in the calibration test is Figure 3 The total number of the first circuit and the second circuit described above.

[0157] exist Figure 8 In FIG. 3 , table THM_T can be regarded as a first table for managing correction amounts originating from the first type of circuit segments, and table BW_T can be regarded as a table for managing correction amounts originating from the second type of circuit segments.

[0158] As the test bit string, an example using the processor output bit string 10BTP is shown, but the main body input bit string 10BTB may also be used as the test bit string.

[0159] (Implementation Method 2)

[0160] In Embodiment 1, a device using a single DA converter 10DAC(A) was described. In Embodiment 2, a device using multiple DA converters is described. Specifically, Embodiment 2 describes a case where the main circuit 10BDY includes an additional DA converter 10DAC(B) in addition to DA converter 10DAC(A). The addition of DA converter 10DAC(B) increases the number of bits that can be input to the DA converter. In this case, as described above, the main circuit 10BDY further includes a splitting circuit 10SPT(A) and a weighted addition circuit 10ADDW.

[0161] Figure 9 This is a block diagram showing the configuration of a device according to the second embodiment. Figure 9 A main body circuit 10BDY and a previous stage circuit 10FNT according to the second embodiment are shown.

[0162] <Main circuit>

[0163] exist Figure 9 In FIG. 1 , the main circuit 10BDY includes a DA converter 10DAC(A), a DA converter 10DAC(B), and a weighted addition circuit 10ADDW. Figure 2 As shown, the DA converter DAC(A) is composed of a division circuit, holding circuits M_HL and S_HL, a main DA converter M_DAC, a sub DA converter S_DAC, and an adding circuit MS_ADDW. In the DA converter DAC(A) of the second embodiment, the division circuit is a division circuit 10SPT(B) provided in the main circuit 10BDY.

[0164] The output of the DA converter 10DAC(A) and the output of the DA converter 10DAC(B) are added by the adding circuit 10ADDW and transmitted as an analog value via the switch 10SW( Figure 1 ) is supplied to the amplifier circuit AMP or the AD converter 10AD. In the second embodiment, although not particularly limited, the adding circuit 10ADDW includes a gain amplifier 10M_GP to which the output from the DA converter 10DAC(A) is supplied; a gain amplifier 10S_GP to which the output from the DA converter 10DAC(B) is supplied; and an adder ADDW that adds the outputs of the gain amplifiers 10M_GP and 10S_GP and outputs the sum.

[0165] <Pre-stage circuit>

[0166] like Figure 9As shown, the front-stage circuit 10FNT includes a bit string correction circuit 10BCT, a division circuit 10SPT(B), holding circuits 10M_HL and 10S_HL, and an adder ADD4. In the first embodiment, the bit string correction circuit 10BCT mainly uses Figure 8 The adder ADD2 adds the processor output bit string 10BTP and outputs it. On the other hand, in embodiment 2, as Figure 9 As shown, such addition is not performed as the bit string correction circuit 10BCT. This is because the adder ADD4 performs a similar role.

[0167] The processor output bit string 10BTP from the processor 10P is supplied to the segmentation circuit 10SPT(B). While not particularly limited, the following description uses the case where the processor output bit string 10BTP is 32 bits. That is, the 32 bits, which are temporally parallel, are treated as a single bit string, and the bit string is supplied from the processor 10P to the preceding circuit 10FNT.

[0168] The segmentation circuit 10SPT(B) segments the supplied 32-bit processor output bit string 10BTP into an upper bit string U_Input and a lower bit string L_Input. Here, the upper bit string U_Input consists of the 16 bits on the MSB side of the processor output bit string 10BTP, and the lower bit string L_Input consists of the 16 bits on the LSB side of the processor output bit string 10BTP. Of course, the 32-bit and 16-bit values ​​are merely examples and are not limiting.

[0169] The upper bit string U_Input is held by a holding circuit 10M_HL and input to a DA converter 10DAC(A). Meanwhile, the lower bit string L_Input is held by a holding circuit 10S_HL and supplied to an adder ADD4. The output of adder ADD4 is input to a DA converter 10DAC(B). The outputs of DA converters 10DAC(A) and 10DAC(B) are added together by a weighted adding circuit 10ADDW and output as, for example, an analog value 10ANG(A).

[0170] The bit string correction circuit 10BCT includes tables THM_T and BW_T, and an adder ADD3. Tables (first table) THM_T and table (second table) BW_T are searched using the upper bit string U_Input. The correction values ​​found by the search are added together by adder ADD3. The addition result from adder ADD3 is supplied to adder ADD4. Adder ADD4 then adds the correction value from the bit string correction circuit 10BCT to the lower bit string L_Input. In other words, the lower bit string L_Input is corrected using the correction value from the bit string correction circuit 10BCT.

[0171] The DA converter 10DAC(A) of the second embodiment is formed by using Figure 2 and Figure 3 The segmented DA converter configuration described above includes a DA converter 10DAC(A) including a thermometer-type DA converter M_DAC and a weighted binary-type DA converter S_DAC.

[0172] In the second embodiment, the DA converter 10DAC(A) whose voltage varies greatly depending on the value of the input bit string is calibrated. Therefore, during the calibration period CAL, a test bit string suitable for the structure of the thermometer type DA converter M_DAC and the weighted binary type DA converter S_DAC constituting the DA converter 10DAC(A) is input as the upper bit string U_Input from the processor 10P( Figure 1 ) is provided to the DA converter 10DAC(A).

[0173] That is, similarly to the first embodiment, test data consisting of a test bit string derived from the structure of the thermometer-type DA converter M_DAC constituting the DA converter 10DAC(A) and test data consisting of a test bit string derived from the structure of the weighted binary-type DA converter S_DAC constituting the DA converter 10DAC(A) are prepared in advance.

[0174] Using the prepared test data, as described in the first embodiment, the processor 10P provides the test bit string to the DA converter 10DAC(A) via the front-stage circuit 10FNT, and based on the test bit string from the AD converter 10AD( Figure 1 ) and the test bit string. Then, the processor 10P registers the correction data related to the thermometer type DA converter M_DAC in the table THM_T and the correction data related to the weighted binary type DA converter S_DAC in the table BW_T. Figure 9 In the table THM_T and BW_T of the bit string correction circuit 10BCT shown in FIG. Figure 7 The table shown similarly registers test bit strings and correction amounts.

[0175] The upper bit string U_Input is divided into an upper input bit string Inp_U for the thermometer type DA converter M_DAC constituting the DA converter 10DAC(A) and a lower input bit string Inp_L for the weighted binary type DA converter S_DAC constituting the DA converter 10DAC(A).

[0176] The table THM_T is searched using the divided upper input bit string Inp_U, and the table THM_T is searched using the divided lower input bit string Inp_L. The correction amount found by searching in each table is added by an adder ADD3 and supplied to an adder ADD4.

[0177] Figure 10 This is a diagram for explaining the correction table according to the second embodiment. Figure 10 and Figure 8 The difference is that the upper bit string U_Input to be input to the DA converter 10DAC(A) as the correction object is used to search the tables THM_T and BW_T. In addition, the correction amount found by the search is added by the adder ADD3 and then output to Figure 9 Adder ADD4, which is also consistent with Figure 8 different.

[0178] like Figure 9 As shown, adder ADD4 adds the lower-order bit string L_Input and the correction amount output from bit string correction circuit 10BCT, thereby inputting the corrected lower-order bit string into DA converter 10DAC(A) and into DA converter 10DAC(B). As a result, similar to Embodiment 1, the number of test bit strings can be reduced, the frequency of calibration can be increased, and significant fluctuations in accuracy due to changes in ambient temperature, etc., can be suppressed. Furthermore, since the number of test bit strings is reduced, the size of bit string correction circuit 10BCT can be suppressed.

[0179] In addition, Figure 9 In FIG. 1 , the DA converter 10DAC(B) is also composed of a segmented DA converter. However, the DA converter 10DAC(B) may not be a segmented DA converter.

[0180] (Implementation 3)

[0181] In the third embodiment, changing Figure 1 The input path of the AD converter 10AD is shown in FIG. Figure 1In the embodiment, the output of the amplifier circuit AMP is supplied to the AD converter 10AD via the attenuator. Thus, the analog value that becomes a high voltage after passing through the amplifier circuit 1403 is attenuated by the attenuator 1100 and supplied to the AD converter 1406, which can prevent the AD converter 1406 from being damaged by the high voltage.

[0182] In the third embodiment, during the calibration period CAL, a correction value is generated based on the test bit string by integrating the input-output characteristics of the DA converter DAC(A) and the input-output characteristics of the amplifier circuit AMP, and the generated correction value is registered as a table in the bit string correction circuit 10BCT.

[0183] Thus, the bitstream correction circuit 10BCT corrects the bitstream input to the DA converter DAC(A) based on a correction amount that takes into account the input / output characteristics of both the DA converter DAC(A) and the amplifier circuit AMP. As a result, the accuracy of the analog value output from the amplifier circuit AMP can be improved. Of course, when two DA converters 10DAC(A) and 10DAC(B) are used, as in Embodiment 2, the input / output characteristics of the amplifier circuit AMP can also be considered in the same manner.

[0184] (Implementation 4)

[0185] In the fourth embodiment, a charged particle beam device will be described as an example of a device including a DA converter.

[0186] Figure 11 This is a schematic diagram showing the configuration of a charged particle beam device according to Embodiment 4. In Embodiment 4, an electron microscope using an electron beam is used as an example. However, the present invention is not limited thereto and may also be an ion microscope using an ion beam.

[0187] exist Figure 11 In FIG. 1 , 1100 denotes a charged particle beam device. The charged particle beam device 1100 generally irradiates a sample 1117 with an electron beam (transient particle beam) B1 emitted from an electron gun (charged particle gun) 1106 and detects the amount of electrons (specifically, secondary electrons and reflected electrons) B2 emitted from the sample 1117 using a detector 1114 .

[0188] Figure 11The charged particle beam device 1100 shown includes a main body 1101, a control unit 1119, a plurality of power supply circuits 1103a, 1103b, 1103c, and 1103d, and an image processing unit 1118. The main body 1101 includes a housing 1104 and a sample chamber 1105. The housing 1104 houses an electron gun (charged particle gun) 1106, a focusing lens 1110, a reflector 1111, a deflector 1112, an objective lens 1113, a detector 1114, and a boosting electrode 1115. The electron gun 1106 includes an electron source (charged particle source) 1107, an extraction electrode 1108, and an accelerating electrode 1109. The sample chamber 1105 houses a stage 1116 on which a sample 1117 is placed.

[0189] The housing 1104 is made of metal and is connected to a grounded power supply Vs. The power supply circuit 1103a generates a negative acceleration voltage V0 and supplies it to the electron source 1107. The power supply circuit 1103b generates a positive extraction voltage based on the voltage (V0) of the electron source 1107 and supplies it to the extraction electrode 1108. The electron source 1107 emits an electron beam (charged particle beam) B1 in response to this extraction voltage. The accelerating electrode 1109 is connected to the grounded power supply Vs. Consequently, a positive acceleration voltage V0 is applied to the accelerating electrode 1109, based on the electron source 1107. The electron beam B1 emitted from the electron source 1107 is accelerated by this acceleration voltage V0.

[0190] The condenser lens 1110 converges the electron beam B1 emitted from the electron gun 1106. The objective lens 1113 converges the electron beam B1 so that it forms a small spot on the sample 1117. At this time, the power supply circuit 1103d generates a positive boost voltage Vb and supplies it to the boost electrode 1115 located near the condenser lens 1110. Consequently, the electron beam B1, which has been accelerated by the acceleration voltage V0, is further accelerated by the boost voltage Vb. This allows for even higher resolution of the electron beam B1.

[0191] The deflector 1112 is a magnetic field or electrostatic deflector. It deflects the electron beam B1 focused by the objective lens 1113, thereby scanning the electron beam B1 (i.e., a small spot) irradiated onto the sample 1117. The power supply circuit 1103c generates a negative deceleration voltage Vr and supplies it to the stage 1116. Consequently, the electron beam B1 passing through the objective lens 1113 is decelerated by the deceleration voltage Vr. This reduces damage to the sample 1117.

[0192] The electron beam B1 is given an energy of, for example, several tens of kV by the accelerating voltage V0 and the boosting voltage Vb. The decelerating voltage Vr reduces the energy of the electron beam B1 to, for example, less than 1 kV. Thus, the energy of the electron beam B1 is appropriately determined by the power supply circuits 1103a to 1103d. However, in some cases, the power supply circuit 1103d and the boosting electrode 1115 are not provided.

[0193] In response to irradiation with electron beam B1, sample 1117 emits electrons (specifically, secondary electrons and reflected electrons) B2. These electrons B2 are accelerated toward electron source 1107 by deceleration voltage Vr and boost voltage Vb, colliding with reflector 1111. Reflector 1111 then emits secondary electrons. Detector 1114 detects the amount of these secondary electrons emitted.

[0194] The control unit 1119 is composed of, for example, a wiring substrate (control substrate) on which various ICs (Integrated Circuits) including processors are installed. The control unit 1119 controls the voltage value of each power supply circuit 1103a to 1103d. In addition, the control unit 1119 controls the deflector 1112, the objective lens 1113, etc. Furthermore, the control unit 1119 processes the output signal from the detector 1114 using a predetermined signal processing circuit. At this time, the control unit 1119 produces raw data for producing a secondary electron image of the scanning area by synchronizing the control signal for the deflector 1112 with the output signal from the detector 1114. In addition, the control unit 1119 does not necessarily need to be installed entirely on one substrate. In addition, the control unit 1119 may also include components included in a computer, such as a volatile memory and a non-volatile memory.

[0195] The image processing unit 1118 is comprised of, for example, a computer such as a personal computer (PC) comprised of various integrated circuits including a processor. The image processing unit 1118 receives raw data of the secondary electron image from the control unit 1119 and creates a secondary electron image based on this raw data. Furthermore, the image processing unit 1118 displays the generated secondary electron image on a display, etc. A secondary electron image is an image in which the brightness at each position within the scanning area varies depending on the amount of secondary electrons emitted.

[0196] In the charged particle beam device 1100 according to Embodiment 4, the control unit 1119 includes the pre-stage circuit 10FNT, the main circuit 10BDY, and the A / D converter 10AD described in Embodiments 1 to 3. While the main circuit 10BDY described in Embodiment 2 is used to control the deflector 1112, this is not limiting. A / D converters can be used to control various components within the charged particle beam device 1100. The A / D converters used may also be those described in Embodiments 1 or 3.

[0197] exist Figure 11 In FIG. 1 , 1120 represents a DA conversion circuit. The DA conversion circuit 1120 has Figure 9 The front stage circuit 10FNT, the main body circuit 10BDY, and the amplifier circuit AMP (equivalent to Figure 1 The deflection signal Scn is input as an input bit string to the DA converter circuit 1120. The DA converter circuit 1120 converts the deflection signal Scn into an analog value, which is then amplified by the amplifier circuit. The amplified analog value deflection signal Scn is applied to the deflector 1112. The DA converter circuit 1120 may also include an AD converter 10AD, a processor 10P, and the like for calibration. Figure 1 In this case, the processor 10P may also serve as a processor included in the control device 1119.

[0198] As the deflection signal Scn increases (decreases) linearly over time, the analog value applied to the deflector 1112 also increases (decreases) linearly. Consequently, the magnetic field or electric field generated by the deflector 1112 also changes, causing the electron beam B1 to move on the sample 1117.

[0199] When the linearity of the DA converter fluctuates due to, for example, changes in ambient temperature, the magnetic or electric field generated by deflector 1112 also fluctuates. As a result, the distance electron beam B1 travels across sample 1117 changes, resulting in an elongation or contraction of the generated secondary electron image. This elongation or contraction, which depends on changes in ambient temperature, becomes particularly pronounced when the observation range is expanded at low resolution.

[0200] As described above, calibration generates correction values ​​for the DA converter circuit, including the amplifier circuit. This corrects the bitstream input to the DA converter circuit, improving linearity. Furthermore, according to embodiments, the calibration period (CAL) can be shortened. Therefore, even when calibration frequency is increased to account for fluctuations in ambient temperature, the amount of time the charged particle beam device 1100 observes the sample can be reduced. Of course, calibration can be performed multiple times, rather than generating all correction values ​​at once.

[0201] exist Figure 11 In the figure, only one pair of deflectors 1112 is shown because the housing 1104 is viewed from the side. However, two pairs of deflectors 1112 are provided in the housing 1104 to move the electron beam B1 in the X and Y directions (two approximately orthogonal directions) on the specimen 1117. The DA converter circuit 1120 provides analog signals to the pair of deflectors 1112 based on the deflection signal Scn. Therefore, the control unit 1119 is provided with two pairs of DA converter circuits 1119 corresponding to the two pairs of deflectors. In this case, by performing calibration tests on both pairs of DA converter circuits simultaneously, it is possible to prevent the test time from being prolonged. Furthermore, the characteristics of the two pairs of DA converter circuits are not necessarily consistent, making it difficult to share calibration data between the two pairs of DA converter circuits.

[0202] In the fourth embodiment, the charged particle beam device is described as an example of a device including a DA converter, but the device 1 is not limited thereto.

[0203] In the first and second embodiments, the example using two tables THM_T and BW_T as the bit string correction circuit 10BCT is shown, but the present invention is not limited to this. For example, the bit string correction circuit 10BCT may also include one table (for convenience, it is set as U_TB). Figure 9 as well as Figure 10 For example, the bit string correction circuit 10BCT includes a table that is searched using the upper bit string U_Input. During the calibration period CAL, multiple test bit strings corresponding to all codes of the upper bit string U_Input are provided to the DA converter 10DAC(A). That is, using the number of bits N (=16 bits) of the upper bit string U_Input as an index, 2^ N During calibration period CAL, processor 10P sequentially supplies the test bit strings to DA converter 10DAC(A). Processor 10P compares the test bit strings with the test result bits from AD converter 10AD, generating correction values ​​corresponding to the test bit strings. Processor 10P registers the generated correction values ​​in table U_TB. This creates table U_TB, which consists of the upper-order bit strings U_Input and the correction values ​​corresponding to the test bit strings.

[0204] In practice, when using DA converter 10DAC(A), the upper bit string U_Input is converted into an analog value by DA converter 10DAC(A) and supplied to bit string correction circuit 10BCT. The upper bit string U_Input supplied to bit string correction circuit 10BCT is searched in table U_TB and converted into a correction value. The correction value is then applied to the lower bit string L_Input, converted into an analog value by DA converter 10DAC(B), and applied to the analog value from DA converter 10DAC(A).

[0205] Thus, by constructing the bit string correction circuit 10BCT, during the calibration period CAL, according to 2^ N Test bit strings, generate 2^ N Even without considering the configuration of the DA converter 10DAC(A), the input bit string of the DA converter 10DAC(B) can be corrected by taking into account the input-output characteristics of the DA converter 10DAC(A).

[0206] Figure 13 It means for Figure 9 The second embodiment shown in FIG. 1 is a diagram of a modified example of a table described so far. Hereinafter, this modified example will be referred to as a modified example of the second embodiment. Figure 13 In the structure of Figure 8 In the first embodiment, the bit string correction circuit 10BCT mainly uses Figure 8 The adder ADD2 adds the processor output bit string 10BTP and outputs it. On the other hand, in embodiment 2, as Figure 9 As shown, the bit string correction circuit 10BCT does not perform such addition. This is because the adder ADD4 performs a similar function. The description of the second embodiment can also be applied to this modification.

[0207] In Embodiments 1 to 4, examples were described in which, in a segmented DA converter, the main DA converter M_DAC, which converts the upper input bit string Inp_U, is composed of a thermometer-type DA converter, and the sub DA converter S_DAC, which converts the lower input bit string Inp_L, is composed of a weighted binary DA converter. However, this is not limiting. Specifically, the main DA converter M_DAC, which converts the upper input bit string Inp_U, can be composed of a weighted binary DA converter, and the sub DA converter S_DAC, which converts the lower input bit string Inp_L, can be composed of a thermometer-type DA converter.

[0208] Furthermore, from the perspective of binary format, byte order, or communication encoding, the bit string generated by the processor, the bit string output by the processor, the bit string input or output by the preceding circuit, the bit string input to the main circuit, the bit string input to the DA converter, and the bit string within the DA converter may be the same or different. For example, the bit string may be different (from the perspective of binary format, byte order, or communication encoding) when the processor generates a DA conversion target value, when the processor 10P outputs the DA conversion target value as the processor output bit string 10BTP, when the DA conversion target value corrected by the preceding circuit is output, and when the corrected DA conversion target value is input to the main circuit 10BDY or the DA converter 10DAC(A).

[0209] As mentioned above, the invention completed by the present inventors has been specifically described based on the embodiments. However, the present invention is not limited to the above-mentioned embodiments, and various modifications can be made without departing from the scope of the invention.

[0210] The following contents have been described above in this specification.

[0211] A device comprising at least:

[0212] A processor that outputs a DA conversion object value;

[0213] a front-stage circuit that receives the DA conversion target value from the processor, corrects it according to the correction data, and then outputs it;

[0214] a main circuit including one or more DA converter elements to be corrected, and performing DA conversion on the corrected DA conversion target value; and

[0215] AD converter,

[0216] The DA converter element to be corrected is a hybrid DA converter element that outputs an analog value from an output terminal, the analog value being the sum of an analog value output by a first circuit segment responsible for upper levels and an analog value output by a second circuit segment responsible for lower levels.

[0217] As a calibration test for creating or updating the calibration data, the processor performs the following processing:

[0218] (A) Obtain a plurality of test pairs, each of which is a pair of test input values ​​and test result values ​​having the following characteristics:

[0219] (A1) the test input value is a value input to the main circuit as the DA conversion target value with or without correction,

[0220] (A2) the test result value is a value obtained by AD-converting, by the AD converter, an analog value output by inputting the test input value to the main body circuit; and

[0221] (B) updating the calibration data based on the plurality of test pairs in (A), wherein:

[0222] the number of said test pairs obtained during said calibration test is less than 2 to the power of N,

[0223] N is the number of bits representing the resolution of the calibration target DA converter element.

[0224] In addition, it is described that the device may also be as follows.

[0225] The updating of the calibration data or the generation of the test input value in (B) is performed based on the following relationship regarding the bit string inputted via the input terminal of the calibration target DA converter element, that is, the input terminal bit string:

[0226] The relationship between the bit groups 0 and 1 included in the input end bit string and the first circuit segment and the second circuit segment.

[0227] In addition, it is described that the device may also be as follows.

[0228] The DA converter element to be corrected has a dividing circuit that outputs a K-bit internal upper bit string and an M-bit internal lower bit string based on an input value from an input terminal and a binary form assumed to be input to the element.

[0229] The internal high-order bit string is input to the first circuit segment,

[0230] The internal lower bit string is input to the second circuit segment,

[0231] The calibration test includes: a first-type test for mastering the DA conversion characteristics of the first-type circuit segment; and a second-type test for mastering the DA conversion characteristics of the second-type circuit segment.

[0232] The first test input value used in the first test is adjusted so that the internal lower bit string becomes the second fixed bit string after passing through the division circuit.

[0233] The second-type test input value used in the second-type test is a value adjusted so that the internal high-order bit string becomes the first fixed bit string after passing through the division circuit.

[0234] In addition, it is described that the device may also be as follows.

[0235] The calibration test further includes an offset measurement test for outputting an analog value that is independent of the value of the internal upper bit string and the value of the internal lower bit string.

[0236] The test input value used in the offset measurement test is a value adjusted so that the internal lower bit string becomes the second fixed bit string and the internal upper bit string becomes the first fixed bit string after passing through the division circuit.

[0237] In addition, it is described that the device may also be as follows.

[0238] The calibration test does not include a first reduced object test using a first reduced object test input value,

[0239] The first reduced test input value is adjusted to a value having the following characteristics after passing through the dividing circuit:

[0240] The internal high-order bit string is a value other than the first fixed bit string, and

[0241] The internal lower-order bit string is a value other than the second fixed bit string.

[0242] In addition, it is described that the device may also be as follows.

[0243] The calibration test includes a first reduced object test using a first reduced object test input value,

[0244] The first reduced test input value is adjusted to a value having the following characteristics after passing through the dividing circuit:

[0245] The internal high-order bit string is a value other than the first fixed bit string, and

[0246] The internal lower bit string is a value other than the second fixed bit string,

[0247] The number of the test pairs used in the first reduced object test is 2 to the power of N - (2 to the power of K + 2 to the power of M + 1).

[0248] In addition, it is described that the device may also be as follows.

[0249] The DA converter element to be corrected has a dividing circuit that outputs a K-bit internal upper bit string and an M-bit internal lower bit string based on an input value from an input terminal and a binary form assumed to be input to the element.

[0250] The internal high-order bit string is input to the first circuit segment,

[0251] The internal lower bit string is input to the second circuit segment,

[0252] The first circuit segment includes a plurality of first circuits and a selector circuit.

[0253] The selector circuit is a circuit that selects one of the first circuits according to the internal high-order bit string, outputs an activation signal to the selected first circuit, and outputs a deactivation signal to the unselected first circuits.

[0254] Each of the first circuits includes a circuit element for outputting a weight of the internal high-order bit string and an analog value corresponding to the activation signal or the inactivation signal.

[0255] The second circuit segment includes a second circuit corresponding to each bit of the internal lower bit string, and analog values ​​output from each second circuit are added together to form an output value of the segment.

[0256] The first circuit includes a circuit element for outputting a weight of the bit and an analog value corresponding to activation / inactivation indicated by the bit.

[0257] In addition, it is described that the device may also be as follows.

[0258] The updating of the calibration data or the generation of the test input value in (B) is performed based on the following relationship regarding the bit string inputted via the input terminal of the calibration DA converter element, ie, the input terminal bit string:

[0259] The relationship between the 0 / 1 of the bit group included in the input end bit string and the activation / inactivation of multiple first circuits and multiple second circuits.

[0260] In addition, it is described that the device may also be as follows.

[0261] The number of the test pairs obtained during the calibration test is greater than the sum of the number of the first circuit type and the number of the second circuit type.

[0262] In addition, it is described that the device may also be as follows.

[0263] The first circuit segment is a thermometer type circuit segment,

[0264] The second circuit segment is a binary or ladder type circuit segment.

[0265] In addition, it is described that the device may also be as follows.

[0266] The preceding circuit stores, as the correction data, a first table for managing correction amounts from the first type of circuit segments and a second table for managing correction amounts from the second type of circuit segments.

[0267] In addition, it is described that the device may also be as follows.

[0268] The main circuit is a circuit that performs N+1-bit or more DA conversion using, in addition to the calibration target DA converter element responsible for the upper level, a sub-DA converter element responsible for the lower level.

[0269] The front-stage circuit has:

[0270] a dividing circuit or dividing wiring that receives the DA conversion target value, divides it into a higher-order DA conversion target value and a lower-order DA conversion target value, and outputs the resultant value;

[0271] a correction circuit that outputs a correction amount obtained from the upper-order DA conversion target value and the correction data; and

[0272] an adding circuit for adding the correction amount to the lower-order DA conversion target value and outputting the corrected lower-order DA conversion target value;

[0273] The correction target DA converter element takes the upper-level DA conversion target value as a conversion target,

[0274] The additional DA converter element uses the corrected lower-level DA conversion target value as a conversion target,

[0275] The main circuit includes a weighted addition circuit that performs weighted addition on the analog value output from the correction target DA converter element and the analog value output from the sub-DA converter element to output an analog value.

[0276] In addition, it is described that the device may also be as follows.

[0277] The main body circuit has a wiring that outputs the analog value output by the weighted addition circuit as the main body output analog value.

[0278] In addition, it is described that the device may also be as follows.

[0279] The main circuit has:

[0280] an amplifier circuit that amplifies the analog value output by the weighted addition circuit; and

[0281] A wiring that outputs the analog value amplified by the amplifier circuit as the main body output analog value.

[0282] In addition, it is described that the device may also be as follows.

[0283] The front-stage circuit includes:

[0284] a correction circuit that receives the processor output bit string and outputs a correction amount bit string based on the correction data; and

[0285] An adding circuit adds the correction amount bit string and the processor output bit string to output the main body input bit string.

[0286] In addition, it is described that the device may also be as follows.

[0287] The front-stage circuit includes a correction circuit that receives the processor output bit string and outputs the main body input bit string according to the correction data.

[0288] In addition, it is described that the device may also be as follows.

[0289] A charged particle beam device comprising:

[0290] a charged particle source that produces a charged particle beam;

[0291] a deflector that deflects the charged particle beam; and

[0292] The device acts as a controller, which controls the deflector.

[0293] In addition, the following contents are described in this specification.

[0294] A device comprising at least:

[0295] a main body circuit including one or more DA converter elements for converting a main body input bit string, which is a received bit string, into a main body output analog value, which is an analog value, and outputting the analog value;

[0296] a processor, whose output is a processor output bit string;

[0297] a front-stage circuit that receives the processor output bit string and outputs the main body input bit string; and

[0298] AD converter,

[0299] The front-stage circuit corrects the processor output bit string based on the correction data and outputs the main body input bit string.

[0300] The main body circuit includes an amplifier circuit that amplifies the analog value output by the DA converter element and outputs the amplified analog value as the main body output analog value.

[0301] The processor performs the following processing:

[0302] (A) Obtain multiple pairs of test bit strings and test result bit strings having the following characteristics:

[0303] (A1) the test bit string is the processor output bit string or the subject input bit string used for calibration testing,

[0304] (A2) the test result bit string is obtained by converting the analog value output by the main body using the AD converter;

[0305] (B) Based on the plurality of pairs in (A), the correction data is updated.

[0306] Explanation of symbols

[0307] 1 device;

[0308] 10AD AD converter;

[0309] 10ADDW weighted addition circuit;

[0310] 10BCT bit string correction circuit;

[0311] 10BDY main circuit;

[0312] 10DAC(A), 10DAC(B)DA converters;

[0313] 10FNT pre-stage circuit;

[0314] 10P processor;

[0315] 10SPT(A), 10SPT(B) split circuit;

[0316] 1100 charged particle beam device;

[0317] Inp_L lower input bit string;

[0318] Inp_U upper input bit string;

[0319] L_Input lower bit string;

[0320] M_DAC main DA converter;

[0321] S_DAC auxiliary DA converter;

[0322] U_Input upper bit string.

Claims

1. A device comprising at least: A processor that outputs a DA conversion object value; a front-stage circuit that receives the DA conversion target value from the processor, corrects it according to the correction data, and then outputs it; a main circuit including one or more DA converter elements to be corrected, and performing DA conversion on the corrected DA conversion target value; and AD converter, It is characterized by: The DA converter element to be corrected is a hybrid DA converter element that outputs an analog value from an output terminal, the analog value being the sum of an analog value output by a first circuit segment responsible for upper levels and an analog value output by a second circuit segment responsible for lower levels. As a calibration test for creating or updating the calibration data, the processor performs the following processing: Process A, obtain multiple test pairs, wherein the test pairs are pairs of test input values ​​and test result values ​​having the following features A1 and A2, Feature A1: The test input value is a value input to the main circuit as the DA conversion target value with or without correction, Feature A2: The test result value is a value obtained by AD-converting, by the AD converter, an analog value output by inputting the test input value into the main circuit; as well as Process B, based on the plurality of test pairs in process A, updates the calibration data, in, the number of said test pairs obtained during said calibration test is less than 2 to the power of N, N is the number of bits representing the resolution of the calibration target DA converter element.

2. The device according to claim 1, characterized in that The updating of the calibration data or the generation of the test input value in the process B is performed based on the following relationship regarding the bit string inputted through the input terminal of the calibration target DA converter element, ie, the input terminal bit string: The relationship between the bit groups 0 and 1 included in the input end bit string and the first circuit segment and the second circuit segment.

3. The device according to claim 1, characterized in that The DA converter element to be corrected has a dividing circuit that outputs a K-bit internal upper bit string and an M-bit internal lower bit string based on an input value from an input terminal and a binary form assumed to be input to the element. The internal high-order bit string is input to the first circuit segment, The internal lower bit string is input to the second circuit segment, The calibration test includes: a first-type test for mastering the DA conversion characteristics of the first-type circuit segment; a second-type test for mastering the DA conversion characteristics of the second-type circuit segment. The first test input value used in the first test is adjusted so that the internal lower bit string becomes the second fixed bit string after passing through the division circuit. The second-type test input value used in the second-type test is a value adjusted so that the internal high-order bit string becomes the first fixed bit string after passing through the division circuit.

4. The device according to claim 3, characterized in that The calibration test further includes an offset measurement test for outputting an analog value that is independent of the value of the internal upper bit string and the value of the internal lower bit string. The test input value used in the offset measurement test is a value adjusted so that the internal lower bit string becomes the second fixed bit string and the internal upper bit string becomes the first fixed bit string after passing through the division circuit.

5. The device according to claim 4, characterized in that The calibration test does not include a first reduced object test using a first reduced object test input value, The first reduced test input value is adjusted to a value having the following characteristics after passing through the dividing circuit: The internal high-order bit string is a value other than the first fixed bit string, and The internal lower-order bit string is a value other than the second fixed bit string.

6. The device according to claim 4, characterized in that The calibration test includes a first reduced object test using a first reduced object test input value, The first reduced test input value is adjusted to a value having the following characteristics after passing through the dividing circuit: The internal high-order bit string is a value other than the first fixed bit string, and The internal lower bit string is a value other than the second fixed bit string, The number of the test pairs used in the first reduced object test is 2 to the power of N - (2 to the power of K + 2 to the power of M + 1).

7. The device according to claim 1, characterized in that The DA converter element to be corrected has a dividing circuit that outputs a K-bit internal upper bit string and an M-bit internal lower bit string based on an input value from an input terminal and a binary form assumed to be input to the element. The internal high-order bit string is input to the first circuit segment, The internal lower bit string is input to the second circuit segment, The first circuit segment includes a plurality of first circuits and a selector circuit. The selector circuit is a circuit that selects one of the first circuits according to the internal high-order bit string, outputs an activation signal to the selected first circuit, and outputs an inactivation signal to the unselected first circuits. Each of the first circuits includes a circuit element for outputting a weight of the internal high-order bit string and an analog value corresponding to the activation signal or the inactivation signal. The second circuit segment includes a second circuit corresponding to each bit of the internal lower bit string, and analog values ​​output from each second circuit are added together to form an output value of the segment. The first circuit includes a circuit element for outputting a weight of the bit and an analog value corresponding to activation / inactivation indicated by the bit.

8. The device according to claim 7, characterized in that The updating of the calibration data or the generation of the test input value in the process B is performed based on the following relationship regarding the bit string inputted through the input terminal of the calibration DA converter element, ie, the input terminal bit string: The relationship between the 0 / 1 of the bit group included in the input end bit string and the activation / inactivation of multiple first circuits and multiple second circuits.

9. The device according to claim 8, characterized in that The number of the test pairs obtained during the calibration test is greater than the sum of the number of the first circuit type and the number of the second circuit type.

10. The device according to claim 1, characterized in that The first circuit segment is a thermometer type circuit segment, The second circuit segment is a binary or ladder type circuit segment.

11. The device according to claim 1, characterized in that The preceding circuit stores, as the correction data, a first table for managing correction amounts from the first type of circuit segments and a second table for managing correction amounts from the second type of circuit segments.

12. The device according to claim 1, characterized in that The main circuit is a circuit that performs N+1-bit or more DA conversion using, in addition to the calibration target DA converter element responsible for the upper level, a sub-DA converter element responsible for the lower level. The front-stage circuit has: a dividing circuit or dividing wiring that receives the DA conversion target value, divides it into a higher-order DA conversion target value and a lower-order DA conversion target value, and outputs the resultant value; a correction circuit that outputs a correction amount obtained from the upper-level DA conversion target value and the correction data; as well as an adding circuit for adding the correction amount to the lower-order DA conversion target value and outputting the corrected lower-order DA conversion target value; The correction target DA converter element takes the upper-level DA conversion target value as a conversion target, The additional DA converter element uses the corrected lower-level DA conversion target value as a conversion target, The main circuit includes a weighted addition circuit that performs weighted addition on the analog value output from the correction target DA converter element and the analog value output from the sub-DA converter element to output an analog value.

13. The device according to claim 9, characterized in that The main body circuit has a wiring that outputs the analog value output by the weighted addition circuit as the main body output analog value.

14. The device according to claim 9, characterized in that The main circuit has: an amplifier circuit that amplifies the analog value output by the weighted addition circuit; and A wiring that outputs the analog value amplified by the amplifier circuit as the main body output analog value.

15. The device according to claim 1, characterized in that The front-stage circuit includes: a correction circuit that receives the processor output bit string and outputs a correction amount bit string based on the correction data; and An adding circuit adds the correction amount bit string and the processor output bit string to output the main body input bit string.

16. The device according to claim 1, characterized in that The front-stage circuit includes a correction circuit that receives the processor output bit string and outputs the main body input bit string according to the correction data.

17. A charged particle beam device, characterized in that Include: a charged particle source that produces a charged particle beam; a deflector that deflects the charged particle beam; and The device according to claims 1 to 16 is used as a controller for controlling the deflector.

18. A device comprising at least: a main body circuit including one or more DA converter elements for converting a main body input bit string, which is a received bit string, into a main body output analog value, which is an analog value, and outputting the analog value; a processor, whose output is a processor output bit string; a front-stage circuit that receives the processor output bit string and outputs the main body input bit string; and AD converter, It is characterized by: The front-stage circuit corrects the processor output bit string based on the correction data and outputs the main body input bit string. The main body circuit includes an amplifier circuit that amplifies the analog value output by the DA converter element and outputs the amplified analog value as the main body output analog value. The processor performs the following processing: Process A, obtain multiple pairs of test bit strings and test result bit strings with the following features A1 and A2, Feature A1: The test bit string is the processor output bit string or the subject input bit string used for calibration testing, Feature A2: The test result bit string is obtained by converting the main body output analog value using the AD converter; and Process B updates the calibration data based on the multiple pairs in process A.

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