General simulation system and method suitable for data processing FPGA

Abstract

The application discloses a general simulation system suitable for a data processing FPGA, and comprises an SDRAM simulation module, a storage board simulation module, a transmitter front-end simulation module, a payload input simulation module and a clock / reset simulation module.The SDRAM simulation module is used for buffering payload data received by a data processing system; the storage board simulation module is used for storing data; the transmitter front-end simulation module is used for receiving and storing various types of payload data after being demodulated and unpacked; the payload input simulation module is used for providing payload data to the data processing system; and the clock / reset simulation module is used for providing a clock and a reset signal used for working of the system.The simulation system is suitable for simulation verification of a data processing FPGA of a common data transmission terminal in the field of spaceflight, can provide different types of payload interface simulation according to model task requirements, and can store classified and compared payload data after being multiplexed and output, so as to verify correctness of the data processing system.

Description

General-purpose simulation system and method for data processing FPGA Technical Field

[0001] This invention relates to the field of aerospace technology, and in particular to a general simulation system and method suitable for data processing FPGAs. Background Technology

[0002] Data processing FPGAs are widely used in data transmission terminal equipment. As a general-purpose device for on-board data processing, the payload data received by the data transmission terminal and the framing format during information transmission are highly variable, and the payload data may travel a long data transmission path after entering the data processing FPGA. How to quickly input the payload data type required by the task into the simulation system and how to quickly locate the fault point in fault mode are worthy of research. In summary, the simulation verification system proposed by existing technology cannot verify the correctness of the data processing system by simulating various payload data inputs using software on the simulation platform, setting data monitoring points on the data path of the data processing FPGA, and classifying and storing the final top-level data. Summary of the Invention

[0003] The purpose of this invention is to provide a general simulation system and method suitable for data processing FPGAs.

[0004] This invention provides a general simulation system suitable for data processing FPGAs, characterized in that it includes:

[0005] The simulated load input module is used to provide an interface and corresponding load data to the data processing FPGA;

[0006] The transmitter-simulated front-end module is used to receive the payload data output by the data processing FPGA, descramble the payload data using a preset descrambling algorithm, and adjust the descrambling method according to the target task.

[0007] A simulated clock / reset module is used to provide clock and reset signals to the data processing FPGA.

[0008] The simulated storage board module is used to receive the payload data output by the SDRAM module, receive or descramble the data from the data processing FPGA, record and store the payload data in recording mode to complete the write operation to the storage board, and read the recorded and stored payload data in playback mode to complete the read operation to the storage board.

[0009] An SDRAM-like module is used to output the payload data to the data processing FPGA according to a preset timing and format.

[0010] A simulated storage control FPGA module is used to send remote sensing commands for storage control to the data processing FPGA;

[0011] During simulation, different types of load interfaces are provided for simulation, and the output multiplexed load data is classified, stored, and compared with the original data to verify the correctness of the data processing FPGA system.

[0012] Preferably, the simulated load input module is further configured to control and send different frame lengths of the load data corresponding to different framing methods in different simulation tasks.

[0013] Preferably, the simulation steps further include:

[0014] Simulate various forms of load data input, adapt to different load data input formats, and construct load data using a state machine;

[0015] Configure the data throughput rate of the data processing FPGA, and adjust the interval between the load data input frames and the jump conditions under different states to control the input rate of the load data. Modify the load data frame format by modifying the state definition.

[0016] A frame counting area is added to the load input frame to mark the input source of the load data, and the continuity of the load data output by the data processing FPGA is checked to confirm the integrity of the data transmission.

[0017] Preferably, the load data input by the simulated load input module includes a virtual channel identifier area and a cyclic redundancy check area.

[0018] Preferably, the simulated SDRAM module includes several storage spaces for dividing the interactive data between the payload and the memory board into independent regions, isolating the data flow between these independent regions, and quickly locating the fault point in a fault mode; wherein the several storage spaces include:

[0019] The first storage space is used for writing to SDRAM via the write path to the storage board; the second storage space is used for reading from SDRAM via the write path to the storage board; the third storage space is used for writing to SDRAM via the read path to the storage board; and the fourth storage space is used for reading from SDRAM via the read path to the storage board.

[0020] Preferably, the data sources for the load data include a first radar, a second radar, a third radar, a fourth radar, a self-test frame, platform storage, and micro-vibration detection.

[0021] Preferably, the data frame structure converted from the payload data includes a free area, a frame header area, a preamble area, a virtual channel identifier, a counting area, a cyclic redundancy check code, and a frame tail area.

[0022] Preferably, the simulated transmitter front-end module is also used to construct a descrambling, unpacking, classification, and storage mechanism for scrambled multiplexed data, to deslice the combined data, and to compare it with the original payload data input by the simulated payload input module to determine the correctness of data transmission.

[0023] This invention also provides a general simulation method suitable for data processing FPGAs, applied to a general simulation system for data processing FPGAs as described in the embodiments of this invention, comprising:

[0024] The payload data is output to the data processing FPGA according to the preset timing and format.

[0025] The range of different regions of the load data and the effective data of the load data are constructed by the state mechanism;

[0026] The virtual channel identifiers of the payload data are randomly assigned using a randomization method.

[0027] The input stimuli are counted through a counting area, and the output of the data processing FPGA determines whether the data transmission is continuous and correct through the counting area.

[0028] The cyclic redundancy check area of ​​the payload data is constructed according to the preset cyclic redundancy check algorithm;

[0029] After the load data enters the data processing FPGA, a data flow operation is performed, key nodes of the data flow are set as checkpoints, data during transmission is output and saved, thereby detecting the correctness of each intermediate state data and the final data transmission, and quickly locating the fault point according to the location of the checkpoint in fault conditions.

[0030] The remote control commands sent by the simulated storage control FPGA are transmitted to the data processing FPGA;

[0031] The receiving logic in the transmitter front-end module is constructed to descramble and classify the multiplexed and scrambled payload data output from the data processing FPGA and store it in different data files.

[0032] Compared with the prior art, the present invention has the following beneficial effects:

[0033] 1. The general simulation method and system for data processing FPGAs provided by this invention can adapt to different load input formats by simulating various forms of load input using software on a simulation platform. The load data is constructed using a state machine, and the load input rate can be flexibly controlled by adjusting the duration and transition conditions of different states. The load data frame format can be easily modified by modifying the state definition.

[0034] 2. The SDRAM data model provided by this invention internally opens up four regions (write SDRAM via memory board path, read SDRAM via write memory board path, write SDRAM via read memory board path, and read SDRAM via read memory board path), which can independently divide the interactive data between the payload and the memory board into four regions, isolate the data stream, and print it out for easy observation and testing. In fault mode, the fault point can be quickly located.

[0035] 3. The transmitter-simulated front-end module in this invention constructs a descrambling, unpacking, classification, and storage mechanism for scrambled multiplexed data, which facilitates the splitting of the combined data and comparison with the original load data input by the simulated load input module to determine the correctness of data transmission. Attached Figure Description

[0036] Figure 1 is a schematic diagram of the structure of the general simulation system for data processing FPGA provided by the present invention;

[0037] Figure 2 is a state machine flowchart for constructing payload data files provided by the present invention;

[0038] Figure 3 is a data frame structure diagram of the simulated load input module provided by the present invention;

[0039] Figure 4 is a schematic diagram of the data descrambling principle provided by the present invention;

[0040] Figure 5 is a state machine flowchart of the descrambling and unpacking data file storage provided by the present invention. Detailed Implementation

[0041] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0042] This invention aims to provide a general simulation method and system suitable for data processing FPGAs, constructing the load input terminal, remote control command input terminal, and data output descrambling, unpacking, and storage terminal required by the data processing system, and providing a complete peripheral environment to realize closed-loop simulation of the data processing system.

[0043] Specifically, for different load input terminals, a state machine is designed using Verilog language to control the content and interface timing of the load input. At the same time, a data output descrambling, unpacking, classification, and storage mechanism is designed in the simulation system to record the loaded data output by the data processing FPGA in *.dat data file format and compare it with the load source data to ensure the correctness of the simulation system.

[0044] As shown in Figure 1, the general simulation system for data processing FPGAs provided by this invention can include: a simulated SDRAM module, a simulated storage board module, a simulated transmitter front-end module, a simulated payload input module, and a simulated clock / reset module. It can flexibly set the payload input format according to the requirements of the model and task, and provides functions for descrambling, unpacking, and classifying and storing multiplexed data, thus enhancing the portability and versatility of the simulation system. It mainly includes:

[0045] ① The simulated load input module can provide different types of load data to the data processing FPGA according to the task requirements;

[0046] ② The simulated load input module can send data of different frame lengths according to the framing method of load data in different tasks;

[0047] ③ The interval between load input frames can be flexibly adjusted according to the data throughput rate designed for the data processing system in order to adjust the data input rate;

[0048] ④ A frame count can be added to the load input frame to mark the load input source, which facilitates the continuity check of the data output from the data processing FPGA to confirm the integrity of data transmission.

[0049] ⑤ Special data areas such as Cyclic Redundancy Check (CRC) can be added to the input data of the simulation load according to the task requirements.

[0050] in:

[0051] This is a simulated SDRAM module, based on the SDRAM model from 3DPLUS's official website. Modifications were made to this model, adding data printing functionality. Four spaces were created internally for writing to SDRAM via the memory board path, reading from SDRAM via the memory board path, writing to SDRAM via the memory board path, and reading from SDRAM via the memory board path. The data operations in these four spaces can be recorded in a print file. The written and read data can be printed out for easy observation and verification. The SDRAM data bit width and capacity can be adjusted as needed.

[0052] This simulated storage board module receives payload data output from the SDRAM module. Depending on the task requirements, it records and stores data in recording mode, completing the write operation to the storage board; in playback mode, it reads the recorded data, completing the read operation from the storage board. It can descramble data from the FPGA data processing unit or receive it directly.

[0053] This transmitter-simulated preamplifier module receives top-level data output from the data processing FPGA, descrambles the data according to a descrambling algorithm defined by the task requirements, and unpacks and categorizes the data based on the virtual channel identifier (VCID) added to the payload input or framing. It can descramble data output from the data processing FPGA and adjust the descrambling method according to task requirements. The descrambled data can restore the original payload input value, and the payload data can be unpacked, categorized, and stored according to the virtual channel identifier (VCID).

[0054] The simulated load input module is used to input the load data required for simulation into the data processing FPGA.

[0055] The simulated clock / reset module provides clock and reset signals for the data processing FPGA.

[0056] Furthermore, it also includes selecting different scrambling / descrambling methods and different cyclic redundancy check areas according to task requirements.

[0057] In one embodiment, the present invention provides a general simulation method suitable for data processing FPGAs, comprising:

[0058] The payload data is output to the data processing FPGA according to the specified timing and format. Special areas such as idle area, frame header area, preamble area (including start word, auxiliary data, etc.), virtual channel identifier (VCID), counter area, payload area, cyclic redundancy check code (CRC), and frame tail can be added to the payload data; the frame structure can be seen in Figure 3.

[0059] The range of different regions of the load data constructed by the state mechanism and the effective data of the load data are shown in Figure 3. The position of the effective data in the load data frame is shown in Figure 3. For the setting method of the effective data, please refer to step S115.

[0060] The virtual channel identifier of the payload is randomly assigned using a randomization method. The position of the virtual channel identifier in the payload data frame is shown in Figure 3. The setting method of the virtual channel identifier is described in step S113.

[0061] The input stimulus is counted by the counting area. At the output of the data processing FPGA, the continuity of the data transmission is examined by whether the counting area is continuous. The position of the counting area in the load data frame is shown in Figure 3. The setting method of the counting area is described in step S114.

[0062] According to the cyclic redundancy check algorithm defined by the task requirements, a cyclic redundancy check code check area for the payload data is constructed. The position of the cyclic redundancy check code in the payload data frame is shown in Figure 3. The method of setting the cyclic redundancy check code is described in step S117.

[0063] Intermediate data from the SDRAM model is extracted, printed, and saved in a file to facilitate the detection of correct intermediate data transmission and rapid fault location. After the payload data enters the data processing FPGA, it undergoes serial-to-parallel conversion, framing, scrambling, writing to SDRAM, reading from SDRAM, and verification based on cyclic redundancy check (CR) codes. This process is called data flow. Data in the data flow excluding the source and destination points is called intermediate data. Checkpoints can be set at key nodes in the data flow to output and save data during transmission, thereby detecting the correctness of intermediate data and the final data transmission. Furthermore, the location of the checkpoints can be used to quickly locate fault points under fault conditions.

[0064] The remote control commands sent by the storage control FPGA are saved as data files. The required remote control commands are input to the data processing FPGA as needed based on the operating conditions. Furthermore, the content of the remote control commands can be flexibly changed by modifying the data files without altering the sending logic, demonstrating strong portability.

[0065] Construct the receiving logic in the transmitter front-end module to classify and store the multiplexed and scrambled data output from the data processing FPGA into different data files.

[0066] The software portion of this invention is written in Verilog and uses Synopsys' VCS simulation verification tool. Based on this invention, further extensions can be made to establish a simulation system library, which is particularly important for the standardization and generalization of aerospace products.

[0067] The present invention provides a general simulation method applicable to data processing FPGAs, comprising:

[0068] I. The implementation steps of the simulated load input module are as follows:

[0069] S101. As shown in Figure 2, after the data processing FPGA is reset, the simulated load input module is started.

[0070] In this embodiment, different load input formats can be set according to different load input characteristics. One of them is selected below as an example.

[0071] S102. After the simulated load input module is started, the state machine enters the idle state (tlk_idle), adapts the input load data to the idle data "C5BCC5BC" (hexadecimal number) defined in the frame structure, sets the flag signal lsb to a high level "1", and resets the valid data counter, preamble counter, and start word counter to 0.

[0072] S103. After the state machine is in the idle state (tlk_idle) for one clock cycle, it enters the frame header state (tlk_head). At this time, the payload data is set to the hexadecimal number "C5FDC5FD" to match the frame header defined in the payload input data frame.

[0073] S104. After the state machine has been in the frame header state (tlk_head) for one clock cycle, it enters the preamble 1 state (tlk_data1). At this time, the payload data is set to "FAFAFAFA", and the flag signal lsb is set to a low level "0".

[0074] S105. Controlled by the start word counter, the state machine enters the start code 2 state (tlk_data2) after two clock cycles in the start code 1 state (tlk_data1), and at the same time sets the payload data to "FAF3FAF3".

[0075] S106. After the state machine is in the preamble 2 state (tlk_data2) for one clock cycle, it enters the preamble 3 state (tlk_data3) and sets the payload data to "F3F3F3F3".

[0076] S107. Controlled by the start word counter, the state machine enters the start code 4 state (tlk_data4) after two clock cycles in the start code 3 state (tlk_data3), and at the same time sets the payload data to "20202020".

[0077] S108. After the state machine is in the 4th state (tlk_data4) for one clock cycle, it enters the 5th state (tlk_data5) to keep the payload data input value "20202020".

[0078] S109. After the state machine is in the 5th state (tlk_data5) for one clock cycle, it enters the 6th state (tlk_data6) and sets the payload input data to "20012006".

[0079] S110. After the state machine is in state 6 (tlk_data6) for one clock cycle, it enters state 7 (tlk_data7) and sets the payload input data to "02030708".

[0080] S111. After the state machine is in the 7th state (tlk_data7) for one clock cycle, it enters the 8th state (tlk_data8) and sets the payload input data to "0405090A".

[0081] S112. After the state machine is in the preamble 8 state (tlk_data8) for one clock cycle, it enters the preamble 9 state (tlk_data9), setting the payload input data to "A5A5A5A5", and the preamble counter starts to accumulate.

[0082] S113. Controlled by the preamp code counter, the state machine enters the virtual channel identifier setting state (tlk_data10) after 9 clock cycles in the preamp code 9 state (tlk_data9). In this state, the virtual channel identifier (VCID) of the payload is set. In this example, the payload data contains 7 data sources: Radar 1 (SAR1), Radar 2 (SAR2), Radar 3 (SAR3), Radar 4 (SAR4), self-test frame, platform memory, and micro-vibration detection. Seven random numbers are generated, appearing randomly between 0 and 6. The appearance of the 7 data sources is randomly set based on the values ​​of the random numbers, and each data source is assigned a unique virtual channel identifier. For example, the virtual channel identifier of radar 1 is set to 32'h01010101, the virtual channel identifier of radar 2 is set to 32'h12121212, the virtual channel identifier of radar 3 is set to 32'h24242424, the virtual channel identifier of radar 4 is set to 32'h18181818, the virtual channel identifier of the self-test frame is set to 32'h2F2F2F2F, the virtual channel identifier of the platform fixed is set to 32'h2B2B2B2B, and the virtual channel identifier of the micro-vibration is set to 32'h00070707.

[0083] S114. After the state machine has been in the virtual channel identifier setting state (tlk_data10) for one clock cycle, it enters the frame counting state (tlk_data11) for the entire frame of payload data.

[0084] S115. After the state machine has been in the frame counting state (tlk_data11) for one clock cycle, it enters the payload valid data state (tlk_data12). The valid data can be set to 32'h02461357, and the valid data counter starts counting the valid data within the frame.

[0085] S116. Controlled by the valid data counter, the state machine enters the load data cyclic redundancy check state (tlk_crc) after the load valid data state (tlk_data12) lasts for 1259 cycles.

[0086] S117. The length of the check area data is maintained for one clock cycle, and the width is 32 bits, where the high 16 bits and low 16 bits use the same cyclic redundancy code algorithm. The cyclic redundancy code algorithm is a public algorithm and is not within the scope of protection of this patent application. Common cyclic redundancy code algorithms include CRC-5 / EPC, CRC-7 / MMC, CRC-16 / CCITT, etc.

[0087] S118. After the state machine is in the Cyclic Redundancy Check (tlk_crc) state for one clock cycle, it enters the frame tail state (tlk_tail) and sets the payload data to the frame tail defined by the payload frame, "C5FBC5FB" (hexadecimal number).

[0088] S119. After the state machine remains in the frame tail state (tlk_tail) for one clock cycle, it returns to the initial state (tlk_idel) to prepare for the control and transmission of the next payload data frame. This process is repeated to complete the continuous input of payload frames.

[0089] Optionally, the duration of each state and the specific control method of each state can be adaptively adjusted according to task requirements.

[0090] The data descrambling and unpacking method of the transmitter-simulated front-end module of the present invention will be described in more detail below with reference to specific embodiments. Specifically, the method in this embodiment includes the following steps:

[0091] The data output from the data processing FPGA to the transmitter front-end is scrambled multiplexed data. To verify the correctness of the data, it is necessary to descramble the data, classify it according to the virtual channel identifier of the payload, store it in the data file, and then compare it.

[0092] II. The implementation steps for the simulated transmitter front-end module are as follows:

[0093] S201. As shown in Figure 5, seven handles are set up to store the load input data for radar 1, radar 2, radar 3, radar 4, self-test frame, platform solidification, and micro-vibration data, respectively. The unpacked data is prepared to be stored in the mapped data files. (The file formats are: receipt_sar1.dat, receipt_sar2.dat, receipt_sar3.dat, receipt_sar4.dat, receipt_selfcheck.dat, receipt_ptgc.dat, receipt_wzd.dat).

[0094] S202. The data entering the front-end module of the transmitter is serial data. In order to find the frame header "1ACFFC1D" (hexadecimal number) added when the data is framed by the FPGA, the serial data needs to be converted into parallel data.

[0095] S203. In this example, the 4-byte frame header data is not scrambled, while the subsequent 1020 bytes of data are scrambled. Therefore, after finding the frame header, descrambling begins on the subsequent data. The scrambling principle in this example is shown in Figure 4. Descrambling is actually re-scrambling the already scrambled data, so the data is descrambled according to Figure 4. Since the data processing FPGA uses parallel scrambling, a serial descrambling method is used in the simulation environment to verify the correctness of the descrambling. The parallel data is converted into serial data. The descrambling polynomial F(X) = X⁸ + X⁷ + X⁵ + X³ + 1, this sequence repeats every 255 bits, and in each synchronization period, the sequence generator is reinitialized to an "all 1s" state. The block diagram of the scrambling principle is shown in Figure 4. The 1020 bytes of the data frame excluding the frame header are scrambled, which is exactly 32 scrambling sequence cycles. The scrambling and descrambling algorithm used in this embodiment is publicly available and will not be described in detail here.

[0096] S204. To determine the load data type by judging the virtual channel identifier, the descrambled serial data needs to be converted back into parallel data, and the virtual channel identifier needs to be extracted for judgment. When the virtual channel identifier is 32'h01010101, it is determined to be radar 1 data; when the virtual channel identifier is 32'h12121212, it is determined to be radar 2 data; when the virtual channel identifier is 32'h24242424, it is determined to be radar 3 data; when the virtual channel identifier is 32'h18181818, it is determined to be radar 4 data; when the virtual channel identifier is 32'h2F2F2F2F, it is determined to be self-test frame data; when the virtual channel identifier is 32'h2B2B2B2B, it is determined to be platform fixed data; when the virtual channel identifier is 32'h00070707, it is determined to be micro-vibration data.

[0097] S205. Based on the data type determination result, each data is stored in its respective storage state. In this example, radar 1 data is stored in the data file receive_sar1.dat, similarly radar 2 data is stored in the data file receive_sar2.dat, radar 3 data is stored in the data file receive_sar3.dat, radar 4 data is stored in the data file receive_sar4.dat, the self-check frame data is stored in the data file receive_selfcheck.dat, the platform solid-state data is stored in receive_ptgc.dat, and the micro-vibration data is stored in receive_wzd.dat.

[0098] III. The implementation steps for the simulated clock / reset module are as follows:

[0099] S301 provides the data processing FPGA with the main clock main_clk_in and the reset signal OC_rst. The clock frequency can be adjusted according to actual needs, and the polarity and width of the reset signal can also be adjusted.

[0100] IV. The implementation steps for the simulated storage board module are as follows:

[0101] S401. In write mode, the simulated storage board module can record data to the file write_cun.dat. In read mode, it can send the data in the file write_cun.dat back to the data processing FPGA.

[0102] V. The implementation steps for the simulated SDRAM module are as follows:

[0103] S501: This module is used to receive various loads when the FPGA is operating in delay mode, and output the load data to the storage board according to the master control instructions.

[0104] VI. The implementation steps of the simulated storage control FPGA module are as follows:

[0105] The S601 stores the remote control commands sent by the storage control FPGA as data files, and inputs the required remote control commands to the data processing FPGA as needed according to the working conditions.

[0106] Optionally, it also includes: when the data processing FPGA receives other payloads, the simulation system can set different virtual channel identifiers according to different payloads, and the simulated transmitter front-end module can also perform unpacking processing according to different virtual channel identifiers.

[0107] This invention is applicable to FPGA simulation and verification of data processing commonly used in the aerospace field. The simulation system is implemented on a VCS simulator platform. Based on this invention, further extensions can be made to establish a simulation system library, which is particularly important for the standardization and generalization of aerospace products.

[0108] It should be noted that the steps in the general simulation method for data processing FPGA provided by the present invention can be implemented using the corresponding modules, devices, units, etc. in the general simulation system for data processing FPGA. Those skilled in the art can refer to the technical solution of the system to implement the steps of the method. That is, the embodiments in the system can be understood as preferred examples of implementing the method, and will not be elaborated here.

[0109] Those skilled in the art will understand that, in addition to implementing the system and its various devices provided by this invention in the form of purely computer-readable program code, the same functions can be achieved entirely through logical programming of the method steps, making the system and its various devices of this invention function as logic gates, switches, application-specific integrated circuits, programmable logic controllers, and embedded microcontrollers. Therefore, the system and its various devices provided by this invention can be considered as a hardware component, and the devices included therein for implementing various functions can also be considered as structures within the hardware component; alternatively, the devices for implementing various functions can be considered as both software modules implementing the method and structures within the hardware component.

[0110] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A general-purpose simulation system suitable for data processing FPGAs, characterized in that, include: The simulated load input module is used to provide an interface and corresponding load data to the data processing FPGA; The transmitter-simulated front-end module is used to receive the payload data output by the data processing FPGA, descramble the payload data using a preset descrambling algorithm, and adjust the descrambling method according to the target task; the clock / reset module is used to provide clock signals and reset signals to the data processing FPGA. The simulated storage board module is used to receive the payload data output by the simulated SDRAM module, receive or descramble the data of the data processing FPGA, record and store the payload data in recording mode, and complete the write operation to the storage board. In playback mode, the recorded and stored payload data is read to complete the read storage board operation; An SDRAM-like module is used to output the payload data to the data processing FPGA according to a preset timing and format; a storage control FPGA-like module is used to send remote sensing commands for storage control to the data processing FPGA; during simulation, different types of payload interfaces are provided for simulation, and the multiplexed output payload data is classified, stored, and compared with the original data to verify the correctness of the data processing FPGA system; the simulation steps also include: simulating various forms of payload data input, adapting to different payload data input formats, constructing a state machine for the payload data; configuring the data throughput rate of the data processing FPGA, and adjusting the interval and jump conditions between payload data input frames under different states to control the input of the payload data. The rate is modified by changing the state definition to modify the payload data frame format; a frame counting area is added to the payload input frame to mark the input source of the payload data, and the continuity of the payload data output by the data processing FPGA is checked to confirm the integrity of data transmission; the simulated SDRAM module is provided with several storage spaces to divide the interactive data between the payload end and the memory board into independent areas, isolate the data flow between the independent areas, and quickly locate the fault point in fault mode; wherein the several storage spaces include: a first storage space for writing to SDRAM via the memory board path; a second storage space for writing to SDRAM via the memory board path; a third storage space for reading to SDRAM via the memory board path; and a fourth storage space for reading to SDRAM via the memory board path.

2. The general simulation system for data processing FPGAs as described in claim 1, characterized in that, The simulated load input module is also used to control and send different frame lengths of the load data corresponding to different framing methods in different simulation tasks.

3. The general simulation system for data processing FPGAs as described in claim 1, characterized in that, The load data input by the simulated load input module includes a virtual channel identifier area and a cyclic redundancy check area.

4. The general simulation system for data processing FPGAs as described in claim 1, characterized in that, The data sources for the payload data include the first radar, the second radar, the third radar, the fourth radar, self-test frames, platform storage, and micro-vibration detection.

5. The general simulation system for data processing FPGAs as described in claim 1, characterized in that, The data frame structure converted from the payload data includes a free area, a frame header area, a preamble area, a virtual channel identifier, a counting area, a cyclic redundancy check code, and a frame tail area.

6. The general simulation system for data processing FPGAs as described in claim 1, characterized in that, The simulated transmitter front-end module is also used to construct a descrambling, unpacking, classification, and storage mechanism for scrambled multiplexed data, to deslice the combined data, and to compare it with the original payload data input by the simulated payload input module to determine the correctness of data transmission.

7. A general simulation method suitable for data processing FPGAs, characterized in that, A general simulation system applicable to a data processing FPGA as described in any one of claims 1 to 6 includes: outputting load data to the data processing FPGA according to a preset timing and format; constructing the range of different regions of the load data and the valid data of the load data through a state mechanism; randomly assigning virtual channel identifiers of the load data using a randomization method; counting the input excitation through a counting area, and determining whether the data transmission is continuous and correct through the counting area at the output of the data processing FPGA; constructing a cyclic redundancy check (CRC) code check area for the load data according to a preset CRC algorithm; performing data flow operation after the load data enters the data processing FPGA, setting key nodes of the data flow as checkpoints, outputting and saving data during transmission, thereby detecting the correctness of data transmission of each intermediate state and the endpoint, and quickly locating the fault point based on the position of the checkpoint under fault conditions; transmitting remote control commands sent by the simulated storage control FPGA to the data processing FPGA; constructing receiving logic in the simulated transmitter front-end module, and descrambling and classifying the multiplexed and scrambled load data output by the data processing FPGA and storing it in different data files.

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