Display substrate, related display mother board and display panel

Abstract

A display substrate (20, 30, 40, 50, 60), a display mother board (70), and a display panel (90) are provided. A display substrate (20, 30, 40, 50, 60) has a central region (AA) and a peripheral region (BB) surrounding the central region (AA). The display substrate (20, 30, 40, 50, 60) includes: a substrate (100); a dielectric layer (500) located on the substrate (100) and including a first portion (510) and a second portion (520) stacked in sequence along a direction perpendicular to the substrate (100); a spacer (200) located within the peripheral region (BB) and on a top surface of the second portion (520) facing away from the substrate (100); and a conductive sealing portion (400) located within the peripheral region (BB) and in the dielectric layer (500), wherein the conductive sealing portion (400) at least includes a first portion (410) adjacent to the spacer (200) along a direction parallel to the substrate (100), and wherein the first portion (410) of the conductive sealing portion (400) is covered by the second portion (520) of the dielectric layer (500).

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of display technologies, and in particular, to a display substrate, a display mother board, and a display panel. Background Art

[0002] In recent years, with the increasing maturity of AR (Augmented Reality) and VR (Virtual Reality) technologies, there are demands for display devices applicable to AR and VR applications in terms of small size, light weight, high contrast, fast response speed, and low power consumption. Therefore, micro-organic light-emitting diode (Micro-OLED) microdisplays with these advantages have received extensive attention. Summary of the Invention

[0003] Embodiments of the present disclosure provide a display substrate and related display mother board and display panel.

[0004] According to a first aspect of the present disclosure, a display substrate is provided. The display substrate has a central region and a peripheral region surrounding the central region. The display substrate includes: a substrate; a dielectric layer located on the substrate and including a first portion and a second portion sequentially arranged along a direction perpendicular to the substrate; a spacer located within the peripheral region of the substrate, at least a part of a surface of the spacer on a side facing away from the substrate being exposed; and a conductive sealing portion located within the peripheral region and within the dielectric layer, where the conductive sealing portion at least includes a first portion adjacent to the spacer along a direction parallel to the substrate, and the first portion is covered by the second portion of the dielectric layer.

[0005] In embodiments of the present disclosure, the second portion of the dielectric layer includes sub-dielectric layers with a quantity less than or equal to 3.

[0006] In embodiments of the present disclosure, the conductive sealing portion further includes a second portion not adjacent to the spacer along a direction parallel to the substrate, and the second portion extends to a top surface of the second portion of the dielectric layer facing away from the substrate.

[0007] In embodiments of the present disclosure, the conductive sealing portion includes a conductive via layer and a conductive wiring layer alternately stacked along a direction perpendicular to the substrate.

[0008] In embodiments of the present disclosure, the conductive wiring layer includes a first conductive wiring layer closest to the substrate along a direction perpendicular to the substrate, serving as the bottommost layer of the conductive sealing component.

[0009] In embodiments of the present disclosure, the material of the first conductive wiring layer includes a semiconductor.

[0010] In embodiments of the present disclosure, the semiconductor includes polysilicon.

[0011] In an embodiment of the present disclosure, the conductive wiring layer further includes a second conductive wiring layer located above the first conductive wiring layer, and the material of the second conductive wiring layer includes a metal.

[0012] In an embodiment of the present disclosure, the first part of the conductive sealing portion includes any one of the following configurations: 6 conductive wiring layers and 6 conductive via layers; 6 conductive wiring layers and 5 conductive via layers; 5 conductive wiring layers and 5 conductive via layers; and 7 conductive wiring layers and 6 conductive via layers.

[0013] In an embodiment of the present disclosure, the gasket is located in the first part of the dielectric layer.

[0014] In an embodiment of the present disclosure, the conductive sealing portion has an annular shape surrounding the central region.

[0015] In an embodiment of the present disclosure, the conductive sealing portion includes a first ring portion and a second ring portion arranged in sequence away from the central region.

[0016] In an embodiment of the present disclosure, the annular shape is rectangular.

[0017] In an embodiment of the present disclosure, the conductive sealing portion has a corner, and the display substrate further includes a reinforcing portion located in the dielectric layer of the peripheral region and adjacent to the corner, and the reinforcing portion has a shape complementary to the corner.

[0018] In an embodiment of the present disclosure, the reinforcing portion has a mesh structure.

[0019] In an embodiment of the present disclosure, the display substrate includes a plurality of gaskets arranged parallel to each other and spaced apart, and two adjacent gaskets are spaced apart by a first distance. The display mother board further includes a cutting region located between adjacent display substrates. The cutting region includes a test gasket, and the size of the test gasket adjacent to the gasket along the direction of arranging the gaskets is smaller than the first distance.

[0020] In an embodiment of the present disclosure, the display substrate includes a backplane driving integrated circuit.

[0021] In an embodiment of the present disclosure, the material of the substrate includes a semiconductor material.

[0022] According to a second aspect of the present disclosure, there is provided a display mother board. The display mother board includes a display substrate according to any one of the first aspects.

[0023] In an embodiment of the present disclosure, the display mother board further includes a test gasket and dummy patterns located in the cutting region of adjacent display substrates. The dummy patterns are located between the test gasket and the gasket adjacent to the test gasket.

[0024] In an embodiment of the present disclosure, the spacing between the test pad and the pads adjacent to the test pad is configured to be greater than the minimum spacing between the conductive wirings adjacent in a direction parallel to the substrate of the display substrate.

[0025] In an embodiment of the present disclosure, the spacing is 40 μm - 80 μm.

[0026] In an embodiment of the present disclosure, the size of the dummy pattern is a square shape of 3 μm x 3 μm.

[0027] According to a third aspect of the present disclosure, a display panel is provided. The display panel includes a display substrate according to any one of the first aspects.

[0028] In an embodiment of the present disclosure, the display panel further includes a circuit board. The circuit board is electrically connected to the display substrate via the pads.

[0029] In an embodiment of the present disclosure, the circuit board includes a flexible circuit board.

[0030] Further aspects and scope of adaptability become apparent from the description provided herein. It should be understood that the various aspects of the present application may be implemented alone or in combination with one or more other aspects. It should also be understood that the description and specific embodiments herein are for illustrative purposes only and are not intended to limit the scope of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The drawings described herein are for illustrative purposes only of the selected embodiments and not all possible implementations, and are not intended to limit the scope of the present application, wherein:

[0032] Figure 1 A top view of a display substrate of the related art is shown;

[0033] Figure 2 A top view of a display substrate according to an embodiment of the present disclosure is shown;

[0034] Figure 3 A cross-sectional view of a display substrate taken along axis C1C2 in Figure 2 is shown;

[0035] Figure 4 A cross-sectional view of a display substrate taken along axis D1D2 in Figure 2 is shown;

[0036] Figure 5 A Figure 3 hierarchical diagram of a first portion 410 of the conductive sealing portion shown in an embodiment of the present disclosure is shown;

[0037] Figure 6Schematic diagram of a display substrate with a reinforced corner structure according to an embodiment of the present disclosure;

[0038] Figure 7 Schematic diagram of a display mother board according to an embodiment of the present disclosure;

[0039] Figure 8 Schematic diagram of the Figure 7 region C of the display mother board in

[0040] Figure 9 Schematic diagram of a display panel according to an embodiment of the present disclosure.

[0041] Throughout the various views of these drawings, corresponding reference numerals indicate corresponding components or features. Detailed Description

[0042] First, it should be noted that, unless the context clearly indicates otherwise, the singular forms of words used in this specification and the appended claims include the plural, and vice versa. Thus, when referring to the singular, it generally includes the plural of the corresponding term. Similarly, the terms "comprising" and "including" will be interpreted as inclusive rather than exclusive. Likewise, the terms "including" and "or" should be interpreted as inclusive, unless otherwise stated in this specification. Where the term "example" is used in this specification, especially when it is located after a group of terms, the "example" is merely exemplary and explanatory, and should not be considered exclusive or extensive.

[0043] In addition, it should also be noted that when introducing the elements and embodiments of the present application, the articles "a", "an", "the", and "said" are intended to mean that there is one or more elements; unless otherwise stated, the meaning of "a plurality" is two or more; the terms "comprising", "including", "containing", and "having" are intended to be inclusive and mean that there may be additional elements other than the listed elements; the terms "first", "second", "third", etc. are only for the purpose of description, and should not be construed as indicating or implying relative importance or forming an order.

[0044] Furthermore, in the drawings, the thicknesses and areas of the various layers are exaggerated for clarity. It should be understood that when a layer, region, or component is referred to as being "on" another part, it means that it is directly on the other part, or there may be other components in between. On the contrary, when a component is referred to as being "directly" on another component, it means that there are no other components in between.

[0045] As described above, with the development of AR and VR technologies, organic light-emitting diode (OLED) microdisplays with the advantages of small size, light weight, high contrast, fast response speed, and low power consumption have received extensive attention. To improve the yield of OLED microdisplays, in addition to improving the manufacturing process of traditional OLED displays, for example, further improvements need to be made to the design and layout of the backplane driving integrated circuit / chip in the display to solve the unwanted electrical connection problems existing in the prior art.

[0046] Generally, an OLED microdisplay typically includes a display substrate and a circuit board joined thereto, such as a flexible printed circuit board (FPC). The display substrate may include a backplane driving integrated circuit (BP Driver) IC. The backplane driving integrated circuit IC can perform image processing functions such as temperature compensation, brightness control, and Gamma correction. Figure 1 A top view of a display substrate of the related art is shown. As Figure 1 shown, the display substrate 10 includes a central region AA and a peripheral region BB surrounding the central region AA. The central region AA may refer to the display area. The peripheral region BB may refer to the non-display area. To achieve color display, the display area AA includes a light-emitting source that emits white light and a color filter (CF) that absorbs specific wavelengths. Additionally, since the components and materials in the display substrate 10 are prone to oxidation, thin-film encapsulation (TFE) technology is required to isolate water and oxygen in the air. As Figure 1 Further shown, the display substrate 10 further includes a substrate 100, a gasket 200, and a conductive seal 300. The gasket 200 is located within the peripheral region BB of the substrate 100. The conductive seal 300 may include a sealing ring. The conductive seal 300 can be used to prevent the stress generated when cutting a display mother board including a plurality of display substrates from acting on the central region AA, thereby avoiding deterioration of the performance of the display substrate 10.

[0047] A circuit board such as a flexible printed circuit board is joined to the gasket 200 on the display substrate 10 through a bonding pad (also referred to as a gold finger) thereon. Due to design deviations of the bonding pad or alignment deviations in bonding, the bonding pad may be undesirably electrically connected (e.g., short-circuited) to the conductive seal 300 of the display substrate 10.

[0048] The present disclosure provides a display substrate that avoids the problem of unwanted electrical connections such as short circuits by redesigning the structure.

[0049] The following refers to Figures 2 to 4 the structure of a display substrate according to an embodiment of the present disclosure for description. As Figure 2 shown, compared with Figure 1Similar to the display substrate 10 shown, the display substrate 20 also includes a central region AA, a peripheral region BB, a substrate 100, and a gasket 200. In an embodiment of the present disclosure, the material of the substrate 100 includes a semiconductor material, for example, a material including silicon. At least a part of the surface (such as the upper surface) of the gasket 200 on the side facing away from the substrate 100 is exposed. As Figure 2 shown, the upper surface of the gasket 200 is exposed. In an embodiment of the present disclosure, up and down are described with respect to the Z direction (i.e., the direction perpendicular to the substrate).

[0050] In the display substrate 20 according to the present disclosure, the conductive sealing portion 400 includes a first portion 410 adjacent to the gasket 200 along a direction parallel to the substrate 100. In an embodiment of the present disclosure, the conductive sealing portion 400 further includes a second portion 420 not adjacent to the gasket 200 along a direction parallel to the substrate 100. As Figure 2 shown, the second portion 420 is not adjacent to the gasket 200 along the Y direction. The term "a part of element S is adjacent to element M along the N direction" means that compared with another part of element S, a part of element S is closer to element M along the N direction. The term "a part of element S is not adjacent to element M along the N direction" means that compared with another part of element S, a part of element S is farther from element M along the N direction.

[0051] In addition, in an embodiment of the present disclosure, the conductive sealing portion 400 has an annular shape, closed or unclosed, surrounding the central region AA. As Figure 2 shown, according to an embodiment of the present disclosure, the annular shape can be rectangular. The first portion 410 of the conductive sealing portion 400 can be a portion corresponding to a side of the rectangular conductive sealing portion 400. It should be understood that this is only exemplary, and the first portion 410 can also be other portions of the rectangular conductive sealing portion 400 adjacent to the gasket 200. Additionally, according to an embodiment of the present disclosure, the conductive sealing portion 400 can be coupled to the ground terminal of the application circuit to shield external magnetic fields, thereby protecting the circuit in the central region AA from the influence of external magnetic fields.

[0052] According to an embodiment of the present disclosure, the conductive sealing portion 400 can include a first ring portion (not shown) and a second ring portion (not shown) sequentially arranged along a direction away from the central region AA. In the embodiment, compared with the second ring portion, the width of the first ring portion closer to the central region AA can be 10 μm. The width of the second ring portion can be 4 μm. The interval between the first ring portion and the second ring portion is 2 μm. In other embodiments of the present disclosure, other widths and spacings of the first ring portion and the second ring portion are also feasible.

[0053] Figure 3 shows along an embodiment of the present disclosureFigure 2 A cross-sectional view of the display substrate taken along the axis C1C2 in []. As Figure 3 shown, the display substrate 30 further includes a dielectric layer 500. The dielectric layer 500 is located on the substrate 100 and includes a first portion 510 and a second portion 520 sequentially arranged along a direction perpendicular to the substrate 100 (e.g., the Z direction). In an embodiment, the first portion 510 and the second portion 520 of the dielectric layer 500 may be integrally formed and include the same material. In other embodiments of the present disclosure, the first portion 510 and the second portion 520 of the dielectric layer 500 may also be separately formed and include the same or different materials.

[0054] In an embodiment of the present disclosure, the spacer 200 is located in the second portion 520 of the dielectric layer 500. As Figure 2 shown, the upper surface of the spacer 200 overlaps with the upper surface of the second portion 520 of the dielectric layer 500 and is exposed. In some embodiments of the present disclosure, the upper surface of the spacer 200 may be higher than the upper surface of the second portion 520 of the dielectric layer 500. In other embodiments of the present disclosure, the upper surface of the spacer 200 may be lower than the upper surface of the second portion 520 of the dielectric layer 500, as long as it can be exposed by the second portion 520 of the dielectric layer 500.

[0055] In an embodiment of the present disclosure, the conductive seal 400 is located in the peripheral region BB and in the dielectric layer 500. The first portion 410 of the conductive seal 400 is only located in the first portion 510 of the dielectric layer 500. The first portion 410 of the conductive seal 400 is covered by the second portion 520 of the dielectric layer 500. As Figure 3 shown, the upper surface of the first portion 410 of the conductive seal 400 may be coplanar with the upper surface of the first portion 510 of the dielectric layer 500. As Figure 3 shown, a second portion 520 of the dielectric layer is spaced between the first portion 410 of the conductive seal 400 and the spacer 200, that is, the first portion 410 of the conductive seal 400 is covered by the second portion 520 of the dielectric layer. According to an embodiment of the present disclosure, since the portion of the conductive seal 400 adjacent to the spacer 200 is always covered by the first portion 510 of the dielectric layer 500, it is possible to prevent the bonding pad on the flexible circuit board intended to be bonded to the spacer 200 from forming an undesired electrical connection with the conductive seal 400 due to alignment deviation. As described above, the conductive seal 400 is generally coupled to the ground terminal, so the conductive seal 400 according to the embodiment of the present disclosure can avoid the corresponding functional circuit on the flexible circuit board losing its original electrical function due to the bonding pad being coupled to the ground terminal.

[0056] Figure 4 Further shown is along an embodiment according to the present disclosure Figure 2In the embodiment of the present disclosure, the second portion 420 of the conductive sealing portion 400 extends to the top surface of the second portion 520 of the dielectric layer 500 on the side away from the substrate 100. Figure 4 As shown, Figure 3 The difference of the structure shown is that the upper surface of the second portion 420 of the conductive sealing part 400 is coplanar with the upper surface of the second portion 520 of the dielectric layer 500. This is only exemplary, and the upper surface of the second portion 420 of the conductive sealing part 400 may also be located between the upper surface and the lower surface of the second portion 520 of the dielectric layer 500.

[0057] According to an embodiment of the present disclosure, the second portion 420 of the conductive sealing portion 400 may also have the same structure as the first portion 410 of the conductive sealing portion 400 , that is, remain covered by the second portion 520 of the dielectric layer 500 .

[0058] According to an embodiment of the present disclosure, the conductive sealing portion 400 may have a layered hierarchical structure. In an embodiment of the present disclosure, the conductive sealing portion 400 includes a conductive via layer and a conductive wiring layer alternately stacked in a direction perpendicular to the substrate 100 (Z direction). In an embodiment of the present disclosure, the second portion 520 of the dielectric layer 500 may include a number of sub-dielectric layers less than or equal to 3. In an embodiment of the present disclosure, the conductive sealing portion 400 includes a first conductive wiring layer that is most adjacent to the substrate 100 as the bottom layer of the conductive sealing portion 400.

[0059] The following will refer to Figures 5 to 6 The structure of the first portion 410 of the conductive sealing portion 400 is described in detail.

[0060] Figure 5 The embodiment according to the present disclosure is shown Figure 3 FIG. 4 is a diagram showing a hierarchical structure of the first portion 410 of the conductive seal 400. Figure 5 As shown, the first part 410 of the conductive sealing part 400 includes 6 conductive wiring layers 4110 and 6 conductive via layers 4120. According to an embodiment of the present disclosure, the second part 520 of the dielectric layer 500 may include a sub-dielectric layer. According to an embodiment of the present disclosure, the second part 420 of the conductive sealing part 400 includes 7 conductive wiring layers 4110 and 6 conductive via layers 4120. The conductive wiring layer 4120 includes a first conductive wiring layer 4130 that is most adjacent to the substrate 100 in a direction perpendicular to the substrate 100 (Z direction). The first conductive wiring layer 4130 is the bottom layer (lowest layer) of the first part 410. In an embodiment, the material of the first conductive wiring layer 4130 includes a semiconductor. For example, polysilicon.

[0061] According to an embodiment of the present disclosure, in addition to the first conductive wiring layer 4130, the conductive wiring layer 4120 further includes other conductive wiring layers (e.g., the remaining five conductive wiring layers) located above the first conductive wiring layer 4130. In an embodiment of the present disclosure, the material of the other conductive wiring layers includes metal.

[0062] According to an embodiment of the present disclosure, the first portion 410 of the conductive seal 400 may include five conductive via layers 4110 and six conductive wiring layers 4120. In this case, the second portion 520 of the dielectric layer 500 includes two sub-dielectric layers.

[0063] According to an embodiment of the present disclosure, the first portion 410 of the conductive seal 400 may include five conductive via layers 4110 and five conductive wiring layers 4120. In this case, the second portion 520 of the dielectric layer 500 may include three sub-dielectric layers.

[0064] Furthermore, the inventors of the present invention have found through research that during the cutting process of separating each display substrate from a display mother board having a plurality of display substrates, the corner portions of the conductive seal 400 are prone to accumulating relatively large cutting stresses, thereby causing damage to the functions of the display area near the corner portions. Therefore, the present disclosure also provides a display substrate having a reinforcing portion. During the cutting process, the display substrate having such a structure can disperse the undesired stress through the reinforcing portion. For example, the reinforcing portion cracks or is removed to reduce or eliminate the stress at the corner portion, thereby protecting the display panel. The following refers to Figure 6 , and describes the substrate having such a structure.

[0065] Figure 6 FIG. shows a schematic diagram of a display substrate having a reinforcing portion according to an embodiment of the present disclosure. In the display substrate 60, the conductive seal 400 has a corner 430. The display substrate 60 further includes a reinforcing portion 600 located in the dielectric layer 500 in the peripheral region BB and adjacent to the corner 430. The reinforcing portion 600 has a shape complementary to the corner 430.

[0066] In an embodiment of the present disclosure, the fact that the reinforcing portion 600 has a shape complementary to the corner 430 means that the portions of the reinforcing portion 600 and the corner 430 adjacent to each other have conformal surfaces. As Figure 6 shown, according to an embodiment of the present disclosure, the overall outer contour of the rectangular conductive seal 400 having the corner 430 and the reinforcing portion 600 is still a rectangular shape. This is not a limitation. In other embodiments of the present disclosure, the conductive seal 400 may be other annular shapes having corners, such as a square shape. In Figure 6 , for the sake of simplicity, only a part of the display substrate 60 is shown, and the remaining three reinforcing corners may have the same as Figure 6Structures with the same or different reinforcing corners as shown. For example, the structures of the reinforcing corners at the upper left and upper right corners are the same but different from Figure 6 the reinforcing corners shown, while the reinforcing corner at the lower right corner has a structure the same as that of Figure 6 the reinforcing corners shown. The display substrate 60 is shown to include a rectangular conductive sealing portion 400 having a corner 430. As Figure 6 shown, the reinforcing portion 600 is a right triangle, specifically, an isosceles right triangle. It can be understood that the specific shape of the reinforcing portion 600 can be set according to the requirements of specific embodiments. The reinforcing portion 600 has a shape complementary to the corner 3140. In an embodiment, the reinforcing portion 600 can be formed in the dielectric layer 500. The reinforcing portion 600 can have the same hierarchical structure as the first portion 410 of the conductive sealing portion 400. The reinforcing portion 600 is only formed in the first portion 510 of the dielectric layer 500 and is covered by the second portion 520 of the dielectric layer 500. It can include a plurality of conductive via layers and a plurality of conductive wiring layers located in the first portion 510 of the dielectric layer 500. According to an embodiment of the present disclosure, the reinforcing portion 600 can include, for example, 6 conductive wiring layers and 6 conductive via layers, 6 conductive wiring layers and 5 conductive via layers, or 5 conductive wiring layers and 5 conductive via layers. According to an embodiment of the present disclosure, the reinforcing portion 600 can have the same hierarchical structure as the second portion 420 of the conductive sealing portion 400, be formed in the first portion 510 and the second portion 520 of the dielectric layer 500, and can include, for example, 7 conductive wiring layers and 6 conductive via layers.

[0067] According to an embodiment of the present disclosure, the reinforcing portion 600 can have a mesh structure. Correspondingly, each of the conductive via layers or conductive wiring layers included in the reinforcing portion 600 also has a corresponding mesh structure.

[0068] The present disclosure also provides a corresponding display mother board. Referring below to Figure 7 and Figure 8 for a description thereof.

[0069] Figure 7 shows a schematic diagram of a display mother board according to an embodiment of the present disclosure. In an embodiment of the present disclosure, the display mother board 70 includes a plurality of display substrates, for example, display substrates 10 to 60. As Figure 7 shown, the display substrates 10 to 60 are arranged in an array. The display mother board 70 includes a cutting area 710 located between two adjacent display substrates 10. Referring below to Figure 8 for a detailed description of the setting of the gasket and the adjacent cutting area.

[0070] Figure 8 shows an embodiment of the present disclosure Figure 7 schematic diagram of area C of the display mother board in. AsFigure 8 As shown, two adjacent pads 200 are spaced apart by a first distance d. In an embodiment, a plurality of pads 200 are arranged at equal intervals (e.g., the first distance d) in the X direction, and each pad 200 is parallel to each other in the Y direction.

[0071] In an embodiment of the present disclosure, the cutting region 710 includes a test pad 7110 and dummy patterns 7120. In an embodiment, although the test pad 7110 and the dummy patterns 7120 shown in Figure 8 are square, this is not a limitation. The test pad 7110 and the dummy patterns 7120 may also be other shapes, such as circular, etc. Additionally, although for the sake of clear and concise drawing, Figure 7 the sizes of the shown test pads 7110 are the same, this is not a limitation. Generally, the sizes of the test pads 7110 vary due to the different functions of the test pads 7110. In an embodiment of the present disclosure, the test pad 7110 may include die alignment mark test element groups (TEGs), die acceptability test TEGs, critical dimension TEGs, and overlay TEGs. As Figure 8 shown, the cutting region 710 is adjacent to the pad 200. The dummy patterns 7120 are located between the test pad 7110 and the pad 200 adjacent to the test pad 7110.

[0072] In an embodiment of the present disclosure, the interval d1 between the test pad 7110 and the pad 200 adjacent to the test pad 7110 is greater than the absolute value of the alignment accuracy when bonding a circuit board to the display substrate 10. In practice, the absolute value of this alignment accuracy can be characterized, for example, by the minimum interval between adjacent conductive wirings along a direction parallel to the substrate of the display substrate. According to an embodiment of the present invention, the absolute value of this alignment accuracy can be about 2 - 5 times the minimum interval. In an embodiment, the circuit board is bonded to the display substrate 10 through a gold finger. It should be understood that for different circuit boards or display substrates or different requirements, the alignment accuracy may be different. In an embodiment, the alignment accuracy can be ±30μm. As Figure 8 shown, the interval d1 between the test pad 7110 and the pad 200 in the Y direction is 40μm - 80μm. By setting the interval, it can be ensured that when bonding the bonding pads of an external circuit such as a flexible printed circuit board to the pad 200, there is no undesired connection between the test pads and adjacent bonding pads resulting in a short circuit. It should be understood that those skilled in the art can further set this interval according to specific applications and requirements. In other embodiments of the present disclosure, the dummy patterns 7120 may also have other shapes and sizes.

[0073] As Figure 8As shown, the dummy pattern 7120 may be arranged in an array. The dummy pattern 7120 may have a square shape of 3 μm x 3 μm. In other embodiments of the present disclosure, the dummy pattern 7120 may also have other shapes and sizes.

[0074] The present disclosure also provides a display panel. The following will be described in detail with reference to the accompanying Figure 9 drawings.

[0075] Figure 9 FIG. shows a schematic structural diagram of a display panel according to an embodiment of the present disclosure. As Figure 9 shown, the display panel 90 may include a display substrate 10 to 60 according to any embodiment of the present disclosure.

[0076] In an embodiment of the present disclosure, the display panel 90 may further include a circuit board. The circuit board is electrically connected to the display substrate 10 via a gasket 200. In an embodiment of the present disclosure, the circuit board may include a flexible circuit board.

[0077] The display panel 90 may be a product or component with a display function such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc.

[0078] The display panel provided by the embodiment of the present disclosure has the same or similar beneficial effects as the display substrate provided by the foregoing embodiments of the present disclosure. Since the display substrate has been described in detail in the foregoing embodiments, it will not be elaborated herein.

[0079] The foregoing description of the embodiments has been provided for purposes of illustration and description. It is not intended to be exhaustive or to limit the application. The various elements or features of a particular embodiment are generally not limited to that particular embodiment, but, where appropriate, these elements and features are interchangeable and may be used in the selected embodiment, even if not specifically shown or described. Similarly, many modifications can be made in many ways. Such modifications should not be regarded as departing from the application, and all such modifications are included within the scope of the application.

Claims

1. A display substrate having a central region and a peripheral region surrounding the central region, the display substrate comprising: A substrate; A dielectric layer located on the substrate and including a first portion and a second portion sequentially arranged along a direction perpendicular to the substrate; A spacer located within the peripheral region on the substrate, wherein at least a portion of a surface of the spacer on a side facing away from the substrate is exposed, and the display substrate includes a plurality of the spacers arranged parallel to and spaced apart from each other; And A conductive sealing portion located within the peripheral region and within the dielectric layer, wherein the conductive sealing portion at least includes a first portion adjacent to the spacer along a direction parallel to the substrate, wherein the first portion of the conductive sealing portion is covered by the second portion of the dielectric layer, and the first portion of the conductive sealing portion is only located in the first portion of the dielectric layer, wherein the conductive sealing portion further includes a second portion not adjacent to the spacer along a direction parallel to the substrate, and the second portion extends to a top surface of the second portion of the dielectric layer facing away from the substrate.

2. The display substrate according to claim 1, wherein The conductive sealing portion includes a conductive via layer and a conductive wiring layer alternately stacked along a direction perpendicular to the substrate.

3. The display substrate according to claim 2, wherein The conductive wiring layer includes a first conductive wiring layer closest to the substrate along a direction perpendicular to the substrate, serving as the bottommost layer of the conductive sealing portion.

4. The display substrate according to claim 3, wherein The material of the first conductive wiring layer includes a semiconductor.

5. The display substrate according to claim 4, wherein, The semiconductor includes polysilicon.

6. The display substrate according to claim 5, wherein The conductive wiring layer further includes a second conductive wiring layer located above the first conductive wiring layer, and the material of the second conductive wiring layer includes a metal.

7. The display substrate according to claim 6, wherein the first portion of the conductive sealing portion includes any one of the following configurations: 6 conductive wiring layers and 6 conductive via layers; 6 conductive wiring layers and 5 conductive via layers; 5 conductive wiring layers and 5 conductive via layers; and 7 conductive wiring layers and 6 conductive via layers.

8. The display substrate according to claim 1, wherein, The spacer is located in the second portion of the dielectric layer.

9. The display substrate according to claim 1, wherein, The conductive sealing portion has an annular shape surrounding the central region.

10. The display substrate according to claim 9, wherein, The conductive sealing portion includes a first ring portion and a second ring portion sequentially arranged along a direction away from the central region.

11. The display substrate according to claim 10, wherein, The conductive sealing portion has a corner, and the display substrate further includes a reinforcing portion located in the dielectric layer of the peripheral region and adjacent to the corner, and the reinforcing portion has a shape complementary to the corner.

12. The display substrate according to claim 11, wherein, The reinforcing portion has a mesh structure.

13. The display substrate according to claim 1, wherein, The display substrate includes a backplane driving integrated circuit.

14. The display substrate according to claim 13, wherein, The material of the substrate includes a semiconductor material.

15. A display mother board including a plurality of display substrates according to any one of claims 1 to 14.

16. The display mother board according to claim 15 further includes a test pad and dummy patterns located within a cutting region of the adjacent display substrate, wherein, The dummy pattern is located between the test spacer and the spacer adjacent to the test spacer.

17. The display motherboard according to claim 16, wherein, The interval between the test spacer and the spacer adjacent to the test spacer is configured to be greater than the minimum interval between adjacent conductive wirings of the display substrate along a direction parallel to the substrate.

18. A display panel including a display substrate according to any one of claims 1 to 14.

19. The display panel according to claim 18 further includes a circuit board, wherein, The circuit board is electrically connected to the display substrate via the gasket.

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