Semiconductor structure and method of manufacturing the same
By forming a protective material layer and a dielectric layer within the trench of the vertically enclosed gate transistor and filling it with a work function structure, the problem of large leakage current is solved, and the electrical stability and performance of the semiconductor structure are improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHANGXIN MEMORY TECH INC
- Filing Date
- 2022-01-17
- Publication Date
- 2026-06-05
AI Technical Summary
Vertically enclosed gate transistors have large leakage currents, which affects the performance of the semiconductor structure.
A protective material layer and a dielectric layer are formed within the trench of a vertically enclosed gate transistor, and a work function structure is filled, including a first work function layer and a second work function layer, wherein the work function of the second work function layer is smaller than that of the first work function layer.
Without changing the resistance, leakage current is reduced, and the electrical stability and performance of the semiconductor structure are improved.
Smart Images
Figure CN116487327B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure and its fabrication method. Background Technology
[0002] In a vertical gate-all-around (VGAA) transistor, the trench region of the transistor extends in a direction perpendicular to the substrate surface. This is beneficial for improving the area utilization of the semiconductor structure with the transistor and achieving further reduction in feature size. However, the leakage current of the transistor is relatively large, which affects the performance of the semiconductor structure. Therefore, how to improve the performance of the semiconductor structure while using VGAA transistors has become an urgent problem to be solved. Summary of the Invention
[0003] This application provides a semiconductor structure and its fabrication method, which can optimize the leakage current of a vertically enclosed gate transistor, thereby reducing the leakage current of the vertically enclosed gate transistor and improving the performance of the semiconductor structure.
[0004] This application provides a method for fabricating a semiconductor structure, including:
[0005] A substrate is provided, in which a first groove is formed;
[0006] A first dielectric layer and a protective material layer are formed in the first trench; the first dielectric layer is located between the protective material layer and the substrate, and the upper surface of the first dielectric layer is lower than the upper surface of the substrate to expose part of the sidewall of the first trench.
[0007] A second dielectric layer is formed on the sidewall exposed by the first trench, a second trench is formed between the second dielectric layer and the protective material layer, and the second dielectric layer is in contact with the first dielectric layer;
[0008] A work function structure is formed by filling the second trench. The work function structure includes a first work function layer and a second work function layer.
[0009] The second work function layer is located on the upper surface of the first work function layer, and the work function of the second work function layer is smaller than that of the first work function layer.
[0010] In one embodiment, forming a first dielectric layer and a protective material layer within a first trench includes:
[0011] A first dielectric material layer is formed on the inner wall of the first trench;
[0012] Remove the first dielectric material layer at the bottom of the first trench;
[0013] Fill the first trench with a layer of protective material;
[0014] The portion of the first dielectric material layer adjacent to the upper surface of the substrate is removed, and the remaining first dielectric material layer is the first dielectric layer.
[0015] In one embodiment, the substrate includes a silicon substrate; the bottom of the first trench exposes a portion of the silicon substrate, and after removing the first dielectric material layer at the bottom of the first trench, the trench further includes:
[0016] Inject the first metallic material into the bottom of the first trench;
[0017] An annealing process is performed to allow the first metal material to react with the silicon substrate to form a metal silicide;
[0018] The metal silicide phases at the bottom of adjacent first trenches are in contact.
[0019] In one embodiment, the substrate further includes active pillars located between adjacent first trenches, and the second dielectric layer includes a first silicon oxide layer. Forming the second dielectric layer on the exposed sidewalls of the first trenches includes:
[0020] A first silicon oxide layer is grown on the sidewall of the first trench using a thermal oxidation process.
[0021] In one embodiment, the bottom of the second dielectric layer forms an angle greater than 0 degrees and less than or equal to 90 degrees with the first direction;
[0022] Here, the first direction refers to the direction from the bottom of the first groove to the opening of the first groove.
[0023] In one embodiment, filling the second trench with a functional structure includes:
[0024] The first work function material layer is filled into the second trench;
[0025] The excess first work function material layer is removed to obtain the first work function structure, the upper surface of the first work function structure being lower than the upper surface of the substrate;
[0026] A second work function material layer is formed on the upper surface of the first work function structure. The upper surface of the second work function material layer is not lower than the upper surface of the substrate. The second work function material layer includes a second metallic material.
[0027] An annealing process is used to diffuse the second metal material to the upper part of the first work function structure to form a second work function layer, while simultaneously obtaining a first work function layer composed of the remaining first work function structure.
[0028] In one embodiment, the annealing process is followed by:
[0029] Remove the second work function material layer from the surface of the second work function layer.
[0030] In one embodiment, the work function structure further includes a third work function layer located on the upper surface of the second work function layer, and after annealing, it further includes:
[0031] By removing a portion of the second work function material layer from the upper surface of the second work function layer, a third work function layer is obtained, consisting of the remaining second work function material layer.
[0032] In one embodiment, the first work function material layer includes a third metal material, the work function of which is greater than that of the second metal material.
[0033] In one embodiment, the third metallic material includes titanium, and the second metallic material includes at least one of lanthanum, zirconium, hafnium, and aluminum.
[0034] In one embodiment, the height of the second work function layer is greater than or equal to the height of the first work function.
[0035] In one embodiment, the upper surface of the work function structure is lower than the upper surface of the substrate, and after filling the second trench to form the work function structure, the following is also included:
[0036] An isolation material layer is formed on the upper surface of the work function structure, and the upper surface of the isolation material layer is not lower than the upper surface of the substrate.
[0037] In one embodiment, the insulating material layer and the protective material layer are made of the same material.
[0038] This application also provides a semiconductor structure, including:
[0039] A substrate, in which a first groove is formed;
[0040] The protective material layer is located within the first trench;
[0041] The first dielectric layer is located on the sidewall of the first trench and between the protective material layer and the substrate;
[0042] The second dielectric layer is located on the sidewall of the first trench and is in contact with the first dielectric layer, and is located between the protective material layer and the substrate, with a second trench between the second dielectric layer and the protective material layer;
[0043] The work function structure is located in the second trench and includes a first work function layer and a second work function layer.
[0044] The second work function layer is located on the upper surface of the first work function layer, and the work function of the second work function layer is smaller than that of the first work function layer.
[0045] In one embodiment, the bottom of the second dielectric layer forms an angle greater than 0 degrees and less than or equal to 90 degrees with the first direction;
[0046] Here, the first direction refers to the direction from the bottom of the first groove to the opening of the first groove.
[0047] In one embodiment, the second work function layer includes a second metallic material, and the first work function layer includes a third metallic material, wherein the work function of the third metallic material is greater than that of the second metallic material.
[0048] In one embodiment, the third metallic material includes titanium, and the second metallic material includes at least one of lanthanum, zirconium, hafnium, and aluminum.
[0049] In one embodiment, the work function structure further includes:
[0050] The third work function layer is located on the upper surface of the second work function layer; wherein, the third work function layer includes a second metallic material.
[0051] In one embodiment, the upper surface of the work function structure is lower than the upper surface of the substrate, and the semiconductor structure further includes:
[0052] An isolation material layer is located on the upper surface of the work function structure, and the upper surface of the isolation material layer is not lower than the upper surface of the substrate.
[0053] In one embodiment, the height of the second work function layer is greater than or equal to the height of the first work function.
[0054] In the above-described method for fabricating a semiconductor structure, a first trench is formed in the substrate, a protective material layer is formed in the first trench, a first dielectric layer is located between the protective material layer and the substrate, a second dielectric layer is located on the exposed sidewall of the first trench and in contact with the first dielectric layer, a second trench is formed between the second dielectric layer and the protective material layer, and a work function structure is filled in the second trench. The work function structure includes a first work function layer and a second work function layer located on the upper surface of the first work function layer, and the work function of the second work function layer is smaller than that of the first work function layer. Without changing the resistance, the leakage current of the semiconductor structure with the work function structure as the gate structure is reduced, and the electrical stability and performance of the semiconductor structure are improved.
[0055] In the aforementioned semiconductor structure, a first trench is formed in the substrate, a protective material layer is located within the first trench, a first dielectric layer is located between the protective material layer and the substrate, a second dielectric layer is located on the exposed sidewall of the first trench and in contact with the first dielectric layer, a second trench is formed between the second dielectric layer and the protective material layer, and a work function structure is located within the second trench. The work function structure includes a first work function layer and a second work function layer located on the upper surface of the first work function layer, wherein the work function of the second work function layer is smaller than that of the first work function layer. Without changing the resistance, the leakage current of the semiconductor structure with the work function structure as the gate structure is reduced, thereby improving the electrical stability and performance of the semiconductor structure. Attached Figure Description
[0056] To more clearly illustrate the technical solutions in the embodiments or related technologies of this application, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0057] Figure 1 This is a schematic flowchart of a method for fabricating a semiconductor structure in one embodiment;
[0058] Figure 2 This is a flowchart illustrating step S104 in one embodiment;
[0059] Figure 3 This is a schematic flowchart of a method for fabricating a semiconductor structure in another embodiment;
[0060] Figure 4 This is a schematic cross-sectional view of a semiconductor structure after metal silicide formation in one embodiment;
[0061] Figure 5 for Figure 4 A cross-sectional schematic diagram of the semiconductor structure after the formation of the protective material layer in one corresponding embodiment;
[0062] Figure 6 for Figure 5 A cross-sectional schematic diagram of the semiconductor structure after the formation of the first dielectric layer in one corresponding embodiment;
[0063] Figure 7 for Figure 6 A cross-sectional schematic diagram of the semiconductor structure after the formation of the second dielectric layer in one corresponding embodiment;
[0064] Figure 8 This is a flowchart illustrating step S108 in one embodiment;
[0065] Figure 9 for Figure 7A cross-sectional schematic diagram of the semiconductor structure after the formation of the first work function material layer in one corresponding embodiment;
[0066] Figure 10 for Figure 9 A cross-sectional schematic diagram of the semiconductor structure after the formation of the first work function structure in one corresponding embodiment;
[0067] Figure 11 for Figure 10 A cross-sectional schematic diagram of the semiconductor structure after the formation of the second work function material layer in one corresponding embodiment;
[0068] Figure 12 for Figure 11 A cross-sectional schematic diagram of the semiconductor structure after the formation of the second work function layer in one corresponding embodiment;
[0069] Figure 13 This is a schematic cross-sectional view of the semiconductor structure after the formation of the isolation material layer in one embodiment;
[0070] Figure 14 This is a cross-sectional schematic diagram of the semiconductor structure after the formation of the isolation material layer in another embodiment.
[0071] Explanation of reference numerals in the attached figures:
[0072] 102, Substrate; 104, First Trench; 106, First Dielectric Material Layer; 108, Barrier Layer; 110, Hard Mask Layer; 112, Metal Silicate; 114, Bit Line Structure; 116, Protective Material Layer; 118, Second Dielectric Layer; 120, Second Trench; 122, First Work Function Material Layer; 124, Second Work Function Material Layer; 126, Work Function Structure; 128, Isolation Material Layer; 202, First Dielectric Layer; 204, First Work Function Structure; 206, Second Work Function Layer; 208, First Work Function Layer; 210, Third Work Function Layer; 212, Drift Region; 214, First Part; 216, Second Part. Detailed Implementation
[0073] To facilitate understanding of the embodiments of this application, a more comprehensive description of the embodiments of this application will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the embodiments of this application. However, the embodiments of this application can be implemented in many different forms and are not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the embodiments of this application more thorough and complete.
[0074] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which embodiments of this application belong. The terminology used herein in the description of embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the embodiments of this application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.
[0075] In the description of the embodiments of this application, it should be understood that the terms "upper", "lower", "vertical", "horizontal", "inner", "outer", etc., indicate the orientation or positional relationship based on the method or positional relationship shown in the drawings. They are only for the convenience of describing the embodiments of this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of this application.
[0076] It is understood that the terms "first," "second," etc., used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of this application, a first dielectric layer may be referred to as a second dielectric layer, and similarly, a second dielectric layer may be referred to as a first dielectric layer. Both the first dielectric layer and the second dielectric layer are dielectric layers, but they are not the same dielectric layer.
[0077] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. In the description of this application, "several" means at least one, such as one, two, etc., unless otherwise explicitly specified.
[0078] Figure 1 This is a schematic flowchart of a method for fabricating a semiconductor structure in one embodiment, as shown below. Figure 1 As shown, in this embodiment, a method for fabricating a semiconductor structure is provided, comprising:
[0079] S102 provides a substrate having a first trench.
[0080] Specifically, a substrate is provided, in which a first trench is formed. The substrate can be made of undoped single-crystal silicon, doped single-crystal silicon, silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), etc. As an example, in this embodiment, the substrate is made of single-crystal silicon.
[0081] S104, a protective material layer and a first dielectric layer located between the protective material layer and the substrate are formed in the first trench.
[0082] Specifically, a first dielectric layer and a protective material layer are formed within the first trench. The first dielectric layer is located between the protective material layer and the substrate, and its upper surface is lower than the upper surface of the substrate, thereby exposing a portion of the sidewalls of the first trench. It is understood that the first dielectric layer is located on the sidewalls of the first trench away from the opening, while the sidewalls of the first trench near the opening are exposed and not covered by the first dielectric layer. For example, the first dielectric layer may extend along the sidewalls of the first trench and cover the bottom of the first trench, or it may only cover the sidewalls of the first trench away from the opening.
[0083] S106, a second dielectric layer is formed on the exposed sidewall of the first trench.
[0084] A second dielectric layer is formed on the exposed sidewall of the first trench. A second trench is formed between the second dielectric layer and the protective material layer, and the second dielectric layer is in contact with the first dielectric layer. Specifically, a second dielectric layer is formed on the sidewall of the first trench near the opening that is not covered by the first dielectric layer. The second dielectric layer is in contact with the first dielectric layer located on the sidewall of the first trench, and the gap between the second dielectric layer and the protective material layer in the first trench is the second trench.
[0085] S108 forms a functional structure in the second trench.
[0086] Specifically, a power function structure is formed by filling the second trench. The power function structure includes a first power function layer and a second power function layer. The second power function layer is located on the upper surface of the first power function layer, and the power function of the second power function layer is smaller than that of the first power function layer. This power function structure can be used as the gate structure of a transistor and the word line structure of a memory device. The power function of the second power function structure is lower than that of the first power function layer.
[0087] In the above-described method for fabricating a semiconductor structure, a first trench is formed in the substrate, a protective material layer is formed in the first trench, a first dielectric layer is located between the protective material layer and the substrate, a second dielectric layer is located on the exposed sidewall of the first trench and in contact with the first dielectric layer, a second trench is formed between the second dielectric layer and the protective material layer, and a work function structure is filled in the second trench. The work function structure includes a first work function layer and a second work function layer located on the upper surface of the first work function layer, and the work function of the second work function layer is smaller than that of the first work function layer. Without changing the resistance, the leakage current of the semiconductor structure with the work function structure as the gate structure is reduced, and the electrical stability and performance of the semiconductor structure are improved.
[0088] Figure 2 This is a flowchart illustrating step S104 in one embodiment. Figure 3 This is a schematic flowchart of a method for fabricating a semiconductor structure in another embodiment. Figure 4 This is a schematic cross-sectional view of the semiconductor structure after the formation of metal silicide in one embodiment. Figure 5 for Figure 4 A cross-sectional view of the semiconductor structure after the formation of the protective material layer in one corresponding embodiment. Figure 6 for Figure 5 A cross-sectional schematic diagram of the semiconductor structure after the formation of the first dielectric layer in one corresponding embodiment; as shown. Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 As shown, in one embodiment, step S104 includes:
[0089] S202, a first dielectric material layer is formed on the inner wall of the first trench.
[0090] like Figure 4 As shown, firstly, a substrate 102 is provided, in which a first trench 104 is formed; secondly, a first dielectric material layer 106 is formed on the sidewalls and bottom of the first trench 104, wherein the first dielectric material layers 106 between the sidewalls of the first trench 104 are not in contact. Exemplarily, the constituent material of the first dielectric material layer 106 includes one or more of nitrides, oxides, and oxynitrides, such as silicon dioxide, silicon nitride, and silicon oxynitride; for example, the constituent material of the first dielectric material layer 106 is silicon dioxide.
[0091] like Figure 4As shown, in one embodiment, the method for fabricating the semiconductor structure further includes: forming a barrier layer 108 on a substrate 102. The barrier layer 108 can isolate the substrates 102 (active pillars) between adjacent first trenches 104, preventing the subsequent formation of metal silicides from affecting the substrates 102 (active pillars) between adjacent first trenches 104. Exemplarily, the constituent material of the barrier layer 108 includes one or more of nitrides, oxides, and oxynitrides, such as silicon dioxide, silicon nitride, and silicon oxynitride.
[0092] In one embodiment, the method for fabricating the semiconductor structure further includes: forming a hard mask layer 110 on a substrate 102. The hard mask layer 110 defines the morphology and location of the first trench 104. The hard mask layer 110 also serves as an isolation structure during the formation of metal silicides, further preventing the formation of metal silicides from affecting the substrate 102 (active pillars) between adjacent first trenches 104. Exemplarily, the hard mask layer 110 is formed on the upper surface of the barrier layer 108. Exemplarily, the constituent material of the hard mask layer 110 includes one or more of nitrides, oxides, and oxynitrides, such as silicon dioxide, silicon nitride, and silicon oxynitride. It is understood that the constituent materials of the hard mask layer 110 and the barrier layer 108 can be the same or different; for example, the constituent material of the hard mask layer 110 is silicon nitride, and the constituent material of the barrier layer 108 is silicon dioxide.
[0093] S204, Remove the first dielectric material layer at the bottom of the first trench.
[0094] like Figure 4 As shown, the first dielectric material layer 106 at the bottom of the first trench 104 is removed by etching. When a barrier layer 108 and / or a hard mask layer 110 are formed on the substrate 102, the barrier layer 108 and / or the hard mask layer 110 can serve as an etching barrier structure to prevent the etching process from damaging the substrate 102 (active pillar) between adjacent first trenches 104, thus protecting the substrate 102.
[0095] like Figure 3 , Figure 4 As shown, in one embodiment, the substrate 102 includes a silicon substrate; the bottom of the first trench 104 exposes a portion of the silicon substrate, and after step S204, the following is further included:
[0096] S302, inject the first metallic material into the bottom of the first trench.
[0097] Specifically, a first metal material is implanted into the silicon substrate exposed at the bottom of the first trench 104 through an ion implantation process. The implantation angle, implantation depth, and implantation dose of the ion implantation process are set according to actual needs. For example, the first metal material includes one or more of cobalt, tungsten, aluminum, and titanium.
[0098] S304, an annealing process is performed to react the first metal material with the silicon substrate to form metal silicide.
[0099] An annealing process, such as rapid thermal annealing or plasma annealing, is performed to react the first metal material implanted into the silicon substrate with the silicon substrate to form a metal silicide 112. The metal silicides 112 at the bottom of adjacent first trenches 104 are in contact to form a bit line structure 114 located in the substrate. Exemplarily, the formation of the metal silicide 112 (bit line structure 114) through steps S302-S304 can be performed before step S202.
[0100] S206, fill the first trench with a protective material layer.
[0101] like Figure 5 As shown, the first trench 104 is filled with a protective material layer 116, that is, the portion of the first trench 104 where the first dielectric material layer 106 is not formed is filled with the protective material layer 116. For example, the constituent material of the protective material layer 116 includes one or more of nitrides, oxides, and oxynitrides, such as silicon dioxide, silicon nitride, and silicon oxynitride. It is understood that at least one of the protective material layer 116, the hard mask layer 110, and the barrier layer 108 may have a different constituent material from the others, or all of them may be different; for example, the constituent material of the protective material layer 116 may be silicon nitride.
[0102] S208, Remove a portion of the first dielectric material layer near the substrate surface to obtain the first dielectric layer.
[0103] like Figure 6 As shown, a portion of the first dielectric material layer 106 adjacent to the upper surface of the substrate is removed using a dry etching process and / or a wet etching process. The remaining first dielectric material layer 106 is the first dielectric layer 202. It can be understood that when a barrier layer 108 and / or a hard mask layer 110 are formed on the substrate 102, the barrier layer 108 and / or the hard mask layer 110 play a role in protecting the substrate 102 (active pillar) between adjacent first trenches 104 when the portion of the first dielectric material layer 106 adjacent to the upper surface of the substrate is removed. At the same time, the barrier layer 108 and / or the hard mask layer 110 can be removed together with the portion of the first dielectric material layer 106 adjacent to the upper surface of the substrate, or they can be removed after the portion of the first dielectric material layer 106 adjacent to the upper surface of the substrate is removed.
[0104] Figure 7 for Figure 6 A cross-sectional schematic diagram of the semiconductor structure after the formation of the second dielectric layer in one corresponding embodiment is shown below. Figure 7As shown, a second dielectric layer 118 is formed on the sidewall of the first trench 104 where the first dielectric layer 202 is not formed. The second dielectric layer 118 is in contact with the first dielectric layer 202, and a second trench 120 is formed between the second dielectric layer 118 and the protective material layer 116, meaning the second dielectric layer 118 does not completely fill the gap between the protective material layer 116 and the first trench 104. Exemplarily, the constituent material of the second dielectric layer 118 includes one or more of nitrides, oxides, and oxynitrides, such as silicon dioxide, silicon nitride, and silicon oxynitride. It is understood that the constituent material of the second dielectric layer 118 can be the same as or different from the first dielectric layer 202. Exemplarily, the second dielectric layer 118 extends along the sidewall of the first trench 104 and covers the substrate 102, serving to isolate the active column from the external environment.
[0105] Continue to refer to Figure 7 In one embodiment, the substrate 102 further includes active pillars located between adjacent first trenches 104, and the second dielectric layer 118 includes a first silicon oxide layer. Step S106 includes: growing the first silicon oxide layer on the sidewall of the first trench 104 using a thermal oxidation process. Compared with other methods of forming the second dielectric layer 118, the process steps of forming the second dielectric layer 118 using the thermal oxidation process are simple and convenient, reducing the production cost of semiconductor structures.
[0106] Continue to refer to Figure 7In one embodiment, the angle β between the bottom of the second dielectric layer 118 and the first direction is greater than 0 degrees and less than or equal to 90 degrees; wherein, the first direction refers to the direction in which the bottom of the first trench 104 points to the opening of the first trench 104. Specifically, when the ratio between the distance D1 in the first direction between the upper surface of the first dielectric layer 202 and the opening of the first trench 104 and the width W1 in the second direction of the first dielectric layer 202 is less than or equal to a preset value, the difference between the concentration of the oxidant on the upper surface of the first dielectric layer 202 and the concentration of the oxidant at the top of the first trench during the thermal oxidation process can be ignored. At this time, the bottom of the second dielectric layer 118 is parallel to the second direction, and the angle β is equal to 90 degrees, wherein, the second direction refers to the direction of the line connecting adjacent first trenches 104, and the second direction is perpendicular to the first direction. When the ratio between the distance D1 in the first direction between the upper surface of the first dielectric layer 202 and the opening of the first trench 104 and the width W1 in the second direction of the first dielectric layer 202 is greater than a preset value, the difference between the concentration of the oxidant on the upper surface of the first dielectric layer 202 and the concentration of the oxidant at the top of the first trench is large during the thermal oxidation process. At this time, the bottom width of the second dielectric layer 118 is smaller than the top width of the second dielectric layer 118. Here, the width refers to the width of the second dielectric layer along the second direction. The bottom of the second dielectric layer 118 has an inclined angle with the first direction, and the angle β is greater than 0 degrees and less than 90 degrees.
[0107] Figure 8 This is a flowchart illustrating step S108 in one embodiment. Figure 9 for Figure 7 A cross-sectional view of the semiconductor structure after the formation of the first work function material layer in one corresponding embodiment. Figure 10 for Figure 9 A cross-sectional schematic diagram of the semiconductor structure after forming the first work function structure in one corresponding embodiment. Figure 11 for Figure 10 A cross-sectional view of the semiconductor structure after forming the second work function material layer in one corresponding embodiment. Figure 12 for Figure 11 A cross-sectional schematic diagram of the semiconductor structure after the formation of the second work function layer in one corresponding embodiment. For example... Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 As shown, in one embodiment, step S108 includes:
[0108] S402, the first work function material layer is filled into the second trench.
[0109] like Figure 9As shown, the second trench 120 is filled with a first work function material layer 122. For example, the upper surface of the first work function material layer 122 is higher than or equal to the upper surface of the substrate 102.
[0110] S404, remove the excess first work function material layer to obtain a first work function structure with the upper surface lower than the upper surface of the substrate.
[0111] like Figure 10 As shown, the excess first work function material layer 122 in the second trench 120 is removed by an etching process, resulting in a first work function structure 204 formed by the remaining first work function material layer 122 in the second trench 120. The upper surface of the first work function structure 204 is lower than the upper surface of the substrate 102. It can be understood that when the upper surface of the first work function material layer 122 is higher than or equal to the upper surface of the substrate 102, the excess first work function material layer 122 in the second trench 120 can be completely removed along with the first work function material layer 122 on the substrate 102, or a portion of the first work function material layer 122 on the substrate 102 can be removed along with the excess first work function material layer 122 in the second trench 120, and then the remaining first work function material layer 122 on the substrate 102 can be removed after the first work function structure 204 is formed.
[0112] S406, a second work function material comprising a second metallic material is formed on the upper surface of the first work function structure.
[0113] like Figure 11 As shown, a second work function material layer 124 is formed on the upper surface of the first work function structure 204. The second work function material layer 124 includes a second metallic material, that is, the second work function material layer 124 fills the second trench 120 in which the first work function structure 204 is not formed. The height T1 of the second work function material layer 124 in the first direction only needs to meet the requirements of subsequent formation of the work function structure. In one embodiment, the upper surface of the second work function material layer 124 is not lower than the upper surface of the substrate 102, that is, the upper surface of the second work function material layer 124 is higher than the upper surface of the substrate 102, or the upper surface of the second work function material layer 124 is flush with the upper surface of the substrate 102.
[0114] S408, an annealing process is used to diffuse the second metal material to the upper part of the first work function structure, resulting in a first work function layer and a second work function layer.
[0115] like Figure 12As shown, an annealing process (such as rapid annealing or plasma annealing) is used to diffuse the second metal material in the second work function material layer 124 to the upper part of the first work function structure 204, forming the second work function layer 206. At the same time, a first work function layer 208 is obtained, which is composed of the remaining first work function structure 204. That is, the part of the first work function structure 204 that is diffused by the second metal material forms the second work function layer 206, and the remaining part is the first work function layer 208.
[0116] Figure 13 This is a schematic cross-sectional view of the semiconductor structure after the formation of the isolation material layer in one embodiment, as shown below. Figure 13 As shown, in one embodiment, step S408 further includes: removing the second work function material layer 124 on the upper surface of the second work function layer 206.
[0117] Figure 14 This is a cross-sectional schematic diagram of the semiconductor structure after the formation of the isolation material layer in another embodiment, as shown below. Figure 14 As shown, in one embodiment, the work function structure 126 further includes a third work function layer 210 located on the upper surface of the second work function layer 206. After step S408, the method further includes: removing a portion of the second work function material layer 124 on the upper surface of the second work function layer 206 to obtain a third work function layer 210 composed of the remaining second work function material layer 124. The work function of the third work function layer 210 is less than that of the second work function layer 206. This setting can further reduce the work function of the work function structure 126, thereby further reducing the leakage current of the semiconductor structure with the work function structure 126 as the gate structure and improving the electrical stability and performance of the semiconductor structure. For example, the upper surface of the third work function layer 210 is lower than the upper surface of the substrate 102.
[0118] In one embodiment, the first work function material layer 122 includes a third metal material, the work function of which is greater than that of the second metal material.
[0119] In one embodiment, the third metallic material includes titanium, and the second metallic material includes at least one of lanthanum, zirconium, hafnium, and aluminum.
[0120] In one embodiment, the first work function material layer 122 includes a titanium nitride material layer, and the second work function material layer 124 includes a lanthanum oxide material layer or a zirconium oxide material layer.
[0121] like Figure 13As shown, in one embodiment, in the first direction, the height T2 of the second work function layer 206 is greater than or equal to the height T3 of the first work function layer 208. The work function of the second work function layer 206 is less than that of the first work function layer 208. With the height of the work function structure 126 remaining constant in the first direction, increasing the height T2 of the second work function layer 206 can reduce the work function of the work function structure 126, thereby improving the electrical stability and performance of the semiconductor structure. For example, the ratio of height T2 to height T3 is greater than or equal to 1 and less than or equal to 2, such as 1, 1.3, 1.5, 1.7, 1.9, 2.0, etc.
[0122] like Figure 14 As shown, in one embodiment, in the first direction, the height T4 of the third work function layer 210 is greater than or equal to the height T2 of the second work function layer 206, and the height T4 of the third work function layer 210 is greater than or equal to the height T3 of the first work function layer 208. The work function of the third work function layer 210 is less than the work function of the second work function layer 206 and less than the work function of the first work function layer 208. With the height of the work function structure 126 remaining unchanged in the first direction, increasing the height T4 of the third work function layer 210 can further reduce the work function of the work function structure 126, thereby improving the electrical stability and performance of the semiconductor structure.
[0123] like Figure 13 , Figure 14 As shown, in one embodiment, the upper surface of the work function structure 126 is lower than the upper surface of the substrate 102. After the work function structure 126 is filled in the second trench 120, the method further includes: forming an isolation material layer 128 on the upper surface of the work function structure 126. The upper surface of the isolation material layer 128 is not lower than the upper surface of the substrate 102. The work function structure 126 can be isolated by the isolation structure layer 128, thereby eliminating the influence of the external environment on the work function structure 126.
[0124] In one embodiment, the insulating material layer 128 and the protective material layer 116 are made of the same material.
[0125] Continue to refer to Figure 14In one embodiment, the method for fabricating the semiconductor structure further includes forming a source region and a drain region in an active pillar between adjacent first trenches 104. The active pillar between the work function structures 126 in adjacent first trenches 104 is a drift region 212. A first portion 214 between the drift region 212 and the bit line structure 114, and a second portion 216 between the drift region and the upper surface of the substrate 102, are respectively the source region and the drain region. For example, the first portion 214 between the drift region 212 and the bit line structure 114 is the drain region, and the second portion 216 between the drift region and the upper surface of the substrate 102 is the source region. It is understood that the source region and the drain region can be formed before or after the formation of the work function structure 126; this is not limited here.
[0126] In one embodiment, the method for fabricating the semiconductor structure further includes: forming a capacitor structure on an isolation material layer 128, wherein the capacitor structure is electrically connected to a work function structure 126 (not shown in the figure) through a conductive structure penetrating the isolation material layer 128.
[0127] It should be understood that, although Figure 1 , Figure 2 , Figure 3 , Figure 8 The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figure 1 , Figure 2 , Figure 3 , Figure 8 At least some of the steps in the process may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least some of the sub-steps or stages of other steps.
[0128] like Figure 4 , Figure 7 , Figure 13As shown, this application also provides a semiconductor structure, including: a substrate 102, a protective material layer 116, a first dielectric layer 202, a second dielectric layer 118, and a work function structure 126, wherein a first trench 104 is formed in the substrate 102; the protective material layer 116 is located in the first trench 104; the first dielectric layer 202 is located on the sidewall of the first trench 104 and is located between the protective material layer 116 and the substrate 102; the second dielectric layer 118 is located on the sidewall of the first trench 104 and is located between the protective material layer 116 and the substrate 102. A dielectric layer 202 is in contact with and located between a protective material layer 116 and a substrate 102. A second trench 120 is formed between a second dielectric layer 118 and a protective material layer 116. A work function structure 126 is located in the second trench 120. The work function structure 126 includes a first work function layer 208 and a second work function layer 206. The second work function layer 206 is located on the upper surface of the first work function layer 208, and the work function of the second work function layer 206 is smaller than that of the first work function layer 208.
[0129] Specifically, the substrate 102 can be made of undoped single-crystal silicon, doped single-crystal silicon, silicon-on-insulator (SOI), silicon-on-insulator stacked (SSOI), silicon-on-insulator stacked (S-SiGeOI), silicon-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), etc. As an example, in this embodiment, the substrate 102 is made of single-crystal silicon. The first dielectric layer 202 is located between the protective material layer 116 and the substrate 102. The upper surface of the first dielectric layer 202 is lower than the upper surface of the substrate 102, thereby exposing part of the sidewalls of the first trench 104. It is understood that the first dielectric layer 202 is located on the sidewalls of the first trench 104 away from the opening, and the sidewalls of the first trench 104 near the opening are exposed and not covered by the first dielectric layer 202. For example, the first dielectric layer 202 may extend along the sidewall of the first trench 104 and cover the bottom of the first trench 104, or it may only cover the sidewall of the first trench 104 away from the opening. The second dielectric layer 118 is located on the sidewall of the first trench 104 near the opening and not covered by the first dielectric layer 202. The second dielectric layer 118 is in contact with the first dielectric layer 202 located on the sidewall of the first trench 104, and the gap between the second dielectric layer 118 and the protective material layer 116 in the first trench 104 is the second trench 120. The work function structure 126 is located in the second trench 120. The work function structure 126 can serve as the gate structure of a transistor and the word line structure of a memory device. The work function of the second work function layer 206 is lower than the work function of the first work function layer 208.
[0130] In the aforementioned semiconductor structure, a first trench is formed in the substrate, a protective material layer is located within the first trench, a first dielectric layer is located between the protective material layer and the substrate, a second dielectric layer is located on the exposed sidewall of the first trench and in contact with the first dielectric layer, a second trench is formed between the second dielectric layer and the protective material layer, and a work function structure is located within the second trench. The work function structure includes a first work function layer and a second work function layer located on the upper surface of the first work function layer, and the work function of the second work function layer is smaller than that of the first work function layer. Without changing the resistance, the leakage current of the semiconductor structure with the work function structure as the gate structure is reduced, thereby improving the electrical stability and performance of the semiconductor structure.
[0131] In one embodiment, the constituent material of the first dielectric layer 202 includes one or more of nitrides, oxides, and oxynitrides, such as silicon dioxide, silicon nitride, and silicon oxynitride. For example, the constituent material of the first dielectric layer 202 is silicon dioxide.
[0132] like Figure 4 As shown, in one embodiment, the semiconductor structure further includes a barrier layer 108 located on the substrate 102. The barrier layer 108 isolates the substrate 102 (active pillars) between adjacent first trenches 104, preventing the substrate 102 (active pillars) between adjacent first trenches 104 from being affected during the subsequent formation of metal silicide. Exemplarily, the material constituting the barrier layer 108 includes one or more of nitrides, oxides, and oxynitrides, such as silicon dioxide, silicon nitride, and silicon oxynitride.
[0133] In one embodiment, the semiconductor structure further includes a hard mask layer 110 located on the substrate 102. The hard mask layer 110 defines the morphology and location of the first trench 104. The hard mask layer 110 also serves as an isolation structure during the metal silicide formation process, further preventing the formation of the metal silicide from affecting the substrate 102 (active pillars) between adjacent first trenches 104. Exemplarily, the hard mask layer 110 is formed on the upper surface of the barrier layer 108. Exemplarily, the constituent material of the hard mask layer 110 includes one or more of nitrides, oxides, and oxynitrides, such as silicon dioxide, silicon nitride, and silicon oxynitride. It is understood that the constituent materials of the hard mask layer 110 and the barrier layer 108 can be the same or different; for example, the constituent material of the hard mask layer 110 is silicon nitride, and the constituent material of the barrier layer 108 is silicon dioxide.
[0134] In one embodiment, the substrate 102 includes a silicon substrate; the bottom of the first trench 104 exposes a portion of the silicon substrate, and the semiconductor structure further includes a metal silicide 112 located at the bottom of the first trench 104, with adjacent metal silicides 112 at the bottom of the first trench 104 in contact to form a bit line structure 114 located in the substrate. Exemplarily, the first metal material in the metal silicide 112 includes one or more of cobalt, tungsten, aluminum, and titanium.
[0135] In one embodiment, the protective material layer 116 is composed of one or more of nitrides, oxides, and oxynitrides, such as silicon dioxide, silicon nitride, and silicon oxynitride. It is understood that at least one of the protective material layer 116, the hard mask layer 110, and the barrier layer 108 may be composed of a different material than the others, or all of them may be different; for example, the protective material layer 116 may be composed of silicon nitride.
[0136] In one embodiment, the second dielectric layer 118 is composed of one or more of nitrides, oxides, and oxynitrides, such as silicon dioxide, silicon nitride, and silicon oxynitride. It is understood that the material of the second dielectric layer 118 may be the same as or different from the first dielectric layer 202. Exemplarily, the second dielectric layer 118 extends along the sidewall of the first trench 104 and covers the substrate 102, serving to isolate the active pillar from the external environment.
[0137] like Figure 7In one embodiment, the bottom of the second dielectric layer 118 forms an angle greater than 0 degrees and less than or equal to 90 degrees with the first direction; wherein, the first direction refers to the direction in which the bottom of the first trench 104 points to the opening of the first trench 104. Specifically, when the ratio between the distance D1 in the first direction between the upper surface of the first dielectric layer 202 and the opening of the first trench 104 and the width W1 in the second direction of the first dielectric layer 202 is less than or equal to a preset value, the difference between the concentration of the oxidant on the upper surface of the first dielectric layer 202 and the concentration of the oxidant at the top of the first trench during the thermal oxidation process can be ignored. At this time, the bottom of the second dielectric layer 118 is parallel to the second direction, and the angle β is equal to 90 degrees, wherein, the second direction refers to the direction of the line connecting adjacent first trenches 104, and the second direction is perpendicular to the first direction. When the ratio between the distance D1 in the first direction between the upper surface of the first dielectric layer 202 and the opening of the first trench 104 and the width W1 in the second direction of the first dielectric layer 202 is greater than a preset value, the difference between the concentration of the oxidant on the upper surface of the first dielectric layer 202 and the concentration of the oxidant at the top of the first trench is large during the thermal oxidation process. At this time, the bottom width of the second dielectric layer 118 is smaller than the top width of the second dielectric layer 118. Here, the width refers to the width of the second dielectric layer along the second direction. The bottom of the second dielectric layer 118 has an inclined angle with the first direction, and the angle β is greater than 0 degrees and less than 90 degrees.
[0138] In one embodiment, the second work function layer 206 includes a second metallic material, and the first work function layer 208 includes a third metallic material, wherein the work function of the third metallic material is greater than that of the second metallic material.
[0139] In one embodiment, the third metallic material includes titanium, and the second metallic material includes at least one of lanthanum, zirconium, hafnium, and aluminum.
[0140] like Figure 14 As shown, in one embodiment, the work function structure 126 further includes a third work function layer 210, which is located on the upper surface of the second work function layer 206; wherein the third work function layer 210 includes a second metal material. The work function of the third work function layer 210 is smaller than that of the second work function layer 206. This arrangement can further reduce the work function of the work function structure 126, thereby further reducing the leakage current of the semiconductor structure with the work function structure 126 as the gate structure and improving the electrical stability and performance of the semiconductor structure. Exemplarily, the upper surface of the third work function layer 210 is lower than the upper surface of the substrate 102.
[0141] In one embodiment, the first work function layer 208 includes a titanium nitride layer, and the second work function layer 206 includes a lanthanum oxide layer or a zirconium oxide layer.
[0142] like Figure 13 As shown, in one embodiment, in the first direction, the height T2 of the second work function layer 206 is greater than or equal to the height T3 of the first work function layer 208. The work function of the second work function layer 206 is less than that of the first work function layer 208. With the height of the work function structure 126 remaining constant in the first direction, increasing the height T2 of the second work function layer 206 can reduce the work function of the work function structure 126, thereby improving the electrical stability and performance of the semiconductor structure. For example, the ratio of height T2 to height T3 is greater than or equal to 1 and less than or equal to 2, such as 1, 1.3, 1.5, 1.7, 1.9, 2.0, etc.
[0143] like Figure 14 As shown, in one embodiment, in the first direction, the height T4 of the third work function layer 210 is greater than or equal to the height T2 of the second work function layer 206, and the height T4 of the third work function layer 210 is greater than or equal to the height T3 of the first work function layer 208. The work function of the third work function layer 210 is less than the work function of the second work function layer 206 and less than the work function of the first work function layer 208. With the height of the work function structure 126 remaining unchanged in the first direction, increasing the height T4 of the third work function layer 210 can further reduce the work function of the work function structure 126, thereby improving the electrical stability and performance of the semiconductor structure.
[0144] like Figure 13 , Figure 14 As shown, in one embodiment, the upper surface of the work function structure 216 is lower than the upper surface of the substrate. The semiconductor structure also includes an isolation material layer 128 located on the upper surface of the work function structure 126. The upper surface of the isolation material layer 128 is not lower than the upper surface of the substrate 102. The work function structure 126 can be isolated by the isolation structure layer 128, thereby eliminating the influence of the external environment on the work function structure 126.
[0145] In one embodiment, the insulating material layer 128 and the protective material layer 116 are made of the same material.
[0146] Continue to refer to Figure 14In one embodiment, the semiconductor structure further includes a source region and a drain region, both located in active pillars between adjacent first trenches 104. The drift region 212 is an active pillar located between work function structures 126 in adjacent first trenches 104. The first portion 214 between the drift region 212 and the bit line structure 114 and the second portion 216 between the drift region and the upper surface of the substrate 102 are the source region and the drain region, respectively. For example, the first portion 214 between the drift region 212 and the bit line structure 114 is the drain region, and the second portion 216 between the drift region and the upper surface of the substrate 102 is the source region.
[0147] In one embodiment, the semiconductor structure further includes a capacitor structure located on the isolation material layer 128, the capacitor structure being electrically connected to the work function structure 126 (not shown) through a conductive structure penetrating the isolation material layer 128.
[0148] In one embodiment, the semiconductor structure includes a transistor or a memory device.
[0149] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0150] The above-described embodiments are merely illustrative of several implementation methods of the embodiments of this application, and their descriptions are relatively specific and detailed. However, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the embodiments of this application, and these all fall within the protection scope of the embodiments of this application. Therefore, the protection scope of the patent for the embodiments of this application should be determined by the appended claims.
Claims
1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, wherein a first groove is formed in the substrate; A first dielectric layer and a protective material layer are formed in the first trench; The first dielectric layer is located between the protective material layer and the substrate, and the upper surface of the first dielectric layer is lower than the upper surface of the substrate to expose part of the sidewall of the first trench; A second dielectric layer is formed on the sidewall exposed by the first trench, a second trench is formed between the second dielectric layer and the protective material layer, and the second dielectric layer is in contact with the first dielectric layer; A work function structure is formed by filling the second trench, the work function structure including a first work function layer and a second work function layer; Wherein, the second work function layer is located on the upper surface of the first work function layer, and the work function of the second work function layer is smaller than the work function of the first work function layer; The successful filling function structure in the second trench includes: The second trench is filled with a first work function material layer; The excess first work function material layer is removed to obtain a first work function structure, wherein the upper surface of the first work function structure is lower than the upper surface of the substrate; A second work function material layer is formed on the upper surface of the first work function structure, the upper surface of the second work function material layer is not lower than the upper surface of the substrate, and the second work function material layer includes a second metal material; An annealing process is used to diffuse the second metal material to the upper part of the first work function structure to form a second work function layer, while simultaneously obtaining a first work function layer composed of the remaining first work function structure. The work function structure further includes a third work function layer located on the upper surface of the second work function layer, and the annealing process further includes: By removing a portion of the second work function material layer from the upper surface of the second work function layer, the third work function layer is obtained, which is composed of the remaining second work function material layer.
2. The preparation method according to claim 1, characterized in that, The formation of the first dielectric layer and the protective material layer within the first trench includes: A first dielectric material layer is formed on the inner wall of the first trench; Remove the first dielectric material layer at the bottom of the first trench; Fill the first trench with a protective material layer; The portion of the first dielectric material layer adjacent to the upper surface of the substrate is removed, and the remaining first dielectric material layer is the first dielectric layer.
3. The preparation method according to claim 2, characterized in that, The substrate includes a silicon substrate; a portion of the silicon substrate is exposed at the bottom of the first trench, and the process of removing the first dielectric material layer at the bottom of the first trench further includes: Inject the first metallic material into the bottom of the first trench; An annealing process is performed to react the first metal material with the silicon substrate to form a metal silicide; The metal silicides at the bottom of the adjacent first trench are in contact.
4. The preparation method according to claim 1, characterized in that, The substrate further includes active pillars located between adjacent first trenches, the second dielectric layer includes a first silicon oxide layer, and forming the second dielectric layer on the exposed sidewalls of the first trenches includes: The first silicon oxide layer is grown on the sidewall of the first trench using a thermal oxidation process.
5. The preparation method according to claim 4, characterized in that, The angle between the bottom of the second dielectric layer and the first direction is greater than 0 degrees and less than or equal to 90 degrees; Wherein, the first direction refers to the direction from the bottom of the first trench to the opening of the first trench.
6. The preparation method according to claim 1, characterized in that, The annealing process further includes: Remove the second work function material layer from the upper surface of the second work function layer.
7. The preparation method according to claim 1, characterized in that, The first work function material layer includes a third metal material, the work function of which is greater than that of the second metal material.
8. The preparation method according to claim 7, characterized in that, The third metallic material includes titanium, and the second metallic material includes at least one of lanthanum, zirconium, hafnium, and aluminum.
9. The preparation method according to claim 1, characterized in that, The height of the second work function layer is greater than or equal to the height of the first work function.
10. The preparation method according to claim 1, characterized in that, The upper surface of the work function structure is lower than the upper surface of the substrate, and after filling the second trench to form the work function structure, the process further includes: An isolation material layer is formed on the upper surface of the work function structure, and the upper surface of the isolation material layer is not lower than the upper surface of the substrate.
11. The preparation method according to claim 10, characterized in that, The insulating material layer and the protective material layer are made of the same material.
12. A semiconductor structure, prepared by any of the methods described in claims 1-11, characterized in that, include: A substrate, wherein a first groove is formed in the substrate; A protective material layer is located within the first trench; A first dielectric layer is located on the sidewall of the first trench and between the protective material layer and the substrate; A second dielectric layer is located on the sidewall of the first trench and in contact with the first dielectric layer, and is located between the protective material layer and the substrate, wherein a second trench is formed between the second dielectric layer and the protective material layer; A work function structure is located in the second trench, and the work function structure includes a first work function layer and a second work function layer. The second work function layer is located on the upper surface of the first work function layer, and the work function of the second work function layer is smaller than the work function of the first work function layer.
13. The semiconductor structure according to claim 12, characterized in that, The angle between the bottom of the second dielectric layer and the first direction is greater than 0 degrees and less than or equal to 90 degrees; Wherein, the first direction refers to the direction from the bottom of the first trench to the opening of the first trench.
14. The semiconductor structure according to claim 12, characterized in that, The second work function layer includes a second metallic material, and the first work function layer includes a third metallic material, wherein the work function of the third metallic material is greater than that of the second metallic material.
15. The semiconductor structure according to claim 14, characterized in that, The third metallic material includes titanium, and the second metallic material includes at least one of lanthanum, zirconium, hafnium, and aluminum.
16. The semiconductor structure according to claim 14, characterized in that, The work function structure also includes: A third work function layer is located on the upper surface of the second work function layer; wherein the third work function layer includes the second metal material.
17. The semiconductor structure according to claim 12, characterized in that, The upper surface of the work function structure is lower than the upper surface of the substrate, and further includes: An isolation material layer is located on the upper surface of the work function structure, and the upper surface of the isolation material layer is not lower than the upper surface of the substrate.
18. The semiconductor structure according to claim 12, characterized in that, The height of the second work function layer is greater than or equal to the height of the first work function.