LVDS Receiver Circuit and Chip with Wide Input Common-Mode Range

Abstract

The present invention discloses a low-voltage differential signal (LVDS) receiving circuit and a chip with a wide input common-mode range, which relates to the technical field of data processing circuits. The input stage of the LVDS receiving circuit includes a first-stage input terminal, a second-stage input terminal, two groups of PMOS transistor input differential pairs, a level-shifting module, a PMOS transistor PM5 used as a switch, a reference voltage module, and a bias circuit module; the bias circuit module is used to provide a bias current I0 and its control configuration, and is used to reduce the output bias current I0 when the input common-mode level is at the intermediate level or near the reference voltage to compensate for the increase in the circuit transconductance Gm when the two groups of PMOS transistor input differential pairs work simultaneously. The present invention can not only achieve an input common-mode range close to rail-to-rail at a low supply voltage, but also has a small change in the circuit transconductance Gm with the common mode, significantly reducing the influence of input common-mode changes on the circuit speed, gain, hysteresis, etc.

Description

Technical Field

[0001] The present invention relates to the technical field of data processing circuits, and particularly to an LVDS receiving circuit and a chip with a wide input common-mode range. Background Art

[0002] The Low-Voltage Differential Signaling (LVDS) transmission technology was proposed in the 1990s. By using differential small-swing signals to transmit data, it can achieve higher transmission speeds, lower electromagnetic radiation interference, better anti-noise performance, and greatly reduced power consumption. Therefore, it is widely used in various communication systems.

[0003] The LDVS data transmission system includes an LDVS transmitting circuit and an LDVS receiving circuit. According to the current LVDS protocol standard, considering the ground voltage difference, direct coupling interference, transmitter interference, etc. between the transmitter and the receiver, for stable operation, the input common-mode range of the LVDS receiving circuit needs to be wide enough (must be significantly larger than the common-mode range of the LDVS transmitting circuit). Especially when the power supply voltage of the receiver is low, ideally, it is desired that the input common-mode range of the LVDS receiving circuit can reach a voltage range close to rail-to-rail. As an example, Figure 1 An example of an existing LVDS receiver circuit is illustrated. PMOS transistors PM1 and PM2 form a differential input pair. According to the positive and negative and magnitude of the differential input (VP - VN) (VP represents the positive signal, VN represents the negative signal, and the differential input signal is equal to VP - VN), the magnitude of the constant source current IBIAS flowing to the drains of PM1 and PM2 is adjusted. Combining NMOS transistors NM1, NM2, NM3, and NM4 to form a diode load with positive feedback to achieve signal amplification and the required hysteresis effect, and through the output stage composed of NM5, NM6, PM3, and PM4, further signal amplification and differential-to-single-ended output VOUT are achieved. However, this structure cannot achieve a wide input common-mode range. Assuming the absolute value of the gate-source voltage of PM1 and PM2 is |V GS |, and the overdrive voltage required for the constant source current IBIAS is V DSAT,IBIAS , then the input common-mode level V CM,IN =(VP + VN) / 2 should be less than VDD - V DSAT , IBIAS -|V GS |. When the power supply voltage VDD is low, it is difficult to meet the standard range required by the LVDS protocol.

[0004] To achieve a near rail-to-rail input common-mode range, the input stage of a typical current LVDS receiving circuit usually uses a combination of a PMOS (Positive channel Metal Oxide Semiconductor) transistor differential pair and an NMOS (Negative channel Metal Oxide Semiconductor) transistor differential pair: when the input common-mode level is low, the PMOS transistor differential pair operates; when the input common-mode level is high, the NMOS transistor differential pair operates; when the input common-mode level is at an intermediate level, both the PMOS transistor differential pair and the NMOS transistor differential pair operate. See Figure 2 As shown, an existing LVDS receiver circuit that realizes a near rail-to-rail input common-mode range is exemplified. This scheme uses a folded operational amplifier composed of a PMOS transistor differential input pair PM1, PM2 and an NMOS transistor differential input pair NM1, NM2 in combination to expand the input common-mode range. When the input common-mode level is low, the PMOS differential input pair PM1, PM2 operates; when the input common-mode level is high, the NMOS differential input pair NM1, NM2 operates; when the input common-mode level is at an intermediate level, both the PMOS input differential pair PM1, PM2 and the NMOS input differential pair NM1, NM2 operate. However, this operating mode will cause the total transconductance Gm, bias current, etc. of the circuit to vary significantly with the input common mode, resulting in a large circuit delay and a small gain in some cases. Moreover, since the gain of the input stage varies greatly with process, temperature, and power supply voltage, it is difficult to achieve a stable hysteresis voltage.

[0005] Accordingly, the prior art also provides some solutions for expanding the input common-mode range by increasing the level shift, such as the input stage for an LVDS receiver circuit disclosed in Chinese Patent Application CN201880065454.3: including at least one power supply voltage connection terminal, a first-stage input terminal and a second-stage input terminal, and the first-stage input terminal and the second-stage input terminal are used for applying a differential input signal pair; the input stage further includes a first differential stage and a second differential stage, wherein the stage input terminals are directly connected to the input terminals of the first differential stage respectively, and are indirectly connected to the input terminals of the second differential stage through a level shift circuit respectively; the input stage further includes two stage output terminals, and the stage output terminals respectively have a connection formed by one output terminal of the first differential stage and one output terminal of the second differential stage; the first differential stage and the second differential stage are respectively connected to the power supply voltage connection terminal through the transistors of the third differential stage, wherein, the control input terminal of one of these transistors is connected to a measurement path, and this measurement path connects the stage input terminals to each other, while the control input terminals of the other transistors are used for providing a reference voltage. The core of the above solution lies in: expanding the common-mode input range by using two sets of input differential pairs and a level shift circuit for reducing the input common-mode level, and at the same time setting a third set of differential pairs, the first set of differential pairs and the second set of differential pairs are respectively connected to the power supply voltage connection terminal through the transistors of the third set of differential pairs, the control input terminal of one transistor in the third set of differential pairs is connected to the reference voltage, the control input terminal of the other transistor in the third set of differential pairs is connected to the measurement path, and the measurement path (specifically, it can be a series circuit composed of two identical resistors, see the measurement path 20 composed of resistors 32 and 33 in Figure 3 ) connects the two stage input terminals to each other, and makes the reference voltage be V REF , connects the input VP (positive signal) and VN (negative signal) through the two identical resistors of the foregoing measurement path, and the potential at the connection of the two resistors is the input common-mode level V CM,IN =(VP + VN) / 2, and the other transistor in the third set of differential pairs is connected to the connection of R1 and R2; by comparing the foregoing reference voltage V REF with the foregoing input common-mode level V CM,IN , to adjust the amount of the constant source current flowing to the drains of the two transistors in the third set of differential pairs; the advantage of the above input stage is that it can maximize the allowed common-mode range, and at the same time has a fixed bias current (that is, it does not change with the input common mode), and it is easy to integrate a hysteresis function, can eliminate the correlation between current consumption and the common mode, and reduce the correlation between circuit parameters such as hysteresis and delay time and the common mode. However, the above solution still has the disadvantage that the total circuit transconductance Gm changes greatly with the common mode (especially when the two transistors of the first set of differential pairs and the two transistors of the second set of differential pairs work simultaneously, the total circuit transconductance Gm increases relatively significantly), resulting in obvious changes in the speed, gain, hysteresis, etc. of the circuit with the common mode.

[0006] In summary, how to provide an LVDS receiving circuit that can achieve a near rail-to-rail input common-mode range under a low power supply voltage, while the circuit transconductance Gm changes less with the common mode is a technical problem that urgently needs to be solved currently. Summary of the Invention

[0007] The purpose of the present invention is to overcome the deficiencies of the prior art and provide an LVDS receiving circuit and chip with a wide input common-mode range. The LVDS receiving circuit with a wide input common-mode range provided by the present invention can not only achieve a near rail-to-rail input common-mode range under a low power supply voltage, but also the circuit transconductance Gm changes less with the common mode. Furthermore, the speed, gain, hysteresis, etc. of the circuit change less with the common mode, significantly reducing the influence of the input common mode change on the speed, gain, hysteresis, etc. of the circuit.

[0008] To achieve the above objectives, the present invention provides the following technical solutions:

[0009] A low-voltage differential signal (LVDS) receiving circuit with a wide input common-mode range includes an input stage. The input stage includes a first-stage input terminal and a second-stage input terminal, a first group of PMOS transistor input differential pairs and a second group of PMOS transistor input differential pairs, and a level-shifting module. The first-stage input terminal and the second-stage input terminal are used to apply a differential input signal pair VP and VN. The differential input signal pair VP and VN are directly connected to the gates of two transistors of the second group of PMOS transistor input differential pairs respectively to control the drain currents of the two transistors. The differential input signal pair VP and VN are also indirectly connected to the gates of two transistors of the first group of PMOS transistor input differential pairs respectively through the level-shifting module to control the drain currents of the two transistors. The level-shifting module is used to reduce the input common-mode level.

[0010] The input stage further includes a PMOS transistor PM5 used as a switch, a reference voltage module, and a bias circuit module.

[0011] The drain of the transistor PM5 is connected to the sources of two transistors of the first group of PMOS transistor input differential pairs to a first node. At the same time, the source of the transistor PM5 is connected to the sources of two transistors of the second group of PMOS transistor input differential pairs to a second node. At the same time, the gate of the transistor PM5 is connected to the reference voltage module.

[0012] The reference voltage module provides a reference voltage V REF to the transistor PM5, and V REF serves as the gate voltage of the transistor PM5.

[0013] The bias circuit module is used to provide the bias current I0 of the input stage and perform control configuration of the bias current. Among them, the bias circuit module is configured to: when it is determined that the input common-mode level is at the intermediate level or the difference between the input common-mode level and the reference voltage V REF is within a preset range, reduce the output bias current I0 so that the bias current I0 flowing to the aforementioned first node and second node is reduced.

[0014] Furthermore, the bias current I0 output by the bias circuit module is related to the input common-mode level V CM,IN , and the input common-mode level V CM,IN = (VP + VN) / 2, where VP represents the positive terminal signal and VN represents the negative terminal signal;

[0015] The relationship expression between the bias current I0 and the input common-mode level V CM,IN is I0 = I 固定 + f(V CM,IN ). In the formula, I 固定 is independent of the input common-mode level V CM,IN , and f(V CM,IN ) represents a function related to the input common-mode level V CM,IN ;

[0016] Configure the weight ratio of f(V CM,IN ) in the aforementioned relationship expression to reduce the influence of the input common-mode level V CM,IN on the bias current I0. Among them, when configuring the f(V CM,IN ) function, when the difference between the input common-mode level V CM,IN and the power supply voltage or the ground voltage is within a preset range, let f(V CM,IN ) = 0; when the difference between the power supply voltage and the reference voltage V REF is within a preset range, let f(V CM,IN ) be a preset negative value.

[0017] Furthermore, the bias circuit module includes a comparison unit and a bias current I0 control unit;

[0018] The comparison unit is configured to: compare the input common-mode level with the reference voltage V REF , the power supply voltage and the ground voltage, and send the comparison result to the bias current I0 control unit;

[0019] The bias current I0 control unit is configured to: obtain the foregoing comparison result, and when the difference between the input common-mode level and the ground voltage is within a preset range, determine that the input common-mode level is close to the ground voltage, the transistor PM5 is in the off state, and the bias current I0 all flows to the foregoing second node. At this time, the two transistors PM3 and PM4 of the second group of PMOS transistor input differential pairs are working; and,

[0020] When the difference between the input common-mode level and the power supply voltage is within a preset range, determine that the input common-mode level is close to the power supply voltage, the two transistors of the second group of PMOS transistor input differential pairs are turned off, and the bias current I0 mainly flows to the source of the transistor PM5. At this time, the two transistors PM1 and PM2 of the first group of PMOS transistor input differential pairs are working, and the DC levels of the differential input signals VP and VN are reduced through the level shift module; and,

[0021] When the difference between the input common-mode level and the reference voltage V REF is within a preset range, determine that the common-mode level is near the reference voltage V REF The bias current I0 flows to the foregoing first node and second node at the same time. At this time, the two transistors of the first group of PMOS transistor input differential pairs and the two transistors of the second group of PMOS transistor input differential pairs work at the same time; the output bias current I0 is adjusted downwards so that the bias current I0 flowing to the two groups of PMOS transistor input differential pairs is reduced.

[0022] Furthermore, the bias circuit module includes PMOS transistors PM0, PM8, PM9, PM10, and PM11, NMOS transistors NM1, NM2, and NM3, and two resistors R3 and R4 with equal resistance values;

[0023] The drain of the transistor PM0 is connected to the sources of the transistors PM3 and PM4 of the second group of PMOS transistor input differential pairs to provide the bias current I0 for the input stage; the source of the transistor PM0 is connected to the power supply voltage VDD; the gate of the transistor PM0 is connected to the gate and drain of the transistor PM8, and is also connected to the drain of the transistor NM1, and is also connected to the drain of the transistor PM9; the transistors PM0 and PM8 form a current mirror; the sources of the transistors PM8 and PM9 are connected to the power supply voltage VDD;

[0024] The gate of the transistor NM1 is connected to the bias voltage V BIAS and the source is connected to the ground voltage VSS, which is used to form a current source;

[0025] The gate of transistor PM9 is connected to the gate and drain of transistor PM10, and transistors PM9 and PM10 form a current mirror; the source of transistor PM10 is connected to the power supply voltage VDD, the drain of transistor PM10 is also connected to the source of transistor PM11, the drain of transistor PM11 is connected to the drain of transistor NM2, the source of transistor NM2 is simultaneously connected to the drain and gate of transistor NM3, and the source of transistor NM3 is grounded to the voltage VSS; the gates of transistor PM11 and transistor NM2 are both connected to the connection point of resistors R3 and R4, the other end of resistor R3 is connected to the positive input signal VP of the receiving circuit, the other end of resistor R4 is connected to the negative input signal VN of the receiving circuit, and the potential at the connection point of resistors R3 and R4 is the input common-mode level V CM,IN 。

[0026] Further, let the ratio of the width-to-length ratio of transistor PM0 to that of transistor PM8 be m, and the ratio of the width-to-length ratio of transistor PM9 and transistor PM10 be 1, then the bias current I0 provided by transistor PM0 is m*I NM1 -m*I PM10 ,where I NM1 represents the current of transistor NM1, and m*I NM1 is a fixed part and does not change with the input common-mode level V CM,IN ; I PM10 represents the current of transistor PM10, and m*I PM10 is a variable part and changes with the change of the input common-mode level V CM,IN ;

[0027] When the input common-mode level is higher than the preset threshold or lower than the preset threshold, transistor PM11 or transistor NM2 is turned off, and at this time I PM10 =0, and the bias current I0 = m*I NM1 ; when the input common-mode level is at the intermediate level or near the reference voltage V REF , the bias circuit module adjusts the sizes of transistors PM11, NM2, and NM3 so that transistors PM11 and NM2 are turned on, and makes I PM10 >0 to reduce the bias voltage I0, thereby compensating for the increase in the total circuit transconductance Gm caused by the simultaneous operation of the first group of PMOS input differential pair PM1 and PM2 and the second group of PMOS input differential pair PM3 and PM4.

[0028] Further, the input stage further includes a load module;

[0029] The drains of one transistor in the first group of PMOS input differential pairs and one transistor in the second group of PMOS input differential pairs are connected to the negative output VON1 of the input stage, and the drains of the other transistor in the first group of PMOS input differential pairs and the other transistor in the second group of PMOS input differential pairs are connected to the positive output VOP1 of the input stage; the load module is connected to the aforementioned VOP1 and VON1 for primary amplification of the signal and generation of the input common-mode level of the subsequent circuit;

[0030] The load module includes two resistors R1 and R2 with equal resistance values to ground. One end of resistor R1 is grounded, and the other end is connected to the negative output VON1. One end of resistor R2 is grounded, and the other end is connected to the positive output VOP1.

[0031] Furthermore, it also includes a comparator module after the input stage. The VOP1 and VON1 are respectively connected to the positive input and negative input of the comparator module, and the VOP1 and VON1 signals are amplified and / or shaped by the comparator module to obtain the output signal VOUT.

[0032] Furthermore, the comparator module includes PMOS transistors PM12, PM13, and PM14, NMOS transistors NM6, NM7, NM8, and NM9, and an output stage;

[0033] Transistors PM13 and PM14 serve as an input differential pair, whose gates are respectively connected to the VOP1 and VON1 signals. The sources of transistors PM13 and PM14 are connected and simultaneously connected to the drain of transistor PM12; the gate of transistor PM12 is connected to the second bias voltage V BIAS2 and the source is connected to the power supply V DDCORE to provide a bias current for transistors PM13 and PM14;

[0034] The drain of transistor PM13 is connected to the drain and gate of transistor NM8, simultaneously connected to the drain of transistor NM6, simultaneously connected to the gate of transistor NM7, and simultaneously connected to the negative input of the output stage; the drain of transistor PM14 is connected to the drain and gate of transistor NM9, simultaneously connected to the drain of transistor NM7, simultaneously connected to the gate of transistor NM6, and simultaneously connected to the positive input of the output stage;

[0035] Transistors NM6, NM7, NM8, and NM9 form a diode load with positive feedback for implementing hysteresis;

[0036] The output stage is used to amplify, differential-to-single-ended convert, and / or shape the signal and output the signal VOUT.

[0037] Further, the level-shifting module includes NMOS transistors NM4 and NM5, as well as NMOS transistors NM16 and NM17; the gates of transistors NM16 and NM17 are respectively connected to the differential input signal pair VP and VN, the sources of transistors NM16 and NM17 are respectively connected to the gates of transistors PM1 and PM2, and are also respectively connected to the drains of transistors NM4 and NM5, and the drains of transistors NM16 and NM17 are both connected to the power supply voltage VDD; the gates of transistors NM4 and NM5 are both connected to the first bias voltage V BIAS1 , the sources of transistors NM4 and NM5 are both connected to the ground voltage VSS, and transistors NM4 and NM5 are used as current sources;

[0038] And / or, the reference voltage module includes PMOS transistor PM15 and NMOS transistor NM10, the source of transistor NM10 is grounded to the voltage VSS, the gate is connected to the first bias voltage V BIAS1 , transistor NM10 is used as a current source; meanwhile, the drain of transistor NM10 is connected to the gate and drain of transistor PM15, the source of transistor PM15 is connected to the power supply voltage VDD, and the output of the drain of transistor NM10 provides the gate voltage V REF for transistor PM5.

[0039] The present invention also provides a chip, on which a receiver capable of converting LVDS signals is integrated, and the receiver includes the aforementioned LVDS receiving circuit.

[0040] Due to the adoption of the above technical solutions, compared with the prior art, for example, the present invention has the following advantages and positive effects: the LVDS receiving circuit with a wide input common-mode range can not only achieve an input common-mode range close to rail-to-rail at a low power supply voltage, but also the transconductance Gm of the circuit changes less with the common mode, so that the speed, gain, hysteresis, etc. of the circuit change less with the common mode, significantly reducing the influence of the input common mode change on the speed, gain, hysteresis, etc. of the circuit. Description of the Drawings

[0041] Figure 1 FIG. is a schematic structural diagram of an LVDS receiver circuit provided in the prior art.

[0042] Figure 2 FIG. is a schematic structural diagram of an LVDS receiver circuit provided in the prior art that realizes an input common-mode range close to rail-to-rail.

[0043] Figure 3 FIG. is a structural diagram of the input stage of another LVDS receiver circuit provided in the prior art that realizes an input common-mode range close to rail-to-rail.

[0044] Figure 4Schematic diagram of the LVDS receiving circuit with a wide input common-mode range provided by the present invention.

[0045] Figure 5 Schematic diagram of the circuit structures of the respective modules of the LVDS receiving circuit provided by the present invention.

[0046] Explanation of reference numerals:

[0047] Level-shifting module 10;

[0048] Reference voltage module 20;

[0049] Bias circuit module 30;

[0050] Load module 40;

[0051] Comparator module 50. Detailed implementation manners

[0052] The following further elaborates in detail on the LVDS receiving circuit and chip with a wide input common-mode range disclosed by the present invention in conjunction with the accompanying drawings and specific embodiments. It should be noted that the technical features or combinations of technical features described in the following embodiments should not be considered as isolated, and they can be combined with each other to achieve better technical effects. In the accompanying drawings of the following embodiments, the same reference numerals appearing in each drawing represent the same features or components, which can be applied to different embodiments. Therefore, once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0053] It should be noted that the structures, ratios, sizes, etc. shown in the drawings of this specification are only used to cooperate with the content disclosed in the specification for those skilled in this technology to understand and read, and are not used to limit the limiting conditions for the implementation of the invention. Any modification of the structure, change of the proportional relationship, or adjustment of the size, without affecting the effects that the invention can produce and the purposes that can be achieved, should fall within the scope covered by the technical content disclosed by the invention. The scope of the preferred implementation manners of the present invention includes additional implementations, in which the functions can be executed in a substantially simultaneous manner or in the reverse order according to the functions involved, rather than in the order described or discussed. This should be understood by those skilled in the technical field of the embodiments of the present invention.

[0054] For technologies, methods, and devices known to those of ordinary skill in the relevant fields, they may not be discussed in detail, but under appropriate circumstances, the said technologies, methods, and devices should be regarded as part of the specification. In all the examples shown and discussed here, any specific value should be interpreted as merely exemplary, rather than as a limitation. Therefore, other examples of the exemplary embodiments may have different values. Embodiment

[0055] SeeFigure 4 As shown, a LVDS receiving circuit with a wide input common-mode range provided by this embodiment.

[0056] The LVDS receiving circuit includes an input stage and a comparator module located after the input stage.

[0057] The input stage includes: a first-stage input terminal and a second-stage input terminal, a first group of PMOS transistor input differential pairs PM1, PM2 and a second group of PMOS transistor input differential pairs PM3, PM4, a level-shifting circuit module, a PMOS transistor PM5 used as a switch, a reference voltage module for providing a gate voltage to the transistor PM5, a bias circuit module, and a load module.

[0058] The first-stage input terminal and the second-stage input terminal are used to apply a differential input signal pair VP (positive terminal signal) and VN (negative terminal signal).

[0059] The differential input signal pair VP and VN are directly connected to the gates of two transistors PM3 and PM4 of the second group of PMOS transistor input differential pairs respectively, to control the drain currents of the two transistors PM3 and PM4. At the same time, the differential input signal pair VP and VN are also indirectly connected to the gates of two transistors PM1 and PM2 of the first group of PMOS transistor input differential pairs through the level-shifting circuit module respectively, to control the drain currents of the two transistors PM1 and PM2.

[0060] The level-shifting module is used to reduce the input common-mode level.

[0061] The drain of the transistor PM5 is connected to the sources of two transistors PM1 and PM2 of the first group of PMOS transistor input differential pairs to a first node, see Figure 4 point A in Figure 4 ; at the same time, the source of the transistor PM5 is connected to the sources of two transistors PM3 and PM4 of the second group of PMOS transistor input differential pairs to a second node, see

[0062] point B in REF ; and the gate of the transistor PM5 is connected to the reference voltage module. REF The reference voltage module provides a reference voltage V

[0063] to the transistor PM5, and V Figure 4 as the gate voltage of the transistor PM5. REFWhen the difference value is within a preset range, the output bias current I0 is lowered so that the bias current I0 flowing to the aforementioned first node and second node is reduced.

[0064] The load module is connected to the positive output VOP1 and negative output VON1 of the input stage, and is used for primary amplification of signals and generating the input common-mode level of the subsequent stage circuit. Specifically, the drains of one transistor in the first group of PMOS transistor input differential pairs and one transistor in the second group of PMOS transistor input differential pairs are connected to the negative output VON1 of the input stage, and the drains of the other transistor in the first group of PMOS transistor input differential pairs and the other transistor in the second group of PMOS transistor input differential pairs are connected to the positive output VOP1 of the input stage; the load module is connected to the aforementioned VOP1 and VON1 for primary amplification of signals and generating the input common-mode level of the subsequent stage circuit.

[0065] The comparator module is connected to the positive output VOP1 and negative output VON1 of the input stage, and is used for amplifying and / or shaping the signal to obtain the output signal VOUT.

[0066] In this embodiment, the bias current I0 output by the bias circuit module is related to the input common-mode level V CM,IN and the input common-mode level V CM,IN =(VP + VN) / 2, where VP represents the positive terminal signal and VN represents the negative terminal signal. That is, the value of the bias current I0 is affected by the input common-mode level V CM,IN =(VP + VN) / 2.

[0067] Specifically, the output bias current I0 is a related function of the input common-mode level V CM,IN , and the relationship expression is denoted as I0 = I 固定 + f(V CM,IN ), where in the formula, I 固定 is independent of the input common-mode level V CM,IN , and f(V CM,IN ) represents a function related to the input common-mode level V CM,IN . Combining Figure 4 with the example, the I 固定 = I B , that is, the fixed part of the bias current I0 is equal to the current value I B at point B.

[0068] Configure the weight ratio of f(V CM,IN ) in the aforementioned relationship expression I0 = I 固定 + f(V CM,IN ) to reduce the influence of the input common-mode level V CM,IN on the bias current I0. In this way, make f(V CM,IN)It has a relatively small weight in the configured current, thereby reducing the degree of variation of the bias current with the change of the input common-mode level.

[0069] Among them, when configuring the f(V CM,IN ) function, when the difference between the input common-mode level V CM,IN and the power supply voltage or the ground voltage is within a preset range - that is, when the input common-mode level is close to the power supply voltage and the ground voltage, let f(V CM,IN ) = 0; when the difference between the power supply voltage and the reference voltage V REF is within a preset range - that is, when the power supply voltage is close to V REF nearby, let f(V CM,IN ) be a preset negative value, thereby reducing the bias current I0.

[0070] In this embodiment, the bias circuit module may specifically include a comparison unit and a bias current I0 control unit.

[0071] The comparison unit is configured to: compare the input common-mode level with the reference voltage V REF , the power supply voltage and the ground voltage, and send the comparison result to the bias current I0 control unit.

[0072] The bias current I0 control unit is configured to: obtain the foregoing comparison result. When the difference between the input common-mode level and the ground voltage is within a preset range, it is determined that the input common-mode level is close to the ground voltage, the transistor PM5 is in the off state, and the bias current I0 all flows to the foregoing second node. At this time, the two transistors PM3 and PM4 of the second group of PMOS transistor input differential pairs work; and when the difference between the input common-mode level and the power supply voltage is within a preset range, it is determined that the input common-mode level is close to the power supply voltage, and the two transistors of the second group of PMOS transistor input differential pairs are turned off. The bias current I0 mainly flows to the source of the transistor PM5. At this time, the two transistors PM1 and PM2 of the first group of PMOS transistor input differential pairs work, and the DC levels of the differential input signals VP and VN are reduced through the level shift module; and when the difference between the input common-mode level and the reference voltage V REF is within a preset range, it is determined that the common-mode level is near the reference voltage V REF nearby, and the bias current I0 flows to the foregoing first node and second node at the same time. At this time, the two transistors of the first group of PMOS transistor input differential pairs and the two transistors of the second group of PMOS transistor input differential pairs work at the same time; the output bias current I0 is lowered so that the bias current I0 flowing to the two groups of PMOS transistor input differential pairs is reduced.

[0073] Combined with Figure 4Understand the LVDS receiver circuit shown: When the input common-mode level is close to the ground voltage, the voltage at point B is also low, and the transistor PM5 is in the off state. All the bias current I0 output by the bias circuit module flows to point B. At this time, the two transistors PM3 and PM4 of the second group of PMOS transistor input differential pair work, and through the load and the subsequent comparator circuit, the input signal is amplified and shaped to obtain the output signal VOUT. When the input common-mode level is close to the power supply voltage, the two transistors PM3 and PM4 of the second group of PMOS transistor input differential pair are turned off, the voltage at point B is high, and the bias current I0 mainly flows to the source of the transistor PM5. At this time, the level shift circuit will reduce the DC levels of the differential input signals VP and VN. The two transistors PM1 and PM2 of the first group of PMOS transistor input differential pair work, and through the load and the subsequent comparator circuit, the input signal is amplified and shaped to obtain the output signal VOUT. When the input common-mode level is near the reference voltage V REF nearby, the bias current I0 flows to the aforementioned points A and B at the same time. The two transistors PM1 and PM2 of the first group of PMOS transistor input differential pair and the two transistors PM3 and PM4 of the second group of PMOS transistor input differential pair work simultaneously. At this time, the bias circuit module can lower the output bias current I0, and then through the load module and the subsequent comparator circuit, the input signal is amplified and shaped to obtain the output VOUT. By lowering the output bias current I0, the increase in the total circuit transconductance Gm caused by the simultaneous operation of the two groups of PMOS transistor input differential pairs PM1, PM2 and PM3, PM4 can be compensated, so that the circuit transconductance Gm changes less with the common mode, and further the speed, gain, hysteresis, etc. of the circuit change less with the common mode, improving the circuit working stability.

[0074] As a preference of the typical method, see Figure 5 shown, the bias circuit module may specifically include PMOS transistors PM0, PM8, PM9, PM10 and PM11, NMOS transistors NM1, NM2 and NM3, and two resistors R3 and R4 with equal resistance values.

[0075] The drain of the transistor PM0 is connected to the sources of the transistors PM3 and PM4 of the second group of PMOS transistor input differential pair to provide the bias current I0 for the input stage; the source of the transistor PM0 is connected to the power supply voltage VDD; the gate of the transistor PM0 is connected to the gate and drain of the transistor PM8, and is also connected to the drain of the transistor NM1, and is also connected to the drain of the transistor PM9; the transistors PM0 and PM8 form a current mirror; the sources of the transistors PM8 and PM9 are connected to the power supply voltage VDD.

[0076] The gate of the transistor NM1 is connected to the bias voltage V BIAS , and the source is connected to the ground voltage VSS, which is used to form a current source.

[0077] The gate of transistor PM9 is connected to the gate and drain of transistor PM10, and transistors PM9 and PM10 form a current mirror. The source of transistor PM10 is connected to the power supply voltage VDD, the drain of transistor PM10 is also connected to the source of transistor PM11, the drain of transistor PM11 is connected to the drain of transistor NM2, the source of transistor NM2 is simultaneously connected to the drain and gate of transistor NM3, and the source of transistor NM3 is grounded to the voltage VSS.

[0078] The gates of transistor PM11 and transistor NM2 are both connected to the connection point of resistors R3 and R4. The other end of resistor R3 is connected to the positive input signal VP of the receiving circuit, the other end of resistor R4 is connected to the negative input signal VN of the receiving circuit, and the potential at the connection point of resistors R3 and R4 is the input common-mode level V CM,IN .

[0079] The adjustment and control process of the bias circuit module is as follows: Let the ratio of the width-to-length ratio of transistor PM0 to transistor PM8 be m, and the ratio of the width-to-length ratio of transistor PM9 and transistor PM10 be 1.

[0080] The bias current I0 provided by transistor PM0 = I PM0 = m * I PM8 = m * (I NM1 - I PM9 ) = m * I NM1 - m * I PM9 = m * I NM1 - m * I PM10 , where, I PM0 represents the current of transistor PM0, I PM8 represents the current of transistor PM8, I PM9 represents the current of transistor PM9, I PM10 represents the current of transistor PM10, I NM1 represents the current of transistor NM1; m * I NM1 is the fixed part and does not change with the input common-mode level V CM,IN ; m * I PM10 is the variable part and changes with the change of the input common-mode level V CM,IN .

[0081] When the input common-mode level is higher than the preset threshold or lower than the preset threshold - that is, when the input common-mode level is higher or lower, transistor PM11 or transistor NM2 is turned off. At this time, I PM10 = 0, and the bias current I0 = m * I NM1 , which is a fixed value; when the input common-mode level is at the intermediate level or at the reference voltage V REFWhen nearby, the bias circuit module can adjust the sizes of transistors PM11, NM2, and NM3 so that transistors PM11 and NM2 are turned on. At this time, I PM10 > 0, and I0 = m * I can be obtained NM1 - m * I NM10 is less than the aforementioned m * I NM1 , that is, the bias voltage I0 decreases, thereby compensating for the increase in the total circuit transconductance Gm caused by the simultaneous operation of the first group of PMOS input differential pairs PM1 and PM2 and the second group of PMOS input differential pairs PM3 and PM4.

[0082] Continuing to refer to Figure 5 shown, is a preferred implementation of each module in the LVDS receiving circuit provided by the present invention, and also exemplifies the circuit compositions of the level shift module 10, the reference voltage module 20, the load module 40, and the comparator module 50.

[0083] The level shift module 10 may specifically include NMOS transistors NM4, NM5, and NMOS transistors NM16, NM17. The gates of transistors NM16 and NM17 are respectively connected to the differential input signal pair VP and VN. The sources of transistors NM16 and NM17 are respectively connected to the gates of transistors PM1 and PM2, and are also respectively connected to the drains of transistors NM4 and NM5. The drains of transistors NM16 and NM17 are both connected to the power supply voltage VDD; the gates of transistors NM4 and NM5 are both connected to the first bias voltage V BIAS1 , the sources of transistors NM4 and NM5 are both connected to the ground voltage VSS, and transistors NM4 and NM5 are used as current sources.

[0084] The reference voltage module 20 may specifically include a PMOS transistor PM15 and an NMOS transistor NM10. The source of the transistor NM10 is grounded to the voltage VSS, and the gate is connected to the first bias voltage V BIAS1 , and the transistor NM10 is used as a current source; at the same time, the drain of the transistor NM10 is connected to the gate and drain of the transistor PM15. The source of the transistor PM15 is connected to the power supply voltage VDD, and the drain output of the transistor NM10 provides the gate voltage V REF for the transistor PM5.

[0085] The load module 40 may specifically include two ground resistors R1 and R2 with equal resistance values; one end of the resistor R1 is grounded, and the other end is connected to VON1; one end of the resistor R2 is grounded, and the other end is connected to VOP1.

[0086] The subsequent comparator module 50 has a hysteresis function and may specifically include PMOS transistors PM12, PM13, PM14, NMOS transistors NM6, NM7, NM8, NM9, and an output stage.

[0087] Transistors PM13 and PM14 serve as an input differential pair, whose gates are respectively connected to the VOP1 and VON1 signals. The sources of transistors PM13 and PM14 are connected together and are simultaneously connected to the drain of transistor PM12; the gate of transistor PM12 is connected to the second bias voltage V BIAS2 , and the source is connected to the power supply V DDCORE to provide a bias current for transistors PM13 and PM14.

[0088] The drain of transistor PM13 is connected to the drain and gate of transistor NM8, simultaneously connected to the drain of transistor NM6, simultaneously connected to the gate of transistor NM7, and simultaneously connected to the negative input terminal of the output stage; the drain of transistor PM14 is connected to the drain and gate of transistor NM9, simultaneously connected to the drain of transistor NM7, simultaneously connected to the gate of transistor NM6, and simultaneously connected to the positive input terminal of the output stage.

[0089] Transistors NM6, NM7, NM8, and NM9 form a diode load with positive feedback for realizing hysteresis.

[0090] The output stage is used to amplify, differential-to-single-ended convert, and / or shape the signal, and output the signal VOUT.

[0091] For the LVDS receiving circuit with an input common-mode range provided by the present invention, on the one hand, through two groups of PMOS transistor input differential pairs, a level shift module, a PMOS transistor used as a switch, and a reference voltage module, it can be used to achieve that the input common-mode level of the circuit can reach a range close to rail-to-rail under a low power supply voltage; on the other hand, the bias circuit module is used to adjust and control the bias current to compensate for the increase in the total transconductance Gm of the circuit caused by the simultaneous operation of the transistor pairs of the two groups of PMOS transistor input differentials, so that the transconductance Gm of the circuit changes less with the common mode, thereby reducing the influence of the input common mode change on the speed, gain, hysteresis, etc. of the circuit and improving the stability of the circuit operation.

[0092] Another embodiment of the present invention further provides a chip, on which a receiver capable of converting LVDS signals is integrated, and the receiver includes the aforementioned LVDS receiving circuit.

[0093] For other technical features, refer to the description of the previous embodiments, and details are not described herein again.

[0094] In the above description, the disclosure of the present invention is not intended to limit itself to these aspects. Instead, within the scope of the object of the present disclosure, the components can be selectively and operatively combined in any number. Additionally, terms such as "including", "comprising", and "having" should be construed as inclusive or open by default, rather than exclusive or closed, unless they are explicitly defined to the contrary. All technical, scientific, or other terms conform to the meanings understood by those skilled in the art, unless they are defined to the contrary. Common terms found in dictionaries should not be construed too idealistically or too unrealistically in the context of the relevant technical documents, unless the present disclosure explicitly defines them as such. Any changes or modifications made by those of ordinary skill in the art of the present invention based on the above disclosure fall within the scope of protection of the claims.

Claims

1. A low-voltage differential signal (LVDS) receiving circuit with a wide input common-mode range, comprising an input stage, wherein the input stage includes a first-stage input terminal and a second-stage input terminal, a first group of PMOS transistor input differential pairs and a second group of PMOS transistor input differential pairs, and a level-shifting module; the first-stage input terminal and the second-stage input terminal are used for applying a differential input signal pair VP and VN, and the differential input signal pair VP and VN are directly connected to the gates of two transistors of the second group of PMOS transistor input differential pairs respectively to control the drain currents of the two transistors; the differential input signal pair VP and VN are also indirectly connected to the gates of two transistors of the first group of PMOS transistor input differential pairs respectively through the level-shifting module to control the drain currents of the two transistors; the level-shifting module is used to reduce the input common-mode level, and is characterized in that: The input stage further includes a PMOS transistor PM5 serving as a switch, a reference voltage module and a bias circuit module; The drain of the transistor PM5 is connected to the sources of two transistors of the first group of PMOS transistor input differential pairs and connected to a first node, and at the same time the source of the transistor PM5 is connected to the sources of two transistors of the second group of PMOS transistor input differential pairs and connected to a second node, and at the same time the gate of the transistor PM5 is connected to the reference voltage module; The reference voltage module provides a reference voltage V REF to transistor PM5, V REF as the gate voltage of transistor PM5; The bias circuit module is used to provide the bias current I0 of the input stage and perform control configuration of the bias current; wherein, the bias circuit module is configured to: when it is determined that the input common-mode level is at the intermediate level or the difference between the input common-mode level and the reference voltage V REF is within a preset range, reduce the output bias current I0 so as to reduce the bias current I0 flowing to the aforementioned first node and second node.

2. The LVDS receiving circuit according to claim 1, wherein: The bias current I0 output by the bias circuit module is related to the input common-mode level V CM,IN wherein the input common-mode level V CM,IN = (VP + VN) / 2, VP represents the positive terminal signal, and VN represents the negative terminal signal; The bias current I0 and the input common-mode level V CM,IN are related by the expression I0 = I 固定 + f(V CM,IN ), where I 固定 is independent of the input common-mode level V CM,IN , and f(V CM,IN ) represents a function related to the input common-mode level V CM,IN ; Configure f(V CM,IN ) to account for the weight ratio in the aforementioned relational expression to reduce the input common-mode level V CM,IN 's impact on the bias current I0; among them, when configuring the function f(V CM,IN ), when the difference between the input common-mode level V CM,IN and the power supply voltage or the ground voltage is within a preset range, let f(V CM,IN ) = 0; when the difference between the power supply voltage and the reference voltage V REF is within a preset range, let f(V CM,IN ) be a preset negative value.

3. The LVDS receiving circuit according to claim 1 or 2, characterized in that: The bias circuit module includes a comparison unit and a bias current I0 control unit; The comparison unit is configured to compare the input common-mode level with the reference voltage V REF , the power supply voltage, and the ground voltage, and send the comparison result to the bias current I0 control unit; The bias current I0 control unit is configured to: obtain the foregoing comparison result, when the difference between the input common-mode level and the ground voltage is within a preset range, determine that the input common-mode level is close to the ground voltage, the transistor PM5 is in the off state, and the bias current I0 all flows to the foregoing second node, and at this time two transistors PM3 and PM4 of the second group of PMOS transistor input differential pairs work; And, When the difference between the input common-mode level and the power supply voltage is within a preset range, determine that the input common-mode level is close to the power supply voltage, two transistors of the second group of PMOS transistor input differential pairs are turned off, and the bias current I0 mainly flows to the source of the transistor PM5, and at this time two transistors PM1 and PM2 of the first group of PMOS transistor input differential pairs work, and the DC levels of the differential input signal pair VP and VN are reduced through the level-shifting module; and, When the difference between the input common-mode level and the reference voltage V REF is within a preset range, it is determined that the common-mode level is near the reference voltage V REF . The bias current I0 flows to the aforementioned first node and second node simultaneously. At this time, the two transistors of the first group of PMOS input differential pairs and the two transistors of the second group of PMOS input differential pairs work simultaneously; the output bias current I0 is lowered so that the bias current I0 flowing to the two groups of PMOS input differential pairs is reduced.

4. The LVDS receiving circuit according to claim 3, wherein: The bias circuit module includes PMOS transistors PM0, PM8, PM9, PM10 and PM11, NMOS transistors NM1, NM2 and NM3, and two resistors R3 and R4 with equal resistance values; The drain of the transistor PM0 is connected to the sources of the transistors PM3 and PM4 of the second group of PMOS transistor input differential pairs to provide a bias current I0 for the input stage; The source of the transistor PM0 is connected to the power supply voltage VDD; the gate of the transistor PM0 is connected to the gate and drain of the transistor PM8, and at the same time connected to the drain of the transistor NM1, and at the same time connected to the drain of the transistor PM9; the transistors PM0 and PM8 form a current mirror; the sources of the transistors PM8 and PM9 are connected to the power supply voltage VDD; The gate of the transistor NM1 is connected to a bias voltage V BIAS , and the source is grounded to the voltage VSS to form a current source; The gate of transistor PM9 is connected to the gate and drain of transistor PM10, and transistors PM9 and PM10 form a current mirror; the source of transistor PM10 is connected to the power supply voltage VDD, the drain of transistor PM10 is also connected to the source of transistor PM11, the drain of transistor PM11 is connected to the drain of transistor NM2, the source of transistor NM2 is simultaneously connected to the drain and gate of transistor NM3, and the source of transistor NM3 is grounded to the voltage VSS; The gates of transistor PM11 and transistor NM2 are both connected to the connection point of resistors R3 and R4. The other end of resistor R3 is connected to the positive input signal VP of the receiving circuit, and the other end of resistor R4 is connected to the negative input signal VN of the receiving circuit. The potential at the connection point of resistors R3 and R4 is the input common-mode level V CM,IN .

5. The LVDS receiving circuit according to claim 4, wherein: Let the ratio of the width-to-length ratio of transistor PM0 to that of transistor PM8 be m, and the ratio of the width-to-length ratio of transistor PM9 and transistor PM10 be 1. Then the bias current I0 provided by transistor PM0 is m*I NM1 -m*I PM10 , where I NM1 represents the current of transistor NM1, and m*I NM1 is the fixed part and does not change with the input common-mode level V CM,IN ; I PM10 represents the current of transistor PM10, and m*I PM10 is the variable part and changes with the change of the input common-mode level V CM,IN . When the input common-mode level is higher than the preset threshold or lower than the preset threshold, transistor PM11 or transistor NM2 is turned off, and at this time I PM10 = 0, and the bias current I0 = m*I NM1 ; when the input common-mode level is at an intermediate level or near the reference voltage V REF around, the bias circuit module adjusts the sizes of transistors PM11, NM2, and NM3 so that transistors PM11 and NM2 are turned on, making I PM10 > 0 to reduce the bias voltage I0, thereby compensating for the increase in the total circuit transconductance Gm caused by the simultaneous operation of the first group of PMOS input differential pairs PM1 and PM2 and the second group of PMOS input differential pairs PM3 and PM4.

6. The LVDS receiving circuit according to claim 1, wherein: The input stage further includes a load module; The drains of one transistor in the first group of PMOS transistor input differential pair and one transistor in the second group of PMOS transistor input differential pair are connected to the negative terminal output VON1 of the input stage, and the drains of the other transistor in the first group of PMOS transistor input differential pair and the other transistor in the second group of PMOS transistor input differential pair are connected to the positive terminal output VOP1 of the input stage; the load module is connected to the aforementioned VOP1 and VON1 for primary amplification of the signal and generation of the input common-mode level of the subsequent circuit; The load module includes two ground resistors R1 and R2 with equal resistance values. One end of resistor R1 is grounded, and the other end is connected to the negative terminal output VON1. One end of resistor R2 is grounded, and the other end is connected to the positive terminal output VOP1.

7. The LVDS receiving circuit according to claim 6, wherein: It further includes a comparator module located after the input stage. The VOP1 and VON1 are respectively connected to the positive terminal input and negative terminal input of the comparator module, and the VOP1 and VON1 signals are amplified and / or shaped by the comparator module to obtain the output signal VOUT.

8. The LVDS receiving circuit according to claim 7, wherein: The comparator module includes PMOS transistors PM12, PM13, and PM14, NMOS transistors NM6, NM7, NM8, and NM9, and an output stage; Transistors PM13 and PM14 serve as an input differential pair, whose gates are respectively connected to the VOP1 and VON1 signals. The sources of transistors PM13 and PM14 are connected together and are simultaneously connected to the drain of transistor PM12; the gate of transistor PM12 is connected to the second bias voltage V BIAS2 , and the source is connected to the power supply V DDCORE , providing a bias current for transistors PM13 and PM14; The drain of transistor PM13 is connected to the drain and gate of transistor NM8, simultaneously connected to the drain of transistor NM6, simultaneously connected to the gate of transistor NM7, and simultaneously connected to the negative input terminal of the output stage; the drain of transistor PM14 is connected to the drain and gate of transistor NM9, simultaneously connected to the drain of transistor NM7, simultaneously connected to the gate of transistor NM6, and simultaneously connected to the positive input terminal of the output stage; Transistors NM6, NM7, NM8, and NM9 form a diode load with positive feedback for realizing hysteresis; The output stage is used for amplifying, differential-to-single-ended conversion, and / or shaping the signal, and outputting the signal VOUT.

9. The LVDS receiving circuit according to claim 1, wherein: The level shifting module includes NMOS transistors NM4 and NM5, as well as NMOS transistors NM16 and NM17; the gates of transistors NM16 and NM17 are respectively connected to the differential input signal pair VP and VN, the sources of transistors NM16 and NM17 are respectively connected to the gates of transistors PM1 and PM2, and are also respectively connected to the drains of transistors NM4 and NM5, and the drains of transistors NM16 and NM17 are both connected to the power supply voltage VDD; the gates of transistors NM4 and NM5 are both connected to the first bias voltage V BIAS1 , the sources of transistors NM4 and NM5 are both connected to the ground voltage VSS, and transistors NM4 and NM5 are used as current sources; And / or, the reference voltage module includes a PMOS transistor PM15 and an NMOS transistor NM10. The source of the transistor NM10 is grounded to the voltage VSS, and the gate is connected to the first bias voltage V BIAS1 , and the transistor NM10 functions as a current source. At the same time, the drain of the transistor NM10 is connected to the gate and drain of the transistor PM15. The source of the transistor PM15 is connected to the power supply voltage VDD, and the output of the drain of the transistor NM10 provides the gate voltage V REF .

10. A chip, on which a receiver capable of converting LVDS signals is integrated, characterized in that: The receiver includes the LVDS receiving circuit according to any one of claims 1-9.

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