Method for detecting an end sequence in a high speed transmission mode

Abstract

The application discloses a method for detecting end sequence in high-speed transmission mode, which comprises the following steps: a. TX end sends an end sequence signal with a set time length to RX end; b. RX end detects the end sequence signal and disconnects the connection with a terminating resistor; c. a level detector detects the change of line level amplitude and feeds back the detection result to TX end; and d. when the change of line level amplitude reaches a set range, TX end stops sending the end sequence signal. The method for detecting end sequence in high-speed transmission mode reduces the time for TX end to drive invalid end sequence signal, effectively improves transmission efficiency, and improves the reliability and universality of transmission between lines.

Description

Technical Field

[0001] This invention relates to the field of digital IC design, and more specifically to a method for detecting the end sequence in a high-speed transmission mode. Background Technology

[0002] In MIPID-PHY's ALP (Alternate Low Power Mode) mode, the TX end stops transmitting data / commands after sending a certain time range of the end sequence (logic signal HS-1). The RX end (connected to the TX end via DP and DN lines) feeds back a signal to the PHY layer after continuously detecting the end sequence within the corresponding time range. The PHY layer then disconnects the termination resistor (changing the DP and DN line voltage levels and returning the line state from high-speed transmission mode to low-power mode). At this time, the line logic is ALP-10, the TX stops driving the logic signal HS-1, and the TX end enters a waiting state with ALP-00, preparing for the next round of transmission. The logic description of the effective line state is shown in Table 1 below:

[0003]

[0004] Table 1

[0005] In the implementation of the above method, after the TX end sends the end sequence, the RX end does not receive any feedback information on when it receives the end sequence or whether it has received the end sequence. As a result, the TX end will only send an end sequence of a fixed length. This will cause the TX end to drive a part of the invalid end sequence signal. In addition, when the clock period of the counting period or the clock period of the detection and judgment trigger is relatively large (such as during reverse transmission), coupled with the special clock phase deviation between TX and RX, it is not guaranteed that the RX end will detect the end sequence, and thus the reliability of the transmission cannot be guaranteed.

[0006] In addition, in the implementation of the above method, if the time for driving the end sequence is set long enough, the TX end will drive an extra end sequence signal under high transmission speed and low bit width, which will increase the transmission time cost. If a relatively short driving time is set, it cannot be guaranteed whether the RX end has correctly determined the end state (whether the end sequence signal has been received within the set time) under low speed and high bit width transmission, and the stability is not strong.

[0007] Therefore, it is necessary to provide a method for detecting the end sequence in an adjusted transmission mode to overcome the above-mentioned defects. Summary of the Invention

[0008] The purpose of this invention is to provide a method for detecting the end sequence in high-speed transmission mode. The method of this invention reduces the time for the TX end to drive the invalid end sequence signal, effectively improves the transmission efficiency, and also improves the reliability and versatility of transmission between lines.

[0009] To achieve the above objectives, the present invention provides a method for detecting the end sequence in high-speed transmission mode, comprising the following steps:

[0010] a. The TX terminal sends an end sequence signal of a set duration to the RX terminal;

[0011] b. The RX terminal detects an end-of-sequence signal and disconnects from the termination resistor;

[0012] c. The level detector detects changes in the line level amplitude and feeds back the detection results to the TX terminal;

[0013] d. When the change in line voltage level reaches the set range, the TX terminal stops sending the end sequence signal.

[0014] Preferably, when the RX terminal is disconnected from the terminating resistor, the voltage levels of the DP and DN lines on the line change.

[0015] Preferably, when the RX terminal is disconnected from the terminating resistor, the line transmission mode switches from high-speed transmission mode to non-high-speed transmission mode.

[0016] Preferably, step d further includes the TX terminal stopping the transmission of the end sequence signal and starting to transmit the logic signal ALP-00.

[0017] Preferably, the range of the change in the line level amplitude is set such that the difference in level between the DP line and the DN line increases by 40% to 450%.

[0018] Preferably, when the logic signal of the line changes from HS-1 to ALP-10, the TX terminal stops sending the end sequence signal.

[0019] Compared with the prior art, the method for detecting the end sequence in high-speed transmission mode of the present invention sets the range of line level amplitude change and uses a level detector to detect the line level amplitude change in real time, and feeds back the detection result to the TX end in real time. This allows the TX end to determine in real time whether it is necessary to stop sending the end sequence signal, thereby reducing the time for the TX end to drive an invalid end sequence signal, effectively improving transmission efficiency, and also improving the reliability and versatility of transmission between lines.

[0020] The invention will become clearer from the following description, taken in conjunction with the accompanying drawings, which are used to explain embodiments of the invention. Attached Figure Description

[0021] Figure 1 This is a flowchart of the method for detecting the end sequence in high-speed transmission mode according to the present invention.

[0022] Figure 2 This is a timing diagram of the line for detecting the end sequence in high-speed transmission mode according to the present invention. Detailed Implementation

[0023] Embodiments of the present invention will now be described with reference to the accompanying drawings, in which similar element reference numerals denote similar elements. As described above, the present invention provides a method for detecting an end sequence in a high-speed transmission mode. This method reduces the time required for the TX end to drive an invalid end sequence signal, effectively improving transmission efficiency and enhancing the reliability and versatility of transmission between lines.

[0024] Please refer to the reference. Figure 1 and Figure 2 , Figure 1 This is a flowchart of the method for detecting the end sequence in high-speed transmission mode according to the present invention. Figure 2 This is the system circuit timing diagram. (For example...) Figure 1 As shown, the method for detecting the end sequence in high-speed transmission mode according to the present invention includes the following steps:

[0025] Step S001: The TX terminal sends a set-duration end sequence signal to the RX terminal. In this step, when the system enters the end time interval, the TX terminal sends a set-duration end sequence signal to the RX terminal to indicate the end of the current data transmission. The end sequence signal can be represented as a logic signal HS-1, that is, the logic value of the DP line is 1 and the logic value of the DN line is 0 (see...). Figure 2 The corresponding logic is DP = 1 and DN = 0, see Table 1 for details; in addition, the duration of the end sequence signal can be flexibly set according to the specific transmission speed, data bit width, etc., and is not uniformly limited in this invention.

[0026] Step S002: The RX terminal detects the end sequence signal and disconnects from the termination resistor. In this step, the RX terminal detects and receives the end sequence signal sent by the TX terminal in real time. When the RX terminal detects the end sequence signal HS-1, the controller disconnects the RX terminal from the termination resistor, causing a change in the voltage levels of the DP and DN lines connected between the TX and RX terminals. This increases the voltage level difference between the DP and DN lines, and simultaneously changes the logic signal of the DP and DN lines from HS-1 to ALP-10 (see...). Figure 2 At the same time, the line transmission mode switches from high-speed transmission mode to non-high-speed transmission mode, such as... Figure 2As shown, the transmission mode transitions from stage H1 to stage L1. Stage H1 is a high-speed transmission mode, while stage L1 is a non-high-speed transmission mode.

[0027] Step S003: The level detector detects changes in the line voltage level and feeds the detection result back to the TX terminal. In this step, the level detector detects changes in the voltage levels of the DP and DN lines and feeds the detected results back to the TX terminal in real time. For example... Figure 2 As shown, the level detector detects the S1 and ALP-10 phases.

[0028] Step S004: When the change in line voltage level reaches a set range, the TX terminal stops sending the end sequence signal. In this step, the set range for the change in line voltage level is that when the difference in voltage level between the DP line and the DN line increases by 40% to 450%, the TX terminal stops sending the end sequence signal. Figure 2 As shown, in stage S1, the levels of the DP and DN lines change (at the instant the resistor is disconnected). However, the line operation is not stable at this time, meaning the level change of the DP and DN lines does not reach the set range. Therefore, setting the range of the level difference between the DP and DN lines can effectively avoid misoperation and also avoid the influence of inherent errors in the line on the detection results. The range of the level difference between the DP and DN lines is based on the level difference between the DP and DN lines in stage HS-1. Furthermore, in this step, the TX terminal only stops sending the end sequence signal when the logic signal of the DP and DN lines changes from HS-1 to ALP-10. The change in the logic signal of the DP and DN lines corresponds to the change in their levels. Although the HS-1 logic signal is the same as the ALP-10 logic signal (see Table 1), in this invention, the ALP-10 logic signal is a logic signal formed in non-high-speed transmission mode after the HS-1 logic signal undergoes a level change. Its actual corresponding level is not the same as the level corresponding to the HS-1 logic signal. Figure 2 As shown.

[0029] In this invention, as shown in Table 1 and Figure 2 As shown, the relationship between the line logic and the line level is as follows: when the DP line level is high, 1 represents the DP line logic; when the DP line level is low, 0 represents the DP line logic. The relationship between the DN line line logic and the line level is the same, and will not be elaborated here.

[0030] Further, in step S004, after the TX terminal stops sending the end sequence signal, it starts sending the logic signal ALP-00, specifically as follows: Figure 2As shown, the logic signal ALP-00 is issued after the logic signal ALP-10, that is, the logic signal ALP-10 is issued after the end process is completely completed, so that the entire system enters a waiting state and waits for the start of the next round of data or instruction transmission.

[0031] Please refer to Table 2 for further details. Table 2 shows the time saved by the solution of this invention compared with the solution of the prior art. Using the prior art solution, the time for the TX end to drive HS-1 should not be less than "RX end detection time + digital clock cycle * 2". If a redirection transmission command is sent, the waiting time for the RX end to respond must also be considered, and the actual driving time should be longer. For example, with a transmission speed of 250M and a bit width of 32bit, the shortest time for the TX end to drive HS-1 is 1152ns, and so on. However, using the solution of this invention, the driving time of the TX end does not need to be set. In actual operation, after the RX end detects the end sequence signal, it pulls the level high. After the level detector detects it, it feeds back to the TX end, and then the TX end ends the driving of the end sequence signal, which can greatly save the time of the entire termination process. For the specific time saved under different solutions, please refer to Table 2.

[0032]

[0033] Table 2

[0034] As shown in Table 2, the method for detecting the end sequence in high-speed transmission mode of the present invention does not save time in the 250M, 32bit transmission environment, but it does not increase the time either. In other transmission environments, it saves a lot of time. Therefore, the solution of the present invention reduces the time for the TX end to drive the invalid end sequence signal, effectively improves the transmission efficiency, and also improves the reliability and versatility of transmission between lines.

[0035] The present invention has been described above in conjunction with the preferred embodiments, but the present invention is not limited to the embodiments disclosed above, but should cover various modifications and equivalent combinations made in accordance with the essence of the present invention.

Claims

1. A method for detecting the end sequence in high-speed transmission mode, characterized in that, Includes the following steps: a. The TX terminal sends an end sequence signal of a set duration to the RX terminal; b. When the RX terminal detects the end sequence signal, it disconnects from the termination resistor. When the RX terminal disconnects from the termination resistor, the voltage levels of the DP and DN lines on the line change. c. The level detector detects changes in the line level amplitude and feeds back the detection results to the TX terminal; d. When the change in line voltage level reaches the set range, the TX terminal stops sending the end sequence signal.

2. The method for detecting the end sequence in high-speed transmission mode as described in claim 1, characterized in that, When the RX terminal is disconnected from the terminating resistor, the line transmission mode switches from high-speed transmission mode to non-high-speed transmission mode.

3. The method for detecting the end sequence in high-speed transmission mode as described in claim 1, characterized in that, In step d, the TX terminal also stops sending the end sequence signal and starts sending the logic signal ALP-00.

4. The method for detecting the end sequence in high-speed transmission mode as described in claim 2, characterized in that, The set range for the change in the line level amplitude is that the difference in level between the DP line and the DN line increases by 40% to 450%.

5. The method for detecting the end sequence in high-speed transmission mode as described in claim 2, characterized in that, When the logic signal of the line changes from HS-1 to ALP-10, the TX terminal stops sending the end sequence signal.

Images