A high voltage ESD electrostatic layout structure

Abstract

The present invention relates to a high-voltage ESD electrostatic layout structure, wherein the ESD vertical layout structure comprises a buried layer, a lower layer of the buried layer and substrate materials on both sides; the buried layer comprises a deep N-well region, and the deep N-well region also comprises a P-well injection region and an N-well injection region; an N-tube source terminal and a P-well contact are arranged in the P-well injection region, and a shallow trench isolation is provided between the two; an N-tube drain terminal is arranged on one side of the N-tube source terminal, and a polycrystalline gate I is arranged above the N-tube drain terminal and the N-tube source terminal. Similarly, a P-tube source terminal and an N-well contact are arranged in the N-well injection region, and a shallow trench isolation is provided between the two, and a polycrystalline gate II is arranged above the N-well contact and the P-tube source terminal. The MOS layout structure adopts a multi-gate interdigitation structure, wherein the source and the drain are respectively at both ends of the gate, overlapping each other, saving area, a certain width ratio is set for the source and the drain, and a contact hole array is arranged.

Description

Technical Field

[0001] The invention relates to a semiconductor device structure, in particular to a high-voltage ESD electrostatic layout structure based on CMOS technology. Background Art

[0002] With the portability and miniaturization of electronic products, integrated circuits are also developing towards system integration, and the process level has also entered the deep submicron era of integrated circuit line width. The ESD protection unit in the chip is one of the most important components of the entire chip, which determines whether the entire chip protection design can be successfully completed. High-voltage ESD needs to maintain high voltage and high current. When an ESD event occurs, a large current needs to be discharged in a short time. The working mode of high-voltage ESD devices will also be different. Therefore, it is very necessary to study high-voltage ESD.

[0003] With the application of high voltage and high power in electronic products, it is becoming increasingly difficult to use the conventional high-voltage ESD protection to protect itself by using the device's own carrying capacity. External high-voltage ESD modules occupy packaging area, so on-chip high-voltage ESD is used to save area.

[0004] When working at a high-voltage IO port, a small amount of charged carriers may be generated in the well or substrate. The anti-latch (Latch-Up) capability of the ESD protection unit also needs to be strengthened, especially paying attention to the well potential connection method.

[0005] In order to solve this problem, the low-voltage ESD protection design is used for high-voltage ESD design in circuit design, which can minimize the layout area and ensure the latching capability of the device. Summary of the invention

[0006] In order to solve the above technical problems, the present invention provides a high-voltage ESD electrostatic layout structure, wherein the ESD vertical layout structure includes a buried layer, a lower layer of the buried layer and substrate materials on both sides; the buried layer includes a deep N-well region, the deep N-well region also includes a P-well injection region and an N-well injection region, and an N-type injection region, and the N-well injection region is used as a well contact of the N-type injection region;

[0007] An N-tube source terminal and a P-well contact are provided in the P-well injection region, and a shallow trench is provided between the two. An N-tube drain terminal is provided on one side of the N-tube source terminal, and a polycrystalline gate I is provided above the N-tube drain terminal and the N-tube source terminal.

[0008] In one embodiment of the present invention, a P-tube source terminal and an N-well contact are also provided in the N-well injection region, and a shallow trench isolation layer is provided between the two. A polycrystalline gate II is provided above the N-well contact and the P-tube source terminal.

[0009] In one embodiment of the present invention, a connection loop is connected in the ESD vertical layout structure, wherein the loop includes resistor I, resistor II, an input terminal IN, and an output terminal OUT;

[0010] The input terminal IN is connected to resistor II, the N-well contact in the N-well injection region, and the P-tube source terminal. The other end of resistor II is connected to polycrystalline gate II. A P-tube drain terminal is also provided at one end of polycrystalline gate II and is connected in series with the N-tube source terminal.

[0011] In one embodiment of the present invention, one end of the resistor I is connected to the polycrystalline gate I, and the other end of the resistor I is connected to the drain end of the N tube, the P well contact and the output end OUT.

[0012] In one embodiment of the present invention, the number of interpolation indexes of the ESD vertical layout structure ranges from 6 to 10, and the total width of a single MOS tube is greater than 360 um.

[0013] The above technical solution of the present invention has the following advantages over the prior art: the ESD vertical layout structure described in the present invention, the MOS layout structure adopts a multi-gate interdigitation structure, the source and drain are respectively at both ends of the gate, overlapping each other, saving area, the source and drain are set with a certain width ratio, and a contact hole array is set. The gate, source and drain are respectively connected by metal wires, arranged according to the equivalent circuit diagram, and are respectively connected to the pad, resistor and MOS tube interconnection. The resistor uses a polycrystalline resistor, and the pad material is selected from metal materials.

[0014] The solution of the present invention provides relevant standard models in most processes, so the model is highly versatile, low cost, and does not increase manufacturing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to make the contents of the present invention more clearly understood, the present invention is further described in detail below based on specific embodiments of the present invention in conjunction with the accompanying drawings.

[0016] Figure 1 A schematic diagram of the high-voltage ESD circuit structure designed for reference of low-voltage ESD protection;

[0017] Figure 2 Based on Figure 1 Schematic diagram of the circuit structure of the enhanced high voltage ESD structure;

[0018] Figure 3 It is a schematic diagram of the layout structure of the high voltage ESD structure described in the present invention;

[0019] Figure 4 It is a schematic diagram of the vertical structure of the layout of the high-voltage ESD structure described in the present invention.

[0020] Figure 3In the attached drawings, 301 is marked as drain metal line; 302 is marked as source metal line; 303 is marked as polycrystalline gate hole; 304 is marked as polycrystalline gate; 305 is marked as active area hole; 306 is marked as implant I; 307 is marked as implant II;

[0021] Figure 4 Marked as 401 in the accompanying drawing, buried layer; 402, deep N-well injection region; 403, P-well injection region; 404, N-well injection region; 405, N-type injection region; 406, polycrystalline gate I; 407, N-tube drain terminal; 408, N-tube source terminal; 409, P-well contact; 410, resistor I; 411, polycrystalline gate II; 412, P-tube source terminal; 413, P-tube drain terminal; 414, N-well contact; 415, resistor II; 416, input terminal IN, 417, output terminal OUT. DETAILED DESCRIPTION

[0022] The ESD electrostatic layout structure of this embodiment can be found in Figure 4 As shown, it includes a buried layer 401, a lower layer of the buried layer 401 and substrate materials on both sides; the buried layer 401 includes a deep N-well region 402, and the deep N-well region 402 also includes a P-well injection region 403 and an N-well injection region 404, and an N-type injection region 405, and the N-well injection region 404 is used as a well contact of the N-type injection region 405;

[0023] An N-tube source terminal 408 and a P-tube contact 409 are provided in the P-well injection region 403 , and a shallow trench isolating the two. An N-tube drain terminal 407 is provided on one side of the N-tube source terminal 408 , and a polycrystalline gate I 406 is provided above the N-tube drain terminal 407 and the N-tube source terminal 408 .

[0024] Similarly, a P-tube source terminal 412 and an N-well contact 414 are provided in the N-well injection region 404 , and a shallow trench isolation layer is provided between the two. A polycrystalline gate II 411 is provided above the N-well contact 414 and the P-tube source terminal 412 .

[0025] A connection loop is connected in the ESD vertical layout structure, wherein the loop includes a resistor I 410, a resistor II 415, an input terminal IN 416, and an output terminal OUT 417;

[0026] The input terminal IN416 is connected to the resistor II415, the N-well contact 414 in the N-well injection region 404, and the P-tube source terminal 412. The other end of the resistor II415 is connected to the polycrystalline gate II411. One end of the polycrystalline gate II411 is also provided with a P-tube drain terminal 413, which is connected in series with the N-tube source terminal 408.

[0027] One end of the resistor I 410 is connected to the poly gate I 406 , and the other end of the resistor I 410 is connected to the N tube drain terminal 407 , the P well contact 409 and the output terminal OUT417 .

[0028] Figure 3 It is a plan view of a single structure, which is also a common low-voltage ESD protection design. It provides a low-voltage MOS layout structure as a universal structure, and is also suitable for NMOS, PMOS and isolated (ISO) device structures.

[0029] The number of interpolation fingers involved in the present invention ranges from 6 to 10, and the total width of a single MOS tube is >360um. A large number of interpolation fingers will cause most of the interpolation fingers to be unopened, resulting in ESD failure. Its uniformity is not guaranteed. The active area hole spacing 305 and the polycrystalline gate 304 have the same array and spacing. Injection I 306 uses a ring design, and injection II 307 needs to cover the entire MOS tube. Injection I 306 and injection II 307 use repulsion (such as injection I 306 uses N injection, and injection II 307 uses P injection). The drain metal wire 301 is connected to the input end in the direction of the current, and the polycrystalline gate 304 is connected to the output end in the direction of the current through the polycrystalline gate hole 303 and the source metal wire 302.

[0030] The present invention provides an ESD electrostatic layout structure that can be used for high-voltage semiconductor electrostatic protection structures. When electrostatic discharge occurs, the high-voltage ESD device will be turned on earlier than the internal circuit to fully protect the device. The high-voltage ESD circuit structure includes an input terminal IN, an output terminal OUT, a low-voltage NMOS and a low-voltage PMOS. The structure adopts a multi-stage series structure. Figure 2 for Figure 1 Reinforced version (Note: Figure 1 The risk point is that high voltage may cause PN junction breakdown) The above low-voltage MOS can use isolated (ISO) devices. The circuit also includes a resistor, and the actual design resistance of the resistor is 1k ohm.

[0031] Its equivalent circuit is Figure 2 , one end of the resistor R1 is connected to the input IN, the source end of MP1 and the N-well potential, and the other end of R1 is connected to the gate. The drain end of MP1 is connected to the drain end of MN1. One end of the resistor R2 is connected to the output OUT, the source end of MN1 and the P-well potential, and the other end of R2 is connected to the gate. The series structure is not limited to 2-stage series connection. According to the input voltage, 3-5 layers of series structure can be set, and the maximum is not more than 5 levels, which will cause the ESD turn-on speed to slow down. The structure first uses the series connection method to improve the ESD withstand voltage. Secondly, the resistor can also accelerate the MOS tube turn-on speed and reduce the conduction voltage. The use of PMOS tubes in the first stage can prevent the voltage drop from being too high to exceed the N-well carrying voltage drop. The second-stage NMOS tube has a better ESD discharge capability.

[0032] Obviously, the above embodiments are merely examples for clear explanation and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived from these are still within the protection scope of the invention.

Claims

1. A high voltage ESD electrostatic layout structure, characterized in that: The ESD vertical layout structure comprises a buried layer (401), a lower layer of the buried layer (401) and substrate materials on both sides; the MOS layout structure adopts a multi-gate interdigitation structure; the buried layer (401) comprises a deep N-well region (402), the deep N-well region (402) also comprises a P-well injection region (403) and an N-well injection region (404), and an N-type injection region (405), and the N-well injection region (404) is used as a well contact of the N-type injection region (405); An N-tube source terminal (408) and a P-tube contact (409) are provided in the P-well injection region (403), and a shallow trench isolation layer is provided between the two. An N-tube drain terminal (407) is provided on one side of the N-tube source terminal (408), and a polycrystalline gate I (406) is provided above the N-tube drain terminal (407) and the N-tube source terminal (408). Similarly, a P-tube source terminal (412) and an N-well contact (414) are provided in the N-well injection region (404), and a shallow trench isolation layer is provided between the two. A polycrystalline gate II (411) is provided above the N-well contact (414) and the P-tube source terminal (412).

2. The ESD electrostatic layout structure according to claim 1, characterized in that: A connection loop is connected in the ESD vertical layout structure, wherein the loop includes a resistor I (410), a resistor II (415), an input terminal IN (416), and an output terminal OUT (417); The input terminal IN (416) is connected to the resistor II (415), the N-well contact (414) in the N-well injection region (404), and the P-tube source terminal (412). The other end of the resistor II (415) is connected to the polycrystalline gate II (411). The polycrystalline gate II (411) is also provided with a P-tube drain terminal (413) at one end. Meanwhile, the other end of the P-tube drain terminal (413) is connected in series with the N-tube source terminal (408).

3. The ESD electrostatic layout structure according to claim 2, characterized in that: One end of the resistor I (410) is connected to the polycrystalline gate I (406), and the other end of the resistor I (410) is connected to the N-tube drain terminal (407), the P-well contact (409) and the output terminal OUT (417).

4. The ESD electrostatic layout structure according to claim 1, characterized in that: The interpolation index of the ESD vertical layout structure ranges from 6 to 10, and the total width of a single MOS tube is >360um.

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