Driving method for a display panel, common voltage output circuit, and display panel

Abstract

The present application discloses a driving method for a display panel, a common voltage output circuit, and a display panel. The driving method for the display panel includes: upon receiving a power-on signal, controlling the first switch to be in a closed state; controlling the first common electrode not to be powered on through the first switch, and the pixel unit is coupled with the second common electrode to reach the same voltage as the second common electrode; in response to receiving the first frame synchronization signal, the control module outputs a high level, causing the first switch to be in an open state and the first common electrode to be input into the display panel; meanwhile, controlling the power output line to input a first voltage higher than the coupling voltage to the pixel unit. The present application differentially controls the input voltages of the first common electrode, the second common electrode, and the pixel unit through the first switch and the second switch, so that when the display panel is powered on, the display panel can display normally without the situations of white display or screen flashing.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a driving method for a display panel. Background Art

[0002] Liquid crystal displays are one of the most widely used flat panel displays. A liquid crystal display typically includes a liquid crystal layer disposed between two substrates, and adjusts the state of the liquid crystal layer according to the magnitude of the electric field applied to the liquid crystal layer, thereby adjusting the light transmission to display an image. With the current popularization of large-size panels, there are relatively many problems with the panel, such as white screen or flash screen phenomena in the far end area at the moment of power-on. Summary of the Invention

[0003] In view of this, this application provides a driving method for a display panel, a common voltage output circuit, and a display panel to solve the problem of white screen or flash screen phenomena in the far end area at the moment of power-on in the prior art.

[0004] To solve the above technical problems, the first technical solution provided by this application is: to provide a driving method for a display panel, including: receiving a power-on signal, controlling a first switch to be in a closed state; controlling, through the first switch, that a first common electrode is not powered on, and a pixel unit is coupled to a second common electrode to reach the same voltage as the second common electrode; in response to receiving a first frame synchronization signal, a control module outputs a high level, causing the first switch to be in an open state, and causing the first common electrode to be input into the display panel; at the same time, controlling a power output line to input a first voltage higher than the coupling voltage to the pixel unit.

[0005] Optionally, the controlling the power output line to input a first voltage higher than the coupling voltage to the pixel unit includes: controlling the power output line to input a first voltage higher than the coupling voltage to the pixel unit within the time of one frame of the picture.

[0006] Optionally, the time of one frame of the picture is obtained by the ratio of the unit time to the working frequency.

[0007] Optionally, the in response to receiving a first frame synchronization signal, the control module outputs a high level, causing the first switch to be in an open state, and causing the first common electrode to be input into the display panel; at the same time, controlling the power output line to input a first voltage higher than the coupling voltage to the pixel unit includes: the control module outputs a high level and controls the power output line to input a first voltage to the pixel unit, such that the voltage difference between the pixel unit and the second common electrode is less than or equal to 1.5V.

[0008] Optionally, in response to receiving the first frame synchronization signal, the control module outputs a high level, causing the first switch to be in an on state and causing the first common electrode to be input into the display panel; meanwhile, after the power supply output line inputs a first voltage higher than the coupling voltage to the pixel unit, it includes: in response to receiving the second frame synchronization signal, the control module controls the power supply output line to input a display screen voltage to the pixel unit; wherein the display screen voltage is higher than the first voltage.

[0009] Optionally, the first common electrode is not powered on through the first switch, and the pixel unit is coupled to the second common electrode to reach the same voltage as the second common electrode, including: while controlling the first common electrode not to be powered on, controlling the second common electrode to be powered on; controlling the second switch to open, then the first common electrode and the second common electrode are conducted; in response to the first common electrode reaching the target potential, controlling the second switch to disconnect, so that the first common electrode stops being powered on.

[0010] To solve the above technical problems, the second technical solution provided by this application is: to provide a common voltage output circuit for a display panel, including: a common electrode and a control switch, the common electrode includes a first common electrode and a second common electrode, and the first common electrode and the second common electrode cooperate to form a voltage for driving the deflection of liquid crystal molecules; the control switch is arranged between the first common electrode and the second common electrode and is used to conduct or disconnect the electrical connection between the first common electrode and the second common electrode; wherein, the control switch includes: a gate, a source and a drain, the gate is electrically connected to the second common electrode; the source is electrically connected to the first common electrode; the drain is connected to the second common electrode through an equivalent resistor, and the equivalent resistor is used to maintain a voltage difference between the gate and the drain.

[0011] Optionally, the circuit further includes: a thin film transistor switch, electrically connected to the power supply output line and used to control the output voltage of the power supply output line; a liquid crystal capacitor, arranged between the thin film transistor switch and the second common electrode and used to drive the deflection of the liquid crystal molecules; a storage capacitor, electrically connected to the liquid crystal capacitor and the thin film transistor switch and used to charge the liquid crystal capacitor to maintain the charge of the liquid crystal capacitor.

[0012] Optionally, both the control switch and the thin film transistor switch are MOS transistors.

[0013] To solve the above technical problems, the third technical solution provided by this application is: to provide a display panel electrically connected to the common voltage output circuit described in any one of the above.

[0014] Advantages of the present application: Different from the prior art, the driving method of the display panel of the present application includes: receiving a power-on signal and controlling the first switch to be in the off state; controlling the first common electrode not to be powered on through the first switch, and the pixel unit is coupled with the second common electrode to reach the same voltage as the second common electrode; in response to receiving the first frame synchronization signal, the control module outputs a high level, so that the first switch is in the on state, and the first common electrode is input into the display panel; at the same time, the control power output line inputs a first voltage higher than the coupling voltage to the pixel unit. By differentially controlling the input voltages of the first common electrode, the second common electrode, and the pixel unit through the first switch and the second switch when the power is turned on, when receiving the first frame synchronization signal, and when receiving the second frame synchronization signal, the display panel can display normally when the power is turned on, and there will be no situation of white display or screen flashing. Description of the Drawings

[0015] To more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0016] Figure 1 It is a schematic block diagram of the main module structure of the common voltage output circuit provided by the present application;

[0017] Figure 2 It is a schematic diagram of the structure of the display panel provided by the present application;

[0018] Figure 3 It is a schematic diagram of the circuit structure of the common voltage output circuit provided by the present application;

[0019] Figure 4 It is a schematic diagram of the structure of the display device provided by the present application;

[0020] Figure 5 It is a schematic flowchart of the driving method of the display panel provided by the present application;

[0021] Figure 6 is Figure 5 A schematic flowchart of the sub-steps of step S2 provided;

[0022] Figure 7 is Figure 5 A schematic flowchart of the sub-steps of step S3 provided;

[0023] Figure 8 It is the power-on timing diagram provided by the present application;

[0024] Figure 9 Yes Figure 5 It is a flowchart showing the steps after step S3 provided;

[0025] Figure 10 It is a schematic diagram showing the situation of regional white screen at the far end at the moment of power-on of a large-size panel provided by this application;

[0026] Explanation of reference numerals:

[0027] 10 - Common electrode, 101 - Whitening area, 11 - First common electrode, 12 - Second common electrode, 13 - Frame signal line, 14 - Scan line, 15 - Power output line, 20 - Driving module, 30 - Power management integrated circuit, 40 - Control module, 50 - Level conversion module, 60 - Liquid crystal capacitor, 61 - Storage capacitor, 70 - Array substrate, 71 - Pixel unit, 711 - Sub-pixel, 72 - Thin film transistor, 80 - Color filter substrate, 90 - Liquid crystal layer, 91 - Liquid crystal molecule, Q1 - Thin film transistor switch / First switch, Q2 - Control switch / Second switch, R1 - Equivalent resistance, 100 - Common voltage output circuit, 200 - Display panel, 400 - Display device. Detailed implementation manners

[0028] Next, the technical solutions in the embodiments of this application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of this application. Obviously, the described embodiments are only a part of the embodiments of this application, rather than all the embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of this application.

[0029] The terms "first" and "second" in this application are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one of such features. All directional indications (such as up, down, left, right, front, back...) in the embodiments of this application are only used to explain the relative positional relationship and movement conditions between components in a specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indications will also change accordingly. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally further include unlisted steps or units, or may optionally further include other steps or units inherent to these processes, methods, products or devices.

[0030] References herein to "embodiments" mean that the particular features, structures, or characteristics described in connection with the embodiments can be included in at least one embodiment of the present application. The phrase appears in various places in the specification and does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.

[0031] The inventors of the present application have found that: at the moment of power-on, there is a problem of regional white screen at the remote end. The TV set can solve the white screen problem by delaying the turning on of the backlight. However, at present, in the preliminary tests or detections by panel manufacturers / TV set manufacturers, there is no dedicated backlight, resulting in the observation of the power-on white screen phenomenon, which affects the test / detection. At the same time, the inventors have found that the reason for the power-on white screen is that at the moment of power-on, the scan line (Gate) and the power output line S_out are in the off state, and the A_COM common electrode and the CF_COM common electrode are powered on simultaneously. However, due to the design of the display panel, the CF_COM at the proximal and distal ends of the panel can reach the target value almost simultaneously. However, A_COM is connected by a transparent conductive layer (such as ITO) in the panel, with a large impedance. The proximal end can reach the target value quickly, and the distal end is powered on slowly due to the impedance.

[0032] As Figure 10 shown, under the combined action of A_COM and CF_COM, the pixel units at the remote end are powered on slowly. During this process, there is a voltage difference between CF_COM and the pixel units, which causes the liquid crystal molecules to rotate and display white. When the scan line is turned on, the power output line charges the pixel units normally, and the abnormality disappears.

[0033] To solve the above problems, the present application provides a driving method for a display panel, a common voltage output circuit, and a display panel.

[0034] Please refer to Figure 1 and Figure 10 , Figure 1 is a schematic block diagram of the main module of the common voltage output circuit provided by the present application, Figure 10 is a schematic diagram of the situation of regional white screen at the remote end at the moment of power-on of a large-size panel provided by the present application.

[0035] A common voltage output circuit 100 provided by the present application can be used for a display panel 200. The common voltage output circuit 100 includes a level conversion module 50, a control module 40, a power management integrated circuit (PMIC) 30, and a driving module 20. The level conversion module 50 can be separately provided on the driving circuit board or integrated in the driving module 20. For example, the driving module 20 can be a Gamma IC (gamma chip).

[0036] Please refer to Figure 2 and Figure 3 , Figure 2 which is a schematic structural diagram of a display panel provided by the present application, Figure 3 and

[0037] As Figure 2 and Figure 3 shown, the display panel 200 includes a common electrode 10, an array substrate 70, a color filter substrate 80, a liquid crystal layer 90, as well as scan lines (Gate lines) 14, data lines (Data lines, not shown in the figure), and a power output line 15; the scan lines 14 and the data lines intersect horizontally and vertically to form a plurality of defined regions. The array substrate 70 includes a plurality of pixel units 71 and a plurality of thin film transistors (TFTs) 72. The thin film transistors 72 are located within the defined regions, and each thin film transistor 72 includes a gate, a source, and a drain. Among them, the drain is electrically connected to the pixel unit 71, and the source is electrically connected to the data line. The liquid crystal layer 90 includes a plurality of liquid crystal molecules 91. Referring to Figure 3 shown, the display panel 200 includes a plurality of sub-pixels 711 arranged in an array, and the sub-pixels 711 can be R (red) sub-pixels, G (green) sub-pixels, and B (blue) sub-pixels. The data line is electrically connected to the pixel unit 71 through the thin film transistor 72 for charging the storage capacitor 61.

[0038] As Figure 3 shown, the common voltage output circuit 100 further includes a common electrode 10, a thin film transistor switch Q1, a liquid crystal capacitor 60, a storage capacitor 61, and a control switch Q2. The common electrode 10 includes a first common electrode 11 and a second common electrode 12. The first common electrode 11 and the second common electrode 12 cooperate to form a voltage for driving the deflection of the liquid crystal molecules 91. For example, the voltage difference between the first common electrode 11 and the second common electrode 12 determines the deflection angle of the liquid crystal molecules 91. In this embodiment, the first common electrode 11 can be a substrate common electrode (A_COM), and the second common electrode 12 can be a common electrode layer (CF_COM) on the color filter substrate 80. The driving module 20 is configured to transmit a gate driving signal to a plurality of scan lines 14 of the display panel 200 under the control of a gate clock signal to turn on the thin film transistor 72, so that the data voltage signal of the data line is written into the pixel unit 71. In this way, a voltage difference is formed between the pixel unit 71 and the common electrode 10, thereby driving the liquid crystal of the display panel 200 to deflect, and further realizing the display of different images.

[0039] The control module 40 is electrically connected to the frame signal line 13 (STV line) and the gate clock signal line (not shown in the figure) respectively, and is configured to provide a first frame signal (STV signal) to the frame signal line 13 and a gate clock signal to the gate clock signal line.

[0040] The above control module 40 may include a timing controller (TCON); the above driving module 20 may include a DC / DC (direct current / direct current) converter, or may further include a P-Gamma IC (programmable gamma chip). If the driving module 20 includes a P-Gamma IC, the above level conversion module 50 may also be integrated in the P-Gamma IC.

[0041] As Figure 3 shown, the thin-film transistor switch Q1 is electrically connected to the scan line 14, the liquid crystal capacitor 60, and the power output line 15, and is used to control the output voltage of the power output line 15. For example, the specific voltage value output by the thin-film transistor switch Q1 to control the power output line 15, and to control whether the power output line 15 outputs a high voltage or a low voltage.

[0042] The liquid crystal capacitor 60 is disposed between the thin-film transistor switch Q1 and the second common electrode 12, and is used to drive the deflection of the liquid crystal molecules 91. The liquid crystal capacitor 60 serves as a driving mechanism for the liquid crystal molecules 91, and drives the liquid crystal molecules 91 to deflect by a corresponding angle according to the value of the voltage difference between the first common electrode 11 and the second common electrode 12.

[0043] The storage capacitor 61 is electrically connected to the liquid crystal capacitor 60 and the thin-film transistor switch Q1. The storage capacitor 61 is a capacitor storage structure with a storage capacity much larger than that of the liquid crystal capacitor 60, and is used to charge the liquid crystal capacitor 60 when the liquid crystal capacitor 60 has no electricity, so as to maintain the power of the liquid crystal capacitor 60.

[0044] The control switch Q2 is disposed between the first common electrode 11 and the second common electrode 12, and is used to conduct or disconnect the electrical connection between the first common electrode 11 and the second common electrode 12. Among them, the control switch Q2 includes a gate, a source, and a drain. The gate is electrically connected to the second common electrode 12, the source is electrically connected to the first common electrode 11. The drain is connected to the second common electrode 12 through an equivalent resistor R1, and a voltage difference is maintained between the gate and the drain through the equivalent resistor R1. The equivalent resistor R1 is a bias resistor, which can maintain a voltage difference between the gate and the drain of the control switch Q2. When the control switch Q2 is in the on state, the first common electrode 11 and the second common electrode 12 can be in the conducting state, so that a voltage difference is generated between the liquid crystal capacitors 60 connecting the thin-film transistor switch Q1 and the second common electrode 12, driving the liquid crystal molecules 91 to deflect.

[0045] In this embodiment, both the control switch Q2 and the thin-film transistor switch Q1 are MOS transistors (metal-oxide-semiconductor field effect transistors). MOS transistors have a very high switching frequency and can be quickly turned on when receiving an on signal.

[0046] Please refer to Figure 4 , Figure 4 which is a schematic structural diagram of the display device provided by the present application.

[0047] The present application also discloses a display panel 200 for a display device 400. The display panel 200 is electrically connected to the common voltage output circuit 100 described in any one of the above. The display panel 200 is electrically connected to the driving module 20 and the level conversion module 50. The specific structures of the driving module 20 and the level conversion module 50 and the specific connection manners with the display panel 200 can refer to the foregoing content. The display panel 200 can be an LCD (Liquid Crystal Display), and the display device 400 can be an LCD display device, such as: an ADS (Advanced Super Dimension Switch) type liquid crystal display device; or, it can also be any product or component with a display function, such as a television, a digital camera, a mobile phone, a tablet computer, etc. including the display device 400. The display device 400 can solve the problem of white flash caused by the common voltage signal being turned on earlier than the gate driving signal in the related art; at the same time, it can also solve the problem of black line defects that occur during the GOA noise reduction operation during the white flash in the related art; it has the characteristics of high product quality and good user experience.

[0048] Please refer to Figure 5 , Figure 5 which is a schematic flowchart of the driving method of the display panel provided by the present application.

[0049] The driving method of the display panel 200 provided by the present application may include:

[0050] S1: When receiving a power-on signal, control the first switch Q1 to be in a closed state.

[0051] Specifically, at the moment of power-on, the control module 40 receives the power-on signal and controls the first switch Q1 to remain in the closed state, so that the first common electrode 11 is not powered on, and the signal of the first common electrode 11 cannot be input into the display panel 200. In this embodiment, the first switch Q1 is a thin-film transistor switch, specifically an N-MOS transistor. The MOS transistor has a very high switching frequency and can quickly turn on or off the first switch Q1 as needed.

[0052] S2: Control the first common electrode 11 not to be powered on through the first switch Q1, and the pixel unit 71 is coupled with the second common electrode 12 to reach the same voltage as the second common electrode 12.

[0053] Specifically, the control module 40 controls the first switch Q1 to be in the off state, so that when the first switch Q1 is in the off state, the first common electrode 11 is not powered on. That is, due to the closing of the first switch Q1, A_COM cannot input a signal into the display panel 200. At this time, the pixel unit 71 in the display panel 200 can also reach the same voltage value as the second common electrode 12 under the coupling of the second common electrode 12. For example Figure 3 the 7V in

[0054] Please refer to Figure 6 , Figure 6 which Figure 5 is a schematic flowchart of the sub-steps of step S2 provided.

[0055] Furthermore, the step S2 of controlling the first common electrode 11 not to be powered on by the first switch Q1 and enabling the pixel unit 71 to reach the same voltage as the second common electrode 12 through coupling with the second common electrode 12 may include:

[0056] S21: While controlling the first common electrode 11 not to be powered on, control the second common electrode 12 to be powered on.

[0057] Specifically, at the moment of power-on, the control module 40 controls the second common electrode 12 at the far end of the display panel 200 to be quickly powered on, and the first common electrode 11 is not powered on due to the impedance of the transparent conductive layer in the display panel 200, such as ITO. Here, the control module 40 can be a timing controller (TCON), and the timing controller is used to control the first common electrode 11 not to be powered on and the second common electrode 12 to be powered on simultaneously.

[0058] S22: Control the second switch Q2 to open, then the first common electrode 11 and the second common electrode 12 are conducted.

[0059] Specifically, the timing controller is used to control the second switch Q2 to open, so that the first common electrode 11 and the second common electrode 12 at the far end are conducted, so that the first common electrode 11 and the second common electrode 12 at the far end and the near end can be almost powered on simultaneously, avoiding too large a voltage difference across the liquid crystal capacitor 60 at the far end and causing the liquid crystal molecules 91 to deflect. In this embodiment, the second switch Q2 is a control switch Q2, which can specifically be a MOS transistor.

[0060] S23: In response to the first common electrode 11 reaching the target potential, control the second switch Q2 to disconnect so that the first common electrode 11 stops being powered on.

[0061] Specifically, the control module 40 determines that the first common electrode 11A_COM reaches the target potential. It can be understood that if the first common electrode 11 does not reach the target potential, the second switch Q2 remains open, enabling the first common electrode 11 and the second common electrode 12 to conduct, and the first common electrode 11 can continue to be powered until it reaches the target potential. If the first common electrode 11 reaches the target potential, the control module 40 can control the second switch Q2 to stop working. Since the voltage difference between the gate and the source of the second switch Q2 MOS transistor is small, the second switch Q2 can be controlled to stop working. At this time, the first common electrode 11 in the display panel 200 is powered by an external common electrode.

[0062] Please refer to Figure 7 and Figure 8 , Figure 7 is Figure 5 a flowchart showing the sub-steps of step S3 provided, Figure 8 and is the power-on timing diagram provided by this application.

[0063] S3: In response to receiving the first frame synchronization signal, the control module 40 outputs a high level, causing the first switch Q1 to be in an on state and enabling the first common electrode 11 to be input into the display panel 200; simultaneously, the control power output line 15 inputs a first voltage higher than the coupling voltage to the pixel unit 71.

[0064] Specifically, when receiving the first frame synchronization signal (STV) sent by the timing controller, that is, when detecting that the timing controller outputs the first STV, a high level is output through the timing controller, causing the first switch Q1 to open, so that the first common electrode 11A_COM can be input into the display panel 200. STV is a clock signal and can also be CK. STV or CK can be equivalent to the scan signal (GATE) inside the display panel 200. While the timing controller controls the first common electrode 11 to be input into the display panel 200, at this time, the timing controller outputs black screen data (data), that is, the timing controller can input a first voltage, that is, the black screen voltage, to the pixel unit 71 through the power output line 15 (S_out). It can be understood that this black screen voltage is higher than the coupling voltage between the second common electrode 12 and the pixel unit 71. Since the voltage rise of the first common electrode 11 has a small coupling effect on the pixel unit 71 at this time, the display panel 200 still shows black at this time. By detecting that when the timing controller TCON sends the first STV signal, the first common electrode 11A_Com starts to send signals to the display panel 200, and at the same time, the first frame data of the timing controller TCON sends black screen, thus avoiding the abnormal situation of screen flashing during startup.

[0065] Such as Figure 7As shown, in this embodiment, step S3 of controlling the power supply output line 15 to input a first voltage higher than the coupling voltage to the pixel unit 71 may include:

[0066] S31: Control the power supply output line 15 to input a first voltage higher than the coupling voltage to the pixel unit 71 within the time of one frame of the picture.

[0067] Specifically, when inputting a first voltage higher than the coupling voltage to the pixel unit 71 through the power supply output line 15, it needs to be input within the time of one frame of the display panel 200, that is, not exceeding the time of one frame of the picture, so as to avoid the voltage of the pixel unit 71 dropping too much and causing problems such as whitening, and further avoid the appearance of a whitening area 101 at the top of the display panel 200. The time of one frame of the picture is related to the current working frequency. In this embodiment, it can be obtained by calculating the ratio of the unit time to the working frequency.

[0068] In this embodiment, in response to receiving the first frame synchronization signal, the control module 40 outputs a high level, so that the first switch Q1 is in the on state, and the first common electrode 11 is input into the display panel 200. At the same time, step S3 of controlling the power supply output line 15 to input a first voltage higher than the coupling voltage to the pixel unit 71 may further include:

[0069] S32: The control module 40 outputs a high level, and controls the power supply output line 15 to input a first voltage to the pixel unit 71, so that the voltage difference between the pixel unit 71 and the second common electrode 12 is less than or equal to 1.5V.

[0070] Specifically, as Figure 8 shown, when the control module 40 outputs a high level and controls the power supply output line 15 to input a first voltage to the pixel unit 71, it is necessary to dynamically detect whether the voltage difference between the pixel unit 71 and the second common electrode 12 is less than or equal to 1.5V. Since if the voltage difference between the pixel unit 71 and the second common electrode 12 is greater than 1.5V, it will cause the liquid crystal molecules 91 to deflect, resulting in the display panel 200 turning white. Therefore, when the control module 40 outputs a high level and controls the power supply output line 15 to input a first voltage to the pixel unit 71, the voltage difference between the pixel unit 71 and the second common electrode 12 being less than or equal to 1.5V can prevent the display panel 200 from turning white when the first voltage is input.

[0071] Please refer to Figure 9 , Figure 9 which Figure 5 is a schematic flowchart of the steps after step S3 provided.

[0072] In response to receiving the first frame synchronization signal, the control module 40 outputs a high level, causing the first switch Q1 to be in an on state and enabling the first common electrode 11 to be input into the display panel 200. Meanwhile, after step S3 of controlling the power output line 15 to input a first voltage higher than the coupling voltage to the pixel unit 71, the following steps may further be included:

[0073] S4: In response to receiving the second frame synchronization signal, the control module 40 controls the power output line 15 to input a display picture voltage to the pixel unit 71; wherein the display picture voltage is higher than the first voltage.

[0074] Specifically, if the timing control module 40 receives the second frame synchronization signal, the timing control module 40 sends normal display picture data and charges the pixel unit 71 through the control of the power output line 15, that is, inputs the voltage of the normal display picture to the pixel unit 71, so that the display panel 200 can display normally.

[0075] The driving method of the display panel disclosed in this application includes: upon receiving a power-on signal, controlling the first switch to be in an off state; controlling the first common electrode not to be powered on through the first switch, and the pixel unit is coupled with the second common electrode to reach the same voltage as the second common electrode; in response to receiving the first frame synchronization signal, the control module outputs a high level, causing the first switch to be in an on state and enabling the first common electrode to be input into the display panel; meanwhile, the power output line is controlled to input a first voltage higher than the coupling voltage to the pixel unit. By differentially controlling the input voltages of the first common electrode, the second common electrode, and the pixel unit through the first switch and the second switch at the moment of power-on, when receiving the first frame synchronization signal, and when receiving the second frame synchronization signal, the display panel can display normally at power-on without the situations of white display or screen flashing.

[0076] The above are only the embodiments of this application, and do not limit the patent scope of this application accordingly. Any equivalent structural or equivalent process transformation made by using the content of the specification and drawings of this application, or directly or indirectly applied in other related technical fields, shall be equally included in the patent protection scope of this application.

Claims

1. A driving method for a display panel, characterized in that, Including: Upon receiving a power-on signal, control the first switch to be in the off state; Control the first common electrode not to be powered on through the first switch, and the pixel unit is coupled with the second common electrode to reach the same voltage as the second common electrode; In response to receiving the first frame synchronization signal, the control module outputs a high level, causing the first switch to be in the on state and the first common electrode to be input into the display panel; meanwhile, control the power output line to input a first voltage higher than the coupling voltage to the pixel unit; Wherein, the control that the first common electrode is not powered on through the first switch, and the pixel unit is coupled with the second common electrode to reach the same voltage as the second common electrode includes: While controlling the first common electrode not to be powered on, control the second common electrode to be powered on; Control the second switch to open, then the first common electrode is conducted with the second common electrode; In response to the first common electrode reaching the target potential, control the second switch to disconnect so that the first common electrode stops being powered on.

2. The method according to claim 1, wherein The control that the power output line inputs a first voltage higher than the coupling voltage to the pixel unit includes: Control the power output line to input a first voltage higher than the coupling voltage to the pixel unit within the time of one frame of the picture.

3. The method according to claim 2, wherein The time of one frame of the picture is obtained by the ratio of the unit time to the working frequency.

4. The method according to claim 1, wherein In response to receiving the first frame synchronization signal, the control module outputs a high level, causing the first switch to be in the on state and the first common electrode to be input into the display panel; meanwhile, control the power output line to input a first voltage higher than the coupling voltage to the pixel unit, including: The control module outputs a high level and controls the power output line to input a first voltage to the pixel unit, such that the voltage difference between the pixel unit and the second common electrode is less than or equal to 1.5V.

5. The method according to claim 4, wherein After in response to receiving the first frame synchronization signal, the control module outputs a high level, causing the first switch to be in the on state and the first common electrode to be input into the display panel; meanwhile, control the power output line to input a first voltage higher than the coupling voltage to the pixel unit, including: In response to receiving the second frame synchronization signal, the control module controls the power output line to input a display picture voltage to the pixel unit; wherein the display picture voltage is higher than the first voltage.

6. A common voltage output circuit for a display panel, characterized in that, Including: A common electrode, including a first common electrode and a second common electrode, the first common electrode and the second common electrode cooperate to form a voltage for driving the liquid crystal molecules to deflect; A control switch, disposed between the first common electrode and the second common electrode, for conducting or disconnecting the electrical connection between the first common electrode and the second common electrode; wherein, the control switch includes: A gate, electrically connected to the second common electrode; The source electrode is electrically connected to the first common electrode; The drain electrode is connected to the second common electrode through an equivalent resistor, and a voltage difference is maintained between the gate electrode and the drain electrode through the equivalent resistor.

7. The circuit according to claim 6, characterized in that, It further includes: A thin-film transistor switch is electrically connected to the power output line and is used to control the output voltage of the power output line; A liquid crystal capacitor is disposed between the thin-film transistor switch and the second common electrode and is used to drive the deflection of the liquid crystal molecules; A storage capacitor is electrically connected to the liquid crystal capacitor and the thin-film transistor switch and is used to charge the liquid crystal capacitor to maintain the charge of the liquid crystal capacitor.

8. The circuit according to claim 7, wherein Both the control switch and the thin-film transistor switch are MOS transistors.

9. A display panel, characterized in that, It is electrically connected to the common voltage output circuit according to any one of claims 6 to 8 above.

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