Radiation-hardened flip-flop circuit resistant to single event transients and single event upsets

Abstract

The application discloses an anti-radiation reinforced flip-flop circuit resisting single event transient and single event upset, which comprises an inverter circuit, a clock control inverter circuit, a latch unit, a delay circuit and a driving inverter circuit; the output end of the first inverter circuit is connected with the input end of the first clock control inverter circuit and the input end of the delay circuit; the output end of the delay circuit is connected with the input end of the second clock control inverter circuit; the output end of the first clock control inverter circuit is connected with the first latch unit and the third clock control inverter circuit; the output end of the second clock control inverter circuit is connected with the first latch unit and the fourth clock control inverter circuit; the output end of the fourth clock control inverter circuit is connected with the second latch unit; and the output end of the third clock control inverter circuit is connected with the second latch unit and the driving inverter circuit. The application can simultaneously realize single event upset reinforcement and single event transient reinforcement.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of circuit design, and particularly relates to an anti-radiation reinforced flip-flop circuit resisting single event transient and single event upset. BACKGROUND

[0002] Single event transient (SET) refers to that when a high-energy particle strikes a sensitive region of a device, a transient pulse is generated in the device. The transient pulse propagates downward along a data path in a circuit and can be latched by a timing unit in the circuit, thereby causing an output fault of the circuit system and a soft error. Single event upset (SEU) refers to that a single high-energy particle strikes a sensitive region of an integrated circuit device, and a logic state of the device is flipped. Error data generated by the single event upset can cause an error instruction and trigger system function disorder, affect the normal operation of a space system, and even cause a catastrophic accident. The single event upset mainly occurs in a timing circuit. When a high-energy particle strikes a sensitive node of the timing circuit, a charged particle interacts with a semiconductor material to generate an electron-hole pair. The carriers move under the action of a concentration gradient and an electric field, and are accumulated at the sensitive node. When a certain degree is reached, the level at the sensitive node is changed, and the storage state of the timing circuit is changed, that is, the single event upset. In addition, when a combinational logic circuit is struck by a particle, SET can be generated in the combinational logic circuit. Although it does not directly cause a storage unit to flip, it can propagate to an input end of a timing circuit and indirectly cause the timing circuit to flip.

[0003] A flip-flop circuit is a basic unit in a timing circuit, and the anti-radiation performance thereof is very critical. At present, the circuit structure for improving the anti-single event upset performance of the flip-flop mainly uses double modular redundancy design, triple modular redundancy design, transistor cascade, transistor stacking and the like. These structures have certain inhibitory effect on the single event upset, but at the same time, a large area and power consumption overhead are increased, and with the decrease of the process size, the reinforcement effect of these structures is getting worse and worse. SUMMARY

[0004] The application solves the problem: overcoming the deficiencies of the prior art, providing an anti-radiation reinforced flip-flop circuit resisting single event transient and single event upset, aiming to simultaneously realize anti-single event upset reinforcement and anti-single event transient reinforcement.

[0005] In order to solve the above technical problems, the application discloses an anti-radiation hardened flip-flop circuit resistant to single event transient and single event upset, comprising: an inverter circuit, a clock control inverter circuit, a latch unit, a delay circuit and a driving inverter circuit; wherein the inverter circuit comprises: a first inverter circuit, a second inverter circuit and a third inverter circuit; the clock control inverter circuit comprises: a first clock control inverter circuit, a second clock control inverter circuit, a third clock control inverter circuit and a fourth clock control inverter circuit; the latch unit comprises: a first latch unit and a second latch unit.

[0006] The output end of the first inverter circuit is connected to the input end of the first clock control inverter circuit and the input end of the delay circuit respectively.

[0007] The output end of the delay circuit is connected to the input end of the second clock control inverter circuit.

[0008] The output end of the first clock control inverter circuit is connected to the input end in11 of the first latch unit and the input end of the third clock control inverter circuit respectively.

[0009] The output end of the second clock control inverter circuit is connected to the input end in12 of the first latch unit and the input end of the fourth clock control inverter circuit respectively.

[0010] The output end of the fourth clock control inverter circuit is connected to the input end in22 of the second latch unit.

[0011] The output end of the third clock control inverter circuit is connected to the input end in21 of the second latch unit and the input end of the driving inverter circuit respectively.

[0012] In the anti-radiation hardened flip-flop circuit resistant to single event transient and single event upset, the second inverter circuit and the third inverter circuit are further included.

[0013] The second inverter circuit and the third inverter circuit are connected in series, and are used for providing clock signal CK1 and clock signal CK2 for the first clock control inverter circuit, the second clock control inverter circuit, the third clock control inverter circuit, the fourth clock control inverter circuit, the first latch unit and the second latch unit.

[0014] In the anti-radiation hardened flip-flop circuit resistant to single event transient and single event upset,

[0015] The input end of the second inverter circuit is connected to an input clock signal CLK.

[0016] The second inverter circuit outputs a clock signal CK1, and the third inverter circuit outputs a clock signal CK2; wherein the clock signal CK1 and the clock signal CK2 are complementary clock signals, that is, the clock signal CK1 is an inverted signal of the clock signal CLK, and the clock signal CK2 is an inverted signal of the clock signal CK1; the clock signal CK1 and the clock signal CK2 jointly control the propagation of the data signal in the flip-flop circuit.

[0017] In the anti-radiation hardened flip-flop circuit with anti-single event transient and anti-single event upset as described above, the clock control inverter circuit is an inverter circuit controlled by a set of complementary clock signals, comprising: a PMOS transistor P21, a PMOS transistor P22, an NMOS transistor N21 and an NMOS transistor N22.

[0018] The PMOS transistor P21, the PMOS transistor P22, the NMOS transistor N21 and the NMOS transistor N22 are connected in series.

[0019] The gate of the PMOS transistor P22 is connected to the clock signal CK1, and the NMOS transistor N21 is connected to the clock signal CK2; or, the gate of the PMOS transistor P22 is connected to the clock signal CK2, and the NMOS transistor N21 is connected to the clock signal CK1.

[0020] The gates of the PMOS transistor P21 and the NMOS transistor N22 are used as the input end of the clock control inverter circuit, for connecting the input signal.

[0021] In the anti-radiation hardened flip-flop circuit with anti-single event transient and anti-single event upset as described above, the delay circuit is composed of N delay units connected in series, for making the time delay between the input signal of the first clock control inverter circuit and the input signal of the second clock control inverter circuit greater than the single event pulse width of the corresponding process.

[0022] In the anti-radiation hardened flip-flop circuit with anti-single event transient and anti-single event upset as described above, the delay unit is composed of a plurality of inverters; the width-length ratio and the stage number of the MOS transistors constituting the inverter are determined according to the range of the process single event pulse width.

[0023] In the anti-radiation hardening flip-flop circuit of the above anti-single event transient and anti-single event upset, the latch unit comprises: an inverter D1, an inverter D2, an inverter D3 and an inverter D4; wherein the inverter D1 comprises: a PMOS tube P41, a PMOS tube P42, an NMOS tube N41 and an NMOS tube N42 connected in series; the inverter D2 comprises: a PMOS tube P43, a PMOS tube P44, an NMOS tube N43 and an NMOS tube N44 connected in series; the inverter D3 comprises: a PMOS tube P45, a PMOS tube P46, an NMOS tube N45 and an NMOS tube N46 connected in series; the inverter D4 comprises: a PMOS tube P47, a PMOS tube P48, an NMOS tube N47 and an NMOS tube N48 connected in series.

[0024] The input signal in1 is connected to the gate of the PMOS tube P42, the gate of the NMOS tube N41, the gate of the PMOS tube P44, the gate of the NMOS tube N43 and the output terminal of the inverter D3 respectively;

[0025] The input signal in2 is connected to the gate of the PMOS tube P41, the gate of the NMOS tube N42, the gate of the PMOS tube P43, the gate of the NMOS tube N44 and the output terminal of the inverter D4 respectively;

[0026] The gates of the PMOS tube P46 and the PMOS tube P48 are connected to the clock signal CK1 respectively, and the gates of the NMOS tube N45 and the NMOS tube N47 are connected to the clock signal CK2 respectively; or, the gates of the PMOS tube P46 and the PMOS tube P48 are connected to the clock signal CK2 respectively, and the gates of the NMOS tube N45 and the NMOS tube N47 are connected to the clock signal CK1 respectively.

[0027] The output terminal n1 of the inverter D1 is connected to the gate of the PMOS tube P45 and the gate of the NMOS tube N48 respectively; and the output terminal n2 of the inverter D2 is connected to the gate of the NMOS tube N46 and the gate of the PMOS tube P47 respectively.

[0028] In the anti-radiation hardening flip-flop circuit of the above anti-single event transient and anti-single event upset, for the latch unit, when the states of the input signal in1 and the input signal in2 are the same, the inverter D1 and the inverter D2 are turned on, the input signal in1 and the input signal in2 are transmitted downward, and then the states of the output terminal n1 and the output terminal n2 are changed.

[0029] In the anti-radiation hardening flip-flop circuit with anti-single event transient and anti-single event upset, for the latch unit, when the clock signal CK1 is high level "1" and the clock signal CK2 is low level "0", the PMOS tube P46, the PMOS tube P48, the NMOS tube N45 and the NMOS tube N47 are in the closed state, and the state of the output end n1 and the output end n2 cannot be transmitted to the data input end of the latch unit through the inverter D3 and the inverter D4; when the clock signal CK1 is low level "0" and the clock signal CK2 is high level "1", the PMOS tube P46, the PMOS tube P48, the NMOS tube N45 and the NMOS tube N47 are in the conducting state, and the state of the output end n1 and the output end n2 is transmitted to the data input end of the latch unit through the inverter D3 and the inverter D4.

[0030] In the anti-radiation hardening flip-flop circuit with anti-single event transient and anti-single event upset, the latch unit adopts the combination of the circuit hardening technology and the layout hardening technology to realize the anti-single event upset hardening of internal nodes.

[0031] The present application has the following advantages:

[0032] (1) The present application discloses an anti-radiation hardening flip-flop circuit with anti-single event transient and anti-single event upset, which can simultaneously harden single event upset and single event transient.

[0033] (2) The circuit structure designed by the present application can reduce the dynamic power consumption of the circuit.

[0034] (3) The present application adopts the combination of circuit design and layout design, and has good hardening effect. DETAILED DESCRIPTION

[0035] Figure 1 Fig. 1 is a circuit structure diagram of an anti-radiation hardening flip-flop circuit with anti-single event transient and anti-single event upset in an embodiment of the present application;

[0036] Figure 2 Fig. 2 is a circuit structure diagram of a clock control inverter circuit in an embodiment of the present application;

[0037] Figure 3 Fig. 3 is a circuit structure diagram of a delay unit in an embodiment of the present application;

[0038] Figure 4 Fig. 4 is a circuit structure diagram of a latch unit in an embodiment of the present application;

[0039] Figure 5 Fig. 5 is a functional schematic diagram of the latch unit in an embodiment of the present application;

[0040] Figure 6is a schematic diagram of a flip-flop circuit for filtering out single event transient pulses in a data input signal D in the embodiments of the present application. DETAILED DESCRIPTION

[0041] In order to make the objects, technical solutions and advantages of the present application clearer, the disclosed embodiments of the present application will be further described in detail below with reference to the drawings.

[0042] The present application discloses an anti-radiation hardened flip-flop circuit against single event transient and single event upset, mainly comprising an inverter circuit, a clock-controlled inverter circuit, a delay circuit and a latch unit. The inverter circuit is used for inverting a data input signal D, an inverted clock input signal CLK and outputting a data output signal Q. The clock-controlled inverter circuit is used for controlling the propagation of the data signal in the flip-flop circuit. The delay circuit is used for generating two data signals with a certain time delay, and the delay width is greater than the single event pulse width of the corresponding process. The latch unit has strong single event upset resistance, and in combination with the delay circuit, it can effectively filter out single event transient pulses in the data input signal D. The anti-radiation hardened flip-flop circuit structure realized by the present application has strong single event transient and single event upset resistance.

[0043] As Figure 1 In the present embodiment, the anti-radiation hardened flip-flop circuit against single event transient and single event upset comprises an inverter circuit, a clock-controlled inverter circuit, a latch unit, a delay circuit and a driving inverter circuit 109. Specifically, the inverter circuit can comprise a first inverter circuit 101, a second inverter circuit 110 and a third inverter circuit 111; the clock-controlled inverter circuit can comprise a first clock-controlled inverter circuit 103, a second clock-controlled inverter circuit 104, a third clock-controlled inverter circuit 105 and a fourth clock-controlled inverter circuit 106; and the latch unit can comprise a first latch unit 107 and a second latch unit 108.

[0044] The output end of the first inverter circuit 101 is connected to the input end of the first clock-controlled inverter circuit 103 and the input end of the delay circuit respectively; the output end of the delay circuit is connected to the input end of the second clock-controlled inverter circuit 104; the output end of the first clock-controlled inverter circuit 103 is connected to the input end in11 of the first latch unit 107 and the input end of the third clock-controlled inverter circuit 105 respectively; the output end of the second clock-controlled inverter circuit 104 is connected to the input end in12 of the first latch unit 107 and the input end of the fourth clock-controlled inverter circuit 106 respectively; the output end of the fourth clock-controlled inverter circuit 106 is connected to the input end in22 of the second latch unit 108; and the output end of the third clock-controlled inverter circuit 105 is connected to the input end in21 of the second latch unit 108 and the input end of the driving inverter circuit 109 respectively.

[0045] In the embodiment, the anti-radiation hardened flip-flop circuit against single event transient and single event upset can further comprise a second inverter circuit 110 and a third inverter circuit 111. The second inverter circuit 110 and the third inverter circuit 111 are connected in series, and are configured to provide clock signal CK1 and clock signal CK2 for the first clock-controlled inverter circuit 103, the second clock-controlled inverter circuit 104, the third clock-controlled inverter circuit 105, the fourth clock-controlled inverter circuit 106, the first latch unit 107, and the second latch unit 108.

[0046] Preferably, the input end of the second inverter circuit 110 is connected to the input clock signal CLK, the second inverter circuit 110 outputs clock signal CK1, and the third inverter circuit 111 outputs clock signal CK2. The clock signal CK1 and the clock signal CK2 are complementary clock signals, that is, the clock signal CK1 is the inverse signal of the clock signal CLK, and the clock signal CK2 is the inverse signal of the clock signal CK1. The clock signal CK1 and the clock signal CK2 jointly control the propagation of the data signal in the flip-flop circuit.

[0047] In the embodiment, the clock-controlled inverter circuit is an inverter circuit controlled by a set of complementary clock signals. As shown in FIG. 1, the clock-controlled inverter circuit comprises a PMOS transistor P21, a PMOS transistor P22, an NMOS transistor N21, and an NMOS transistor N22. Figure 2 The PMOS transistor P21, the PMOS transistor P22, the NMOS transistor N21, and the NMOS transistor N22 are connected in series. The gate of the PMOS transistor P22 is connected to the clock signal CK1, and the NMOS transistor N21 is connected to the clock signal CK2; or, the gate of the PMOS transistor P22 is connected to the clock signal CK2, and the NMOS transistor N21 is connected to the clock signal CK1; for example, for the first clock-controlled inverter circuit 103 and the second clock-controlled inverter circuit 104, the gate of the PMOS transistor P22 is connected to the clock signal CK2, and the NMOS transistor N21 is connected to the clock signal CK1; for the third clock-controlled inverter circuit 105 and the fourth clock-controlled inverter circuit 106, the gate of the PMOS transistor P22 is connected to the clock signal CK1, and the NMOS transistor N21 is connected to the clock signal CK2. The gates of the PMOS transistor P21 and the NMOS transistor N22 are connected together as the input end of the clock-controlled inverter circuit, and are configured to receive the input signal.

[0048] In the embodiment, the delay circuit is composed of N delay units 102 connected in series, and is configured to make the time delay between the input signal of the first clock-controlled inverter circuit 103 and the input signal of the second clock-controlled inverter circuit 104 greater than the single event pulse width of the corresponding process. Figure 3As shown, the delay unit 102 is composed of several inverters; the width-length ratio of MOS tubes constituting the inverters and the number of stages are determined according to the range of the single-particle pulse width of the process.

[0049] Preferably, the delay circuit requires an overall delay greater than the single-particle pulse width of the selected process. Since the delay circuit is not on the data path D to Q, it does not increase the Tdelay of the flip-flop circuit. The output signal of the delay circuit is connected to the input end in12 of the first latch unit 107. When a single particle enters the delay circuit, even if a single-particle transient pulse is generated, due to the presence of the clock-controlled inverter and latch unit behind, the transient pulse will not be captured by the flip-flop circuit.

[0050] In the present embodiment, the latch unit has two data input ends and two clock signal input ends, and is mainly used to realize the function of storing data according to the timing signal. The latch unit realizes the anti-single-particle flip-flop reinforcement of the internal nodes by combining the circuit reinforcement technology and the layout reinforcement technology. As shown in the figure, Figure 4 As shown, the latch unit can specifically include: an inverter D1, an inverter D2, an inverter D3 and an inverter D4. Among them, the inverter D1 includes: PMOS tube P41, PMOS tube P42, NMOS tube N41 and NMOS tube N42 connected in series; the inverter D2 includes: PMOS tube P43, PMOS tube P44, NMOS tube N43 and NMOS tube N44 connected in series; the inverter D3 includes: PMOS tube P45, PMOS tube P46, NMOS tube N45 and NMOS tube N46 connected in series; the inverter D4 includes: PMOS tube P47, PMOS tube P48, NMOS tube N47 and NMOS tube N48 connected in series.

[0051] Preferably, the input signal in1 is connected to the gate of PMOS P42, the gate of NMOS N41, the gate of PMOS P44, the gate of NMOS N43 and the output of inverter D3, respectively. The input signal in2 is connected to the gate of PMOS P41, the gate of NMOS N42, the gate of PMOS P43, the gate of NMOS N44 and the output of inverter D4, respectively. The gates of PMOS P46 and PMOS P48 are connected to clock signal CK1, and the gates of NMOS N45 and NMOS N47 are connected to clock signal CK2, respectively; or, the gates of PMOS P46 and PMOS P48 are connected to clock signal CK2, and the gates of NMOS N45 and NMOS N47 are connected to clock signal CK1, respectively; for example, for the first latch unit 107, the gates of PMOS P46 and PMOS P48 are connected to clock signal CK1, and the gates of NMOS N45 and NMOS N47 are connected to clock signal CK2, respectively; for the second latch unit 108, the gates of PMOS P46 and PMOS P48 are connected to clock signal CK2, and the gates of NMOS N45 and NMOS N47 are connected to clock signal CK1, respectively. The output n1 of inverter D1 is connected to the gate of PMOS P45 and the gate of NMOS N48, respectively; and the output n2 of inverter D2 is connected to the gate of NMOS N46 and the gate of PMOS P47, respectively.

[0052] Preferably, for the latch unit, when the states of input signal in1 and input signal in2 are different (one is low "0" and the other is high "1"), one PMOS and one NMOS of inverter D1 and inverter D2 are in the off state, and the inverters are not conducting. Only when the states of input signal in1 and input signal in2 are the same (both are low "0" or both are high "1"), the inverters D1 and D2 can conduct, and the input data signals in1 and in2 can be passed down, and then the states of output n1 and output n2 are changed. As shown in Fig. 2, between t1 and t2, in1 is high "1" and in2 is low "0", and the states of n1 and n2 are not changed. Only when in1 and in2 are changed from low "0" to high "1" (at t2), n1 and n2 begin to change the original states from high "1" to low "0". Other cases are analyzed similarly. Figure 5

[0053] ​Preferably, for the latch unit, when the clock signal CK1 is high "1" and the clock signal CK2 is low "0", the PMOS P46, PMOS P48, NMOS N45 and NMOS N47 are in the off state, and the state of the output n1 and the output n2 cannot be transmitted to the data input of the latch unit through the inverters D3 and D4; when the clock signal CK1 is low "0" and the clock signal CK2 is high "1", the PMOS P46, PMOS P48, NMOS N45 and NMOS N47 are in the on state, and the state of the output n1 and the output n2 is transmitted to the data input of the latch unit through the inverters D3 and D4.

[0054] Preferably, the four inverters D1-D4 in the latch unit are all composed of four transistors in series, which have stronger anti-single event upset characteristics than ordinary inverters. Analyzing the internal node n1 of the latch unit, when in1 and in2 inputs are high "1", the output signal n1 of the inverter D1 is low "0", at this time, all PMOS tubes are closed and all NMOS tubes are opened, in this case, a single particle incident to the NMOS N41 or NMOS N42 tube will not cause n1 to flip, regardless of the angle. When a single particle only hits the PMOS P41, at this time, the PMOS P42 is closed and will not cause n1 to flip, when a single particle hits the PMOS P42, at this time, since the PMOS P41 is closed, the voltage fluctuation of n1 will not cause n1 to flip. Only when a single particle hits the PMOS P41 and the PMOS P42 at the same time, it is possible to cause n1 to flip. Compared with the traditional inverter structure, the latch unit has better SEU characteristics. The internal node n2 of the latch unit is analyzed in the same way.

[0055] Preferably, in the latch unit structure, the input signal in1 is connected to the gate of the PMOS P42, the gate of the NMOS N41, the gate of the PMOS P44 and the gate of the NMOS N43; the input signal in2 is connected to the gate of the PMOS P41, the gate of the NMOS N42, the gate of the PMOS P43 and the gate of the NMOS N44. Due to the similar C-cell circuit connection structure between the four transistors inside the inverter (D1 or D2), regardless of the state of the input signals in1 and in2, there is no case of four transistors (two PMOS and two NMOS) being turned on at the same time in operation, and there will be no large current between VDD and GND, so there will be no large dynamic power consumption.

[0056] In this embodiment, in the latch cell structure, when the clock signal CK1 is high "1" and the clock signal CK2 is low "0", the PMOS P46, NMOS N45, PMOS P48, NMOS N47 are in the off state, and since no cross-coupled inverter structure is formed, SET will only be generated, not SEU, when all single nodes inside the latch cell are struck by a single particle. When the clock signal CK1 is low "0" and the clock signal CK2 is high "1", the four inverters are all in the on state. The internal node single particle resistance characteristics are analyzed below.

[0057] When in1 and in2 inputs are high "1", the output signals n1 and n2 of the inverter D1 and the inverter D2 are low "0". The NMOS N41 and the NMOS N42, the NMOS N43 and the NMOS N44, the PMOS P45 and the PMOS P46, the PMOS P47 and the PMOS P48 are struck by a single particle, and none of them will have an impact on the circuit. Considering the worst case that the PMOS P41 and the PMOS P42 are struck by a single particle at the same time, and n1 state becomes high "1". At this time, the NMOS N46 and the PMOS P45 in the inverter D3 are off, and the state of in1 will not be changed. The data path D to Q is not affected, and the state of the data output port of the flip-flop circuit is not changed. Considering the worst case that the PMOS P43 and the PMOS P44 are struck by a single particle at the same time, and n2 state becomes high "1". At this time, the PMOS P47 and the NMOS N48 in the inverter D4 are off, and the state of in2 will not be changed. The four transistors in the inverter D3 are all in the on state, and the voltage of in1 is pulled low from high "1". When the circuit is designed, the driving capability of the PMOS P45 and the PMOS P46 is increased, and at this moment, it can be ensured that in1 maintains the high "1" state. After the single particle strike ends, the electron-hole pair recombines or is collected by light, the n1 node voltage is pulled back to low "0", and the circuit returns to normal. The state of the data output port of the flip-flop circuit is not changed. Considering the worst case that the NMOS N45 and the NMOS N46 are struck by a single particle at the same time, and in1 state becomes low "0". Since in1 and in2 states are different, n1 and n2 nodes will not be affected. After the single particle strike ends, the electron-hole pair recombines or is collected by light, the in1 node voltage is pulled back to high "1", and the circuit returns to normal. Considering the worst case that the NMOS N47 and the NMOS N48 are struck by a single particle at the same time, and in2 state becomes low "0". Since in1 and in2 states are different, n1 and n2 nodes will not be affected. Also, the state of in1 will not be changed. The data path D to Q is not affected. The state of the data output port of the flip-flop circuit is not changed.

[0058] When the in1 and in2 inputs are low "0", the output signals n1 and n2 of the inverters D1 and D2 are high "1". The PMOS P41 and PMOS P42, PMOS P43 and PMOS P44, NMOS N45 and NMOS N46, NMOS N47 and NMOS N48 are respectively hit by single particles, and none of them will affect the circuit. Considering the worst case that the NMOS N41 and NMOS N42 are hit by single particles at the same time, and the n1 state becomes low "0". The PMOS P47 and NMOS N48 in the inverter D4 are closed, and will not affect the in2 node. The four transistors in the inverter D3 are all in the open state, and since the driving ability of the PMOS P45 and PMOS P46 is strong, the in1 node voltage is pulled up and is greater than the threshold voltage. In this case, after the single particle hits, since the in1 is high and the in2 is low, the inverter D1 is in the closed state, and cannot pull the n1 back to high "1", the in1 abnormal state is locked, so the NMOS N41 and NMOS N42 are sensitive nodes. The present application combines layout hardening technology to isolate the sensitive nodes of the NMOS N41 and NMOS N42. The probability of the NMOS N41 and NMOS N42 being hit at the same time is reduced, so as to achieve the purpose of resisting single particle flip. Considering the worst case that the NMOS N43 and NMOS N44 are hit by single particles at the same time, and the n2 state becomes low "0". Since the PMOS P45 and NMOS N46 in the inverter D3 are in the closed state, the in1 state will not be changed. The data path D to Q is not affected. The state of the data output port of the flip-flop circuit is not changed. Considering the worst case that the PMOS P45 and PMOS P46 are hit by single particles at the same time, and the in1 state becomes high "1". Since the in1 and in2 states are different, the n1 and n2 nodes will not be affected. After the single particle hits, the electron-hole pairs are recombined or collected by light, the in1 node voltage is pulled back to low "0", and the circuit returns to normal. Considering the worst case that the PMOS P47 and PMOS P48 are hit by single particles at the same time, and the in2 state becomes high "1". Since the in1 and in2 states are different, the n1 and n2 nodes will not be affected. The state of the in1 will not change. The data path D to Q is not affected. The state of the data output port of the flip-flop circuit is not changed.

[0059] In the embodiment, the output signal of the data input signal D after passing through the first inverter circuit 101 is connected to the input end of the first clock control inverter circuit 103 and the input end of the delay circuit respectively; the output signal of the delay circuit is connected to the input end of the second clock control inverter circuit 104; the output of the first clock control inverter circuit 103 is connected to the input end in11 of the first latch unit 107 and the input end of the third clock control inverter circuit 105 respectively; the output of the second clock control inverter circuit 104 is connected to the input end in12 of the first latch unit 107 and the input end of the fourth clock control inverter circuit 106 respectively; the output of the fourth clock control inverter circuit 106 is connected to the input end in22 of the second latch unit 108; the output of the third clock control inverter circuit 105 is connected to the input end in21 of the second latch unit 108 and the input end of the drive inverter circuit 109 respectively, and the output data output signal Q is output after passing through the drive inverter circuit 109. When the combinational logic circuit is bombarded by particles, SET may be generated in the combinational logic circuit, which does not directly cause the storage unit to flip, but can propagate to the input end of the timing circuit to indirectly cause the data to flip. The flip-flop circuit constructed by the first clock control inverter circuit 103, the second clock control inverter circuit 104, the delay circuit and the latch unit in the embodiment can effectively filter out the single event transient pulse in the data input signal D. As shown in FIG. 3, at t0-t4, CK2 is low "0". The data input signal D is initially low "0". At t1, the data input signal D is affected by the single particle and a transient pulse upward appears, and the data input signal D remains in the high level "1" state for a period of time. Due to the existence of the delay circuit, the two input signals in1 and in2 of the latch unit have a certain time delay between each other, and the high level state of the input signals in1 and in2 is not at the same time, so it will not be captured by the latch unit. Other cases are analyzed in the same way. Figure 6

[0060] Although the present application has been disclosed with the above preferred embodiments, it is not intended to limit the present application, and any person skilled in the art can make possible changes and modifications to the technical solutions of the present application by using the disclosed methods and technical contents without departing from the spirit and scope of the present application. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application, which does not deviate from the technical solutions of the present application, shall fall within the protection scope of the technical solutions of the present application.

[0061] The contents not described in detail in the specification of the present application belong to the known technology of the person skilled in the art.​

Claims

1. A radiation-hardened flip-flop circuit resistant to single event transients and single event upsets, characterized in that, Comprise: Inverter circuit, clock control inverter circuit, latch unit, delay circuit and drive inverter circuit (109); wherein, the inverter circuit, comprising: first inverter circuit (101), second inverter circuit (110) and third inverter circuit (111); Clock control inverter circuit, comprising: first clock control inverter circuit (103), second clock control inverter circuit (104), third clock control inverter circuit (105) and fourth clock control inverter circuit (106); Latch unit, comprising: first latch unit (107) and second latch unit (108); The output terminal of first inverter circuit (101) is connected with the input terminal of first clock control inverter circuit (103) and the input terminal of delay circuit respectively; The output terminal of delay circuit is connected with the input terminal of second clock control inverter circuit (104); The output terminal of first clock control inverter circuit (103) is connected with the input terminal in11 of first latch unit (107) and the input terminal of third clock control inverter circuit (105) respectively; The output terminal of second clock control inverter circuit (104) is connected with the input terminal in12 of first latch unit (107) and the input terminal of fourth clock control inverter circuit (106) respectively; The output terminal of fourth clock control inverter circuit (106) is connected with the input terminal in22 of second latch unit (108); The output terminal of third clock control inverter circuit (105) is connected with the input terminal in21 of second latch unit (108) and the input terminal of drive inverter circuit (109) respectively; The latch unit comprises: inverters D1, D2, D3 and D4; wherein the inverter D1 comprises: PMOS tubes P41, P42, NMOS tubes N41 and N42 connected in series; the inverter D2 comprises: PMOS tubes P43, P44, NMOS tubes N43 and N44 connected in series; the inverter D3 comprises: PMOS tubes P45, P46, NMOS tubes N45 and N46 connected in series; the inverter D4 comprises: PMOS tubes P47, P48, NMOS tubes N47 and N48 connected in series; wherein the input signal in1 is connected to the gate of the PMOS tube P42, the gate of the NMOS tube N41, the gate of the PMOS tube P44, the gate of the NMOS tube N43 and the output terminal of the inverter D3 respectively; the input signal in2 is connected to the gate of the PMOS tube P41, the gate of the NMOS tube N42, the gate of the PMOS tube P43, the gate of the NMOS tube N44 and the output terminal of the inverter D4 respectively; the gate of the PMOS tube P46 and the gate of the PMOS tube P48 are connected to the clock signal CK1 respectively, and the gate of the NMOS tube N45 and the gate of the NMOS tube N47 are connected to the clock signal CK2 respectively; or, the gate of the PMOS tube P46 and the gate of the PMOS tube P48 are connected to the clock signal CK2 respectively, and the gate of the NMOS tube N45 and the gate of the NMOS tube N47 are connected to the clock signal CK1 respectively; the output terminal n1 of the inverter D1 is connected to the gate of the PMOS tube P45 and the gate of the NMOS tube N48 respectively; and the output terminal n2 of the inverter D2 is connected to the gate of the NMOS tube N46 and the gate of the PMOS tube P47 respectively.

2. The anti-single event transient and anti-single event upset hardened flip-flop circuit of claim 1, wherein, The second inverter circuit (110) and the third inverter circuit (111) are connected in series, and are used for providing the clock signal CK1 and the clock signal CK2 for the first clock control inverter circuit (103), the second clock control inverter circuit (104), the third clock control inverter circuit (105), the fourth clock control inverter circuit (106), the first latch unit (107) and the second latch unit (108).

3. The radiation-hardened flip-flop circuit according to claim 2, wherein, an input terminal of the second inverter circuit (110) is connected to an input clock signal CLK; the second inverter circuit (110) outputs a clock signal CK1, and the third inverter circuit (111) outputs a clock signal CK2; wherein the clock signal CK1 and the clock signal CK2 are complementary clock signals, that is, the clock signal CK1 is an inverted signal of the clock signal CLK, and the clock signal CK2 is an inverted signal of the clock signal CK1; the clock signal CK1 and the clock signal CK2 jointly control the propagation of a data signal in the flip-flop circuit.

4. The anti-single event transient and anti-single event upset radiation-hardened flip-flop circuit of claim 1, wherein, The clock control inverter circuit is an inverter circuit controlled by a set of complementary clock signals, comprising a PMOS transistor P21, a PMOS transistor P22, an NMOS transistor N21 and an NMOS transistor N22. The PMOS transistor P21, the PMOS transistor P22, the NMOS transistor N21 and the NMOS transistor N22 are connected in series. The gate of the PMOS transistor P22 is connected to a clock signal CK1, and the gate of the NMOS transistor N21 is connected to a clock signal CK2; or, the gate of the PMOS transistor P22 is connected to a clock signal CK2, and the gate of the NMOS transistor N21 is connected to a clock signal CK1. The gates of the PMOS transistor P21 and the NMOS transistor N22 are connected together as an input terminal of the clock control inverter circuit, for connecting an input signal.

5. The anti-single event transient and anti-single event upset radiation-hardened flip-flop circuit of claim 1, wherein, The delay circuit is composed of N delay units (102) connected in series, for making the time delay between the input signal of the first clock control inverter circuit (103) and the input signal of the second clock control inverter circuit (104) greater than the single particle pulse width of the corresponding process.

6. The anti-single event transient and anti-single event upset hardened flip-flop circuit of claim 5, wherein, The delay unit (102) is composed of a plurality of inverters; the width-length ratio and the number of MOS transistors constituting the inverter are determined according to the range of the single particle pulse width of the process.

7. The anti-single event transient and anti-single event upset hardened flip-flop circuit of claim 1, wherein, For the latch unit, when the states of the input signal in1 and the input signal in2 are the same, the inverter D1 and the inverter D2 are turned on, and the input signal in1 and the input signal in2 are transmitted downward, thereby changing the states of the output terminal n1 and the output terminal n2.

8. The anti-single event transient and anti-single event upset radiation-hardened flip-flop circuit of claim 1, wherein, For the latch unit, when the clock signal CK1 is high "1" and the clock signal CK2 is low "0", the PMOS transistor P46, the PMOS transistor P48, the NMOS transistor N45 and the NMOS transistor N47 are in the off state, and the states of the output terminal n1 and the output terminal n2 cannot be transmitted to the data input terminal of the latch unit through the inverter D3 and the inverter D4; when the clock signal CK1 is low "0" and the clock signal CK2 is high "1", the PMOS transistor P46, the PMOS transistor P48, the NMOS transistor N45 and the NMOS transistor N47 are in the on state, and the states of the output terminal n1 and the output terminal n2 are transmitted to the data input terminal of the latch unit through the inverter D3 and the inverter D4.

9. The anti-single event transient and anti-single event upset radiation-hardened flip-flop circuit of claim 1, wherein, The latch unit adopts a combination of circuit hardening technology and layout hardening technology to realize the anti-single event upset hardening of internal nodes.

Images