Device for generating a control signal

Abstract

The present application provides a control signal generating device, which includes: a first unit, a second unit, and a third unit. The generating device can generate a control signal with a duty cycle gradually increasing from 0 to 100%, or generate a control signal with an output pulse width gradually increasing. Thus, the high-side switch provides a gradually increasing current to a large-capacitance capacitor according to the control signal, so that the load-carrying capacity of the high-side switch is gradually enhanced.

Description

Technical Field

[0001] The present application relates to the field of electrical control technologies, and particularly to a control signal generation device. Background Art

[0002] A high-side switch usually integrates an overcurrent protection function. When the high-side switch triggers the overcurrent protection function, the high-side switch is in an off state. After the high-side switch triggers the overcurrent protection function, after waiting for a certain period of time, the high-side switch will restart. During the restart process of the high-side switch, if the overcurrent protection function is not triggered again, the high-side switch restarts successfully; if the overcurrent protection function can still be triggered, the high-side switch will turn off again. Each time the high-side switch restarts, the power supply can charge a capacitor.

[0003] The restart period of the high-side switch is much longer than the sum of the current rise time and fall time during the restart process of the high-side switch, so that the current provided by the high-side switch to a load such as a capacitor is limited. For example, when the restart period is 2 ms, the current is 0.3 A. That is to say, during the restart of the high-side switch, the load-carrying capacity of the high-side switch is only 0.3 A. For a large-capacitance capacitor as a load, the high-side switch is likely to trigger the overcurrent protection function.

[0004] In the traditional technology, a pulse width modulation signal (PWM) with a fixed pulse width or duty cycle is used to control the on and off of the high-side switch, so that the power supply charges the capacitor. However, if the pulse width is too narrow or the duty cycle is too small, the current pulse provided by the high-side switch to the capacitor is too small. If the pulse width is too wide or the duty cycle is too large, the high-side switch will trigger the overcurrent protection function. In this way, it is not conducive to the power supply to charge the capacitor. Summary of the Invention

[0005] The present application provides a control signal generation device, which can generate a control signal with a duty cycle gradually increasing from 0 to 100%, or generate a control signal with an output pulse width gradually increasing.

[0006] In a first aspect, the present application provides a control signal generation device, which includes: a first unit, a second unit, and a third unit;

[0007] A first input terminal of the first unit is electrically connected to the second unit, a second input terminal of the first unit is electrically connected to the third unit, and an output terminal of the first unit is used to output a control signal with a duty cycle gradually increasing from 0 to 100%, or output a control signal with an output pulse width gradually increasing;

[0008] The second unit is configured to output a first signal to the first unit, and the voltage value of the first signal gradually increases within a first period;

[0009] The third unit is configured to output a second signal to the first unit. During the first period, the voltage value of the second signal repeats a process of gradually increasing from a first voltage value to a second voltage value, where the first voltage value is less than the second voltage value. The first signal and the second signal can intersect multiple times, and the intersection area formed by the Nth and the (N + 1)th intersections is less than the intersection area formed by the (N + 2)th and the (N + 3)th intersections, where N is the number of intersections and N is an odd number taking all values greater than or equal to 1 and less than or equal to the total number of intersections;

[0010] The first unit is configured to output a control signal according to the first signal and the second signal. The control signal is used to control the conduction and turn-off of the high-side switch during the first period. The high level of the control signal is related to the intersection area of the first signal and the second signal.

[0011] Through the control signal generation device of the first aspect, the generation device includes: a first unit, a second unit, and a third unit. The second unit can output a first signal to the first unit, and the voltage value of the first signal gradually increases during the first period. The third unit can output a second signal to the first unit. During the first period, the voltage value of the second signal repeats a process of gradually increasing from a first voltage value to a second voltage value, where the first voltage value is less than the second voltage value. Among them, the first signal and the second signal can intersect multiple times, and the intersection area formed by the Nth and the (N + 1)th intersections is less than the intersection area formed by the (N + 2)th and the (N + 3)th intersections, so that the intersection area of the first signal and the second signal gradually increases. The first unit can output a control signal for controlling the conduction and turn-off of the high-side switch during the first period according to the first signal and the second signal. By virtue of the high level of the control signal being related to the intersection area of the first signal and the second signal, the duty cycle of the control signal can gradually increase from 0 to 100%. Thus, the high-side switch provides a gradually increasing current to the large-capacity capacitor according to the control signal, and the load-carrying capacity of the high-side switch gradually increases.

[0012] In a possible design, the first unit is a first comparator; the positive input terminal of the first comparator is electrically connected to the second unit, and the negative input terminal of the first comparator is electrically connected to the third unit;

[0013] The first comparator is configured to output the high level of the control signal when the voltage value of the first signal is greater than the voltage value of the second signal; and output the low level of the control signal when the voltage value of the first signal is less than the voltage value of the second signal.

[0014] In a possible design, the second unit includes a first current source and a first capacitor; the first end of the first capacitor is electrically connected to the first current source, the second end of the first capacitor is grounded, and the connection point between the first end of the first capacitor and the first current source is electrically connected to the first input terminal of the first unit.

[0015] In a possible design, the third unit includes a second current source, a second capacitor, a switching transistor, a second comparator, and a delay module;

[0016] A first end of the second capacitor is electrically connected to the second current source, a second end of the second capacitor is grounded, a connection point between the first end of the second capacitor and the second current source is electrically connected to a positive input terminal of the second comparator, a negative input terminal of the second comparator is configured to receive a second voltage value, an output terminal of the second comparator is electrically connected to a first end of the delay module, a second end of the delay module is electrically connected to a first end of the switching transistor, a second end of the switching transistor is connected between the connection point and the positive input terminal of the second comparator, and a third end of the switching transistor is grounded.

[0017] In a possible design, a change rate of a duty cycle of the control signal is related to a change rate of the first signal and a change rate of the second signal.

[0018] In a second aspect, the present application provides a control signal generating device, which includes: a first unit, a second unit, and a third unit;

[0019] A first input terminal of the first unit is electrically connected to the second unit, a second input terminal of the first unit is electrically connected to a first end of the third unit, a second end of the third unit is electrically connected to an output terminal of the first unit, and the output terminal of the first unit is configured to output a control signal whose duty cycle gradually increases from 0 to 100%, or output a control signal whose pulse width gradually increases;

[0020] The second unit is configured to output a first signal to the first unit. During a first period, a voltage value of the first signal repeatedly undergoes a process of gradually decreasing step by step from a first voltage value to a second voltage value, where the first voltage value is greater than the second voltage value;

[0021] The third unit is configured to output a second signal to the first unit. During the first period, a voltage value of the second signal increases step by step, and a minimum voltage value of the second signal is greater than the second voltage value and less than the first voltage value;

[0022] The first unit is configured to output a control signal according to the first signal and the second signal. The control signal is used to control conduction and turn-off of a high-side switch during the first period, and a high level of the control signal is related to a voltage value of the first signal and a voltage value of the second signal.

[0023] A generating device for the control signal of the second aspect, the generating device includes: a first unit, a second unit and a third unit. The second unit can output a first signal to the first unit. During the first period, the voltage value of the first signal repetitively undergoes a process of gradually decreasing step by step from a first voltage value to a second voltage value, where the first voltage value is greater than the second voltage value. The third unit can output a second signal to the first unit. During the first period, the voltage value of the second signal increases step by step. The minimum voltage value of the second signal is greater than the second voltage value and less than the first voltage value, making the moment when the voltage value of the second signal is equal to the voltage value of the first signal gradually advance. The first unit can output a control signal for controlling the conduction and cutoff of the high-side switch during the first period according to the first signal and the second signal. By virtue of the high level of the control signal being related to the voltage values of the first signal and the second signal, the duty cycle of the control signal gradually increases from 0 to 100%. Thus, the high-side switch provides a gradually increasing current to the large-capacitance capacitor according to the control signal, making the load-carrying capacity of the high-side switch gradually increase.

[0024] In a possible design, the first unit includes a comparator and an inverter; the positive input terminal of the comparator is electrically connected to the second unit, the negative input terminal of the comparator is electrically connected to the first terminal of the third unit, the output terminal of the comparator is electrically connected to the first terminal of the inverter, and the second terminal of the inverter is electrically connected to the second terminal of the third unit;

[0025] The comparator is used to output the high level of the control signal when the voltage value of the first signal is greater than the voltage value of the second signal; and output the low level of the control signal when the voltage value of the first signal is less than the voltage value of the second signal;

[0026] The inverter is used to invert the level of the control signal.

[0027] In a possible design, the second unit is a counter. The input terminal of the counter is connected to a clock signal, and the output terminal of the counter is electrically connected to the first input terminal of the first unit.

[0028] In a possible design, the third unit includes a step controller, an adder and a D flip-flop; the first input terminal of the adder is used to be electrically connected to the step controller, the step controller is used to set the minimum voltage value of the second signal, the second input terminal of the adder is electrically connected between the output terminal of the D flip-flop and the second input terminal of the first unit, the output terminal of the adder is electrically connected to the D input terminal of the D flip-flop, the clock control terminal of the D flip-flop is electrically connected to the output terminal of the first unit, and the output terminal of the D flip-flop is electrically connected to the second input terminal of the first unit.

[0029] In a possible design, the change rate of the duty cycle of the control signal is related to the duration of the voltage value of the first signal decreasing step by step from the first voltage value to the second voltage value, the first voltage value, and the minimum voltage value of the second signal. Description of the Drawings

[0030] Figure 1 Schematic diagram of the restart period of a high-side switch provided in an embodiment of the present application;

[0031] Figure 2 Schematic diagram of the duty cycle of a PWM provided in an embodiment of the present application;

[0032] Figure 3 Schematic structural diagram of a control signal generation device provided in an embodiment of the present application;

[0033] Figure 4 Signal waveform diagram of a control signal generation device provided in an embodiment of the present application;

[0034] Figure 5 Schematic structural diagram of a control signal generation device provided in an embodiment of the present application;

[0035] Figure 6 Schematic structural diagram of a first unit provided in an embodiment of the present application;

[0036] Figure 7 Schematic structural diagram of a control signal generation device provided in an embodiment of the present application;

[0037] Figure 8 Signal waveform diagram of a control signal generation device provided in an embodiment of the present application;

[0038] Figure 9 Schematic structural diagram of a control signal generation device provided in an embodiment of the present application;

[0039] Figure 10 Schematic diagram of a control signal generation device in actual application provided in an embodiment of the present application. Detailed Embodiments

[0040] In this application, "at least one" means one or more, and "a plurality" means two or more. "And / or" describes the relationship between related objects and indicates that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, or B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the related objects before and after are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single items or plural items. For example, at least one of a alone, b alone, or c alone can represent: a alone, b alone, c alone, the combination of a and b, the combination of a and c, the combination of b and c, or the combination of a, b, and c, where a, b, and c can be single or multiple. In addition, the terms "first" and "second" are only used for descriptive purposes and should not be construed as indicating or implying relative importance.

[0041] The orientation or positional relationship indicated by terms such as "center", "longitudinal", "lateral", "upper", "lower", "left", "right", "front", "rear", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing this application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application.

[0042] The terms "connected" and "coupled" should be understood in a broad sense. For example, the "connection" or "coupling" of a circuit structure can refer not only to a physical connection but also to an electrical connection or a signal connection. For example, it can be a direct connection, that is, a physical connection, or it can be indirectly connected through at least one intermediate element, as long as the circuit is electrically connected. It can also be the internal connection of two elements; a signal connection can refer not only to a signal connection through a circuit but also to a signal connection through a media medium, such as radio waves. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0043] The light-emitting diode (LED) drive circuit operates in the PWM mode. For the need of electromagnetic compatibility (EMC), generally a large-capacitance filter capacitor is added at the front end of the LED drive circuit.

[0044] The above-described LED drive circuit usually uses a high-side switch to drive a large-capacitance filter capacitor. In addition, the high-side switch can also drive large-capacitance capacitors in other circuits or chips.

[0045] The high-side switch integrates an overcurrent protection function. When the high-side switch triggers the overcurrent protection function, the high-side switch is in the off state. Among them, the overcurrent protection function means that when the current of the load exceeds the set threshold, the high-side switch turns off, disconnecting the electrical connection between the load and the power supply.

[0046] Among them, the threshold is also the overcurrent (OC) threshold.

[0047] The high-side switch has a hiccup restart function. That is to say, after the high-side switch triggers the overcurrent protection function, after waiting for a certain time, the high-side switch will restart. During the restart process of the high-side switch, if the high-side switch does not trigger the overcurrent protection function again, the high-side switch restarts successfully; if the high-side switch can still trigger the overcurrent protection function, the high-side switch turns off again. Among them, the restart period of the high-side switch is generally on the order of milliseconds, such as 2ms.

[0048] When the high-side switch drives a capacitor with a large capacitance value, when the high-side switch is turned on, the power supply can charge the capacitor. During the charging process of the capacitor, a surge current will be caused. If the surge current is too high, the high-side switch will trigger the overcurrent protection function. After the high-side switch triggers the overcurrent protection function, every time the high-side switch restarts, the power supply can charge the capacitor.

[0049] Among them, the capacitor with a large capacitance value is the load.

[0050] The restart period of the high-side switch is much larger than the sum of the current rise time and fall time during the restart process of the high-side switch, so that the current provided by the high-side switch to the capacitor is limited.

[0051] Refer to Figure 1 , Figure 1 is a schematic diagram of the restart period of a high-side switch provided by an embodiment of the present application. As Figure 1 shown, the restart period is 2ms (i.e., 2000us), and the OC threshold is 30A. During the restart process, the current rise time is 20us, and the current fall time is 20us.

[0052] During the restart of the high-side switch, the current provided by the high-side switch to the load can be determined by the following formula (1):

[0053]

[0054] Among them, I avg1 is the current provided by the high-side switch to the capacitor, Q1 is the first electric quantity, f retry is the restart frequency, I OC is the OC threshold, t r is the rise time, t f is the fall time, T retry is the restart period.

[0055] Therefore, during the restart of the high-side switch, the current provided by the high-side switch to the load is 0.3 A. That is to say, the load-carrying capacity of the high-side switch is only 0.3 A.

[0056] If the actual current consumed by the load is less than 0.3 A, the high-side switch will not trigger the overcurrent protection function again, which means that the high-side switch restarts successfully. In this way, the input voltage of the load will gradually increase with each restart.

[0057] Among them, once the high-side switch restarts successfully, the load-carrying capacity of the high-side switch will increase rapidly.

[0058] If the actual current consumed by the load is greater than 0.3 A, the high-side switch can still trigger the overcurrent protection function, which means that the high-side switch will turn off again. In this way, the high-side switch will always be in the restart state. That is to say, for a large-capacitance capacitor as the load, this will make it difficult for the input voltage of the load to reach the power supply voltage.

[0059] In summary, the high-side switch can only drive capacitors with a small capacitance value (such as 330 uF). If the high-side switch drives a capacitor with a large capacitance value (such as more than 330 uF), the overcurrent protection function will be triggered.

[0060] In the traditional technology, a pulse width modulation signal (PWM) with a fixed pulse width or duty cycle is used to control the on and off of the high-side switch, so that the high-side switch can avoid triggering the overcurrent protection function when driving a capacitor with a large capacitance value. Thus, the power supply can charge the capacitor, and the voltage across the capacitor gradually increases.

[0061] However, if the pulse width is too narrow or the duty cycle is too small, the current pulse provided by the high-side switch to the capacitor is too small. If the pulse width is too wide or the duty cycle is too large, the high-side switch will trigger the overcurrent protection function. In this way, it is not conducive to the power supply to charge the capacitor.

[0062] In addition, the equivalent series resistance (ESR) of the capacitor can affect the rising rate of the current provided by the high-side switch to the capacitor, and the temperature will affect the ESR of the capacitor. In this way, at different temperatures, the ESR of the capacitor will change greatly, resulting in a large rising slope of the current. That is to say, the change rate of the current per microsecond (us) is large.

[0063] Therefore, at different temperatures, different ESRs of capacitors and different power supply voltages, the pulse width or duty cycle of the PWM required by the high-side switch is different.

[0064] If a PWM with a fixed pulse width or duty cycle is adopted, then it is very difficult for the high-side switch to determine a suitable pulse width or a PWM with a duty cycle under different temperatures, different ESRs of capacitors, and different power supply voltages.

[0065] Refer to Figure 2 , Figure 2 which is a schematic diagram of the duty cycle of a PWM provided by an embodiment of the present application. As Figure 2 shown, as the duty cycle of the PWM increases, the output current capacity of the high-side switch gradually increases. This means that the load-carrying capacity of the high-side switch gradually increases.

[0066] It should be noted that: the output current capacity of the high-side switch does not refer to the current that the high-side switch can actually output. In actual applications, it is very likely that the voltage across the capacitor reaches the power supply voltage before the high-side switch triggers the overcurrent protection function. After the capacitor is fully charged, the current input from the high-side switch to the capacitor will decrease.

[0067] During the process of the duty cycle of the PWM gradually increasing, the duty cycle of the PWM only increases to a certain value, and then the high-side switch will trigger the overcurrent protection function. Since the duty cycle of the PWM gradually increases, the duty cycle before the high-side switch triggers the overcurrent protection function will be very close to the duty cycle corresponding to the moment when the overcurrent protection function is triggered. That is to say, before the high-side switch triggers the overcurrent protection function, the current provided by the high-side switch to the load is very close to the OC threshold.

[0068] Among them, the frequency of the PWM is determined according to the period of the PWM. The smaller the period of the PWM, the larger the frequency of the PWM. And the frequency of the PWM will affect the load-carrying capacity of the high-side switch. Therefore, the embodiment of the present application adopts a high-frequency PWM.

[0069] In this way, for example, when the frequency of the PWM is 10 KHz, before the high-side switch triggers the overcurrent protection function, the current provided by the high-side switch to the load can be determined by the following formula (2):

[0070]

[0071] Among them, I avg2 is the current provided by the high-side switch to the load, f PWM is the frequency of the PWM, Q2 is the second electric quantity, I OC is the OC threshold, t r is the rise time, t f is the fall time, and T PWM is the period of the PWM.

[0072] Therefore, before the overcurrent protection function is triggered at the high side, the current provided by the high-side switch to the load is 6A. 6A is much larger than the load-carrying capacity of 0.3A of the high-side switch during restart.

[0073] In summary, before the overcurrent protection function is triggered at the high side, during the charging process of the capacitor, the current consumed by the capacitor is less than 6A. Therefore, it is only necessary to ensure that the change rate of the duty cycle of the PWM is small enough, and the power supply can gradually charge the load until the voltage across the capacitor reaches the power supply voltage.

[0074] Based on this, the present application provides a control signal generation device, which can generate a control signal with a duty cycle gradually increasing from 0 to 100%, or generate a control signal with a gradually increasing pulse width. Among them, the control signal generation device can be implemented based on an analog circuit implementation or a digital signal implementation.

[0075] Next, the implementation of the control signal generation device based on the analog circuit and the implementation of the control signal generation device based on the digital circuit will be introduced separately.

[0076] The implementation of the control signal generation device based on the analog circuit includes the following content:

[0077] Refer to Figure 3 , Figure 3 which is a schematic structural diagram of a control signal generation device provided by an embodiment of the present application. As Figure 3 shown, the generation device may include: a first unit 10, a second unit 20, and a third unit 30.

[0078] Among them, the first unit 10, the second unit 20, and the third unit 30 can be set separately or integrated.

[0079] In addition, the first unit 10, the second unit 20, and the third unit 30 can adopt a chip for analog signal transmission, or a circuit composed of components, etc.

[0080] The first input end of the first unit 10 is electrically connected to the second unit 20, the second input end of the first unit 10 is electrically connected to the third unit 30, and the output end of the first unit 10 can output a control signal with a duty cycle gradually increasing from 0 to 100%. That is to say, the output end of the first unit 10 can output a control signal with a gradually increasing pulse width.

[0081] The second unit 20 can output a first signal to the first unit 10, and the voltage value of the first signal gradually increases within the first period.

[0082] Among them, the first period refers to the duration during which the duty cycle of the control signal gradually increases from 0 to 100%.

[0083] The third unit 30 can output a second signal to the first unit 10, and within the first period, the voltage value of the second signal repeats the process of gradually increasing from a first voltage value to a second voltage value. Herein, the first voltage value is less than the second voltage value.

[0084] That is to say, the first period can include multiple time durations, and within each time duration, the voltage value of the second signal gradually increases from the first voltage value to the second voltage value.

[0085] Within the first period, the voltage value of the first signal gradually increases, and within the first period, the voltage value of the second signal repeats the process of gradually increasing from the first voltage value to the second voltage value. The first signal and the second signal can intersect multiple times. In this way, the intersections of the first signal and the second signal can form multiple intersection areas.

[0086] Among them, the intersection area formed by the first signal and the second signal at the Nth and (N + 1)th intersections is a, and the intersection area formed by the first signal and the second signal at the (N + 2)th and (N + 3)th intersections is b, where a is less than b. N is the number of intersections, and N is an odd number that takes all values greater than or equal to 1 and less than or equal to the total number of intersections. That is to say, the intersection area of the first signal and the second signal gradually increases.

[0087] Thus, the first unit 10 can output a control signal according to the first signal and the second signal.

[0088] Among them, the control signal controls the conduction and turn-off of the high-side switch within the first period. The control signal includes the high level of the control signal and the low level of the control signal. The high level of the control signal controls the high-side switch to conduct, and the low level of the control signal controls the high-side switch to turn off.

[0089] Among them, the high level of the control signal is related to the intersection area of the first signal and the second signal.

[0090] As the intersection area of the first signal and the second signal gradually increases, the duration of the high level of the control signal can gradually increase. This means that the duty cycle of the control signal gradually increases from 0 to 100%, or the pulse width of the control signal gradually increases.

[0091] Refer to Figure 4 , Figure 4 which is the signal waveform diagram of a control signal generation device provided in an embodiment of the present application. Figure 4 The solid line A in

[0092] represents the first signal, the dashed line B represents the second signal, and PWM represents the control signal. Figure 4As shown, when N = 1, the intersection area formed by the 1st and 2nd times is smaller than the intersection area formed by the 3rd and 4th times. Correspondingly, the duty cycle of the control signal within T0 - T1 is smaller than the duty cycle of the control signal within T1 - T2.

[0093] As Figure 4 shown, when N = 3, the intersection area formed by the 3rd and 4th times is smaller than the intersection area formed by the 5th and 6th times. Correspondingly, the duty cycle of the control signal within T1 - T2 is smaller than the duty cycle of the control signal within T2 - T3.

[0094] As Figure 4 shown, when N = 5, the intersection area formed by the 5th and 6th times is smaller than the intersection area formed by the 7th and 8th times. Correspondingly, the duty cycle of the control signal within T2 - T3 is smaller than the duty cycle of the control signal within T3 - T4.

[0095] As Figure 4 shown, when N = 7, the intersection area formed by the 7th and 8th times is smaller than the intersection area formed by the 9th and 10th times. Correspondingly, the duty cycle of the control signal within T3 - T4 is smaller than the duty cycle of the control signal within T4 - T5.

[0096] As Figure 4 shown, when N = 9, the intersection area formed by the 9th and 10th times is smaller than the intersection area formed by the 11th and 12th times. Correspondingly, the duty cycle of the control signal within T4 - T5 is smaller than the duty cycle of the control signal within T5 - T6.

[0097] It can be seen that Figure 4 in, the duty cycle or pulse width of the control signal is gradually increasing within T0 - T1, within T1 - T2, within T2 - T3, within T3 - T4, within T4 - T5, and within T5 - T6.

[0098] Among them, the change rate of the duty cycle or pulse width of the control signal is related to the change rate of the first signal and the change rate of the second signal.

[0099] The change rate of the first signal is small, and the change rate of the second signal is small. Furthermore, the rate of increase in the intersection area of the first signal and the second signal is the smallest, and the change rate of the duty cycle of the control signal is the slowest.

[0100] The change rate of the first signal is large, and the change rate of the second signal is small. Furthermore, the rate of increase in the intersection area of the first signal and the second signal is relatively small, and the change rate of the duty cycle of the control signal is relatively slow.

[0101] The change rate of the first signal is small, and the change rate of the second signal is large. Furthermore, the rate of increase in the intersection area of the first signal and the second signal is relatively fast, and the change rate of the duty cycle of the control signal is relatively fast.

[0102] The change rate of the first signal is large, and the change rate of the second signal is large. Furthermore, the rate of change of the intersection area between the first signal and the second signal is the largest, and the rate of change of the duty cycle of the control signal is the fastest.

[0103] Therefore, by adjusting the change rate of the first signal and / or the second signal, the change rate of the duty cycle or the pulse width of the control signal can be adjusted.

[0104] The control signal generating device provided by this application includes: a first unit, a second unit, and a third unit. The second unit can output a first signal to the first unit, and the voltage value of the first signal gradually increases within the first period. The third unit can output a second signal to the first unit, and within the first period, the voltage value of the second signal repeatedly goes through the process of gradually increasing from a first voltage value to a second voltage value, where the first voltage value is less than the second voltage value. Among them, the first signal and the second signal can intersect multiple times, and the intersection area formed by the Nth and the N + 1st times is less than the intersection area formed by the N + 2nd and the N + 3rd times, so that the intersection area between the first signal and the second signal gradually increases. The first unit can output a control signal for controlling the conduction and cutoff of the high-side switch within the first period according to the first signal and the second signal. By virtue of the high level of the control signal being related to the intersection area between the first signal and the second signal, the duty cycle of the control signal can gradually increase from 0 to 100%. Therefore, the high-side switch provides a gradually increasing current to the large-capacity capacitor according to this control signal, and the load-carrying capacity of the high-side switch gradually increases.

[0105] Based on the description of the above embodiments, the first unit 10 can have multiple implementation manners.

[0106] As a possible implementation manner of the first unit 10, refer to Figure 5 , Figure 5 which is a schematic structural diagram of a control signal generating device provided by an embodiment of this application. As shown in Figure 5 , the first unit 10 is a first comparator 11.

[0107] The positive input terminal of the first comparator 11 is electrically connected to the second unit 20, and the negative input terminal of the first comparator 11 is electrically connected to the third unit 30.

[0108] Among them, the positive input terminal of the first comparator 11 is the first input terminal of the first unit 10. The negative input terminal of the first comparator 11 is the second input terminal of the first unit 10.

[0109] Among them, the first signal is input to the first comparator 11 through the positive input terminal of the first comparator 11. The second signal is input to the first comparator 11 through the negative input terminal of the first comparator 11.

[0110] In summary, when the voltage value of the first signal is greater than the voltage value of the second signal, the first comparator 11 outputs a high level. In this way, the first unit 10 can output a high level of the control signal.

[0111] When the voltage value of the first signal is less than the voltage value of the second signal, the first comparator 11 outputs a low level. In this way, the first unit 10 can output a low level of the control signal.

[0112] As another possible implementation of the first unit 10, refer to Figure 6 , Figure 6 which is a schematic structural diagram of a first unit provided in an embodiment of the present application. As shown in Figure 6 , the first unit 10 may include: a third comparator 12 and an inverter 13.

[0113] The positive input terminal of the third comparator 12 is electrically connected to the third unit 30, the negative input terminal of the third comparator 12 is electrically connected to the second unit 20, the output terminal of the third comparator 12 is electrically connected to the input terminal of the inverter 13, and the output terminal of the inverter 13 is the output terminal of the first unit 10.

[0114] Among them, the positive input terminal of the third comparator 12 is the second input terminal of the first unit 10. The negative input terminal of the third comparator 12 is the first input terminal of the first unit 10.

[0115] Among them, the first signal is input to the third comparator 12 through the negative input terminal of the third comparator 12. The second signal is input to the third comparator 12 through the positive input terminal of the third comparator 12.

[0116] In summary, when the voltage value of the first signal is greater than the voltage value of the second signal, the third comparator 12 outputs a low level. Further, the inverter 13 can output a high level, so that the first unit 10 can output a high level of the control signal.

[0117] When the voltage value of the first signal is less than the voltage value of the second signal, the third comparator 12 outputs a high level. Further, the inverter 13 can output a low level, so that the first unit 10 can output a low level of the control signal.

[0118] Based on the description of the above embodiments, exemplarily, a possible implementation of the second unit 20. Continuing to refer to Figure 5 , the second unit 20 may include: a first current source 21 and a first capacitor C1.

[0119] The first end of the first capacitor C1 is electrically connected to the first current source 21, the second end of the first capacitor C1 is grounded, and the connection point D between the first end of the first capacitor C1 and the first current source 21 is electrically connected to the first input terminal of the first unit 10.

[0120] Since the second end of the first capacitor C1 is grounded, the voltage across the first capacitor C1 is equal to the voltage at the first end of the first capacitor C1. Thus, the first current source 21 charges the first capacitor C1, so that the voltage value of the voltage at the first end of the first capacitor C1 gradually increases from 0V. Thus, the voltage value of the first signal output by the second unit 20 gradually increases in the first period.

[0121] The first current source 21 and the first capacitor C1 affect the rate of change of the first signal. When the capacitance of the first capacitor C1 remains unchanged, the greater the current of the first current source 21, the greater the rate of change of the first signal. Conversely, the smaller the current of the first current source 21, the smaller the rate of change of the first signal.

[0122] When the current of the first current source 21 remains unchanged, the smaller the capacitance of the first capacitor C1 is, the greater the change rate of the first signal is; conversely, the larger the capacitance of the first capacitor C1 is, the smaller the change rate of the first signal is.

[0123] In some examples, the first current source 21 is a constant current source, so that the voltage value of the first signal gradually increases in a linear manner within the first period.

[0124] In summary, during the process of the first current source 21 charging the first capacitor C1, the voltage value of the first terminal of the first capacitor C1 gradually increases from 0 V. Thus, the voltage value of the first signal output by the second unit 20 gradually increases in the first period.

[0125] Based on the description of the above embodiment, a possible implementation of the third unit 30 is exemplified. Figure 5 The third unit 30 may include: a second current source 33, a second capacitor C2, a switch tube Q, a second comparator 31 and a delay module 32.

[0126] The first end of the second capacitor C2 is electrically connected to the second current source 33, the second end of the second capacitor C2 is grounded, the connection point E between the first end of the second capacitor C2 and the second current source 33 is electrically connected to the positive input end of the second comparator 31, the negative input end of the second comparator 31 is used to access the second voltage value, the output end of the second comparator 31 is electrically connected to the first end of the delay module 32, the second end of the delay module 32 is electrically connected to the first end of the switch tube Q, the second end of the switch tube Q is connected between the connection point E and the positive input end of the second comparator 31, and the third end of the switch tube Q is grounded.

[0127] The negative input terminal of the second comparator 31 is electrically connected to the first terminal of the current source 34 , and the second terminal of the current source 34 is grounded, so that the negative input terminal of the second comparator 31 can be connected to the second voltage value.

[0128] Among them, the switching transistor is, for example, an NMOS transistor. The first end of the switching transistor is the gate, the second end is the drain, and the third end is the source.

[0129] Since the second end of the second capacitor C2 is grounded, the voltage across the second capacitor C2 is equal to the voltage at the first end of the second capacitor C2, that is, the voltage at the connection point E. Thus, the second current source 33 charges the second capacitor C2, and the voltage value at the first end of the second capacitor C2 gradually increases from the first voltage value to the second voltage value. During this process, the voltage value at the first end of the second capacitor C2 is lower than the second voltage value.

[0130] Thus, when the first voltage value is less than the second voltage value, the second comparator 31 outputs a low level. This low level is transmitted to the gate of the switching transistor Q through the delay module 32, causing the switching transistor Q to be in the cut-off state. Thus, the second current source 33, the second capacitor C2, and the ground form a path, enabling the second current source 33 to charge the second capacitor C2. During the charging process of the second capacitor C2, the voltage value at the first end of the second capacitor C2 can gradually increase from the first voltage value to the second voltage value.

[0131] When the voltage value at the first end of the second capacitor C2 is higher than the second voltage value, the second comparator 31 outputs a high level. This high level is transmitted to the gate of the switching transistor Q through the delay module 32, causing the switching transistor Q to be in the conducting state. Thus, the second capacitor C2, the switching transistor Q, and the ground can form a loop, enabling the second capacitor C2 to discharge. During the discharging process of the second capacitor C2, the voltage value at the first end of the second capacitor C2 can quickly drop from the second voltage value to the first voltage value.

[0132] Among them, the second current source 33 and the second capacitor C2 affect the change rate of the second signal. When the capacitance value of the second capacitor C2 remains unchanged, the larger the current of the second current source 33, the greater the change rate of the second signal. Conversely, the smaller the current of the second current source 33, the smaller the change rate of the second signal.

[0133] When the current of the second current source 33 remains unchanged, the smaller the capacitance value of the second capacitor C2, the greater the change rate of the second signal. Conversely, the larger the capacitance value of the second capacitor C2, the smaller the change rate of the second signal.

[0134] In some examples, the second current source 33 is a constant current source, causing the voltage value of the second signal to linearly increase from the first voltage value to the second voltage value within the first period.

[0135] In addition, when the current of the first current source 21 is greater than the current of the second current source 33, and the capacitance value of the first capacitor C1 is less than the capacitance value of the second capacitor C2, the change rate of the first signal is greater than the change rate of the second signal.

[0136] When the current of the first current source 21 is less than the current of the second current source 33 and the capacitance value of the first capacitor C1 is greater than the capacitance value of the second capacitor C2, the change rate of the first signal is less than the change rate of the second signal.

[0137] In summary, the second capacitor C2 can be charged and discharged repeatedly in the above manner, so that the voltage value of the second signal can repeatedly increase gradually from the first voltage value to the second voltage value within the first period.

[0138] The implementation scheme of the control signal generation device based on digital circuits includes the following:

[0139] Refer to Figure 7 , Figure 7 which is a schematic structural diagram of a control signal generation device provided in an embodiment of the present application. As Figure 7 shown, the generation device may include: a first unit 40, a second unit 50, and a third unit 60.

[0140] Among them, the first unit 40, the second unit 50, and the third unit 60 may be separately provided or integrated.

[0141] In addition, the first unit 40, the second unit 50, and the third unit 60 may adopt a chip for digital signal transmission, or a circuit composed of components, etc.

[0142] The first input end of the first unit 40 is electrically connected to the second unit 50, the second input end of the first unit 40 is electrically connected to the first end of the third unit 60, the second end of the third unit 60 is electrically connected to the output end of the first unit 40, and the output end of the first unit 40 can output a control signal with a duty cycle gradually increasing from 0 to 100%. That is to say, the output end of the first unit 40 can output a control signal with a gradually increasing pulse width.

[0143] The second unit 50 can output a first signal to the first unit 40, and within the first period, the voltage value of the first signal repeatedly decreases step by step from the first voltage value to the second voltage value. Among them, the first voltage value is greater than the second voltage value.

[0144] Among them, the first period refers to the duration during which the duty cycle of the control signal gradually increases from 0 to 100%.

[0145] That is to say, the first period may include multiple time durations, and within each time duration, the voltage value of the first signal decreases step by step from the first voltage value to the second voltage value.

[0146] The third unit 60 can output a second signal to the first unit 40, and within the first period, the voltage value of the second signal increases step by step. Among them, the minimum voltage value of the second signal is greater than the second voltage value and less than the first voltage value.

[0147] Thus, the first unit can output a control signal according to the first signal and the second signal.

[0148] Wherein, the control signal controls the conduction and turn-off of the high-side switch within the first period. The control signal includes a high level of the control signal and a low level of the control signal. The high level of the control signal controls the conduction of the high-side switch, and the low level of the control signal controls the turn-off of the high-side switch.

[0149] Wherein, the high level of the control signal is related to the voltage value of the first signal and the voltage value of the second signal.

[0150] Wherein, within the first period, the voltage value of the first signal repeats the process of gradually decreasing step by step from the first voltage value to the second voltage value, and within the first period, the voltage value of the second signal increases step by step. Furthermore, the moment when the voltage value of the second signal is equal to the voltage value of the first signal gradually advances.

[0151] And the high level of the control signal is related to the voltage value of the first signal and the voltage value of the second signal. Furthermore, the longer the duration of the high level of the control signal, thus the duty cycle of the control signal gradually increases, or the pulse width of the control signal gradually increases.

[0152] Refer to Figure 8 , Figure 8 which is a signal waveform diagram of a control signal generation device provided in an embodiment of the present application. Figure 8 In [the figure], cnt represents the first signal, duty_current represents the second signal, PWM represents the control signal, PWM_b represents the reverse signal of the control signal, and clk represents the clock signal. As Figure 8 shown, the counting result corresponding to the first voltage value of the first signal is 15, and the counting result corresponding to the second voltage value is 0. The counting result corresponding to the minimum voltage value of the second signal is 2, that is, the step size of the counting result corresponding to the voltage value of the second signal gradually increases by 2.

[0153] As Figure 8 shown, the counting result corresponding to the voltage value of the first signal repeats the process of gradually decreasing step by step from 15 to 0. The counting result corresponding to the voltage value of the second signal starts from 2 and increases step by step with a step size of 2.

[0154] Within T0 - T2, the counting result corresponding to the voltage value of the first signal decreases step by step from 15 to 0. Within T0 - T1, the counting result corresponding to the voltage value of the second signal is 2. Within T1 - T2, the counting result corresponding to the voltage value of the second signal is 4.

[0155] Thus, within T0 - T1, the voltage value of the first signal is greater than that of the second signal. Consequently, the first unit 40 outputs a low level of the control signal.

[0156] At T1, when the counting result corresponding to the voltage value of the first signal is 2, the voltage value of the second signal is equal to that of the first signal. Therefore, within T1 - T2, the first unit 40 outputs a high level of the control signal. It can be seen that within T0 - T2, the moment when the voltage value of the second signal is equal to that of the first signal is T1. Thus, the first unit 40 outputs a low level of the control signal within T0 - T1, and the first unit 40 outputs a high level of the control signal within T1 - T2.

[0157] Within T2 - T4, the counting result corresponding to the voltage value of the first signal gradually decreases from 15 to 0 in a stepped manner. Within T2 - T3, the counting result corresponding to the voltage value of the second signal is 4. Within T3 - T4, the counting result corresponding to the voltage value of the second signal is 6.

[0158] So, within T2 - T3, the voltage value of the first signal is greater than that of the second signal. Thus, the first unit 40 outputs a low level of the control signal.

[0159] At T3, when the counting result corresponding to the voltage value of the first signal is 4, the voltage value of the second signal is equal to that of the first signal. Therefore, within T3 - T4, the first unit 40 outputs a high level of the control signal. It can be seen that within T2 - T4, the moment when the voltage value of the second signal is equal to that of the first signal is T3. Thus, the first unit 40 outputs a low level of the control signal within T2 - T3, and the first unit 40 outputs a high level of the control signal within T3 - T4.

[0160] In summary, the duration of T1 - T2 is less than that of T3 - T4. Therefore, the duty cycle of the control signal within T0 - T2 is less than that within T2 - T4, or the pulse width of the control signal within T0 - T2 is less than that within T2 - T4.

[0161] Therefore, the first unit can output a high level or a low level of the control signal according to the magnitude relationship between the voltage value of the first signal and that of the second signal. The high level of the control signal is related to the voltage values of the first signal and the second signal, and the longer the high level of the control signal lasts, the greater the duty cycle of the control signal gradually becomes, or the greater the pulse width of the control signal gradually becomes.

[0162] Among them, the change rate of the duty cycle or pulse width of the control signal is related to the duration of the voltage value of the first signal decreasing from the first voltage value to the second voltage value in a stepped manner, the first voltage value, and the minimum voltage value of the second signal.

[0163] The duration of the first signal voltage value decreasing from the first voltage value to the second voltage value in a stepwise manner affects the duration of the first cycle, and thus the duration of the first signal voltage value decreasing from the first voltage value to the second voltage value in a stepwise manner can affect the change rate of the duty cycle or pulse width of the control signal.

[0164] The first voltage value can affect the initial voltage value of the first signal, and thus the first voltage value can affect the duration of the first signal changing from the first voltage value to the second voltage value in a stepwise manner, thereby affecting the duty cycle or pulse width change rate of the control signal.

[0165] The minimum voltage value of the second signal can affect the magnitude between the voltage value of the first signal and the voltage value of the second signal, and thus the minimum voltage value of the second signal can affect the change rate of the duty cycle or pulse width of the control signal.

[0166] Thus, by adjusting the duration of the voltage value of the first signal changing from the first voltage value to the second voltage value in a step-by-step manner, the first voltage value and the minimum voltage value of the second signal, the duty cycle of the control signal or the rate of change of the pulse width can be adjusted.

[0167] The present application provides a control signal generating device, which includes: a first unit, a second unit and a third unit. The second unit can output a first signal to the first unit, and the voltage value of the first signal repeats the process of step-down from the first voltage value to the second voltage value in the first cycle, wherein the first voltage value is greater than the second voltage value; the third unit can output a second signal to the first unit, and the voltage value of the second signal increases in a step-by-step manner in the first cycle. Among them, the minimum voltage value of the second signal is greater than the second voltage value and less than the first voltage value, so that the moment when the voltage value of the second signal is equal to the voltage value of the first signal is gradually advanced. The first unit can output a control signal for controlling the conduction and shutdown of the high-side switch in the first cycle according to the first signal and the second signal, and the high level of the control signal is related to the voltage value of the first signal and the voltage value of the second signal, so that the duty cycle of the control signal gradually increases from 0 to 100%. Thereby, the high-side switch provides a gradually increasing current to the capacitor with a large capacitance according to the control signal, so that the load carrying capacity of the high-side switch is gradually enhanced.

[0168] Based on the description of the above embodiment, a possible implementation of the first unit 40 is exemplified. Figure 9 , Figure 9 This is a schematic diagram of the structure of a control signal generating device provided in one embodiment of the present application. Figure 9 As shown, the first unit 40 may include: a comparator 41 and an inverter 42 .

[0169] The positive input terminal of the comparator 41 is electrically connected to the second unit 50, the negative input terminal of the comparator 41 is electrically connected to the first terminal of the third unit 60, the output terminal of the comparator 41 is electrically connected to the first terminal of the inverter 42, and the second terminal of the inverter 42 is electrically connected to the second terminal of the third unit 60.

[0170] Among them, the positive input terminal of the comparator 41 is the first input terminal of the first unit 40. The negative input terminal of the comparator 41 is the second input terminal of the first unit 40.

[0171] Among them, the first signal is input to the comparator 41 through the positive input terminal of the comparator 41. The second signal is input to the comparator 41 through the negative input terminal of the comparator 41.

[0172] In this way, when the voltage value of the first signal is greater than the voltage value of the second signal, the comparator 41 outputs a high level, and this high level is inverted to a low level by the inverter. Thus, the first unit 40 can output a low level of the control signal.

[0173] When the voltage value of the first signal is less than the voltage value of the second signal, the comparator 41 outputs a low level, and this low level is inverted to a high level by the inverter. Thus, the first unit 40 can output a high level of the control signal.

[0174] In summary, when the voltage value of the first signal is greater than the voltage value of the second signal, the first unit 40 outputs a low level of the control signal. When the voltage value of the first signal is less than the voltage value of the second signal, the first unit 40 outputs a high level of the control signal.

[0175] Based on the description of the above embodiments, exemplarily, a possible implementation manner of the second unit 50. As Figure 9 shown, the second unit 50 is a counter 51.

[0176] The input terminal of the counter 51 is connected to the clock signal, and the output terminal of the counter 51 is electrically connected to the first input terminal of the first unit 40.

[0177] As Figure 8 shown, the counter 51 can convert the voltage value of the first signal into a counting result.

[0178] Based on the description of the above embodiments, exemplarily, a possible implementation manner of the third unit 60. As Figure 9 shown, the third unit 60 may include: a step controller 61, an adder 62, and a D flip-flop 63.

[0179] The first input terminal of the adder 62 is used for electrically connecting to the step controller 61. The second input terminal of the adder 62 is electrically connected between the output terminal of the D flip-flop 63 and the second input terminal of the first unit 40. The output terminal of the adder 62 is electrically connected to the D input terminal of the D flip-flop 63. The clock control terminal of the D flip-flop 63 is electrically connected to the output terminal of the first unit 40. The output terminal of the D flip-flop 63 is electrically connected to the second input terminal of the first unit 40.

[0180] Among them, the step controller 61 can set the counting result corresponding to the minimum voltage value of the second signal. For example, Figure 8 in, the step controller 61 sets the counting result corresponding to the minimum voltage value of the second signal to 2.

[0181] As Figure 8 shown, within T0 - T1, the output of the step controller 61 is 2. Through the adder 62, the D input terminal of the D flip-flop 63 is 2. The clock control terminal of the D flip-flop 63 is not a rising edge. Further, the D flip-flop 63 is set to 0, so that the output terminal of the D flip-flop 63 is 2. That is to say, within T0 - T1, the counting result corresponding to the voltage value of the second signal is 2.

[0182] At T1, the output of the step controller 61 is 2. Through the adder 62, the D input terminal of the D flip-flop 63 is 4. The clock control terminal of the D flip-flop 63 is a rising edge. Further, the D flip-flop 63 is set to 1, so that the output terminal of the D flip-flop 63 is 4. That is to say, at T1, the counting result corresponding to the voltage value of the second signal is 4.

[0183] Within T1 - T2, the output of the step controller 61 is 2. Through the adder 62, the D input terminal of the D flip-flop 63 is 6. The clock control terminal of the D flip-flop 63 is not a rising edge. Further, the D flip-flop 63 is set to 0, so that the output terminal of the D flip-flop 63 is 4. That is to say, within T1 - T2, the counting result corresponding to the voltage value of the second signal is 4.

[0184] At T2, the output of the step controller 61 is 2. Through the adder 62, the D input terminal of the D flip-flop 63 is 6. The clock control terminal of the D flip-flop 63 is not a rising edge. Further, the D flip-flop 63 is set to 0, so that the output terminal of the D flip-flop 63 is 4. That is to say, at T2, the counting result corresponding to the voltage value of the second signal is 4.

[0185] Within T2 - T3, the output of the step controller 61 is 2. Through the adder 62, the D input terminal of the D flip-flop 63 is 6. The clock control terminal of the D flip-flop 63 is not a rising edge. Further, the D flip-flop 63 is set to 0, so that the output terminal of the D flip-flop 63 is 4. That is to say, within T2 - T3, the counting result corresponding to the voltage value of the second signal is 4.

[0186] At T3, the output of the step controller 61 is 2. Through the adder 62, the D input terminal of the D flip-flop 63 is 6. The clock control terminal of the D flip-flop 63 is the rising edge. Then, the D flip-flop 63 is set to 1, so that the output terminal of the D flip-flop 63 is 6. That is to say, at T2, the counting result corresponding to the voltage value of the second signal is 6.

[0187] Within T3 - T4, the output of the step controller 61 is 2. Through the adder 62, the D input terminal of the D flip-flop 63 is 8. The clock control terminal of the D flip-flop 63 is not the rising edge. Then, the D flip-flop 63 is set to 0, so that the output terminal of the D flip-flop 63 is 6. That is to say, within T3 - T4, the counting result corresponding to the voltage value of the second signal is 6.

[0188] In summary, through the step controller 61, the adder 62, and the D flip-flop 63, the voltage value of the second signal can be made to increase step by step within the first period.

[0189] Next, the application of the control signal generation device provided in the embodiments of the present application in an actual scenario will be introduced.

[0190] Using the control signal generation device provided in the embodiments of the present application, a control signal with a duty cycle gradually increasing from 0 to 100% or a control signal with a gradually increasing pulse width is generated. Figure 10 Among them, the frequency of the PWM is 10KHz, the capacitance value of the capacitor bank is 3000uF, the ESR of the capacitor bank is 10Ω, and the power supply voltage is 13.5V. Among them, the capacitor bank is a capacitor bank formed by three 1000uF capacitors in parallel.

[0191] Refer to Figure 10 , Figure 10 is a schematic diagram of the application of a control signal generation device provided in an embodiment of the present application in actual use. Figure 10 In, VCC represents the power supply voltage, Vout represents the output voltage of the high-side switch, Ic represents the charging current of the capacitor, and PWM represents the control signal.

[0192] As Figure 10 shown, the duty cycle of the PWM gradually increases from 0. When the duty cycle of the PWM is very small, the conduction time of the high-side switch is very small, making the charging current Ic of the capacitor almost equal to 0. As the duty cycle of the PWM gradually increases, the conduction time of the high-side switch gradually becomes longer, the charging current Ic of the capacitor gradually increases, and the output voltage Vout of the high-side switch gradually increases, enabling the voltage of the capacitor to reach the power supply voltage VCC. At the duty cycle of the PWM corresponding to T0, the capacitor stores enough electrical energy, so that the charging current Ic of the capacitor gradually decreases.

[0193] In summary, by using the control signal generation device provided in the embodiments of the present application, the high-side switch can drive three parallel capacitor banks of 1000 uF and an ESR of 10 Ω.

[0194] Finally, it should be noted that the above embodiments are only specific implementation manners of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions within the technical scope disclosed in the present application should be covered within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A control signal generating device, characterized in that, The generating device includes: a first unit, a second unit, and a third unit; A first input end of the first unit is electrically connected to the second unit, a second input end of the first unit is electrically connected to the third unit, and an output end of the first unit is configured to output a control signal whose duty cycle gradually increases from 0 to 100%, or output a control signal whose pulse width gradually increases; The second unit is configured to output a first signal to the first unit, and a voltage value of the first signal gradually increases within a first period; The third unit is configured to output a second signal to the first unit, and within the first period, the voltage value of the second signal repeatedly undergoes a process of gradually increasing from a first voltage value to a second voltage value, where the first voltage value is less than the second voltage value, the first signal and the second signal can intersect multiple times, and the intersection area formed by the Nth and the N + 1th is less than the intersection area formed by the N + 2th and the N + 3th, N is the number of intersections, and N is an odd number that takes all values greater than or equal to 1 and less than or equal to the total number of intersections; The first unit is configured to output the control signal according to the first signal and the second signal, and the control signal is used to control the conduction and cutoff of the high-side switch within the first period, and the high level of the control signal is related to the intersection area of the first signal and the second signal.

2. The generating device according to claim 1, wherein The first unit is a first comparator; a positive input end of the first comparator is electrically connected to the second unit, and a negative input end of the first comparator is electrically connected to the third unit; The first comparator is configured to output a high level of the control signal when the voltage value of the first signal is greater than the voltage value of the second signal; and output a low level of the control signal when the voltage value of the first signal is less than the voltage value of the second signal.

3. The generating device according to claim 1, wherein The second unit includes a first current source and a first capacitor; a first end of the first capacitor is electrically connected to the first current source, a second end of the first capacitor is grounded, and a connection point between the first end of the first capacitor and the first current source is electrically connected to the first input end of the first unit.

4. The generating device according to claim 1, characterized in that The third unit includes a second current source, a second capacitor, a switching tube, a second comparator, and a delay module; A first end of the second capacitor is electrically connected to the second current source, a second end of the second capacitor is grounded, a connection point between the first end of the second capacitor and the second current source is electrically connected to a positive input end of the second comparator, a negative input end of the second comparator is configured to access the second voltage value, an output end of the second comparator is electrically connected to a first end of the delay module, a second end of the delay module is electrically connected to a first end of the switching tube, a second end of the switching tube is connected between the connection point and the positive input end of the second comparator, and a third end of the switching tube is grounded.

5. The generating device according to any one of claims 1-4, characterized in that, The change rate of the duty cycle of the control signal is related to the change rate of the first signal and the change rate of the second signal.

6. A control signal generation device, characterized in that, The generating device includes: a first unit, a second unit, and a third unit; The first input terminal of the first unit is electrically connected to the second unit, the second input terminal of the first unit is electrically connected to the first end of the third unit, the second end of the third unit is electrically connected to the output terminal of the first unit, and the output terminal of the first unit is configured to output a control signal whose duty cycle gradually increases from 0 to 100%, or a control signal whose pulse width gradually increases; The second unit is configured to output a first signal to the first unit. During a first period, the voltage value of the first signal repeatedly undergoes a process of decreasing step by step from a first voltage value to a second voltage value, where the first voltage value is greater than the second voltage value; The third unit is configured to output a second signal to the first unit. During the first period, the voltage value of the second signal increases step by step, and the minimum voltage value of the second signal is greater than the second voltage value and less than the first voltage value; The first unit is configured to output the control signal according to the first signal and the second signal. The control signal is used to control the conduction and cutoff of the high-side switch during the first period, and the high level of the control signal is related to the voltage values of the first signal and the second signal.

7. The generating device according to claim 6, wherein The first unit includes a comparator and an inverter; the positive input terminal of the comparator is electrically connected to the second unit, the negative input terminal of the comparator is electrically connected to the first end of the third unit, the output terminal of the comparator is electrically connected to the first end of the inverter, and the second end of the inverter is electrically connected to the second end of the third unit; The comparator is configured to output the high level of the control signal when the voltage value of the first signal is greater than the voltage value of the second signal; and output the low level of the control signal when the voltage value of the first signal is less than the voltage value of the second signal; The inverter is configured to invert the level of the control signal.

8. The generating device according to claim 6, wherein The second unit is a counter, the input terminal of the counter is connected to a clock signal, and the output terminal of the counter is electrically connected to the first input terminal of the first unit.

9. The generating device according to claim 6, wherein The third unit includes a step controller, an adder, and a D flip-flop; the first input terminal of the adder is configured to be electrically connected to the step controller, the step controller is used to set the minimum voltage value of the second signal, the second input terminal of the adder is electrically connected between the output terminal of the D flip-flop and the second input terminal of the first unit, the output terminal of the adder is electrically connected to the D input terminal of the D flip-flop, the clock control terminal of the D flip-flop is electrically connected to the output terminal of the first unit, and the output terminal of the D flip-flop is electrically connected to the second input terminal of the first unit.

10. The generating device according to any one of claims 6-9, characterized in that, The change rate of the duty cycle of the control signal is related to the duration of the voltage value of the first signal decreasing step by step from the first voltage value to the second voltage value, the first voltage value, and the minimum voltage value of the second signal.

Images