Semiconductor device manufacturing method and semiconductor device

Abstract

The purpose is to provide a technology capable of reducing the variation of oxygen concentration between silicon wafers. The method for manufacturing a semiconductor device comprises: a first step of introducing oxygen to increase the oxygen concentration of the silicon wafer when the oxygen concentration of the silicon wafer is less than a predetermined threshold value, and extracting oxygen to reduce the oxygen concentration of the silicon wafer when the oxygen concentration of the silicon wafer is greater than the threshold value; a second step of forming a first surface structure; a third step of grinding the silicon wafer from the second surface; and a fourth step of forming a second surface structure.

Description

Technical Field

[0001] The present disclosure relates to a method for manufacturing a semiconductor device and a semiconductor device. Background Art

[0002] In a power semiconductor device, which is a type of semiconductor device, in order to increase the switching speed, a composite defect is sometimes formed by compounding point defects and impurities existing in a silicon wafer. Patent Documents 1 and 2 disclose that by forming a composite defect in a power semiconductor device, in addition to improving the switching characteristics, it is possible to reduce switching losses, improve reverse recovery characteristics (reducing recovery surge voltage, etc.), improve short-circuit tolerance, etc.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: International Publication No. 2007 / 000838

[0006] Patent Document 2: International Publication No. 2016 / 204097 Summary of the invention

[0007] However, the concentration of oxygen, which is one of the impurities that form complex defects, varies from one silicon wafer to another due to manufacturing variations of silicon wafers, so there is a problem that the characteristics of the power semiconductor device vary.

[0008] Therefore, the present disclosure has been made in view of the above-mentioned problems, and an object of the present disclosure is to provide a technology capable of reducing the variation in oxygen concentration between silicon wafers.

[0009] The manufacturing method of the semiconductor device involved in the present disclosure comprises: a first step, when the oxygen concentration of the silicon wafer is less than a predetermined threshold value, oxygen is introduced to increase the oxygen concentration of the silicon wafer, and when the oxygen concentration of the silicon wafer is greater than the threshold value, oxygen is extracted to reduce the oxygen concentration of the silicon wafer; a second step, after the first step, forming a first-surface structure on the first surface of the silicon wafer; a third step, after the first step, grinding the silicon wafer from the second surface opposite to the first surface; and a fourth step, after the third step, forming a second-surface structure on the second surface of the silicon wafer.

[0010] According to the present disclosure, when the oxygen concentration of the silicon wafer is less than a threshold value, oxygen is introduced to increase the oxygen concentration of the silicon wafer, and when the oxygen concentration of the silicon wafer is greater than the threshold value, oxygen is extracted to reduce the oxygen concentration of the silicon wafer. According to such a structure, the deviation of oxygen concentration between silicon wafers can be reduced.

[0011] The objects, features, aspects and advantages of the present disclosure will become more apparent from the following detailed description and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 This is a flowchart showing the method for manufacturing the power semiconductor device according to the first embodiment.

[0013] Figure 2 This is a diagram for explaining the oxygen introduction and introduction process according to the first embodiment.

[0014] Figure 3 This is a diagram for explaining the oxygen introduction and introduction process according to the first embodiment.

[0015] Figure 4 This is a diagram for explaining the oxygen introduction and introduction process according to the first embodiment.

[0016] Figure 5 It is a diagram for explaining the polishing step involved in the first embodiment.

[0017] Figure 6 FIG. 1 is a diagram showing the results of the method for manufacturing the power semiconductor device according to the first embodiment.

[0018] Figure 7 This is a cross-sectional view showing a main part of the structure of a power semiconductor device according to the second embodiment.

[0019] Figure 8 This is a cross-sectional view showing a main part of the structure of a power semiconductor device according to the second embodiment.

[0020] Fig. 9 This is a cross-sectional view showing a main part of the structure of a power semiconductor device according to the third embodiment.

[0021] Fig.10 This is a cross-sectional view showing a main part of the structure of a power semiconductor device according to the third embodiment.

[0022] (Explanation of symbols)

[0023] 1, 11: semiconductor region; 2a: anode region; 2b: anode electrode; 3a: cathode region; 3b: cathode electrode; 7, 17: composite defects; 12a: base region; 12b: emitter region; 12c: base contact region; 12d: gate insulating film; 12e: trench gate electrode; 12f: emitter electrode; 13a: collector region; 13b: collector electrode. DETAILED DESCRIPTION

[0024] <Implementation Method 1>

[0025] Before describing a method for manufacturing a power semiconductor device as the semiconductor device according to the first embodiment, a composite defect will be described.

[0026] Composite defects are formed by combining point defects and impurities existing in silicon wafers used in power semiconductor devices. Impurities are originally contained in silicon wafers, such as oxygen, carbon, or nitrogen. In this embodiment 1, oxygen is focused on as such impurities. In addition, point defects are local disorders of the crystal lattice, and there are vacancy types (vacancy) and interstitial atom types (interstitial silicon).

[0027] Composite defects formed by the combination of point defects and impurities form deep energy levels, so holes and electrons are recombined through composite defects. Therefore, by controlling the composite defects formed in the silicon wafer, the carrier lifetime of the power semiconductor device can be controlled. As a result, although the on-resistance of the power semiconductor device increases slightly, the switching speed can be increased. In addition, by forming composite defects in the power semiconductor device, in addition to improving the switching characteristics, it is also possible to reduce switching losses, improve reverse recovery characteristics (reduce recovery surge voltage, etc.), improve short-circuit tolerance, etc.

[0028] Composite defects are often formed in silicon wafers by using charged particle irradiation. As the charged particle beam, at least one of electrons and light element ions (protons, helium ions) is used. Point defects are formed in the region of the silicon wafer irradiated with the charged particle beam.

[0029] However, in general, the amount of oxygen originally contained in the silicon wafer and serving as the source of complex defects is different in each silicon wafer. The reason for this is the method of manufacturing the ingot that is the source of the silicon wafer. There are two methods for manufacturing silicon ingots for power semiconductor devices: the MCZ (Magnetic Czochralski) method and the FZ (Floating-Zone) method. In the MCZ method, a quartz crucible is used to manufacture the ingot, so the oxygen dissolved from the quartz crucible is taken into the ingot. As a result, the oxygen concentration of the ingot manufactured by the MCZ method tends to be several hundred to a thousand times higher than that of the ingot manufactured by the FZ method. In addition, in the ingot manufactured by the MCZ method, the oxygen concentration is different in the upper or lower part of the ingot due to the separation phenomenon between the ingot and the silicon melt. Therefore, the oxygen concentration of the silicon wafer is different depending on the position where the silicon wafer is cut out from the ingot.

[0030] It is speculated that the amount of composite defects is strongly affected by the amount of oxygen and point defects, whichever is less involved in the composite. Therefore, the oxygen concentration of the silicon wafer is different for each silicon wafer, so the characteristics (such as switching speed and on-voltage) of the power semiconductor device formed by multiple silicon wafers may sometimes vary. As a result, there is a possibility that the characteristics of the power semiconductor device do not meet the specifications of the power semiconductor device, and there is a possibility that the yield rate is reduced.

[0031] On the other hand, according to the method for manufacturing a power semiconductor device according to the first embodiment described below, it is possible to reduce the variation in oxygen concentration of a silicon wafer and, in turn, the variation in characteristics of a power semiconductor device.

[0032] Figure 1 This is a flowchart showing a method for manufacturing a power semiconductor device according to the first embodiment. - A method for manufacturing a vertical diode with a thickness of 60μm using a silicon wafer of the type.

[0033] Before starting step S1, a silicon wafer having a front surface (first surface) and a back surface (second surface) opposite to the front surface is prepared. The oxygen concentration of the silicon wafer before step S1 is, for example, 1×10 15 cm -3 Above and 1×10 18 cm -3 The oxygen concentration can be measured, for example, by infrared absorption measurement or secondary ion mass spectrometry. In addition, since a silicon wafer is thinner than an ingot, the oxygen concentration can be considered to be uniform in the depth direction.

[0034] <Oxygen introduction and derivation step (first step)>

[0035] exist Figure 1 In step S1, an oxygen introduction and de-introduction process for actively controlling the oxygen concentration of the silicon wafer is performed. In the present first embodiment, in the oxygen introduction and de-introduction process, the silicon wafer is annealed in a state of being in contact with at least one of an oxide film and an oxygen atmosphere. For example, the silicon wafer is annealed in a furnace such as a vertical furnace in a temperature range of 1000 to 1300° C. (627 to 1027K) in a state where the surface of the silicon wafer is covered with an oxide film or the surface of the silicon wafer is exposed to an oxygen atmosphere.

[0036] During the annealing, there occurs a phenomenon in which oxygen from an oxide film or an oxygen atmosphere is introduced into the interior of a silicon wafer, or a phenomenon in which oxygen from the interior of a silicon wafer is exported to an oxide film or an oxygen atmosphere. The equilibrium concentration of oxygen between the silicon wafer and the outside (hereinafter referred to as "equilibrium concentration") affects which of the import and export is performed. That is, when the oxygen originally contained in the interior of the silicon wafer is less than the equilibrium concentration, the oxygen is imported by transferring it from the outside such as an oxide film to the silicon wafer. On the other hand, when the oxygen originally contained in the interior of the silicon wafer is more than the equilibrium concentration, the oxygen is exported by transferring it from the silicon wafer to the outside such as an oxide film or an atmosphere. In addition, when an oxide film is used for covering, it is possible to suppress the import and export of oxygen from being performed more than necessary.

[0037] The following is a description of the results of actually performing the oxygen introduction and decompression step. As the worst case of oxygen concentration variation between silicon wafers for power semiconductor devices, wafer A and wafer B were used. As wafer A, a wafer with a 1×10 15 cm -3 As wafer B, a silicon wafer having an oxygen concentration of 1×10 18 cm -3 The oxygen concentration of the silicon wafer.

[0038] While the surfaces of wafer A and wafer B were thermally oxidized, annealing was performed at 1150°C, and the annealing time was set in 10 levels (2.6, 5, 10, 15, 20, 25, 36, 50, 70, and 100 hours), and changes in oxygen concentration of wafer A and wafer B were checked.

[0039] Figure 2 as well as Figure 3 is a graph showing the results. Specifically, Figure 2 is a diagram showing the relationship between the depth from the surface of wafer A and the oxygen concentration. Figure 3 : is a graph showing the relationship between the depth from the surface of the wafer B and the oxygen concentration. Figure 2 as well as Figure 3 The equilibrium concentration (predetermined threshold) is about 1×10 17 cm -3 .

[0040] like Figure 2 As shown, in Figure 2 When the oxygen concentration of the silicon wafer indicated by the solid line in FIG. 1 is lower than the equilibrium concentration, oxygen is introduced to increase the oxygen concentration of the silicon wafer. Figure 2 The oxygen concentration distribution indicated by the bold line in FIG. 1 shifts to the oxygen concentration distribution indicated by the dotted line. Figure 3 As shown, in Figure 3 When the oxygen concentration of the silicon wafer indicated by the solid line in FIG. 1 is greater than the equilibrium concentration, oxygen is extracted to reduce the oxygen concentration of the silicon wafer. Figure 3 The oxygen concentration distribution indicated by the bold line in FIG. 1 shifts to the oxygen concentration distribution indicated by the dotted line.

[0041] Figure 4 The graph shows the oxygen concentration of wafer A and wafer B before the oxygen introduction and derivation process, after the oxygen introduction and derivation process for about 2.6 to 2.7 hours, and after the oxygen introduction and derivation process for 100 hours. The oxygen concentration difference D1 between wafer A and wafer B after the oxygen introduction and derivation process is lower than the oxygen concentration difference D2 before the oxygen introduction and derivation process. In addition, the longer the annealing time, the lower the oxygen concentration. Figure 4 As the graph moves from the thin dotted line to the thick dotted line, the oxygen concentration difference between wafer A and wafer B becomes smaller, and the depth at which the oxygen concentration difference is reduced also becomes deeper.

[0042] Next, the annealing conditions in the oxygen introduction and decompression process are described. Here, the annealing time is set to t (seconds), the annealing temperature is set to T (K) which is above 1000°C and below 1300°C, the thickness of the portion of the silicon wafer corresponding to the silicon wafer after the polishing process described later is set to d (cm), and k is set to the Boltzmann constant converted in eV / K. In this case, it is preferred that the following equations (1) to (3) hold. In addition, erfc in the following equation (1) is -1 It means the inverse function of the complementary error function erfc.

[0043] t≥{d / [2×√D×erfc -1 (1×10 15 / C s )]} 2 … (1)

[0044] D=0.28×exp(-2.53 / kT)… (2)

[0045] C s =6×10 22 exp(-1.61 / kT)… (3)

[0046] For example, when the thickness d is 60 μm and the annealing temperature T is 1150°C, the above formula (1) becomes t≥8203, indicating that the annealing time t is preferably 2.3 h or longer. When the annealing time t is shorter than the lower limit of the above formula (1), the introduction or extraction of oxygen is insufficient, and a large amount of oxygen originally contained in the silicon wafer remains, so the oxygen concentration deviation between the silicon wafers is relatively large. On the contrary, when the annealing time t is longer than the lower limit of the above formula (1), the oxygen concentration deviation between the silicon wafers is relatively small. In addition, as shown in FIG. Figure 2 to Figure 4It is known that when the lower limit of the annealing time t is longer than the lower limit of the above formula (1), the oxygen concentration deviation can be further reduced. When the lower limit of the annealing time t is longer than the lower limit of the following formula (4), the oxygen concentration deviation can be further reduced.

[0047] t≥{d / [2×√D×erfc -1 (1×10 16 / C s )]} 2 … (4)

[0048] t≥{d / [2×√D×erfc -1 (1×10 17 / C s )]} 2 … (5)

[0049] In addition, when the annealing temperature T is low, the annealing time t, which becomes the lower limit of the above formula (1), becomes longer, and the manufacturing efficiency becomes poor. On the other hand, when the annealing temperature T is higher than 1300°C, there is a possibility that the silicon wafer will melt, so it is not preferred. Considering these conditions, it is preferred to set the annealing temperature T to a range of 1000 to 1300°C.

[0050] The oxygen concentration on the surface of the silicon wafer after the oxygen introduction and extraction process becomes an equilibrium concentration determined by the annealing temperature T. In the temperature range of 1000 to 1300° C., the equilibrium concentration is 2×10 16 cm -3 Above and 5×10 17 cm -3 In addition, in the region shallower than the diffusion length of oxygen, the oxygen concentration of the silicon wafer is adjusted to be within the range of the equilibrium concentration.

[0051] As described above, the oxygen concentration difference between wafer A and wafer B after the oxygen introduction and decompression process ( Figure 4 D1) is 1×10 18 cm -3 The oxygen concentration difference ( Figure 4 The D2) is reduced.

[0052] <Surface structure forming step (second step)>

[0053] exist Figure 1 In step S2, a surface structure forming step of forming a surface structure (first surface structure) of a diode on the surface of the silicon wafer is performed. In the surface structure forming step involved in the first embodiment, in order to form a p +In the anode region of the p-type, ion implantation of p-type impurities such as boron and activation annealing treatment for activating the p-type impurities are performed. Furthermore, an anode electrode is formed on the anode region.

[0054] <Polishing step (third step)>

[0055] exist Figure 1 In step S3, a grinding process is performed to grind the back side of the silicon wafer to a desired thickness. In the grinding process, for example, after protecting the surface structure, the back side of the silicon wafer is ground using a grinding method such as CMP (Chemical Mechanical Polish). In addition, in the following description, the ground silicon wafer is sometimes recorded as a semiconductor region.

[0056] Figure 5 Schematically shows the oxygen concentration of the semiconductor region of the power semiconductor device according to the first embodiment, that is, the oxygen concentration of the silicon wafer after the polishing process. The oxygen introduction and de-introduction process of step S1 sufficiently suppresses the variation of the oxygen concentration between the silicon wafers on the front side of the silicon wafer. However, on the back side of the silicon wafer, the variation of the oxygen concentration between the silicon wafers may not be sufficiently suppressed depending on the annealing time.

[0057] Therefore, in step S3, by performing a grinding process of grinding from the back side of the silicon wafer, the oxygen concentration variation between the silicon wafers can be sufficiently suppressed even on the back side of the silicon wafer. In the first embodiment, the oxygen concentration of the entire part or the surface side of the silicon wafer after the grinding process is 2×10 16 cm -3 Above and 5×10 17 cm -3 the following.

[0058] However, even after grinding, there is a slightly uneven distribution of oxygen concentration in the depth direction of the silicon wafer. The uneven distribution here refers to a state where the oxygen concentration is lower than that on the main body side of the silicon wafer surface ( Figure 5 C1 state) or a state where the oxygen concentration is higher than that on the surface main body side ( Figure 5 The state of C2), and the state where there is a gradient in oxygen concentration across the entire silicon wafer.

[0059] <Back Structure Forming Step (4th Step)>

[0060] exist Figure 1 In step S4, a back surface structure forming step of forming a back surface structure (second surface structure) of a diode on the back surface of the silicon wafer is performed. In the back surface structure forming step involved in the first embodiment, in order to form a cathode region on the back surface of the silicon wafer, an n-type or n-type -The back side of the silicon wafer of the type 1 is subjected to ion implantation of n-type impurities such as phosphorus and activation annealing to activate the n-type impurities. Furthermore, a cathode electrode is formed on the cathode region.

[0061] <Charged Particle Beam Irradiation Step (Fifth Step)>

[0062] exist Figure 1 In step S5, a charged particle beam irradiation process is performed to irradiate the silicon wafer with a charged particle beam to form point defects.

[0063] In the first embodiment, an electron beam is irradiated from the surface (anode side) of the silicon wafer as a charged particle beam, thereby uniformly forming point defects in the entire portion of the silicon wafer. In addition, an electron beam may be irradiated from the back side (cathode side) of the silicon wafer as needed. When an electron beam is used as a charged particle beam, an accelerator may also be used to irradiate the silicon wafer with electrons accelerated to several hundred KeV to several tens of MeV. The dose of the electron beam is, for example, 1×10 12 ~1×10 15 cm -2 .

[0064] In addition, the irradiation with the charged particle beam is not limited to the above, and for example, point defects may be formed in a local portion of the silicon wafer by irradiating the surface or back side of the silicon wafer with protons or helium ions as a charged particle beam.

[0065] <Recovery Annealing Step (Step 6)>

[0066] exist Figure 1 In step S6, a recovery annealing process is performed as an annealing for at least one of the formation of composite defects including point defects and oxygen and the elimination of a part of the point defects. In the recovery annealing process, for example, the silicon wafer is annealed in an inert gas atmosphere such as nitrogen at a temperature in the range of 200 to 500°C. In the recovery annealing process, the oxygen in the semiconductor region, that is, the oxygen introduced and exported in the oxygen introduction and export process from the oxygen originally contained in the silicon wafer, reacts with the point defects to form composite defects. In annealing at a temperature lower than 200°C, the efficiency of forming composite defects decreases, so it is not preferred. In annealing at a temperature higher than 500°C, the diffusion and elimination of point defects become significant, so it is not preferred. Therefore, the annealing temperature is preferably in the range of 200 to 500°C.

[0067] By subjecting the silicon wafer to charged particle beam and recovery annealing, complex defects are efficiently formed. Complex defects formed in this process include VO (Vacancy-Oxygen pair) defects and CiOi (Interstitial Carbon-Interstitial Oxygen pair) defects.

[0068] Here, the process of forming a composite defect is described in detail. When an electron beam is irradiated to a semiconductor region, silicon is ejected from a regular lattice position due to the energy of the electrons, forming a vacancy (V) which is a type of point defect and interstitial silicon (I) which is a type of point defect. Vacancies and interstitial silicon are thermally unstable and react with oxygen or carbon, an impurity present in the surroundings, to become thermally stable composite defects. For example, vacancies and oxygen form VO defects with an energy level of about 0.17 eV below the conduction band. In addition, interstitial silicon is replaced by carbon to form interstitial carbon (Ci). Interstitial carbon and oxygen form CiOi defects with an energy level of about 0.36 eV above the valence band.

[0069] Next, the results of evaluating the effect of the method for manufacturing a power semiconductor device according to the first embodiment are described. Here, a 60 μm thick vertical diode is manufactured using the wafer A and the wafer B, and the drift layer voltage Vm corresponding to the conduction characteristics thereof is examined. The charged particle beam is set to an electron beam, and the representative composite defects formed are set to VO defects and CiOi defects.

[0070] Figure 6 is a graph showing the results, specifically, a graph showing the relationship between the deviation of the drift layer voltage Vm of the diode and the annealing time of the oxygen introduction and deduction process. The deviation of the drift layer voltage Vm indicates the deviation of the drift layer voltage between the diode formed by wafer A and the diode formed by wafer B. More specifically, wafer B has more complex defects than wafer A and has a higher drift layer voltage, so the deviation of the drift layer voltage Vm is equivalent to the value obtained by subtracting the drift layer voltage of wafer A from the drift layer voltage of wafer B.

[0071] The general method for manufacturing a power semiconductor device corresponds to the case where the annealing time in the oxygen introduction and extraction step is 0. In this manufacturing method, the variation in the drift layer voltage Vm is 0.34V.

[0072] In contrast, in the method for manufacturing a power semiconductor device according to the first embodiment, when the annealing temperature of the oxygen introduction and deduction process is set to 1150° C. and the annealing time is set to 2.6 to 2.7 h corresponding to the lower limit of the formula (1), the deviation of the drift layer voltage Vm is reduced to 0.24 V. In addition, when the annealing time of the oxygen introduction and deduction process is extended to 100 h, the deviation of the drift layer voltage Vm is reduced to 0.05 V.

[0073] In addition, in the above description, the worst case of the deviation of the oxygen concentration between silicon wafers for power semiconductor devices is assumed. However, regardless of whether the oxygen concentration is lower or higher than this case, the same effect as described above can be obtained according to the method for manufacturing a power semiconductor device according to the first embodiment. Therefore, the effect of the method for manufacturing a power semiconductor device according to the first embodiment is not limited to the original oxygen concentration of the silicon wafer.

[0074] In addition, the characteristics of the power semiconductor device are affected by the structure of the power semiconductor device and the concentration of impurities other than oxygen, but are also strongly affected by the oxygen concentration of the main body. Therefore, according to the manufacturing method involved in the first embodiment, regardless of the oxygen concentration of the main body, the deviation of the oxygen concentration of the main body can be suppressed by performing the oxygen introduction and deduction process, so the characteristic deviation of the power semiconductor device can be suppressed.

[0075] <Summary of Implementation Method 1>

[0076] In the manufacturing method of the power semiconductor device according to the first embodiment, an oxygen introduction and deduction process is performed to change the oxygen concentration of the silicon wafer with respect to the equilibrium concentration (predetermined threshold value). According to such a manufacturing method, the oxygen concentration of the silicon wafer (semiconductor region) can be adjusted, and the deviation of the oxygen concentration between silicon wafers can be suppressed. As a result, the deviation of the concentration of the composite defects including oxygen that functions as a trap, and even the deviation of the characteristics such as the on-voltage, can be suppressed between the power semiconductor devices formed by different silicon wafers.

[0077] According to the first embodiment, a power semiconductor device can be formed that includes: a semiconductor region of a silicon wafer having a composite defect including oxygen and a point defect, a surface structure provided on the surface of the semiconductor region, and a back surface structure provided on the back surface of the semiconductor region. Figure 5 As shown, the oxygen concentration of the entire semiconductor region or the surface side portion can be 1×10 17 ~8×10 17 cm -3 , a power semiconductor device is constructed in such a way that the oxygen concentration in the semiconductor region changes continuously from the surface to the back surface.

[0078] <Implementation Method 2>

[0079] Figure 7 1 is a cross-sectional view showing a main part of the structure of the power semiconductor device according to the second embodiment. The following mainly describes the components of the second embodiment that are different from the above components. The power semiconductor device according to the second embodiment is a vertical diode having a composite defect formed in a semiconductor region by the manufacturing method of the first embodiment.

[0080] Figure 7 The vertical diode includes a semiconductor region 1, an anode region 2a, a cathode region 3a, a drift region 4, an anode electrode 2b, and a cathode electrode 3b. In addition, the anode region 2a and the anode electrode 2b are included in the concept of the surface structure of the first embodiment, and the cathode region 3a and the cathode electrode 3b are included in the concept of the back structure of the first embodiment.

[0081] The semiconductor region 1 is included in the semiconductor region of the first embodiment and is formed of a silicon wafer. The semiconductor region 1 includes an anode region 2a containing p-type impurities (typically boron) at a relatively high concentration, a cathode region 3a containing n-type impurities (typically phosphorus) at a relatively high concentration, and a drift region 4 disposed between the anode region 2a and the cathode region 3a. The drift region 4 may contain n-type impurities at a relatively low concentration or may substantially contain no conductive type impurities. The anode electrode 2b is electrically connected to the anode region 2a, and the cathode electrode 3b is electrically connected to the cathode region 3a.

[0082] In the semiconductor region 1, the oxygen concentration of the entire semiconductor region 1 or the surface side portion is 2×10 16 cm -3 Above and 5×10 17 cm -3 Hereinafter, the oxygen concentration changes continuously from the surface to the back surface of the semiconductor region 1. In addition, the semiconductor region 1 has a composite defect 7 including oxygen and a point defect.

[0083] Figure 7 The vertical diode is a non-punch-through diode in which the cathode region 3a and the drift region 4 are connected. In the non-punch-through diode, the position of the maximum concentration of the composite defect 7 is preferably formed near the interface between the anode region 2a and the drift region 4. By forming the composite defect 7 near the interface between the anode region 2a and the drift region 4, the reverse recovery characteristics of the vertical diode can be improved.

[0084] In addition, the vertical diode according to the second embodiment may also be configured as follows: Figure 8 The punch-through diode is shown. The punch-through diode further includes: a field stop region 3c disposed between the cathode region 3a and the drift region 4, wherein the concentration of n-type impurities is higher than that of the drift region 4. The field stop region 3c is included in the concept of the back structure of the first embodiment. In the punch-through diode, the position of the maximum concentration of the composite defect 7 is preferably formed near the interface between the cathode region 3a and the field stop region 3c. By forming the composite defect 7 near the interface between the cathode region 3a and the field stop region 3c, the reverse recovery characteristics of the vertical diode can be improved.

[0085] <Implementation Method 3>

[0086] Fig. 9 1 is a cross-sectional view showing the main part of the structure of the power semiconductor device involved in the present embodiment 3. The following mainly describes the components involved in the present embodiment 3 that are different from the above-mentioned components. The power semiconductor device involved in the present embodiment 3 is an IGBT (Insulated Gate Bipolar Transistor) in which a composite defect is formed in the semiconductor region by the manufacturing method of the embodiment 1.

[0087] Fig. 9 The IGBT includes a semiconductor region 11, a base region 12a, an emitter region 12b, a base contact region 12c, a gate insulating film 12d, a trench gate electrode 12e, an emitter electrode 12f, a collector region 13a, and a collector electrode 13b. In addition, the base region 12a, the emitter region 12b, the base contact region 12c, the gate insulating film 12d, the trench gate electrode 12e, and the emitter electrode 12f are included in the concept of the surface structure of the first embodiment. The collector region 13a and the collector electrode 13b are included in the concept of the back surface structure of the first embodiment.

[0088] The semiconductor region 11 is included in the semiconductor region of the first embodiment and is formed of a silicon wafer. The semiconductor region 11 includes a collector region 13a containing p-type impurities. The semiconductor region 11 includes a drift region 14 disposed on the collector region 13a. The drift region 14 may contain n-type impurities at a relatively low concentration or may substantially contain no conductive type impurities. A base region 12a containing p-type impurities is disposed on the drift region 14. The base region 12a is separated from the collector region 13a by the drift region 14.

[0089] On the base region 12a, an emitter region 12b containing n-type impurities and a base contact region 12c containing p-type impurities at a relatively high concentration are selectively disposed. The emitter region 12b is separated from the drift region 14 by the base region 12a.

[0090] The trench gate electrode 12e faces the base region 12a that separates the emitter region 12b and the drift region 14 via the gate insulating film 12d. The gate insulating film 12d is made of, for example, silicon oxide, and the trench gate electrode 12e is made of, for example, polysilicon.

[0091] An emitter electrode 12f made of aluminum, for example, is disposed on the emitter region 12b and the base contact region 12c. The emitter electrode 12f is electrically connected to the emitter region 12b and the base contact region 12c. The trench gate electrode 12e and the emitter electrode 12f are electrically separated from each other. The collector electrode 13b is electrically connected to the collector region 13a.

[0092] In the semiconductor region 11, the oxygen concentration of the entire portion of the semiconductor region 11 or the portion on the surface side is 2×10 16 cm -3 Above and 5×10 17 cm -3 Hereinafter, the oxygen concentration changes continuously from the surface to the back surface of the semiconductor region 11. In addition, the semiconductor region 11 has a composite defect 17 including oxygen and a point defect.

[0093] Fig. 9 The IGBT is a non-punch-through IGBT in which the collector region 13a and the drift region 14 are connected. In the non-punch-through IGBT, the position of the maximum concentration of the composite defects 17 is preferably formed near the interface between the collector region 13a and the drift region 14. By forming the composite defects 17 near the interface between the collector region 13a and the drift region 14, the reverse recovery characteristics of the IGBT can be improved.

[0094] In addition, the IGBT according to the third embodiment may also be Fig.10 The punch-through IGBT is shown. The punch-through IGBT further includes a field stop region 13c disposed between the collector region 13a and the drift region 14, wherein the concentration of n-type impurities is higher than that of the drift region 14. The field stop region 13c is included in the concept of the back surface structure of the first embodiment. In the punch-through IGBT, the position of the maximum concentration of the composite defects 17 is preferably formed near the interface between the collector region 13a and the field stop region 13c. By forming the composite defects 17 near the interface between the collector region 13a and the field stop region 13c, the reverse recovery characteristics of the IGBT can be improved.

[0095] <Modification>

[0096] In the first embodiment, the charged particle beam irradiation process is performed in step S5, but even if the charged particle beam irradiation process is not performed, there are some point defects in the silicon wafer. Therefore, the charged particle beam irradiation process of step S5 is not necessary. In addition, in the first embodiment, the charged particle beam irradiation process of step S5 is performed after the back structure forming process of step S4, but it is not limited to this. For example, the charged particle beam irradiation process of step S5 can also be performed after the oxygen introduction and derivation process of step S1.

[0097] In the first embodiment, in the oxygen introduction and derivation process of step S1, only one of oxygen introduction and derivation is performed on one silicon wafer, but the present invention is not limited thereto. For example, when the oxygen concentration of the silicon wafer is sufficiently close to the equilibrium concentration before the oxygen introduction and derivation process is performed, both oxygen introduction and derivation may be performed on one silicon wafer in the oxygen introduction and derivation process.

[0098] In the first embodiment, the oxygen introduction and deduction process is performed on the surface of the silicon wafer, but the present invention is not limited to this. For example, the oxygen introduction and deduction process may be performed not only on the surface of the silicon wafer but also on the side surface.

[0099] In the above description, the silicon wafer is only a Si wafer, but the present invention is not limited thereto. For example, the silicon wafer may be a wafer made of a wide bandgap semiconductor such as a SiC wafer.

[0100] In addition, in the above description, no special description is given about the material of the electrode, the film forming method, the concentration of each region of the p-type or n-type, etc., and the design conditions of the general power semiconductor device can also be applied in accordance with the purpose. In addition, MOSFET (Metal Oxide Semiconductor Field Effect Transistor), SBD (Schottky Barrier Diode), PND (PN junction diode), etc. can also be formed by the manufacturing method described in Embodiment 1.

[0101] In addition, each embodiment and each modification example can be freely combined or each embodiment and each modification example can be appropriately modified or omitted.

[0102] The above description is illustrative in all aspects and is not restrictive. It should be understood that numerous modifications not shown in the examples are conceivable.

Claims

1. A method for manufacturing a semiconductor device, comprising: The first step is to introduce oxygen to increase the oxygen concentration of the silicon wafer when the oxygen concentration of the silicon wafer is less than a predetermined threshold value, and to extract oxygen to reduce the oxygen concentration of the silicon wafer when the oxygen concentration of the silicon wafer is greater than the threshold value; A second step of forming a first surface structure on the first surface of the silicon wafer after the first step; A third step of polishing the silicon wafer from a second surface opposite to the first surface after the first step; and The fourth step is to form a second surface structure on the second surface of the silicon wafer after the third step.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: In the first step, the silicon wafer is annealed in a state of being in contact with at least one of an oxide film and an oxygen atmosphere. The annealing time is t, the unit is seconds, the annealing temperature is T, which is 1000° C. to 1300° C., the unit is K, the thickness of the silicon wafer after the third step is d, the unit is cm, k is the Boltzmann constant converted in eV / K, and erfc -1 When erfc is set as the inverse function of the complementary error function, the following equation holds: t≥{d / [2×√D×erfc -1 (1×10 15 / C s )]} 2 、 D = 0.28 × exp (-2.53 / kT), C s =6×10 22 exp(-1.61 / kT)。 3. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein: Also available: A fifth step, after the first step, irradiating the silicon wafer with a charged particle beam to form a point defect; and The sixth step is to perform annealing for at least one of forming a composite defect including the point defect and the oxygen and eliminating a part of the point defect after the fifth step.

4. The method for manufacturing a semiconductor device according to claim 3, wherein: In the fifth step, the first surface or the second surface of the silicon wafer is irradiated with an electron beam as the charged particle beam, thereby forming the point defects in the entire portion of the silicon wafer after the third step.

5. The method for manufacturing a semiconductor device according to claim 3, wherein: In the fifth step, the first surface or the second surface of the silicon wafer is irradiated with protons or helium ions as the charged particle beam, thereby forming the point defects in a local portion of the silicon wafer after the third step.

6. The method for manufacturing a semiconductor device according to claim 1, 2, 4 or 5, wherein: The oxygen concentration of the entire portion of the silicon wafer or the portion on the first surface side after the third step is 2×10 16 cm -3 Above and 5×10 17 cm -3 the following.

7. The method for manufacturing a semiconductor device according to claim 1, 2, 4 or 5, wherein: The oxygen concentration of the silicon wafer before the first step is 1×10 15 cm -3 Above and 1×10 18 cm -3 the following.

8. A semiconductor device comprising: A semiconductor region of a silicon wafer having composite defects including oxygen and point defects; a first-surface structure disposed on a first surface of the semiconductor region; and a second surface structure provided on a second surface of the semiconductor region opposite to the first surface; The oxygen concentration of the entire semiconductor region or the portion on the first surface side is 2×10 16 cm -3 Above and 5×10 17 cm -3 Hereinafter, the oxygen concentration of the semiconductor region from the first surface to the second surface increases or decreases monotonically from the first surface toward the second surface.

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