A bandgap reference voltage source with adjustable reference voltage

Abstract

The present invention provides a bandgap reference voltage source with an adjustable reference voltage, comprising a first circuit section, a second circuit section, and a third circuit section; the first circuit section is connected to the second circuit section, and the second circuit section is connected to the third circuit section, and the first circuit section and the second circuit section are in a mirror-symmetrical structure. The first circuit section comprises: a first switching stage circuit, a second switching stage circuit, a third switching stage circuit, a fourth switching stage circuit, a mirror switching stage circuit, and a series-connected NMOS tube circuit; the drain end of the first switching stage circuit is connected to the drain end of the mirror switching stage circuit, thereby solving the problem that the existing bandgap reference voltage source uses an amplifier as a voltage-coupled device for motor regulation, thereby requiring consideration of loop stability, resulting in weak anti-interference capability of the circuit and a long circuit design cycle.

Description

Technical Field

[0001] The invention belongs to the technical field of analog integrated circuits, and in particular relates to a bandgap reference voltage source with adjustable reference voltage. Background Art

[0002] With the rapid development of modern technology, previous chip technology is far from meeting the requirements of modern technology. The requirements for chip power consumption, low noise, volume, speed and other issues have also increased dramatically. Therefore, by increasing the power supply suppression, the stability and sensitivity of the system can be increased.

[0003] Bandgap voltage references are important modules in modern power management and hybrid integrated circuit systems. They are widely used in various electronic devices, including analog-to-digital and digital-to-analog converters and data acquisition devices. Their main feature is their ability to output a DC voltage that is independent of power supply and process, and exhibits specific temperature characteristics.

[0004] The existing bandgap reference voltage source is used as a voltage-coupled device through an amplifier for motor regulation, which requires consideration of loop stability, resulting in weak anti-interference capability of the circuit and a long circuit design cycle. Summary of the Invention

[0005] Therefore, the technical problem to be solved by the present invention is to provide a bandgap reference voltage source with adjustable reference voltage, which can solve the problem that the existing bandgap reference voltage source is used as a voltage-coupled device through an amplifier to perform motor regulation, and thus needs to take into account the stability of the loop, resulting in weak anti-interference ability of the circuit and a long circuit design cycle.

[0006] In order to solve the above problems, the present invention provides a bandgap reference voltage source with adjustable reference voltage, comprising a first circuit, a second circuit and a third circuit;

[0007] The first circuit is connected to the second circuit, and the second circuit is connected to the third circuit. The first circuit includes a first switch stage circuit, a second switch stage circuit, a third switch stage circuit, a fourth switch stage circuit, a mirror switch stage circuit, and a series-connected NMOS transistor circuit.

[0008] The drain end of the first switch stage circuit is connected to the drain end of the mirror switch stage circuit, the series NMOS tube circuit is connected to the drain end of the second switch stage circuit, the drain end of the third switch stage circuit is connected to the other end of the resistor, and the gate segment of the fourth switch stage circuit is connected to the drain end of the third switch stage circuit.

[0009] Optionally, the first switch stage circuit includes a PMOS transistor M6 and a PMOS transistor M7;

[0010] The source of the PMOS transistor M6 is connected to VDD, the gate of the PMOS transistor M6 is connected to the start voltage ENE, the drain of the PMOS transistor M6 is connected to VBP1, the source of the PMOS transistor M7 is connected to VDD, the gate of the PMOS transistor M7 is connected to ENB, and the drain of the PMOS transistor M7 is connected to VBN.

[0011] Optionally, the second switch stage circuit includes a PMOS transistor M0 , a source of the PMOS transistor M0 connected to VDD, a gate of the PMOS transistor M0 connected to a logical inverse ENB of a start voltage, and a drain of the PMOS transistor M0 connected to the first end of the resistor string.

[0012] Optionally, the third switch stage circuit includes an NMOS transistor M10 , a source of the NMOS transistor M10 connected to VSS, a gate of the NMOS transistor M10 connected to VBN, and a drain of the NMOS transistor M10 connected to the second end of the resistor string.

[0013] Optionally, the fourth switch stage circuit includes an NMOS transistor M8 and an NMOS transistor M9, the source of the NMOS transistor M8 is connected to the drain of the NMOS transistor M9, the gate of the NMOS transistor M8 is connected to the second end of the resistor string, and the drain of the NMOS transistor M8 is connected to VBP1;

[0014] The source of the NMOS transistor M9 is connected to VSS, and the gate of the NMOS transistor M9 is connected to the start-up voltage ENE.

[0015] Optionally, the second circuit includes: a cascode current mirror circuit, a PNP transistor mirror network, and a VREF output current mirror path, wherein the common gate terminal of the cascode current mirror circuit is connected to VBP1;

[0016] The S terminal of the cascode current mirror circuit is connected in parallel to the drain terminal of the third part of the circuit and the PNP transistor mirror network, and the VREF output current mirror path is connected to the cascode current mirror circuit.

[0017] Optionally, the cascode current mirror circuit includes: a PMOS transistor M13, a PMOS transistor M14, a PMOS transistor M17, an NMOS transistor M16, an NMOS transistor M15, a resistor R0, a resistor R2, a PNP transistor Q0, a PNP transistor Q1 and a PNP transistor Q2;

[0018] The source of the PMOS transistor M13 is connected to VDD, the gate of the PMOS transistor M13 is connected to VBP1, the drain of the PMOS transistor M13 is connected to VBP1, the source of the PMOS transistor M14 is connected to VDD, the gate of the PMOS transistor M14 is connected to VBP1, the drain of the PMOS transistor M14 is connected to VBP1, the source of the PMOS transistor M17 is connected to VDD, the gate of the PMOS transistor M17 is connected to VBP1, the drain of the PMOS transistor M17 is connected to the first end of the resistor R2, the drain of the NMOS transistor M15 is connected to the drain of the PMOS transistor M14, the gate of the NMOS transistor M15 is connected to the drain of the PMOS transistor M14, the source of the NMOS transistor M15 is connected to the emitter of the PNP transistor Q1, the drain of the NMOS transistor M16 is connected to VBP1, and the NMOS transistor The gate of the body transistor M16 is connected to the drain terminal of the PMOS transistor M14, the source of the NMOS transistor M16 is connected to the first terminal of the resistor R0, the first terminal of the resistor R0 is connected to the source terminal of the NMOS transistor M16, the second terminal of the resistor R0 is connected to the S terminal, the first terminal of the resistor R2 is connected to the drain terminal of the PMOS transistor M17, the second terminal of the resistor R2 is connected to the emitter of the PNP transistor Q2, the collector of the PNP transistor Q0 is grounded, the base of the PNP transistor Q0 is grounded, the emitter of the PNP transistor Q0 is connected to the source terminal of the NMOS transistor M15, the collector of the PNP transistor Q1 is grounded, the base of the PNP transistor Q1 is grounded, the emitter of the PNP transistor Q1 is connected to the E terminal, the collector of the PNP transistor Q2 is grounded, the base of the PNP transistor Q2 is grounded, and the emitter of the PNP transistor Q2 is connected to the second terminal of the resistor R2.

[0019] Optionally, the third part of the circuit includes: a resistor, an NMOS network and a digital gating network, the digital gating network is connected to the gate terminal of the NMOS, and the resistor and the NMOS network are connected to the source terminal of the common-source and common-gate current mirror circuit.

[0020] Optionally, the third circuit includes: an NMOS transistor M19, an NMOS transistor M20, an NMOS transistor M21, a resistor R3, a resistor R4, and a resistor R5;

[0021] The drain of the NMOS transistor M19 is connected to the E terminal, the gate of the NMOS transistor M19 is connected to TRIM2, the source of the NMOS transistor M19 is connected to the drain of the NMOS transistor M20, the drain of the NMOS transistor M20 is connected to the source of the NMOS transistor M19, the gate of the NMOS transistor M20 is connected to TRIM1, the source of the NMOS transistor M20 is connected to the drain of the NMOS transistor M21, the drain of the NMOS transistor M21 is connected to the source of the NMOS transistor M20, the gate of the NMOS transistor M21 is connected to TRIM0, the source of the NMOS transistor M21 is connected to the S terminal, a first terminal of the resistor R3 is connected to the E terminal, a second terminal of the resistor R3 is connected to the drain of the NMOS transistor M20, a first terminal of the resistor R4 is connected to the drain of the NMOS transistor M20, a second terminal of the resistor R4 is connected to the drain of the NMOS transistor M21, a first terminal of the resistor R5 is connected to the drain of the NMOS transistor M2, and a second terminal of the resistor R5 is connected to the S terminal. Beneficial effects

[0022] An embodiment of the present invention provides a bandgap reference voltage source with an adjustable reference voltage. This source incorporates an NMOS transistor as a switching transistor, which, in conjunction with a resistor, forms a complete bandgap reference voltage source with an adjustable reference voltage. Upon power-up, the system activates the startup circuit, primarily the NMOS transistor on the left. This startup circuit provides a voltage VBP1 to the cascode current mirror. This mutual mirroring forces the two currents to be equal, thereby generating a positive temperature coefficient voltage using PNP transistors of equal area but different numbers. This design employs a transistor ratio of 1:8 to generate the positive temperature coefficient voltage. After mirroring through the MP17 PMOS transistor, a positive temperature coefficient voltage is generated across the resistor, which in turn generates a negative temperature coefficient voltage through the PNP transistor Q2. This design, through calculation and analysis, results in the design of a bandgap reference voltage source. The circuit utilizes three pairs of NMOS transistors and resistors connected in parallel. This network connects to the bandgap reference voltage adjustment point S. Digital signals, when turned on and off, vary the total resistance of the cascode network, thereby achieving voltage regulation. The bandgap reference that adjusts the output voltage through a digital signal can output a high power supply voltage rejection ratio voltage while adjusting the output voltage through a digital signal, thereby reducing the design cycle of the integrated circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 A circuit diagram of a bandgap reference voltage source with adjustable reference voltage according to an embodiment of the present invention;

[0024] Figure 2 This is a waveform diagram of the output voltage of the bandgap reference voltage source with adjustable reference voltage according to an embodiment of the present invention that varies with temperature;

[0025] Figure 3This is a waveform diagram of output voltage changes with temperature corresponding to different trim values ​​of the bandgap reference voltage source with adjustable reference voltage according to an embodiment of the present invention. DETAILED DESCRIPTION

[0026] See also Figures 1 to 3 As shown, according to an embodiment of the present invention, a bandgap reference voltage source with adjustable reference voltage is provided. Figure 1 , including a first circuit, a second circuit and a third circuit;

[0027] The first circuit is connected to the second circuit, and the second circuit end is connected to the third circuit.

[0028] Furthermore, the first circuit portion is a pre-start circuit, the second circuit portion is a bandgap reference circuit of a cascode current mirror structure, and the third circuit portion is a TRIM adjustment circuit.

[0029] The first part of the circuit includes a first switching level circuit, a second switching level circuit, a third switching level circuit, a fourth switching level circuit, a mirror switching level circuit and a series-connected NMOS transistor circuit; the drain end of the first switching level circuit is connected to the drain end of the mirror switching level circuit, the series-connected NMOS transistor circuit is connected to the drain end of the second switching level circuit, the drain end of the third switching level circuit is connected to the other end of the resistor, and the gate segment of the fourth switching level circuit is connected to the drain end of the third switching level circuit.

[0030] Furthermore, the entire first part of the circuit serves as a pre-start circuit and a switching circuit to ensure that the circuit is available at the moment of power-on. When not powered on, ENE is low and ENB is high, so that M6 and M12 are turned on, and the entire circuit is in the off state. Here, the pre-start circuit raises the VBN voltage to the critical point. After power-on, ENE is high and ENB is low. At this time, M0 is turned on and pulls down VBP1. The VBN voltage is instantly pulled up to turn on M10, and then M8 is turned on, and the restart circuit starts working.

[0031] The first switch stage circuit includes a PMOS transistor M6 and a PMOS transistor M7; the source of the PMOS transistor M6 is connected to VDD, the gate of the PMOS transistor M6 is connected to the start voltage ENE, the drain of the PMOS transistor M6 is connected to VBP1, the source of the PMOS transistor M7 is connected to VDD, the gate of the PMOS transistor M7 is connected to ENB, and the drain of the PMOS transistor M7 is connected to VBN.

[0032] Furthermore, M6 and M7 are used as switching tubes. When power is not supplied, M6 is turned on and M7 is turned off, preparing for VBN to reach the startup voltage.

[0033] The second switch stage circuit includes a PMOS transistor M0 , a source of the PMOS transistor M0 connected to VDD, a gate of the PMOS transistor M0 connected to a logic inverse ENB of a start voltage, and a drain of the PMOS transistor M0 connected to a first end of the resistor string.

[0034] Furthermore, M0 is used as a switching tube, and the resistor string here plays a role in delaying power-on to avoid damage to the device due to excessive voltage caused by instantaneous power-on.

[0035] The third switch stage circuit includes an NMOS transistor M10 , a source of the NMOS transistor M10 connected to VSS, a gate of the NMOS transistor M10 connected to VBN, and a drain of the NMOS transistor M10 connected to the second end of the resistor string.

[0036] Furthermore, M10 is used as a switching tube and works in conjunction with M0.

[0037] The fourth switch stage circuit includes an NMOS transistor M8 and an NMOS transistor M9, wherein the source of the NMOS transistor M8 is connected to the drain of the NMOS transistor M9, the gate of the NMOS transistor M8 is connected to the second end of the resistor string, and the drain of the NMOS transistor M8 is connected to VBP1;

[0038] The source of the NMOS transistor M9 is connected to VSS, and the gate of the NMOS transistor M9 is connected to the start-up voltage ENE.

[0039] Furthermore, M8 and M9 are also used as switching tubes to ensure that the circuit can work normally after power-on.

[0040] The second part of the circuit includes: a common source and common gate current mirror circuit, a PNP transistor mirror network and a VREF output current mirror path, the common gate end of the common source and common gate current mirror circuit is connected to VBP1; the S end of the common source and common gate current mirror circuit is connected in parallel to the drain end of the third part of the circuit and the PNP transistor mirror network, and the VREF output current mirror path is connected to the common source and common gate current mirror circuit.

[0041] The cascode current mirror circuit includes: a PMOS transistor M13, a PMOS transistor M14, a PMOS transistor M17, an NMOS transistor M16, an NMOS transistor M15, a resistor R0, a resistor R2, a PNP transistor Q0, a PNP transistor Q1 and a PNP transistor Q2;

[0042] The source of the PMOS transistor M13 is connected to VDD, the gate of the PMOS transistor M13 is connected to VBP1, the drain of the PMOS transistor M13 is connected to VBP1, the source of the PMOS transistor M14 is connected to VDD, the gate of the PMOS transistor M14 is connected to VBP1, the drain of the PMOS transistor M14 is connected to VBP1, the source of the PMOS transistor M17 is connected to VDD, the gate of the PMOS transistor M17 is connected to VBP1, the drain of the PMOS transistor M17 is connected to the first end of the resistor R2, the drain of the NMOS transistor M15 is connected to the drain of the PMOS transistor M14, the gate of the NMOS transistor M15 is connected to the drain of the PMOS transistor M14, the source of the NMOS transistor M15 is connected to the emitter of the PNP transistor Q1, the drain of the NMOS transistor M16 is connected to VBP1, the gate of the NMOS transistor M16 is connected to the drain of the PMOS transistor M14, and the source of the NMOS transistor M16 is connected to the first end of the resistor R0. A first terminal of resistor R0 is connected to the source terminal of NMOS transistor M16. A second terminal of resistor R0 is connected to terminal S. A first terminal of resistor R2 is connected to the drain terminal of PMOS transistor M17. A second terminal of resistor R2 is connected to the emitter of PNP transistor Q2. The collector of PNP transistor Q0 is grounded. The base of PNP transistor Q0 is grounded. The emitter of PNP transistor Q0 is connected to the source terminal of NMOS transistor M15. The collector of PNP transistor Q1 is grounded. The base of PNP transistor Q1 is grounded. The emitter of PNP transistor Q1 is connected to terminal E. The collector of PNP transistor Q2 is grounded. The base of PNP transistor Q2 is grounded. The emitter of PNP transistor Q2 is connected to the second terminal of resistor R2.

[0043] Furthermore, M14 and M13 are in a current mirror relationship, so their drain currents are equal, and M15 and M16 below them are still in a current mirror relationship, which plays a role in strengthening the equality of the currents of M14 and M13. The principle is that such a structure mirrors the current of M13 to M14, and M15 mirrors the current of M13 to M16, which plays a role in strengthening the equality of the currents of I1 and I2. The currents flowing through M15 and M16 are equal, and their gate voltages are also equal, so their corresponding source voltages are also equal. In this way, the source voltage VQ1 corresponding to M15, the source voltage VQ2 corresponding to M16 and the voltage VR0 on a resistor are still the voltage difference between VQ1 and VQ2. The expression we can deduce is, IR=(VD1+VGS1-VGS2-VD2) / R=(KT / Q)(1 / R)ln(Q2 / Q1).

[0044] The third circuit includes: NMOS transistor M19, NMOS transistor M20, NMOS transistor M21, resistor R3, resistor R4 and resistor R5;

[0045] The drain of the NMOS transistor M19 is connected to the E terminal, the gate of the NMOS transistor M19 is connected to TRIM2, the source of the NMOS transistor M19 is connected to the drain of the NMOS transistor M20, the drain of the NMOS transistor M20 is connected to the source of the NMOS transistor M19, the gate of the NMOS transistor M20 is connected to TRIM1, the source of the NMOS transistor M20 is connected to the drain of the NMOS transistor M21, the drain of the NMOS transistor M21 is connected to the source of the NMOS transistor M20, the gate of the NMOS transistor M21 is connected to TRIM0, the source of the NMOS transistor M21 is connected to the S terminal, a first terminal of the resistor R3 is connected to the E terminal, a second terminal of the resistor R3 is connected to the drain of the NMOS transistor M20, a first terminal of the resistor R4 is connected to the drain of the NMOS transistor M20, a second terminal of the resistor R4 is connected to the drain of the NMOS transistor M21, a first terminal of the resistor R5 is connected to the drain of the NMOS transistor M2, and a second terminal of the resistor R5 is connected to the S terminal.

[0046] Furthermore, it plays the role of a gate switch, and by selecting different NMOS tubes, different resistance paths are opened, the ratio of the resistances is changed, and the output voltage of the bandgap reference is changed.

[0047] The present invention can adjust the output voltage of a bandgap reference using digital signals. This allows the output voltage to be adjusted using digital signals while simultaneously outputting a high power supply voltage rejection ratio (PSRR) voltage, thereby reducing the design cycle of integrated circuits. This is particularly true when using a bandgap reference circuit with an ultra-high power supply voltage rejection ratio and the output voltage can be adjusted using digital signals.

[0048] Please refer to Figure 2 As the temperature of the bandgap reference voltage source with adjustable reference voltage rises from -40° to 125°, the voltage first rises and then falls, presenting an arched form. This temperature curve is the desired pattern of the bandgap reference source, and it can be seen that the difference between the highest point and the lowest point is 0.0004, which can stabilize the voltage very well.

[0049] Please refer to Figure 3 , using NMOS tube as a switch, changing the ratio of the resistance, and thus changing the output voltage. Here, with different values ​​of T2, T1, and T0, different voltages are output. Finally, the output voltage is shown in Table 1:

[0050] Table 1

[0051]

[0052] From the output voltage in Table 1, we can see that the different voltages brought about by different Trim values ​​in the table are as follows, and the final output voltage has the following relationship: (8) Existing (8) Here, by changing the resistance value of R0, we can achieve different proportional relationships and thus output different voltages. Here, R0 is achieved by turning on and off the NMOS transistors M19, M20, and M21 of the third circuit. The magnitude of each voltage is debugged. The voltage here is best when the Trim value is 000, which is 1.246. After that, the Trim can be changed according to the power supply voltage required by the system to obtain the voltage required by the system. This is the core of the present invention. That is, the bandgap reference is no longer re-matched according to the voltage required by the system, but the desired voltage can be obtained by changing the Trim value, which greatly shortens the design time.

[0053] The present invention employs a bandgap reference voltage source with a current source structure. This source utilizes an NMOS transistor as a switching transistor, which, in conjunction with a resistor, forms a complete bandgap reference voltage source with adjustable reference voltage. Upon power-up, the system activates the startup circuit, primarily driven by the NMOS transistor on the left side. This startup circuit provides a voltage VBP1 to the cascode current mirror. This mutual mirroring forces the two current paths to be equal, thereby generating a positive temperature coefficient voltage using PNP transistors of equal area but varying in number. This design employs a transistor ratio of 1:8 to generate the positive temperature coefficient voltage. Mirroring through the MP17 PMOS transistor generates a positive temperature coefficient voltage across the resistor, which in turn generates a negative temperature coefficient voltage through the PNP transistor Q2. This design, through calculation and analysis, results in the design of a bandgap reference voltage source. The circuit utilizes three pairs of NMOS transistors and resistors connected in parallel. This network connects to the bandgap reference voltage adjustment point S. Digital signals, when turned on and off, vary the total resistance of the cascode network, thereby achieving voltage regulation. The present invention can use a common source and common gate current mirror as a regulation point because an amplifier is not used as a voltage-coupled device. The advantage of doing so is that there is no need to consider the loop stability at higher frequencies, which improves the anti-interference ability of the circuit. At the same time, the introduced TRIM signal can adjust a stable output voltage, making the reference voltage source more practical and more conducive to large-scale circuit design. At the same time, it solves the problem that the existing bandgap reference voltage source uses an amplifier as a voltage-coupled device to perform motor regulation, and then needs to consider the stability of the loop, resulting in weak anti-interference ability of the circuit and a long design cycle of the circuit.

[0054] It is easy for those skilled in the art to understand that, under the premise of no conflict, the above-mentioned advantageous methods can be freely combined and superimposed.

Claims

1. A bandgap reference voltage source with adjustable reference voltage, characterized in that: including a first circuit, a second circuit, and a third circuit; The first circuit is connected to the second circuit, and the second circuit is connected to the third circuit. The first circuit includes: a first switch stage circuit, a second switch stage circuit, a third switch stage circuit, a fourth switch stage circuit, a mirror switch stage circuit and a series-connected NMOS tube circuit; The drain terminal of the first switch stage circuit is connected to the drain terminal of the mirror switch stage circuit, the series NMOS transistor circuit is connected to the drain terminal of the second switch stage circuit, the drain terminal of the third switch stage circuit is connected to the other end of the series NMOS transistor circuit, and the gate segment of the fourth switch stage circuit is connected to the drain terminal of the third switch stage circuit; The first switch stage circuit includes a PMOS transistor M6 and a PMOS transistor M7; The source of the PMOS transistor M6 is connected to VDD, the gate of the PMOS transistor M6 is connected to the start voltage ENE, the drain of the PMOS transistor M6 is connected to VBP1, the source of the PMOS transistor M7 is connected to VDD, the gate of the PMOS transistor M7 is connected to ENB, and the drain of the PMOS transistor M7 is connected to VBN; The second switch stage circuit includes a PMOS transistor M0, wherein the source of the PMOS transistor M0 is connected to VDD, the gate of the PMOS transistor M0 is connected to the logical inverse ENB of the start voltage, and the drain of the PMOS transistor M0 is connected to the first end of the resistor string; The third switch stage circuit includes an NMOS transistor M10, wherein the source of the NMOS transistor M10 is connected to VSS, the gate of the NMOS transistor M10 is connected to VBN, and the drain of the NMOS transistor M10 is connected to the second end of the resistor string; The fourth switch stage circuit includes an NMOS transistor M8 and an NMOS transistor M9, wherein the source of the NMOS transistor M8 is connected to the drain of the NMOS transistor M9, the gate of the NMOS transistor M8 is connected to the second end of the resistor string, and the drain of the NMOS transistor M8 is connected to VBP1; The source of the NMOS transistor M9 is connected to VSS, and the gate of the NMOS transistor M9 is connected to the start voltage ENE; The second circuit includes: a cascode current mirror circuit, a PNP transistor mirror network, and a VREF output current mirror path; the common gate terminal of the cascode current mirror circuit is connected to VBP1; The S terminal of the cascode current mirror circuit is connected in parallel to the drain terminal of the third circuit and the PNP transistor mirror network, and the VREF output current mirror path is connected to the cascode current mirror circuit; The third circuit includes a resistor, an NMOS network and a digital gating network. The digital gating network is connected to the gate terminal of the NMOS. The resistor and the NMOS network are connected to the source terminal of the common-source and common-gate current mirror circuit.

2. The bandgap reference voltage source with adjustable reference voltage according to claim 1, characterized in that: The source of the PMOS transistor M13 is connected to VDD, the gate of the PMOS transistor M13 is connected to VBP1, the drain of the PMOS transistor M13 is connected to VBP1, the source of the PMOS transistor M14 is connected to VDD, the gate of the PMOS transistor M14 is connected to VBP1, the drain of the PMOS transistor M14 is connected to VBP1, the source of the PMOS transistor M17 is connected to VDD, the gate of the PMOS transistor M17 is connected to VBP1, the drain of the PMOS transistor M17 is connected to the first end of the resistor R2, the drain of the NMOS transistor M15 is connected to the drain of the PMOS transistor M14, the gate of the NMOS transistor M15 is connected to the drain of the PMOS transistor M14, the source of the NMOS transistor M15 is connected to the emitter of the PNP transistor Q1, the drain of the NMOS transistor M16 is connected to VBP1, and the NMOS transistor The gate of the body transistor M16 is connected to the drain terminal of the PMOS transistor M14, the source of the NMOS transistor M16 is connected to the first terminal of the resistor R0, the first terminal of the resistor R0 is connected to the source terminal of the NMOS transistor M16, the second terminal of the resistor R0 is connected to the S terminal, the first terminal of the resistor R2 is connected to the drain terminal of the PMOS transistor M17, the second terminal of the resistor R2 is connected to the emitter of the PNP transistor Q2, the collector of the PNP transistor Q0 is grounded, the base of the PNP transistor Q0 is grounded, the emitter of the PNP transistor Q0 is connected to the source terminal of the NMOS transistor M15, the collector of the PNP transistor Q1 is grounded, the base of the PNP transistor Q1 is grounded, the emitter of the PNP transistor Q1 is connected to the E terminal, the collector of the PNP transistor Q2 is grounded, the base of the PNP transistor Q2 is grounded, and the emitter of the PNP transistor Q2 is connected to the second terminal of the resistor R2; The cascode current mirror circuit includes: a PMOS transistor M13, a PMOS transistor M14, a PMOS transistor M17, an NMOS transistor M16, an NMOS transistor M15, a resistor R0, a resistor R2, a PNP transistor Q0, a PNP transistor Q1 and a PNP transistor Q2; The third circuit includes: NMOS transistor M19, NMOS transistor M20, NMOS transistor M21, resistor R3, resistor R4 and resistor R5; The drain of the NMOS transistor M19 is connected to the E terminal, the gate of the NMOS transistor M19 is connected to TRIM2, the source of the NMOS transistor M19 is connected to the drain of the NMOS transistor M20, the drain of the NMOS transistor M20 is connected to the source of the NMOS transistor M19, the gate of the NMOS transistor M20 is connected to TRIM1, the source of the NMOS transistor M20 is connected to the drain of the NMOS transistor M21, the drain of the NMOS transistor M21 is connected to the source of the NMOS transistor M20, the gate of the NMOS transistor M21 is connected to TRIM0, the source of the NMOS transistor M21 is connected to the S terminal, a first terminal of the resistor R3 is connected to the E terminal, a second terminal of the resistor R3 is connected to the drain of the NMOS transistor M20, a first terminal of the resistor R4 is connected to the drain of the NMOS transistor M20, a second terminal of the resistor R4 is connected to the drain of the NMOS transistor M21, a first terminal of the resistor R5 is connected to the drain of the NMOS transistor M2, and a second terminal of the resistor R5 is connected to the S terminal.

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