Antifuse memory array circuit and memory

Abstract

This disclosure provides an antifuse memory array circuit and a memory. The antifuse memory array circuit includes: an antifuse memory array comprising multiple antifuse memory cells arranged in an array and multiple bit lines, each bit line being coupled to a column of antifuse memory cells; and a level setting circuit coupled to each bit line, configured to set the level of each bit line to a preset level when the antifuse memory array is in an idle state. Since the level of each bit line is determined in the idle state, the antifuse memory array is prevented from burning out due to excessive transient current when transitioning from an idle state to an operating state, thereby reducing the memory failure rate.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to an antifuse memory array circuit and a memory. Background Technology

[0002] In Dynamic Random Access Memory (DRAM), antifuse memory arrays can store the address information of defective memory cells, and then replace the defective memory cells with redundant cells. When the antifuse memory array transitions from an idle state to an active state, the antifuse memory array may be damaged, leading to an increased memory failure rate. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0004] This disclosure provides an antifuse storage array circuit and a memory.

[0005] According to a first aspect of the present disclosure, an antifuse memory array circuit is provided, the antifuse memory array circuit comprising:

[0006] An antifuse memory array, comprising multiple antifuse memory cells arranged in an array and multiple bit lines, each bit line being coupled to a column of the antifuse memory cells;

[0007] A level setting circuit is coupled to each of the bit lines and is configured to set the level of each bit line to a preset level when the antifuse memory array is in an idle state.

[0008] According to some embodiments of this disclosure, the level setting circuit includes:

[0009] A status identification circuit, comprising multiple identification input terminals and a status output terminal, is configured to output a level through the status output terminal based on the identification signal received at each of the identification input terminals to reflect the status of the antifuse storage array;

[0010] A level control circuit is coupled to the status indicator circuit and each bit line. The level control circuit is configured to set the level of each bit line to a preset level or keep the level of each bit line unchanged according to the level output by the status indicator circuit.

[0011] According to some embodiments of this disclosure, the identification signal includes a programming enable signal, a first read enable signal, and a second read enable signal. The programming enable signal is an enable signal for programming the antifuse memory cell; the first read enable signal is an enable signal for reading the antifuse memory array in test mode; and the second read enable signal is an enable signal for reading the antifuse memory array in run mode.

[0012] According to some embodiments of this disclosure, the status identification circuit includes:

[0013] A NOR gate, wherein the input terminal of the NOR gate constitutes the identifier input terminal, and the output terminal of the NOR gate constitutes the status output terminal; or,

[0014] The XNOR gate, wherein the input terminal of the XNOR gate constitutes the identifier input terminal, and the output terminal of the XNOR gate constitutes the status output terminal;

[0015] Each of the identification input terminals receives one identification signal, and the status output terminal is coupled to the level control circuit.

[0016] According to some embodiments of this disclosure, the status identification circuit includes:

[0017] Multiple identification transistors are connected in series, and the control terminal of each identification transistor constitutes an identification input terminal. The first terminal of the first identification transistor is coupled to the power supply, the first terminal of the subsequent identification transistor is coupled to the second terminal of the previous identification transistor, and the second terminal of the last identification transistor constitutes the status output terminal.

[0018] According to some embodiments of this disclosure, the level control circuit includes:

[0019] A plurality of set transistors, each set transistor being coupled between a bit line and a common terminal, and the control terminal of each set transistor being coupled to the status output terminal of the status identification circuit.

[0020] According to some embodiments of this disclosure, the antifuse memory array circuit further includes:

[0021] A plurality of column transistors, each column transistor having a first terminal coupled to a bit line, each column transistor having a second terminal coupled to form a sensing node, each column transistor having a control terminal coupled to a column address signal, the column transistor being used to turn on or off the bit line corresponding to the column address signal.

[0022] According to some embodiments of this disclosure, the antifuse memory array circuit further includes:

[0023] An amplifier, the first end of which is coupled to the sensing node and the second end of which is coupled to a reference voltage signal, is used to read the state of the antifuse storage cell.

[0024] According to some embodiments of this disclosure, the antifuse memory array circuit further includes:

[0025] A precharge transistor, wherein a first terminal of the precharge transistor is coupled to a power supply, a second terminal of the precharge transistor is coupled to the sensing node, and a control terminal of the precharge transistor is coupled to a precharge control signal, the precharge transistor being used to precharge the sensing node before the amplifier is enabled.

[0026] A second aspect of this disclosure provides a memory comprising an antifuse memory array circuit as described above.

[0027] In the antifuse memory array circuit and memory provided in this embodiment, each bit line of the antifuse memory array is coupled to a column of antifuse memory cells to store the address information of the memory cells. The antifuse memory array circuit also includes a level setting circuit coupled to each bit line. When the antifuse memory array is in an idle state, the level setting circuit sets the level of each bit line to a preset level. Since the level of each bit line is determined in the idle state, the antifuse memory array is prevented from burning out due to excessive transient current when transitioning from an idle state to an operating state, thereby reducing the memory failure rate.

[0028] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0029] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of these embodiments. In these drawings, similar reference numerals are used to denote similar elements. The drawings described below are some embodiments of the present disclosure, but not all embodiments. Other drawings will be readily available to those skilled in the art based on these drawings without inventive effort.

[0030] Figure 1 This is a schematic diagram of an antifuse memory array based on an example;

[0031] Figure 2 This is a schematic diagram of an antifuse memory array circuit according to an exemplary embodiment;

[0032] Figure 3 This is a schematic diagram of an antifuse memory array circuit according to another exemplary embodiment;

[0033] Figure 4 This is a schematic diagram of an antifuse memory array circuit according to another exemplary embodiment;

[0034] Figure 5 This is a schematic diagram of an antifuse memory array circuit according to another exemplary embodiment;

[0035] Figure 6 This is a schematic diagram of an antifuse memory array circuit according to another exemplary embodiment;

[0036] Figure 7 This is a flowchart illustrating a control method for an antifuse memory array circuit according to an exemplary embodiment.

[0037] In the diagram: 1. Antifuse memory array; 2. Level set circuit; 3. Column select circuit; 4. Read circuit; 5. Precharge circuit; 6. Programming control circuit; 11. Antifuse memory cell; 21. Status indicator circuit; 22. Level control circuit; BL0, ... BLn, bit lines; NOR gate; OP amplifier; C, precharge capacitor; Q P Programmable transistor; Q S Select transistor; Q F , Identifying transistor; Q V , Set transistor; Q Y , array transistors; Q C Precharge transistor; Q Z 1. Programmable control transistor; VDD, power supply; VSS, common terminal; IN0, ... INn, identifier input terminals; OUT, status output terminal; PG0, ... PGn, programming signals; Xadd0, ... Xaddn, row address signals; Yadd0, ... Yaddn, column address signals; Pre, precharge control signal; PZ, programming control signal; V ref Reference voltage signal. Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions in the disclosed embodiments will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0039] In dynamic random access memory (DRAM), when a memory cell is defective, an antifuse array is used to store the address information of the defective cell. Based on the address information, the defective cell is repaired by replacing it with a redundant cell, thereby improving the yield of DRAM.

[0040] For example, such as Figure 1 As shown, in related technologies, the antifuse memory array 1 includes multiple antifuse memory cells 11 and multiple bit lines (BLs), for example... Figure 1 The memory consists of bit lines BL0…BLn (where n is a positive integer representing the last bit), each bit line coupled to multiple antifuse memory cells 11. Each antifuse memory cell 11 includes a programmable transistor Q. P and select transistor Q S Select transistor Q S Coupled to programmable transistor Q P Between the bit lines. Each select transistor Q S The control terminal is coupled to a row address signal, for example... Figure 1 The row address signals Xadd0…Xaddn, each programmed transistor Q P The control terminal is coupled to a programming signal, for example... Figure 1 The programming signals PG0…PGn are used. When it is necessary to determine whether a memory cell is defective, the antifuse memory array 1 is checked, and the state of the antifuse memory cell 11 is read to determine this. When it is necessary to record that a memory cell is defective, in programming mode, the antifuse memory cell 11 corresponding to the address information of that memory cell is programmed.

[0041] However, in the aforementioned antifuse memory array, when the antifuse memory array is in an idle state, the voltage level of each bit line is floating. When the antifuse memory array transitions from an idle state to an active state, the transient current on the bit lines may be too high, causing damage to the antifuse memory array and thus increasing the failure rate of the dynamic random access memory.

[0042] Based on this, this disclosure provides an antifuse memory array circuit. When the antifuse memory array is in an idle state, a level setting circuit sets the level of each bit line to a preset level, thereby changing each bit line from a floating state to a preset level. When the antifuse memory array transitions from an idle state to an operating state, because each bit line has a stable preset level set, excessive transient current is avoided, thereby reducing the memory failure rate.

[0043] An exemplary embodiment of this disclosure provides an antifuse memory array circuit, such as... Figure 2As shown, the antifuse memory array circuit includes an antifuse memory array 1 and a level setting circuit 2. The antifuse memory array 1 includes multiple antifuse memory cells 11 arranged in an array and multiple bit lines, for example... Figure 2 The array consists of bit lines BL0…BLn, each coupled to a column of antifuse memory cells 11. A level setting circuit 2 is coupled to each bit line and configured to set the level of each bit line to a preset level when the antifuse memory array 1 is in an idle state. The preset level can be an intermediate level, such as a subthreshold level, or it can be a low level. The multiple bit lines extend along a first direction and are arranged along a second direction.

[0044] In this embodiment, each bit line of the antifuse memory array is coupled to a column of antifuse memory cells to store the address information of the memory cells. The antifuse memory array circuit also includes a level setting circuit coupled to each bit line. When the antifuse memory array is in an idle state, the level setting circuit sets the level of each bit line to a preset level. Because the level of each bit line is determined in the idle state, the antifuse memory array is prevented from burning out due to excessive transient current when transitioning from an idle state to an operating state, thereby reducing the memory failure rate.

[0045] For example, the transition of the antifuse memory array 1 from an idle state to an operational state includes at least the transition of the antifuse memory array 1 from an initialization state to an operational state, and the switching process between different operational states. The switching process between different operational states can be, for example, the process of the antifuse memory cell 11 switching from a programming mode to a read mode in test mode.

[0046] It is understood that the antifuse memory array circuit provided in this disclosure can also be applied to the following situations: after the memory is powered on and before broadcasting, such as during post-package repair (PPR); during the switching process of the memory's operating voltage domain, such as adjusting the voltage of a signal from 1.5V to 3V.

[0047] In some exemplary embodiments provided in this disclosure, such as Figure 3 As shown, the antifuse memory cell 11 includes a programmable transistor Q. P and select transistor Q S Programmable transistor Q P The control terminal is coupled to a programming signal, for example... Figure 3 The programming signals PG0…PGn are used to select transistor Q. S Coupled to programmable transistor Q P Between the bit lines, the control terminal is coupled to a row address signal, for example... Figure 3 The row address signals Xadd0…Xaddn are selected by transistor Q.S The first terminal can be connected to the programmable transistor Q. p The second terminal is coupled to the bit line. Alternatively, the first terminal can be coupled to the bit line, and the second terminal to the programmable transistor Q. p The first end is coupled.

[0048] In this embodiment, the antifuse memory cell includes a programming transistor and a selection transistor. When it is necessary to record that a memory cell is defective, the programming transistor of the antifuse memory cell corresponding to the address information of that memory cell is programmed in programming mode, so that redundant cells can be replaced later, thereby improving the yield of the memory.

[0049] In some exemplary embodiments provided in this disclosure, such as Figure 2 As shown, the level setting circuit 2 includes a status flag circuit 21 and a level control circuit 22. The status flag circuit 21 includes multiple flag input terminals and a status output terminal OUT, for example... Figure 2 The identifier input terminals IN0…INn are configured to output a level through the status output terminal OUT based on the identifier signal received at each identifier input terminal to reflect the status of the antifuse memory array 1. The level control circuit 22 is coupled to the status identifier circuit 21 and each bit line, and is configured to set the level of each bit line to a preset level or keep the level of each bit line unchanged based on the level output by the status identifier circuit 21. The identifier signal is used to characterize different operating modes of the memory.

[0050] In this embodiment, the level setting circuit consists of a status flag circuit and a level control circuit. The status flag circuit determines whether the antifuse memory array is in an active or idle state based on the received flag signal, and outputs a level corresponding to the state to the level control circuit. Based on the level output by the status flag circuit, the level control circuit sets the level of each bit line to a preset level when the antifuse memory array is in an idle state, preventing burnout due to excessive transient current when the antifuse memory array transitions from an idle to an active state. When the antifuse memory array is in an active state, the level of each bit line remains unchanged to avoid interfering with the operating state of the antifuse memory array. By setting different levels for each bit line in different states of the antifuse memory array, the failure rate of the memory is reduced while avoiding impact on its operation.

[0051] In some exemplary embodiments provided in this disclosure, the identification signals include a programming enable signal (Rupture-flag), a first read enable signal (Resread-flag), and a second read enable signal (Sensing-flag). The programming enable signal is an enable signal for programming the antifuse memory cells. The first read enable signal is an enable signal for reading the antifuse memory array in test mode. The second read enable signal is an enable signal for reading the antifuse memory array in operation mode. It is understood that the identification signals are not limited to the above-mentioned enable signals and may also be other enable signals that put the antifuse memory array into an operational state.

[0052] In this embodiment, since the identification signal can reflect whether the antifuse memory array is in an active state, the identification signal is used as the basis for controlling the output level of the status identification circuit. The antifuse memory array is in an active state due to different enable signals; these different enable signals are used as a reference to determine whether the antifuse memory array is in an active state. The active state of the antifuse memory array can include a programming active state, a first read active state in test mode, and a second read active state in running mode. Using the enable signals corresponding to these three active states as identification signals can determine whether the antifuse memory array is in an active state, thereby improving the reliability of the memory operation. Furthermore, since the identification signal is composed of different enable signals, only the corresponding enable signals need to be introduced into the status identification circuit without adding additional detection circuitry, reducing the complexity of the antifuse memory array structure.

[0053] For example, the programming enable signal is an enable signal for programming the antifuse memory cells. When the programming function is enabled, the programming enable signal changes, and the antifuse memory array 1 can program the antifuse memory cells 11 to record the address information of defective memory cells. The first read enable signal is an enable signal for reading the antifuse memory array in test mode. When the first read function is enabled, the first read enable signal changes, and the antifuse memory array 1 can read the current or resistance of the selected antifuse memory cell 11 in test mode to determine the state of the antifuse memory cell 11. The second read enable signal is an enable signal for reading the antifuse memory array in operation mode. When the second read function is enabled, the second read enable signal changes, and the antifuse memory array 1 can read the current of the selected antifuse memory cell 11 in operation mode to determine the state of the antifuse memory cell 11. The second read enable signal may be a signal that enables the sensitive amplifier in the memory. When the tester needs to program the antifuse memory array 1 or read the current or resistance of the antifuse memory cell 11 in test mode, an externally input command will cause the corresponding programming enable signal or the first read enable signal to go high. When the memory needs to self-check for defects in the memory cells during operation, it will be automatically enabled by an internal control signal, and the corresponding second read enable signal will go high. That is, the second read enable signal can be an enable signal automatically generated by the memory during broadcasting. In the working state, only one identification signal of the antifuse memory array 1 is high, and the rest are low. That is, each identification signal is not exactly the same. In the idle state, all identification signals of the antifuse memory array 1 are low. That is, each identification signal is exactly the same. Based on the characteristics of the identification signal levels in different states, or whether they are exactly the same in different states, the state of the antifuse memory array 1 can be determined.

[0054] For example, taking the programming enable signal as an example, we will explain how identification signals characterize different operating modes of the memory. When the memory leaves the factory, an instruction is input to the memory's command address pin. The memory determines that the programming enable signal is valid based on the input instruction and then operates in programming mode. After the memory leaves the factory, it needs to be packaged and repaired. An instruction is input to the memory to make it operate in programming mode, and the programming enable signal becomes valid.

[0055] In some exemplary embodiments provided in this disclosure, the status identification circuit 21 includes logic gates. Each logic gate includes multiple identification inputs and a status output OUT. Each identification input receives an identification signal, and the status output OUT is coupled to the level control circuit 22.

[0056] In this embodiment, since the identification signal of the antifuse memory array has corresponding characteristics in different states, the state of the antifuse memory array can be determined by using corresponding logic gates based on the characteristics of the identification signal. By using logic gates as the state identification circuit, the state of the antifuse memory array can be automatically identified without adding a control circuit for detecting the identification signal, thereby reducing the complexity of the state identification circuit structure and control.

[0057] In some exemplary embodiments provided in this disclosure, when the preset level is low, such as Figure 3 As shown, the logic gate may include a NOR gate. The input terminals of the NOR gate constitute the flag input terminals, and the output terminals constitute the status output terminal OUT. Each flag input terminal receives a flag signal, and the status output terminal OUT is coupled to the level control circuit 22.

[0058] In this embodiment, when the preset level is low, the antifuse memory array requires a logic gate to output a high level in the idle state so that the level control circuit outputs a low level. Based on the characteristics of the antifuse memory array's identification signals in different states, corresponding logic gates are used to automatically output the corresponding levels. Based on the premise that only one identification signal is high and the rest are low in the working state, and all identification signals are low in the idle state, a NOR gate is used as the logic gate to process the identification signals. In the working state, if the identification signal input to the NOR gate is high, the NOR gate outputs a low level. In the idle state, if the identification signal input to the NOR gate is not high, the NOR gate outputs a high level. By using a NOR gate as the logic gate, different levels can be automatically output according to different identification signals to reflect the state of the antifuse memory array, thereby reducing the complexity of the state identification circuit's structure and control.

[0059] In some exemplary embodiments provided in this disclosure, when the preset level is low, the logic gate may also include an XNOR gate. The input terminal of the XNOR gate constitutes an identifier input terminal, and the output terminal constitutes a status output terminal OUT. Each identifier input terminal receives an identifier signal, and the status output terminal OUT is coupled to the level control circuit 22.

[0060] In this embodiment, when the preset level is low, the antifuse memory array requires a logic gate to output a high level in the idle state so that the level control circuit outputs a low level. An XOR gate is used to process the flag signals. When all flag inputs are low, the status output can output a high level, thus setting each bit line to prevent the antifuse memory array from burning out. Simultaneously, when multiple flag signals fail but remain valid, the XOR gate can also set the bit lines to prevent the antifuse memory array circuit from burning out, thereby improving the robustness of the antifuse memory array circuit.

[0061] It is understandable that when the preset level is high, a low level can be output through the status output terminal OUT using the corresponding logic gate.

[0062] In some exemplary embodiments provided in this disclosure, when the preset level is low, such as Figure 4 As shown, the status identification circuit 21 includes multiple identification transistors Q. F Each identifier transistor Q F They can be connected in series, and the control terminals form an identification input terminal. The first identification transistor is Q. F The first terminal is coupled to the power supply VDD, and the second terminal is identified by transistor Q. F The first terminal is connected to the previous identifier transistor Q. F The second terminal is coupled, and the last identifier is transistor Q. F The second terminal constitutes the status output terminal OUT. Here, transistor Q is identified. F The number is the same as the number of identification signals. For example, the identification transistor Q... F All are PMOS transistors. Alternatively, each transistor is identified by its Q identifier. F They can also be connected in parallel, with the control terminals forming an identification input. Each identification transistor Q... F The first terminal of each transistor is coupled to form the status output terminal OUT, and the second terminal is coupled to a low level. The status indicator circuit 21 also includes a pull-up resistor coupled between the power supply VDD and the status output terminal OUT. For example, the indicator transistor Q... F All are NMOS transistors.

[0063] In this embodiment, when the preset level is low, the antifuse memory array requires a logic gate to output a high level in the idle state so that the level control circuit outputs a low level. Based on the premise that only one identifier signal is high and the rest are low in the working state, and all identifier signals are low in the idle state, a status identifier circuit composed of multiple identifier transistors is used to process the identifier signals. In the working state, the control terminal of one identifier transistor is high, and this identifier transistor is not conducting. At this time, the last identifier transistor cannot output a high level, thus preventing the level control circuit from outputting the preset level to the bit line. In the idle state, the control terminal of each identifier transistor is low, and all identifier transistors are conducting. At this time, the power supply is output to the level control circuit through each identifier transistor, causing the level control circuit to output the preset level to the bit line. By using multiple identifier transistors, different levels can be automatically output according to different identifier signals to reflect the state of the antifuse memory array, thereby reducing the complexity of the status identifier circuit's structure and control.

[0064] In some exemplary embodiments provided in this disclosure, when the preset level is low, such as Figure 3 and Figure 4 As shown, the level control circuit 22 includes multiple set transistors Q. V Each set transistor Q V Coupled between a bit line and the common terminal VSS (low level), all control terminals are coupled to the status output terminal OUT of the status flag circuit 21. The set transistor Q... V The number of bits is the same as the number of bit lines. For example, each set transistor Q... V The first terminal is coupled to a bit line, and the second terminal is coupled to the common terminal VSS. The set transistor Q... V All are NMOS transistors. It is understandable that when the preset level is high, the set transistor Q can be adjusted. V This is achieved through the type of the signal and the level of its coupling.

[0065] In this embodiment, when the preset level is low, a level control circuit is constructed using multiple set transistors, all coupled to a common terminal. When the antifuse memory array is in the working state, the control terminal of each set transistor is low, and the set transistors are not turned on, thus not affecting the level of each bit line. When the antifuse memory array is in the idle state, the control terminal of each set transistor is high, and the set transistors are turned on, thus setting the level of each bit line to low. By using the different levels output by the status indicator circuit in different states of the antifuse memory array, the set transistors can automatically set the level of the bit line to the preset level when setting is required, thereby reducing the complexity of the level control circuit and the failure rate of the memory.

[0066] Taking the identification signals, including the programming enable signal, the first read enable signal, and the second read enable signal, as an example, combined with... Figure 3 The working principle of the antifuse memory array circuit provided in this disclosure is explained as shown. When the antifuse memory array 1 is in the working state, one of the programming enable signal, the first read enable signal, and the second read enable signal is at a high level, and the rest are at a low level. One of the flag input terminals of the NOR gate is at a high level, the other two flag input terminals are at a low level, and the status output terminal OUT is at a low level. Each set transistor Q V All control terminals are at low level, setting transistor Q. V None of them are conducting, and they do not affect the level of any bit line. When the antifuse memory array 1 is in an idle state, the programming enable signal, the first read enable signal, and the second read enable signal are all low. The three flag inputs of the NOR gate are all low, and the status output terminal OUT is high. Each set transistor Q V All control terminals are at high level, setting transistor Q. VAll are turned on, and the level of each bit line is set to low through the common terminal VSS. Since the level of each bit line is determined in the idle state, the antifuse memory array 1 is prevented from burning out due to excessive transient current when it transitions from the idle state to the working state, thereby reducing the failure rate of the memory.

[0067] In some exemplary embodiments provided in this disclosure, such as Figure 5 As shown, the antifuse memory array circuit also includes a column select circuit 3. The column select circuit 3 is coupled to each bit line and, based on the column address signal, turns the bit line selected by the column address signal on and off, for example... Figure 5 The column address signals Yadd0 and Yaddn are in the column address signal.

[0068] In this embodiment, the column selection circuit can select the bit line corresponding to the column address signal, and then, in conjunction with the row address signal, select the corresponding antifuse memory cell. By selecting the corresponding antifuse memory cell, the antifuse memory cell can be programmed or read for burning or status detection, thereby improving the yield of the memory.

[0069] In some exemplary embodiments provided in this disclosure, such as Figure 6 As shown, column selection circuit 3 includes multiple column transistors Q. Y Each column of transistors Q Y The first end is coupled to a bit line, and the second end is coupled to form a sensing node Vsense. The control terminal is coupled to a column address signal, used to turn on or off the bit line corresponding to the column address signal. The column transistor Q... Y The number of bits is the same as the number of bit lines.

[0070] In this embodiment, a column selection circuit is constructed using column transistors, which can automatically select the corresponding bit line based on the column address signal and thus select the required antifuse memory cell, thereby improving the yield of the memory.

[0071] In some exemplary embodiments provided in this disclosure, such as Figure 5 As shown, the antifuse storage array circuit also includes a read circuit 4. The read circuit 4 is coupled to the column selection circuit 3 and is configured to read the state of the antifuse storage cell 11. Exemplarily, the read circuit 4 is coupled to the sensing node Vsense.

[0072] In this embodiment, the read circuit can read the state of the antifuse memory cell selected based on the row address signal and column address signal. Based on the state of the antifuse memory cell, it can determine whether the memory cell at the corresponding address is defective. By reading and detecting the antifuse memory cell through the read circuit, redundant cells can be replaced, thereby improving the yield of the memory.

[0073] In some exemplary embodiments provided in this disclosure, such as Figure 6 As shown, the readout circuit 4 includes an amplifier OP. The first terminal of the amplifier OP is coupled to the sensing node Vsense, and the second terminal is coupled to the reference voltage signal V. ref The amplifier OP is coupled to read the state of the antifuse memory cell. Exemplarily, the first terminal of the amplifier OP is a non-inverting input, and the second terminal is an inverting input. It is understood that in other embodiments, the read circuit 4 may have other circuit structures, and this disclosure is not limited thereto.

[0074] In this embodiment, the resistance of the antifuse memory cell changes before and after programming, resulting in a change in the input voltage to the first terminal of the amplifier. By comparing the input voltage at the first terminal with the reference voltage signal at the second terminal, it is determined whether the selected antifuse memory cell has been programmed. Determining the state of the antifuse memory cell through comparison by the amplifier reduces the complexity of the read circuit structure and control, and improves the efficiency of antifuse memory cell detection.

[0075] For example, when it is necessary to read the state of the antifuse storage unit 11 coupled to the amplifier OP, the amplifier OP is enabled by a control signal to perform read detection.

[0076] In some exemplary embodiments provided in this disclosure, such as Figure 5 As shown, the antifuse storage array circuit also includes a precharge circuit 5. The precharge circuit 5 is coupled to both the column select circuit 3 and the read circuit 4, and is configured to precharge the read circuit 4 before it is enabled. Exemplarily, the precharge circuit 5 is coupled to the sensing node Vsense.

[0077] In this embodiment, by pre-charging the read circuit before it is enabled to set the corresponding level to high, the read circuit can read the state of the antifuse memory cell, thereby improving the reliability of the read circuit detection.

[0078] In some exemplary embodiments provided in this disclosure, such as Figure 6 As shown, the pre-charge circuit 5 includes a pre-charge transistor Q. C Precharged transistor Q C The first terminal is coupled to the power supply VDD, the second terminal is coupled to the sensing node Vsense, and the control terminal is coupled to the pre-charge control signal Pre. The antifuse memory array circuit also includes a pre-charge capacitor C. The pre-charge capacitor C is a parasitic capacitance of the antifuse memory array circuit, coupled between the sensing node Vsense and the common terminal VSS, and is used to charge the signal through the pre-charge transistor Q. CAfter charging the sensing node Vsense, the voltage of the sensing node Vsense relative to the common terminal VSS is maintained. For example, the pre-charge transistor Q... C It is a PMOS transistor. It is understood that in other embodiments, the pre-charge circuit 5 may have other circuit structures, and this disclosure is not limited thereto.

[0079] In this embodiment, the first terminal of the amplifier in the read circuit is pre-charged by a pre-charge transistor, and energy is stored and maintained by a pre-charge capacitor, reducing the complexity of the pre-charge circuit structure. Since the pre-charge capacitor is a parasitic capacitance in the antifuse memory array circuit, no additional configuration is required, further reducing the complexity of the antifuse memory array circuit structure. When reading the state of a selected antifuse memory cell, this is achieved through a pre-charge-discharge method, enabling the read circuit to output the state of the antifuse memory cell, thereby improving the reliability of the read circuit detection.

[0080] For example, the pre-charge capacitor C can be a parasitic capacitor in the antifuse storage array circuit or a preset capacitor to adjust the pre-charge-discharge capability of the pre-charge circuit 5 and increase controllability.

[0081] For example, when pre-charging of the read circuit 4 is required, the pre-charge control signal Pre is low, and the pre-charge transistor Q... C Turn on to transmit the high level of the first terminal to the first terminal of the amplifier OP.

[0082] In some exemplary embodiments provided in this disclosure, such as Figure 5 As shown, the antifuse memory array circuit also includes a programming control circuit 6. The programming control circuit 6 is coupled to the column selection circuit 3, the read circuit 4, and the precharge circuit 5, and is configured to program selected antifuse memory cells 11. Exemplarily, the programming control circuit 6 is coupled to the sensing node Vsense.

[0083] In this embodiment, the antifuse memory cells are programmed via a programming control circuit to record the addresses of defective memory cells. The read circuit can then read the programmed antifuse memory cells, determine the addresses of defective cells, and replace them with redundant cells, thereby improving the memory yield.

[0084] In some exemplary embodiments provided in this disclosure, such as Figure 6 As shown, the programming control circuit 6 includes a programming control transistor Q. Z Programmable control of transistor Q Z The first terminal is coupled to the sensing node Vsense, the second terminal is coupled to the common terminal VSS, and the control terminal is coupled to the programming control signal PZ. For example, the programming control transistor Q... ZIt is an NMOS transistor. It is understood that in other embodiments, the programming control circuit 6 may have other circuit structures, and this disclosure is not limited thereto.

[0085] In this embodiment, when it is necessary to program the selected antifuse memory cell, the programming control transistor is activated by the programming control signal, and one end of the programming transistor in the corresponding antifuse memory cell is set to a low level. Programming is achieved by breaking down the gate oxide layer of the programming transistor and changing its resistance, thereby recording the address of the defective memory cell to improve the yield of the memory.

[0086] For example, when the programming control signal PZ is high, the programming control transistor Q... Z When the transistor is turned on, the low level corresponding to the common terminal VSS is transmitted to the selected programmable transistor Q. P One end. The programming signal is applied to the programming transistor Q. P Apply a high voltage to the gate of the programmable transistor Q. P When the gate oxide layer is broken down, the antifuse memory cell 11 is programmed to exhibit a low-resistance state. An unprogrammed antifuse memory cell 11 exhibits a high-resistance state.

[0087] This disclosure also provides a memory, which includes an antifuse memory array circuit as described in any of the above embodiments.

[0088] This disclosure provides an exemplary embodiment of a control method for an antifuse memory array circuit, which is executed by the aforementioned antifuse memory array circuit. For example... Figure 7 As shown, Figure 7 A flowchart illustrating a control method for an antifuse memory array circuit according to an exemplary embodiment of the present disclosure is shown, including:

[0089] S100: Receives the input instruction identifier signal.

[0090] S200, Set the input level of the instruction identifier signal.

[0091] In this embodiment, when it is necessary to manually adjust the operating mode of the antifuse memory array circuit, a command identifier signal is input to the antifuse memory array circuit to enable the operating mode corresponding to the command identifier signal. After receiving the command identifier signal, the antifuse memory array circuit enters the corresponding operating mode and inputs the command identifier signal to the level setting circuit. When it is determined to be in an idle state based on the command identifier signal and the control identifier signal, the level setting circuit sets the level of each bit line to a preset level, thereby reducing the memory failure rate.

[0092] This disclosure is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (devices), and computer program products according to embodiments of this disclosure. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create a machine for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0093] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0094] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0095] In this disclosure, the terms “comprising,” “including,” or any other variations thereof are intended to cover non-exclusive inclusion, such that an article or device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such an article or device. Without further limitation, an element defined by the phrase “comprising…” does not exclude the presence of additional identical elements in the article or device that includes said element.

[0096] Although preferred embodiments of the present disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0097] Obviously, those skilled in the art can make various modifications and variations to this disclosure without departing from its spirit and scope. Therefore, if such modifications and variations fall within the scope of the claims of this disclosure and their equivalents, the intent of this disclosure also includes these modifications and variations.

Claims

1. An antifuse memory array circuit, characterized in that, The antifuse storage array circuit includes: An antifuse memory array, comprising multiple antifuse memory cells arranged in an array and multiple bit lines, each bit line being coupled to a column of antifuse memory cells; A level setting circuit, coupled to each bit line, is configured to set the level of each bit line to a preset level when the antifuse memory array is in an idle state. The level setting circuit includes: A status identification circuit, comprising multiple identification input terminals and a status output terminal, is configured to output a level through the status output terminal based on the identification signal received at each of the identification input terminals to reflect the status of the antifuse storage array; A level control circuit is coupled to the status indicator circuit and each bit line. The level control circuit is configured to set the level of each bit line to a preset level or keep the level of each bit line unchanged according to the level output by the status indicator circuit.

2. The antifuse storage array circuit according to claim 1, characterized in that, The identification signal includes a programming enable signal, a first read enable signal, and a second read enable signal. The programming enable signal is an enable signal for programming the antifuse memory cell; the first read enable signal is an enable signal for reading the antifuse memory array in test mode; and the second read enable signal is an enable signal for reading the antifuse memory array in run mode.

3. The antifuse storage array circuit according to claim 1, characterized in that, The status identification circuit includes: A NOR gate, wherein the input terminal of the NOR gate constitutes the identifier input terminal, and the output terminal of the NOR gate constitutes the status output terminal; or, The XNOR gate, wherein the input terminal of the XNOR gate constitutes the identifier input terminal, and the output terminal of the XNOR gate constitutes the status output terminal; Each of the identification input terminals receives one identification signal, and the status output terminal is coupled to the level control circuit.

4. The antifuse storage array circuit according to claim 1, characterized in that, The status identification circuit includes: Multiple identification transistors are connected in series, and the control terminal of each identification transistor constitutes an identification input terminal. The first terminal of the first identification transistor is coupled to the power supply, the first terminal of the subsequent identification transistor is coupled to the second terminal of the previous identification transistor, and the second terminal of the last identification transistor constitutes the status output terminal.

5. The antifuse storage array circuit according to claim 1, characterized in that, The level control circuit includes: A plurality of set transistors, each set transistor being coupled between a bit line and a common terminal, and the control terminal of each set transistor being coupled to the status output terminal of the status identification circuit.

6. The antifuse storage array circuit according to any one of claims 1 to 5, characterized in that, The antifuse storage array circuit also includes: A plurality of column transistors, each column transistor having a first terminal coupled to a bit line, each column transistor having a second terminal coupled to form a sensing node, each column transistor having a control terminal coupled to a column address signal, the column transistor being used to turn on or off the bit line corresponding to the column address signal.

7. The antifuse storage array circuit according to claim 6, characterized in that, The antifuse storage array circuit also includes: An amplifier, the first end of which is coupled to the sensing node and the second end of which is coupled to a reference voltage signal, is used to read the state of the antifuse storage cell.

8. The antifuse storage array circuit according to claim 7, characterized in that, The antifuse storage array circuit also includes: A precharge transistor, wherein a first terminal of the precharge transistor is coupled to a power supply, a second terminal of the precharge transistor is coupled to the sensing node, and a control terminal of the precharge transistor is coupled to a precharge control signal, the precharge transistor being used to precharge the sensing node before the amplifier is enabled.

9. A memory, characterized in that, The memory includes the antifuse memory array circuit as described in any one of claims 1 to 8.

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