Methods for forming semiconductor structures

Abstract

A method for forming a semiconductor structure includes: providing a substrate, the substrate including a base and a layer to be etched, the substrate including a first region and a second region; forming a plurality of first initial mask structures on the first region, and forming a plurality of second mask structures on the second region, the initial first mask structures having a first width deviation dimension, and the second mask structures having a second width deviation dimension; forming a first sacrificial layer on the layer to be etched and the second mask structures; and etching the first initial mask structures to form a first mask structure based on a first advanced process control technology, the first mask structure having a second width dimension and a third width deviation dimension, wherein the third width deviation dimension is equal to the second width deviation dimension. By using the first advanced process control technology for algorithm optimization, the third width deviation dimension is made equal to the second width deviation dimension, eliminating the process step of forming an additional sacrificial layer and then covering the first mask structure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a method for forming a semiconductor structure. Background Technology

[0002] The purpose of Advanced Process Control (APC) research in semiconductor manufacturing is to effectively monitor the process and equipment in order to improve yield and overall equipment efficiency.

[0003] As semiconductor process nodes continue to shrink, the process window for semiconductor device fabrication becomes increasingly narrow. This places more stringent requirements on integrated circuit equipment and testing equipment for process control. Traditional statistical process control (SPC) and methods that control only a single parameter are no longer adequate for current process technology requirements. Therefore, advanced process control technology has become one of the key technologies in semiconductor manufacturing. Advanced process control technology, as a primary solution, has gradually gained acceptance from semiconductor equipment suppliers, measurement equipment suppliers, and manufacturers, and is currently being increasingly applied in processes such as chemical mechanical polishing, chemical vapor deposition, photolithography, and etching.

[0004] The goal of advanced process control technology is to solve the problem of drift in the average value of results caused by fluctuations in various parameters and performance indicators during the process between different wafers. It can effectively shorten the measurement time and adjust process variables in a timely manner. Its implementation helps to improve productivity, reduce energy consumption, improve product quality and continuity, and improve process safety, enabling process equipment to achieve more stringent process windows to meet the requirements of the continuous shrinking of semiconductor process nodes.

[0005] Although advanced process control technology is used to control the etching process in existing technologies, the existing technologies still suffer from low wafer production yield and low reliability. Summary of the Invention

[0006] The technical problem solved by this invention is to provide a method for forming a semiconductor structure to improve wafer production yield and reliability.

[0007] To address the aforementioned problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a base and a layer to be etched located on the base, the substrate including a first region and a second region; forming a plurality of first initial mask structures arranged parallel to each other along a first direction on the first region, and forming a plurality of second mask structures arranged parallel to each other along the first direction on the second region, the initial first mask structures having a first width dimension and a first width deviation dimension in the first direction, and the second mask structures having a second width deviation dimension difference in the first direction; forming a first sacrificial layer on the layer to be etched and the second mask structures, the first sacrificial layer exposing the first region and the first initial mask structures; and etching the first initial mask structures using the first sacrificial layer as a mask based on a first advanced process control technology to form a first mask structure, the first mask structure being formed in the first region... The first patterned structure has a second width dimension and a third width deviation dimension in one direction, the second width dimension being smaller than the first width dimension, and the third width deviation dimension being equal to the second width deviation dimension; the first sacrificial layer is removed; based on a second advanced process control technology, a protective layer is formed covering the first mask structure and the second mask structure, such that the first mask structure and the protective layer form a first patterned structure, and the second mask structure and the protective layer form a second patterned structure, the first patterned structure having a fourth deviation width dimension in the first direction, and the second patterned structure having a fifth width deviation dimension in the first direction, and the fourth width deviation dimension being equal to the fifth width deviation dimension; the layer to be etched is etched using the first patterned structure and the second patterned structure as masks, forming a plurality of first device structures in the first region and a plurality of second device structures in the second region.

[0008] Optionally, the fourth width deviation dimension is 0; the fifth width deviation dimension is 0.

[0009] Optionally, the layer to be etched further includes a third region, on which a plurality of third mask structures are arranged in parallel along the first direction, and the third mask structures have a sixth offset dimension in the first direction.

[0010] Optionally, after removing the first sacrificial layer and before forming the protective layer, the method further includes: forming a second sacrificial layer on the layer to be etched and on the third mask structure, the second sacrificial layer exposing the first mask structure and the second mask structure; after forming the protective layer, the fourth width deviation dimension is equal to the sixth width deviation dimension, and the fifth width deviation dimension is equal to the sixth width deviation dimension.

[0011] Optionally, the first device structure and the second device structure are formed based on a third advanced process control technology, and the process of forming the first device structure and the second device structure further includes: etching the layer to be etched with the third mask structure to form a plurality of third device structures in the third region, wherein the first device structure has a seventh width deviation dimension in the first direction, the second device structure has an eighth width deviation dimension in the first direction, and the third device structure has a ninth width deviation dimension in the first direction.

[0012] Optionally, the seventh width deviation dimension is 0; the eighth width deviation dimension is 0; and the ninth width deviation dimension is 0.

[0013] Optionally, the method for forming the first initial mask structure and the second mask structure includes: forming a mask material layer on the layer to be etched; forming a patterned layer on the mask material layer, the patterned layer exposing a portion of the top surface of the mask material layer; etching the mask material layer using the patterned layer as a mask until the top surface of the layer to be etched is exposed, thereby forming the first initial mask structure and the second mask structure.

[0014] Optionally, the process of etching the mask material layer using the patterned layer as a mask includes: a dry etching process.

[0015] Optionally, the material of the mask material layer includes silicon oxide or silicon nitride.

[0016] Optionally, the protective layer is also located on the top surface of the layer to be etched.

[0017] Optionally, the protective layer is formed using an atomic layer deposition process.

[0018] Optionally, the material of the protective layer includes silicon oxide.

[0019] Optionally, the etching process for the first initial mask structure includes a dry etching process.

[0020] Optionally, the process of etching the layer to be etched using the first mask structure, the second mask structure, and the protective layer as masks includes: a plasma dry etching process.

[0021] Optionally, the material of the layer to be etched includes: a semiconductor material; the semiconductor material includes: silicon or silicon germanium.

[0022] Optionally, the first device structure and the second device structure each include a fin.

[0023] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0024] In the semiconductor structure formation method of the present invention, the first advanced process control technology is used to optimize the algorithm so that the third width deviation dimension of the first mask structure is equal to the second width deviation dimension of the second mask structure; then, a globally covering protective layer is formed by additional second advanced process control technology. Through thickness compensation of the protective layer, it can be ensured that the fourth width deviation dimension of the first patterned structure is equal to the fifth width deviation dimension of the second patterned structure, thereby eliminating the process step of forming an additional sacrificial layer to cover the first mask structure.

[0025] Furthermore, the fourth width deviation dimension is 0; the fifth width deviation dimension is 0, which enables the simultaneous and precise elimination of width deviation dimensions for multiple types of patterns, thereby ensuring the accuracy of subsequent pattern transfer and improving wafer production yield and reliability.

[0026] Furthermore, after removing the first sacrificial layer and before forming the protective layer, the process further includes: forming a second sacrificial layer on the layer to be etched and on the third mask structure, the second sacrificial layer exposing the first mask structure and the second mask structure; after forming the protective layer, the fourth width deviation dimension is equal to the sixth width deviation dimension, and the fifth width deviation dimension is equal to the sixth width deviation dimension. By utilizing the existing process steps of forming the second sacrificial layer, which exposes the first mask structure and the second mask structure, it is possible to ensure that the fourth width deviation dimension of the first patterned structure, the fifth width deviation dimension of the second patterned structure, and the sixth width deviation dimension of the third mask structure are equal, thereby eliminating the need for an additional process step of forming a sacrificial layer to cover the first mask structure and the second mask structure.

[0027] Furthermore, the first device structure and the second device structure are formed based on a third advanced process control technology. During the formation of the first device structure and the second device structure, the process further includes: etching the layer to be etched using the third mask structure to form a plurality of third device structures in the third region. The first device structure has a seventh width deviation dimension in the first direction, the second device structure has an eighth width deviation dimension in the first direction, and the third device structure has a ninth width deviation dimension in the first direction; the seventh width deviation dimension is 0; the eighth width deviation dimension is 0; and the ninth width deviation dimension is 0. This enables the simultaneous and precise elimination of width deviation dimensions for multiple types of patterns, thereby improving the accuracy of the width dimensions of the first device structure, the second device structure, and the third device structure, and enhancing wafer production yield and reliability. Attached Figure Description

[0028] Figures 1 to 3 This is a schematic diagram of the steps involved in forming a semiconductor structure.

[0029] Figures 4 to 10 This is a schematic diagram of the steps in the method for forming a semiconductor structure in an embodiment of the present invention;

[0030] Figures 11 to 18 This is a schematic diagram of the steps in the method for forming a semiconductor structure in another embodiment of the present invention. Detailed Implementation

[0031] As described in the background section, although advanced process control technology is used in the prior art to control the etching process, the prior art still suffers from low wafer production yield and low reliability. The following will provide a detailed explanation in conjunction with the accompanying drawings.

[0032] Figures 1 to 3 This is a schematic diagram of the steps involved in forming a semiconductor structure.

[0033] Please refer to Figure 1 A substrate is provided, the substrate including a base 100 and an etchable layer 101 located on the base 100. The substrate includes a first region I and a second region II. The first region I has a plurality of first initial mask structures 102 arranged in parallel along a first direction. The first initial mask structures 102 have a first width dimension d1 and a first width deviation dimension Δ1. The second region II has a plurality of second mask structures 103 arranged in parallel along the first direction. The second mask structures 103 have a second width deviation dimension Δ2.

[0034] Please refer to Figure 2 A first sacrificial layer 104 is formed on the layer to be etched 101 and the second mask structure 103. The first sacrificial layer 104 exposes the first region I and the first initial mask structure 102. Based on the first advanced process control technology, the first initial mask structure 102 is etched to form a first mask structure 105. The first mask structure 105 has a second width dimension d2, which is smaller than the first width dimension d1, and the first mask structure 105 does not have a width deviation dimension.

[0035] Please refer to Figure 3After forming the first mask structure 105, the first sacrificial layer 104 is removed; a protective layer 106 is formed on the sidewalls and top surface of the first mask structure 105 and on the sidewalls and top surface of the second mask structure 103, such that the first mask structure 105 and the protective layer 106 form a first patterned structure (not shown), and the second mask structure 103 and the protective layer 106 form a second patterned structure; the layer to be etched 101 is etched using the first patterned structure and the second patterned structure as masks, forming a plurality of first device structures 107 in the first region I and a plurality of second device structures 108 in the second region II.

[0036] In this embodiment, during the formation of the first initial mask structure 102 and the second mask structure 103, due to process fluctuations, there is a difference between the first width dimension d1 of the first initial mask structure 102 and the preset first target width dimension, which causes the first initial mask structure 102 to have the first width deviation dimension Δ1, and similarly causes the second mask structure 103 to have the second width deviation dimension Δ2.

[0037] Because the width of the first mask structure 105 differs from that of the second mask structure 103 in the manufacturing process, the first initial mask structure 102 needs to be etched and adjusted. During the etching adjustment process, a first advanced process control technology is employed to ensure that the resulting first mask structure 105 has no width deviation.

[0038] However, when etching and adjusting the first initial mask structure 102, the second mask structure 103 needs to be covered by the first sacrificial layer 104. Therefore, the first advanced process control technology cannot compensate for the second width deviation dimension Δ2 of the second mask structure 103, resulting in the persistent existence of the second width deviation dimension Δ2. Subsequent etching of the layer 101 to be etched using the second patterned structure as a mask will also cause deviations in the feature dimensions of the final formed second device structure 108, leading to lower wafer production yield and reliability.

[0039] In addition, since advanced process control technology is a global process, the deviation adjustment of each structure is kept consistent. If it is desired to compensate for the second width deviation dimension Δ2 again through advanced process control technology in the future, a sacrificial layer needs to be formed to cover the first mask structure 105, which increases the number of process steps.

[0040] Based on this, the present invention provides a method for forming a semiconductor structure. The method utilizes the first advanced process control technology to perform algorithm optimization, so that the third width deviation dimension of the first mask structure is equal to the second width deviation dimension of the second mask structure. Then, a globally covering protective layer is formed by additional second advanced process control technology. Through thickness compensation of the protective layer, it can be ensured that the fourth width deviation dimension of the first patterned structure is equal to the fifth width deviation dimension of the second patterned structure, thereby eliminating the process step of forming an additional sacrificial layer to cover the first mask structure.

[0041] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0042] Figures 4 to 10 This is a schematic diagram of the steps in the method for forming a semiconductor structure in an embodiment of the present invention.

[0043] Please refer to Figure 4 A substrate is provided, the substrate including a base 200 and an etchable layer 201 located on the base 200, the substrate including a first region I and a second region II.

[0044] In this embodiment, the substrate 200 is made of silicon. In other embodiments, the substrate may also be made of germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide.

[0045] In this embodiment, the material of the layer 201 to be etched is a semiconductor material; the semiconductor material is silicon. In other embodiments, the semiconductor material may also be silicon-germanium.

[0046] In other embodiments, the material of the layer to be etched may also be a metal.

[0047] In this embodiment, the etching layer 201 in the first region I is used to form a plurality of first fins in the future, and the etching layer 201 in the second region II is used to form a plurality of second fins in the future. The first fins have a smaller width in terms of design requirements and a larger spacing between adjacent first fins, while the second fins have a larger width in terms of design requirements and a smaller spacing between adjacent second fins.

[0048] Please refer to Figure 5A plurality of first initial mask structures 202 are formed in the first region I, which are arranged in parallel along the first direction X. A plurality of second mask structures 203 are formed in the second region II, which are arranged in parallel along the first direction X. The initial first mask structures 202 have a first width dimension d1 and a first width deviation dimension Δ1 in the first direction X. The second mask structures 203 have a second width deviation dimension Δ2 in the first direction X.

[0049] In this embodiment, the first deviation dimension Δ1 is the deviation between the actual width and the target width of the first initial mask structure 202, and the second deviation dimension Δ2 is the deviation between the actual width and the target width of the second mask structure 203.

[0050] In this embodiment, the method for forming the first initial mask structure 202 and the second mask structure 203 includes: forming a mask material layer (not shown) on the layer to be etched 201; forming a patterned layer (not shown) on the mask material layer, wherein the patterned layer exposes a portion of the top surface of the mask material layer; etching the mask material layer using the patterned layer as a mask until the top surface of the layer to be etched 201 is exposed, thereby forming the first initial mask structure 202 and the second mask structure 203.

[0051] In this embodiment, the process of etching the mask material layer using the patterned layer as a mask adopts a dry etching process.

[0052] In this embodiment, the mask material layer is made of silicon oxide; in other embodiments, the mask material layer may also be made of silicon nitride.

[0053] Please refer to Figure 6 A first sacrificial layer 204 is formed on the layer to be etched 201 and the second mask structure 203, and the first sacrificial layer 204 exposes the first region I and the first initial mask structure 202.

[0054] It should be noted that, in order to reduce process costs, the first initial mask structure 202 and the second mask structure 203 are formed using the same photomask. However, since the first fin and the second fin have different feature sizes, the feature sizes of the second mask structure 203 and the subsequently formed first mask structure also need to be different. However, due to the limitations of photolithography, the first initial mask structure 202 and the second mask structure 203 formed from a single photomask cannot simultaneously meet the corresponding feature size requirements. Therefore, the first initial mask structure 202 needs to be further adjusted to further reduce the critical dimensions, so that the first mask structure and the second mask structure 203 can meet the corresponding feature size requirements.

[0055] In this embodiment, when adjusting the first initial mask structure 202, in order to avoid affecting the second mask structure 203, the sacrificial layer 204 is used to cover the second mask structure 203.

[0056] In this embodiment, the material of the sacrificial layer 204 is photoresist.

[0057] Please refer to Figure 7 Based on the first advanced process control technology, the first initial mask structure 202 is etched using the first sacrificial layer 204 as a mask to form a first mask structure 205. The first mask structure 205 has a second width dimension d2 and a third width deviation dimension Δ3 in the first direction X. The second width dimension d2 is smaller than the first width dimension d1, and the third width deviation dimension Δ3 is equal to the second width deviation dimension Δ2.

[0058] In this embodiment, the third width deviation dimension Δ3 is the deviation between the actual width and the target width of the first mask structure 205.

[0059] In this embodiment, the algorithm is optimized using the first advanced process control technology so that the third width deviation dimension Δ3 of the first mask structure 202 is equal to the second width deviation dimension Δ2 of the second mask structure 203, thereby ensuring that the second width deviation dimension Δ2 and the third width deviation dimension Δ3 can be eliminated simultaneously through additional advanced process control technology.

[0060] In this embodiment, the etching process for the first initial mask structure 202 is a dry etching process.

[0061] Please refer to Figure 8 After the first mask structure 205 is formed, the first sacrificial layer 204 is removed.

[0062] In this embodiment, the process of removing the first sacrificial layer 204 is an ashing process.

[0063] Please refer to Figure 9After removing the first sacrificial layer 204, based on the second advanced process control technology, a protective layer 206 is formed on the sidewalls and top surface of the first mask structure 205 and on the sidewalls and top surface of the second mask structure 203, such that the first mask structure 205 and the protective layer 206 form a first patterned structure, and the second mask structure 203 and the protective layer 206 form a second patterned structure. The first patterned structure has a fourth deviation width dimension Δ4 in the first direction X, and the second patterned structure has a fifth width deviation dimension Δ5 in the first direction X, and the fourth width deviation dimension Δ4 and the fifth width deviation dimension Δ5 are equal.

[0064] In this embodiment, the fourth deviation width dimension Δ4 is ​​the deviation between the actual width and the target width of the first graphical structure, and the fifth deviation width dimension Δ5 is the deviation between the actual width and the target width of the second graphical structure.

[0065] In this embodiment, the algorithm is optimized using the first advanced process control technology, so that the third width deviation dimension Δ3 of the first mask structure 205 is equal to the second width deviation dimension Δ2 of the second mask structure 203. Then, a globally covering protective layer 206 is formed by additional second advanced process control technology. Through thickness compensation of the protective layer 206, the fourth width deviation dimension Δ4 of the first patterned structure is equal to the fifth width deviation dimension Δ5 of the second patterned structure, thereby eliminating the process step of forming an additional sacrificial layer to cover the first mask structure 205.

[0066] In this embodiment, the fourth width deviation dimension Δ4 is ​​0; the fifth width deviation dimension Δ5 is 0, which enables the simultaneous and precise elimination of width deviation dimensions for multiple types of patterns, thereby ensuring the accuracy of subsequent pattern transfer and improving wafer production yield and reliability.

[0067] In this embodiment, the protective layer 206 serves to reduce the impact of lateral etching on the width dimensions of the first mask structure 205 and the second mask structure 203 during subsequent patterning transfer, so as to ensure that the first fin and the second fin formed after patterning transfer are consistent with the target feature size.

[0068] In this embodiment, the protective layer 206 is also located on the top surface of the layer to be etched 201.

[0069] In this embodiment, the protective layer 206 is formed using atomic layer deposition (ALD).

[0070] In this embodiment, the protective layer 206 is made of silicon oxide.

[0071] It should be noted that although the protective layer 206 is still located on the top surface of the layer to be etched 201, its thickness is very thin. During the subsequent patterning process, the plasma etching process can directly bombard and etch away the protective layer 206 located on the top surface of the layer to be etched 201. Therefore, after the protective layer 206 is formed by atomic layer deposition, no further processing is required even if the protective layer 206 is still located on the top surface of the layer to be etched 201.

[0072] Please refer to Figure 10 Using the first patterned structure and the second patterned structure as masks, the layer to be etched 201 is etched, forming a plurality of first device structures 207 in the first region I and a plurality of second device structures 208 in the second region II.

[0073] In this embodiment, the process of etching the layer 201 to be etched using the first mask structure 205, the second mask structure 203, and the protective layer 206 as masks adopts a plasma dry etching process.

[0074] In this embodiment, the first device structure 207 and the second device structure 208 are fins. That is, the first device structure 207 is the first fin, and the second device structure 208 is the second fin.

[0075] In other embodiments, when the material of the layer to be etched is metal, the first device structure and the second device structure may also be conductive layers.

[0076] Figures 11 to 18 This is a schematic diagram of the steps in the method for forming a semiconductor structure in another embodiment of the present invention.

[0077] This embodiment further describes the method for forming a semiconductor structure based on the above embodiments. The difference between this embodiment and the above embodiments is that the etchable layer 201 further includes a third region III, and the third region III has a plurality of third mask structures arranged parallel to the first direction X. The third mask structures have a sixth deviation dimension in the first direction X. The following will describe in detail with reference to the accompanying drawings.

[0078] Please refer to Figure 11 The layer to be etched 201 further includes a third region III, on which a plurality of third mask structures 209 are arranged in parallel along the first direction X, and the third mask structures 209 have a sixth deviation dimension Δ6 in the first direction X.

[0079] In this embodiment, the sixth deviation dimension Δ6 is the deviation between the actual width and the target width of the third mask structure 209.

[0080] In this embodiment, the third mask structure 209 is used to form a third device structure in a subsequent process of graphical transfer.

[0081] In this embodiment, the method for forming the first initial mask structure 202, the second mask structure 203, and the third mask structure 209 includes: forming a mask material layer (not shown) on the layer to be etched 201; forming a patterned layer (not shown) on the mask material layer, wherein the patterned layer exposes a portion of the top surface of the mask material layer; etching the mask material layer using the patterned layer as a mask until the top surface of the layer to be etched 201 is exposed, thereby forming the first initial mask structure 202, the second mask structure 203, and the third mask structure 209.

[0082] Please refer to Figure 12 A first sacrificial layer 204 is formed on the layer to be etched 201, the second mask structure 203 and the third mask structure 209, and the first sacrificial layer 204 exposes the first region I and the first initial mask structure 202.

[0083] In this embodiment, the function and material of the first sacrificial layer 204 are the same as in the above embodiments, and will not be described again here.

[0084] Please refer to Figure 13 Based on the first advanced process control technology, the first initial mask structure 202 is etched using the first sacrificial layer 204 as a mask to form a first mask structure 205. The first mask structure 205 has a second width dimension d2 and a third width deviation dimension Δ3 in the first direction X. The second width dimension d2 is smaller than the first width dimension d1, and the third width deviation dimension Δ3 is equal to the second width deviation dimension Δ2.

[0085] In this embodiment, the third width deviation dimension Δ3 is the deviation between the actual width and the target width of the first mask structure 205.

[0086] In this embodiment, the etching process for the first initial mask structure 202 is the same as in the above embodiments, and will not be described again here.

[0087] Please refer to Figure 14 After the first mask structure 205 is formed, the first sacrificial layer 204 is removed.

[0088] In this embodiment, the process for removing the first sacrificial layer 204 is the same as in the above embodiments, and will not be described again here.

[0089] Please refer to Figure 15 After removing the first sacrificial layer 204, a second sacrificial layer 210 is formed on the layer to be etched 201 and the third mask structure 209, and the second sacrificial layer 210 exposes the first mask structure 205 and the second mask structure 203.

[0090] In this embodiment, the material of the second sacrificial layer 210 is photoresist.

[0091] Please refer to Figure 16 After the second sacrificial layer 210 is formed, based on the second advanced process control technology, a protective layer 206 is formed on the sidewalls and top surface of the first mask structure 205 and on the sidewalls and top surface of the second mask structure 203, such that the first mask structure 203 and the protective layer 206 form a first patterned structure, and the second mask structure 203 and the protective layer 206 form a second patterned structure. The first patterned structure has a fourth deviation width dimension Δ4 in the first direction X, and the second patterned structure has a fifth width deviation dimension Δ5 in the first direction X, and the fourth width deviation dimension Δ4 and the fifth width deviation dimension Δ5 are equal.

[0092] In this embodiment, the fourth deviation width dimension Δ4 is ​​the deviation between the actual width and the target width of the first graphical structure, and the fifth deviation width dimension Δ5 is the deviation between the actual width and the target width of the second graphical structure.

[0093] In this embodiment, the fourth width deviation dimension Δ4 is ​​not 0, and the fifth width deviation dimension Δ5 is not 0.

[0094] In this embodiment, the fourth width deviation dimension Δ4 is ​​equal to the sixth width deviation dimension Δ6, and the fifth width deviation dimension Δ5 is equal to the sixth width deviation dimension Δ6. By utilizing the existing process step of forming a second sacrificial layer 210, which exposes the first mask structure 205 and the second mask structure 203, it is possible to ensure that the fourth width deviation dimension Δ4 of the first patterned structure, the fifth width deviation dimension Δ5 of the second patterned structure, and the sixth width deviation dimension Δ6 of the third mask structure 209 are equal, thereby eliminating the need for the additional process step of forming a sacrificial layer to cover the first mask structure 205 and the second mask structure 203.

[0095] In this embodiment, the material and forming process of the protective layer 206 are the same as in the above embodiments, and will not be described again here.

[0096] Please refer to Figure 17 After the protective layer 206 is formed, the second sacrificial layer 210 is removed.

[0097] In this embodiment, the process of removing the second sacrificial layer 210 is an ashing process.

[0098] Please refer to Figure 18 The first device structure 207 and the second device structure 208 are formed based on the third advanced process control technology. During the formation of the first device structure 207 and the second device structure 208, the layer to be etched 201 is etched with the third mask structure 209, and a plurality of third device structures 211 are formed in the third region III. The first device structure 207 has a seventh width deviation dimension Δ7 in the first direction X, the second device structure 208 has an eighth width deviation dimension Δ8 in the first direction X, and the third device structure 211 has a ninth width deviation dimension Δ9 in the first direction X.

[0099] In this embodiment, the seventh width deviation dimension Δ7 is the deviation between the actual width and the target width of the first device structure 207, the eighth width deviation dimension Δ8 is the deviation between the actual width and the target width of the second device structure 208, and the ninth width deviation dimension Δ9 is the deviation between the actual width and the target width of the third device structure 211.

[0100] In this embodiment, the seventh width deviation dimension Δ7 is 0; the eighth width deviation dimension Δ8 is 0; and the ninth width deviation dimension Δ9 is 0. Through this advanced process control technology, the width deviation dimensions of multiple types of patterns can be simultaneously and accurately eliminated, thereby improving the accuracy of the width dimensions of the first device structure 207, the second device structure 208, and the third device structure 211, and enhancing wafer production yield and reliability.

[0101] In this embodiment, the first device structure 207 and the second device structure 208 are the same as in the above embodiments, and will not be described again here.

[0102] In this embodiment, the third device structure 211 is a third fin.

[0103] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate comprising a base and a layer to be etched located on the base, the substrate comprising a first region and a second region; A plurality of first initial mask structures are formed in parallel along a first direction in the first region, and a plurality of second mask structures are formed in parallel along the first direction in the second region. The initial first mask structures have a first width dimension and a first width deviation dimension in the first direction, and the second mask structures have a second width deviation dimension difference in the first direction. A first sacrificial layer is formed on the layer to be etched and on the second mask structure, the first sacrificial layer exposing the first region and the first initial mask structure; Based on the first advanced process control technology, the first initial mask structure is etched using the first sacrificial layer as a mask to form a first mask structure. The first mask structure has a second width dimension and a third width deviation dimension in the first direction. The second width dimension is smaller than the first width dimension, and the third width deviation dimension is equal to the second width deviation dimension. Remove the first sacrificial layer; Based on the second advanced process control technology, a protective layer is formed covering the first mask structure and the second mask structure, such that the first mask structure and the protective layer form a first patterned structure, and the second mask structure and the protective layer form a second patterned structure. The first patterned structure has a fourth width deviation dimension in the first direction, and the second patterned structure has a fifth width deviation dimension in the first direction, and the fourth width deviation dimension and the fifth width deviation dimension are equal. Using the first patterned structure and the second patterned structure as masks, the layer to be etched is etched to form a plurality of first device structures in the first region and a plurality of second device structures in the second region.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The fourth width deviation dimension is 0; the fifth width deviation dimension is 0.

3. The method for forming a semiconductor structure as described in claim 1, characterized in that, The layer to be etched further includes a third region, on which a plurality of third mask structures are arranged in parallel along the first direction, and the third mask structures have a sixth width deviation dimension in the first direction.

4. The method for forming a semiconductor structure as described in claim 3, characterized in that, After removing the first sacrificial layer and before forming the protective layer, the method further includes: forming a second sacrificial layer on the layer to be etched and on the third mask structure, the second sacrificial layer exposing the first mask structure and the second mask structure; after forming the protective layer, the fourth width deviation dimension is equal to the sixth width deviation dimension, and the fifth width deviation dimension is equal to the sixth width deviation dimension.

5. The method for forming a semiconductor structure as described in claim 4, characterized in that, The first device structure and the second device structure are formed based on the third advanced process control technology, and the process of forming the first device structure and the second device structure further includes: etching the layer to be etched with the third mask structure, forming a plurality of third device structures in the third region, wherein the first device structure has a seventh width deviation dimension in the first direction, the second device structure has an eighth width deviation dimension in the first direction, and the third device structure has a ninth width deviation dimension in the first direction.

6. The method for forming a semiconductor structure as described in claim 5, characterized in that, The seventh width deviation dimension is 0; the eighth width deviation dimension is 0; the ninth width deviation dimension is 0.

7. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method for forming the first initial mask structure and the second mask structure includes: forming a mask material layer on the layer to be etched; forming a patterned layer on the mask material layer, wherein the patterned layer exposes a portion of the top surface of the mask material layer; and etching the mask material layer using the patterned layer as a mask until the top surface of the layer to be etched is exposed, thereby forming the first initial mask structure and the second mask structure.

8. The method for forming a semiconductor structure as described in claim 7, characterized in that, The process of etching the mask material layer using the patterned layer as a mask includes: a dry etching process.

9. The method for forming a semiconductor structure as described in claim 7, characterized in that, The material of the mask material layer includes silicon oxide or silicon nitride.

10. The method for forming a semiconductor structure as described in claim 1, characterized in that, The protective layer is also located on the top surface of the layer to be etched.

11. The method for forming a semiconductor structure as described in claim 10, characterized in that, The process for forming the protective layer includes atomic layer deposition.

12. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the protective layer includes silicon oxide.

13. The method for forming a semiconductor structure as described in claim 1, characterized in that, The etching process for the first initial mask structure includes: dry etching process.

14. The method for forming a semiconductor structure as described in claim 1, characterized in that, The process of etching the layer to be etched using the first mask structure, the second mask structure, and the protective layer as masks includes: a plasma dry etching process.

15. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the layer to be etched includes: semiconductor material; the semiconductor material includes: silicon or silicon germanium.

16. The method for forming a semiconductor structure as described in claim 15, characterized in that, The first device structure and the second device structure each include a fin.

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