Methods for forming semiconductor structures

By optimizing the width deviation of the mask structure using advanced process control technology during the semiconductor structure formation process, and combining the use of sacrificial and protective layers, the problems of low wafer production yield and reliability have been solved, resulting in higher production efficiency and product quality.

CN116564807BActive Publication Date: 2026-05-26SEMICON MFG INT (SHANGHAI) CORP
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Patent Information

Application Number
CN202210113709.7
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2022-01-30
Publication Date
2026-05-26
Estimated Expiration
2042-01-30

AI Technical Summary

Technical Problem

Current technologies suffer from low wafer production yield and reliability. Existing advanced process control technologies cannot effectively eliminate the drift of average results caused by fluctuations in process parameters and performance indicators between different wafers.

Method used

The method of optimizing the formation of semiconductor structures by using advanced process control technology involves forming a sacrificial layer and a protective layer on a mask structure, and using algorithm optimization and thickness compensation to ensure the consistency of width deviation of the patterned structure. This eliminates the need for an additional step of forming a sacrificial layer and enables precise elimination of width deviation for various types of patterns.

Benefits of technology

This improved wafer production yield and reliability, ensured the accuracy of subsequent pattern transfer, reduced process steps, and enhanced production efficiency and product quality.

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Abstract

A method for forming a semiconductor structure includes: providing a substrate, the substrate including a base and a layer to be etched, the substrate including a first region and a second region; forming a plurality of first initial mask structures on the first region, and forming a plurality of second mask structures on the second region, the initial first mask structures having a first width deviation dimension, and the second mask structures having a second width deviation dimension; forming a first sacrificial layer on the layer to be etched and the second mask structures; and etching the first initial mask structures to form a first mask structure based on a first advanced process control technology, the first mask structure having a second width dimension and a third width deviation dimension, wherein the third width deviation dimension is equal to the second width deviation dimension. By using the first advanced process control technology for algorithm optimization, the third width deviation dimension is made equal to the second width deviation dimension, eliminating the process step of forming an additional sacrificial layer and then covering the first mask structure.
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