A linear voltage regulator

Abstract

The application relates to the field of integrated circuit design, and discloses a linear voltage regulator, which comprises a soft start module for outputting an adjusting signal; an error amplifier module connected with the soft start module and used for adjusting an output voltage of the linear voltage regulator according to the adjusting signal; and a logic control module connected with the soft start module and the error amplifier module respectively and used for controlling the state of the soft start module according to the output voltage of the linear voltage regulator; wherein when the adjusting signal is a gradually rising level signal, the output voltage of the linear voltage regulator gradually rises, and when the output voltage of the linear voltage regulator is higher than a first reference voltage, the logic control module controls the soft start module to stop working, and the output voltage of the linear voltage regulator follows a second reference voltage. The linear voltage regulator in the application has a simple structure, can ensure that the linear voltage regulator can successfully complete starting, and can realize step-by-step adjustment of the output voltage in the initial starting stage of the linear voltage regulator, thereby inhibiting the generation of inrush current.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit design, and in particular to a linear voltage regulator. BACKGROUND

[0002] With the wide application of handheld devices and portable electronic products, the market demand for power management chips is rising, and LDO (Low Dropout Regulator) is widely used due to its high efficiency, low output voltage noise, and small voltage ripple. Specifically, LDO is mainly used to use the voltage difference to ground to make the power tube in its internal saturated conduction state, so as to output stable load voltage to stabilize the driving of external load.

[0003] However, when starting LDO to drive external load, since the output voltage of the traditional LDO is 0V before starting in the power-on process, there is no charge on the output capacitor, so after the circuit is turned on instantaneously, a large inrush current will be generated when the power tube charges the capacitor, which may cause the linear voltage regulator to generate a transient overvoltage impact exceeding the normal working voltage of the external load, causing chip damage, and even destroying the circuit system. SUMMARY

[0004] To solve the problem that the linear voltage regulator in the prior art may generate a transient overvoltage impact exceeding the normal working voltage of the external load, causing chip damage, and even destroying the circuit system, the embodiments of the present application provide a linear voltage regulator which can reduce the generation of inrush current.

[0005] The embodiments of the present application provide a linear voltage regulator, comprising:

[0006] a soft start module for outputting an adjustment signal;

[0007] an error amplifier module connected with the soft start module, for adjusting the output voltage of the linear voltage regulator according to the adjustment signal;

[0008] a logic control module connected with the soft start module and the error amplifier module respectively, for controlling the state of the soft start module according to the output voltage of the linear voltage regulator;

[0009] When the adjustment signal is a gradually rising level signal, the output voltage of the linear voltage regulator gradually rises, and when the output voltage of the linear voltage regulator is higher than the first reference voltage, the logic control module controls the soft start module to stop working, and the output voltage of the linear voltage regulator follows the second reference voltage.

[0010] Specifically, the soft start module is configured to output the regulation signal to make the output voltage of the linear regulator slowly increase in an initial start phase of the linear regulator (i.e. when the output voltage of the linear regulator is less than or equal to the first reference voltage), so as to reduce the inrush current and the influence on the input power supply. The logic control module is configured to detect the output voltage and compare the output voltage with the first reference voltage, so as to determine whether the start is completed, and output the control signal to close the soft start function of the soft start module when the start is completed. Further, the error amplifier module is configured to receive the second reference voltage, and the output voltage of the linear regulator is stabilized at the second reference voltage when the soft start function of the soft start module is closed.

[0011] In a possible implementation of the first aspect, the soft start module is further configured to adjust a ramping speed of the output voltage of the linear regulator.

[0012] In a possible implementation of the first aspect, the soft start module comprises an adjusting unit connected to the error amplifier module, the adjusting unit being configured to adjust the ramping speed of the output voltage of the linear regulator, and the adjusting unit comprises:

[0013] a first capacitor having one end configured to receive the output voltage of the linear regulator and the other end connected to the first node;

[0014] a second NMOS transistor having its drain and gate interconnected and connected to the first node through a second resistor, and its source grounded.

[0015] Since the output voltage of the linear regulator gradually increases, the first capacitor can inject a current to the first node, and the current I at the first node and the output voltage Vout of the linear regulator satisfy where C1 is a capacitance value of the first capacitor, and in the embodiment, the current at the first node is also equal to a current flowing through the second NMOS transistor and the second resistor, so that the ramping speed of the output voltage of the linear regulator can be adjusted by adjusting the sizes or resistance values (capacitance values) of the second NMOS transistor, the first capacitor and the second resistor.

[0016] In a possible implementation of the first aspect, the adjusting unit further comprises a third NMOS transistor having its gate configured to receive a bias voltage, its drain connected to the first node, and its source grounded.

[0017] Specifically, in the embodiment, the current at the first node is equal to a sum of currents flowing through the third NMOS transistor and the second NMOS transistor, so that the ramping speed of the output voltage of the linear regulator can be adjusted by adjusting the sizes or resistance values (capacitance values) of the second NMOS transistor, the third NMOS transistor, the first capacitor and the second resistor.

[0018] In a possible implementation of the first aspect, the adjusting unit further includes a second capacitor, one end of which is connected to the first node and the other end of which is grounded.

[0019] The second capacitor can further enhance the stability of the current at the first node.

[0020] In a possible implementation of the first aspect, the soft-start module is further configured to receive an external enable signal and output the adjustment signal according to the external enable signal.

[0021] Specifically, the soft-start module can be configured to receive the external enable signal and output the adjustment signal according to the external enable signal, wherein when the external enable signal is a low-level signal, the adjustment signal is a low-level signal, and when the external enable signal is a high-level signal, the adjustment signal is a gradually rising voltage signal.

[0022] In a possible implementation of the first aspect, the soft-start module includes:

[0023] an output unit connected to the second node and configured to output the adjustment signal according to the voltage of the second node;

[0024] a bias unit configured to provide a bias current;

[0025] a pull-up unit connected to the second node and the bias unit respectively and configured to receive the external enable signal, and when the external enable signal is a high-level signal, the pull-up unit performs a voltage boosting process on the voltage of the second node to make the adjustment signal a gradually rising voltage signal;

[0026] a soft-start control unit connected to the logic control module, and the logic control module controls the soft-start control unit to pull up the voltage of the second node to a first preset voltage value to make the output unit stop outputting the adjustment signal.

[0027] Specifically, the output unit stopping outputting the adjustment signal means that the voltage of the second node is pulled up to the first preset voltage value to make the fifth PMOS transistor turn off, that is, at this time, the adjustment signal is no longer controlled by the soft-start module but by the internal control of the error amplifier module, at this time, the soft-start function of the soft-start module is closed, and the soft-start module stops working. Further, the first preset value can be the power supply voltage.

[0028] In a possible implementation of the first aspect, the pull-up unit includes a first inverter, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, and a first NMOS transistor.

[0029] The input end of the first inverter is configured to receive an external enable signal, the output end of the first inverter is connected to the gate of the first PMOS, the source of the first PMOS is connected to the first current source, the drain of the first PMOS and the gate of the first NMOS are interconnected and connected to the bias unit, the drain and the gate of the second PMOS and the gate of the third PMOS are interconnected and connected to the drain of the first NMOS, the source of the second PMOS and the source of the third PMOS are connected to the power supply end, the drain of the third PMOS is connected to the second node, and the source of the first NMOS is connected to the bias unit.

[0030] Specifically, when the external enable signal is a high-level signal, the first PMOS to the third PMOS and the first NMOS are all turned on, so that the second node is turned on with the power supply end to gradually pull up the voltage of the second node, thereby making the output voltage of the linear regulator climb.

[0031] In a possible implementation of the first aspect, the soft start module further includes:

[0032] The adjustment unit is connected to the error amplification module and is configured to adjust the climbing speed of the output voltage of the linear regulator.

[0033] In a possible implementation of the first aspect, the adjustment unit includes:

[0034] The first capacitor has one end connected to the error amplification module and is configured to receive the output voltage of the linear regulator;

[0035] The second NMOS has its drain and gate interconnected and connected to the other end of the first capacitor through the second resistor, and has its source grounded.

[0036] In a possible implementation of the first aspect, the adjustment unit further includes a third NMOS having its gate configured to receive a bias voltage, its drain connected to the other end of the first capacitor, and its source grounded.

[0037] In a possible implementation of the first aspect, the adjustment unit further includes a second capacitor having one end connected to the first node and the other end grounded.

[0038] In a possible implementation of the first aspect, the linear regulator further includes a fourth NMOS having its gate connected to the adjustment unit and the pull-up unit at the first node respectively, its drain connected to the second node, and its source grounded.

[0039] The adjustment unit is further configured to adjust the conduction state of the fourth NMOS according to the voltage of the first node to enable the pull-up unit to perform voltage boosting on the voltage of the second node.

[0040] Specifically, with the injection of the current at the first node, the voltage at the first node gradually decreases, so that the conduction degree of the fourth NMOS pipe decreases, thereby gradually lifting the voltage at the second node.

[0041] In a possible implementation of the first aspect, the soft start module further includes:

[0042] The pull-down unit is connected to the first node and configured to receive an external enable signal, and when the external enable signal is a low-level signal, the pull-down unit pulls down the voltage at the second node to a second preset voltage value by pulling up the voltage at the first node to turn on the fourth NMOS pipe.

[0043] Specifically, the second preset voltage value can be 0, and at this time, the adjustment signal voltage outputs a low-level signal.

[0044] In a possible implementation of the first aspect, the pull-down unit includes a fourth PMOS pipe, a gate of the fourth PMOS pipe configured to receive the external enable signal, a source of the fourth PMOS pipe connected to the second current source, and a drain of the fourth PMOS pipe connected to the first node.

[0045] Specifically, when the external enable signal is a low-level signal, the fourth PMOS pipe is turned on, the voltage at the first node is pulled up to a high level, so that the fourth NMOS pipe is turned on, thereby pulling down the voltage at the second node to 0.

[0046] In a possible implementation of the first aspect, the soft start control unit includes a fifth NMOS pipe, a gate of the fifth NMOS pipe connected to the logic control module, a drain of the fifth NMOS pipe connected to the gate of the fourth NMOS pipe, and a source of the fifth NMOS pipe grounded.

[0047] Specifically, when the output voltage of the linear voltage regulator is higher than the first reference voltage, the logic control module outputs a high-level signal, so that the fifth NMOS pipe is turned on, thereby pulling down the voltage at the first node to 0, making the fourth NMOS pipe off, and in turn making the voltage at the second node pull up to the first preset value, so that the output module stops outputting the adjustment signal.

[0048] In a possible implementation of the first aspect, the output unit includes a fifth PMOS pipe, a gate of the fifth PMOS pipe connected to the second node, a source of the fifth PMOS pipe configured to output the adjustment signal, and a drain of the fifth PMOS pipe grounded.

[0049] In a possible implementation of the first aspect, the error amplification module includes:

[0050] a power pipe, a drain of the power pipe configured to output an output voltage of the linear voltage regulator, a gate of the power pipe connected to the third node, and a source of the power pipe connected to a power supply end;

[0051] a current mirror load unit,

[0052] The climbing unit is connected with the soft start module, the current mirror load unit and the third node respectively, and is configured to receive the adjusting signal and output a voltage to the third node according to the adjusting signal to adjust the conduction state of the power tube, so that the output voltage of the linear regulator gradually increases.

[0053] The input pair is connected with the current mirror load unit, and is configured to receive the second reference voltage and the output voltage of the linear regulator to stabilize the output voltage of the linear regulator at the second reference voltage when the soft start module stops working.

[0054] The bias current unit is connected with the power tube, the climbing unit and the input pair respectively, and is configured to provide a bias current.

[0055] In a possible implementation of the first aspect, the linear regulator further comprises a switch unit configured to receive an external enable signal and control the opening and closing of the power tube according to the external enable signal.

[0056] Specifically, when the external enable signal is a low-level signal, the power tube is closed, and at this time, the output voltage of the linear regulator is 0; when the external enable signal is a high-level signal, the power tube is opened, and at this time, the output voltage of the linear regulator gradually tends to and stabilizes at the second reference voltage.

[0057] In a possible implementation of the first aspect, the switch unit comprises a sixth PMOS tube, a gate of the sixth PMOS tube is configured to receive the external enable signal, a source of the sixth PMOS tube is connected with the power supply end, and a drain of the sixth PMOS tube is connected with the third node.

[0058] In a possible implementation of the first aspect, the climbing unit comprises a seventh PMOS tube, a gate of the seventh PMOS tube is connected with the soft start module and is configured to receive the adjusting signal, a source of the seventh PMOS tube is connected with the power supply end, and a drain of the seventh PMOS tube is connected with the third node.

[0059] Specifically, the power tube is a PMOS tube, a drain of the power tube is configured to output the output voltage of the linear regulator, during the process that the soft start module outputs the gradually increasing adjusting signal, the gate voltage of the seventh PMOS tube gradually increases, so that the conduction state of the seventh PMOS tube gradually decreases, and then the voltage at the third node gradually decreases, that is, the gate voltage of the power tube gradually decreases, the power tube gradually conducts, and thus the output voltage gradually increases.

[0060] In a possible implementation of the first aspect, the logic control module comprises a comparator connected with the error amplification module and the soft start module respectively, two input ends of the comparator are configured to receive the output voltage of the linear regulator and the first reference voltage respectively, and when the output voltage of the linear regulator is higher than the first reference voltage, the logic control module outputs a high-level control signal.

[0061] In a possible implementation of the first aspect, the logic control module further includes a second inverter and a third inverter connected in sequence at the output of the comparator.

[0062] By setting two inverters, the signal output by the comparator is rectified without changing the level type (i.e., high level and low level) of the comparator output signal, so as to improve the stability of the signal. BRIEF DESCRIPTION OF DRAWINGS

[0063] Figure 1 According to some embodiments of the present application, a structural block diagram of a linear voltage regulator is shown;

[0064] Figure 2 According to some embodiments of the present application, a circuit schematic diagram of a soft start module is shown;

[0065] Figure 3 According to some embodiments of the present application, a circuit schematic diagram of an error amplification module is shown;

[0066] Figure 4 According to some embodiments of the present application, a circuit schematic diagram of a logic control module is shown. DETAILED DESCRIPTION

[0067] The present application will be further described by way of specific embodiments and drawings. It can be understood that the illustrative embodiments of the present disclosure include but are not limited to linear voltage regulators, and the specific embodiments described herein are merely intended to explain the present application, but not to limit the present application. In addition, for the convenience of description, only part of the structures or processes related to the present application are shown in the drawings, but not all.

[0068] The specific embodiments of the present application are described below by way of specific embodiments, and those skilled in the art can easily understand other advantages and effects of the present application from the disclosure. Although the description of the present application will be introduced in combination with the preferred embodiments, this does not mean that the features of the present application are limited to the embodiments. On the contrary, the purpose of introducing the application in combination with the embodiments is to cover other options or modifications that can be extended based on the claims of the present application. In order to provide a deep understanding of the present application, many specific details will be included in the following description. The present application can also be implemented without using these details. In addition, in order to avoid confusion or obscure the focus of the present application, some specific details will be omitted in the description. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other without conflict.

[0069] The linear voltage regulator according to the embodiments of the present application comprises a soft start module for outputting an adjustment signal STG, an error amplifier module connected with the soft start module and used for adjusting an output voltage VOUT of the linear voltage regulator according to the adjustment signal STG, and a logic control module connected with the soft start module and the error amplifier module respectively and used for controlling a state of the soft start module according to the output voltage VOUT of the linear voltage regulator. When the adjustment signal STG is a gradually rising level signal, the output voltage VOUT of the linear voltage regulator gradually rises, and when the output voltage VOUT of the linear voltage regulator is higher than a first reference voltage VREF1, the logic control module controls the soft start module to stop working, and thereafter the output voltage of the linear voltage regulator follows a second reference voltage.

[0070] In some embodiments of the present application, the soft start module comprises an adjustment unit connected with the error amplifier module, and the adjustment unit is used for adjusting a rising speed of the output voltage VOUT of the linear voltage regulator.

[0071] For example, the adjustment unit comprises a first capacitor and a second NMOS transistor. Specifically, one end of the first capacitor is used for receiving the output voltage VOUT of the linear voltage regulator, and the other end of the first capacitor is connected to a first node; the drain and the gate of the second NMOS transistor are interconnected and connected to the first node through a second resistor, and the source of the second NMOS transistor is grounded.

[0072] Since the output voltage VOUT of the linear voltage regulator gradually rises, the first node can be injected with a current through the first capacitor C1, and the current I at the first node and the output voltage VOUT of the linear voltage regulator satisfy wherein C1 is the capacitance value of the first capacitor, and in the embodiment, the current at the first node is also equal to the current flowing through the second NMOS transistor, and therefore, the rising speed of the output voltage VOUT of the linear voltage regulator can be adjusted by adjusting the sizes (resistance / capacitance) of the second NMOS transistor, the first capacitor and the second resistor.

[0073] In some embodiments of the present application, the soft start module further comprises:

[0074] an output unit connected with the second node and used for outputting the adjustment signal STG according to the voltage of the second node;

[0075] a bias unit used for providing a bias current;

[0076] a pull-up unit connected with the second node and the bias unit respectively and used for receiving an external enable signal EN, and when the external enable signal EN is a high-level signal, the pull-up unit performs a voltage boosting process on the voltage of the second node to make the adjustment signal STG a gradually rising level signal;

[0077] The soft start control unit is connected with the logic control module. The logic control module controls the soft start control unit to pull up the voltage of the second node to the first preset voltage value to stop the output unit from outputting the adjustment signal STG.

[0078] In the present application, the soft start module outputs the adjustment signal STG to make the output voltage VOUT of the linear regulator slowly rise in the initial start phase of the linear regulator (i.e. when the output voltage VOUT of the linear regulator is less than or equal to the first reference voltage VREF1), thereby reducing the inrush current and the influence on the input power supply. And the logic control module detects the output voltage VOUT and compares it with the first reference voltage VREF1 to determine whether the start is completed, and outputs the control signal to close the soft start function of the soft start module when the start is completed. Moreover, the linear regulator in the present application has the characteristics of simple structure, which can ensure that the linear regulator can successfully complete the start and gradually adjust the output voltage VOUT in the initial start phase of the linear regulator.

[0079] Specifically, Figure 1 According to some embodiments of the present application, a structural block diagram of a linear regulator is shown.

[0080] As Figure 1 shown, the linear regulator comprises a soft start module 1, an error amplification module 2 and a logic control module 3. The soft start module 1 is used to output an adjustment signal STG;

[0081] The error amplification module 2 is connected with the soft start module 1, used to receive the adjustment signal STG and the second reference voltage VREF2, and adjust the output voltage VOUT of the linear regulator according to the adjustment signal STG;

[0082] The logic control module 3 is connected with the soft start module 1 and the error amplification module 2 respectively, used to control the state of the soft start module 1 according to the output voltage VOUT of the linear regulator;

[0083] When the adjustment signal STG is a gradually rising level signal, the output voltage VOUT of the linear regulator gradually rises, and when the output voltage VOUT of the linear regulator is higher than the first reference voltage VREF1, the logic control module 3 controls the soft start module 1 to stop working, and thereafter the output voltage VOUT of the linear regulator follows the second reference voltage VREF2.

[0084] For example, the soft start module 1 is also used to receive an external enable signal EN and output the adjustment signal STG according to the external enable signal EN. As Figure 2 shown, the soft start module 1 comprises an output unit 16, a bias unit 12, a pull-up unit 11, a pull-down unit 14, a soft start control unit 15 and an adjustment unit 13.

[0085] Specifically, the bias unit 12 is configured to provide a bias current for the circuit, the pull-up unit 11 is connected to the second node b and the bias unit 12 respectively, and configured to receive the external enable signal EN, and when the external enable signal EN is a high level signal, the pull-up unit 11 boosts the voltage of the second node b to make the adjustment signal STG present as a gradually boosted level signal; the pull-down unit 14 is connected to the second node b, and configured to receive the external enable signal EN, and when the external enable signal EN is a low level signal, the pull-down unit 14 pulls down the voltage of the second node b to the second preset voltage value to make the adjustment signal STG present as a low level signal; the output unit 16 is connected to the second node b, and configured to output the adjustment signal STG according to the voltage of the second node b; the adjustment unit 13 is connected to the error amplifier module 2, and configured to adjust the ramping speed of the output voltage VOUT of the linear voltage regulator; the soft start control unit 15 is connected to the logic control module 3, and the logic control module 3 controls the soft start control unit 15 to pull up the voltage of the second node b to the first preset voltage value to make the output unit 16 stop outputting the adjustment signal STG. Specifically, when the output voltage VOUT of the linear voltage regulator is higher than the first reference voltage VREF1, the logic control module 3 sends a high level signal to the soft start control unit 15 to make the output unit 16 stop outputting, at this time the adjustment signal STG is completely adjusted by the error amplifier module 2 internally, that is, the soft start is completed, and the logic control module 3 controls the soft start function of the soft start module 1 to be closed.

[0086] Further, the soft start module 1 further comprises a fourth NMOS transistor MN4, the gate of which is connected to the adjustment unit 13 and the pull-up unit 11 at the first node a respectively, the drain is connected to the second node b, and the source is grounded.

[0087] Specifically, the adjustment unit 13 is further configured to adjust the conduction state of the fourth NMOS transistor MN4 according to the voltage of the first node a to make the pull-up unit 11 boost the voltage of the second node b. The pull-down unit 14 is further connected to the fourth NMOS transistor MN4, and when the external enable signal EN is a low level signal, the pull-down unit 14 makes the fourth NMOS transistor MN4 conductive to pull down the voltage of the second node b to the second preset voltage value (such as zero level).

[0088] Specifically, continuing to refer to Figure 2The pull-up unit 11 comprises a first inverter INV1, a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3 and a first NMOS transistor MN1; the adjusting unit 13 comprises a first capacitor C1, a second NMOS transistor MN2, a third NMOS transistor MN3, a second resistor R2 and a second capacitor C2; the pull-down unit 14 comprises a fourth PMOS transistor MP4; the soft start control unit 15 comprises a fifth NMOS transistor MN5; the output unit 16 comprises a fifth PMOS transistor MP5; the bias unit 12 comprises a sixth NMOS transistor MN6, a seventh NMOS transistor MN7 and a first resistor R1.

[0089] In some other embodiments of the present application, an NMOS transistor can also be used instead, with the gate of the NMOS transistor used for receiving the external enable signal EN, the source connected to the bias unit 12 and the drain connected to the first current source II, which can also function in the same way in combination with the first inverter INV1 and the first PMOS transistor MP1.

[0090] Specifically, the input of the first inverter INV1 is used for receiving the external enable signal EN, the output of the first inverter INV1 is connected to the gate of the first PMOS transistor MP1, and the first inverter INV1 is used for inverting the external enable signal EN and outputting it to the first PMOS transistor MP1. The source of the first PMOS transistor MP1 is connected to the first current source II, the drain of the first PMOS transistor MP1 and the gate of the first NMOS transistor MN1 are interconnected and connected to one end of the first resistor R1 in the bias unit 12, the drain and the gate of the second PMOS transistor MP2 and the gate of the third PMOS transistor MP3 are interconnected and connected to the drain of the first NMOS transistor MN1, the source of the second PMOS transistor MP2 and the source of the third PMOS transistor MP3 are connected to the power supply end VIN, the drain of the third PMOS transistor MP3 is connected to the second node b, and the source of the first NMOS transistor MN1 is connected to the drain of the seventh NMOS transistor MN7 in the bias unit 12; the drain and the gate of the sixth NMOS transistor MN6 and the gate of the seventh NMOS transistor MN7 are interconnected and connected to the other end of the first resistor R1, and the sources of the sixth NMOS transistor MN6 and the seventh NMOS transistor MN7 are grounded. Specifically, the sixth NMOS transistor MN6 and the seventh NMOS transistor MN7 can be used to generate a bias voltage VBN, which is led out from the gate connection end of the sixth NMOS transistor MN6 and the seventh NMOS transistor MN7. Specifically, the bias voltage VBN can turn on the third NMOS transistor MN3 and the eighth NMOS transistor MN8, the ninth NMOS transistor MN9 and the tenth NMOS transistor MN10 in the error amplification module 2.

[0091] The gate of the fourth PMOS transistor MP4 is configured to receive an external enable signal EN, the source is connected to the second current source I2, and the drain is connected to the first node a, so as to pull up the voltage of the first node a to a high voltage level when the external enable signal EN is a low voltage signal. Alternatively, an inverter and an NMOS transistor can also be used as another alternative to the fourth PMOS transistor MP4. In this embodiment, the input of the inverter is configured to receive the external enable signal EN, the output is connected to the gate of the NMOS transistor, the source of the NMOS transistor is connected to the first node a, and the drain is connected to the second current source I2.

[0092] One end of the first capacitor C1 is connected to the error amplifier module 2 and configured to receive the output voltage VOUT of the linear voltage regulator, and the other end is connected to the first node a. When the output voltage VOUT of the linear voltage regulator rises, the output voltage VOUT charges the first capacitor C1 to generate a current to pull up the voltage of the first node a. The gate of the third NMOS transistor MN3 is connected to the bias voltage VBN, the drain is connected to the first node a, and the source is grounded. One end of the second resistor R2 is connected to the first node a, the gate and the drain of the second NMOS transistor MN2 are interconnected and connected to the other end of the second resistor R2, and the source of the second NMOS transistor MN2 is grounded. Specifically, the third NMOS transistor MN3 and the second NMOS transistor MN2 are configured to share the current injected by the first capacitor C1 to the first node a. Alternatively, a second capacitor C2 is also connected in parallel between one end of the second resistor R2 and the source of the second NMOS transistor MN2, so as to further stabilize the current injected by the first capacitor C1 to the first node a.

[0093] The gate of the fourth NMOS transistor MN4 is connected to the first node a, the drain is connected to the second node b, and the source is grounded. The gate of the fifth PMOS transistor MP5 is connected to the second node b, the source is configured to output the adjustment signal STG, and the drain is grounded. When the voltage at the first node a is pulled up to a high level, the fourth NMOS transistor MN4 is fully open to pull the voltage at the second node b to zero level, and the fifth PMOS transistor MP5 is open.

[0094] Specifically, the fifth NMOS transistor MN5 is also included, the gate is connected to the logic control module 3 and configured to receive the control signal output by the logic control module 3, the source is grounded, and the drain is connected to the gate of the fourth NMOS transistor MN4. When the logic control module 3 sends a control signal (which is a high voltage signal), the fifth NMOS transistor MN5 is open to pull down the voltage at the gate of the fourth NMOS transistor MN4 to zero level, causing the fourth NMOS transistor MN4 to be closed, thereby pulling up the voltage at the second node b to the power supply voltage, so that the fifth PMOS transistor MP5 is closed. At this time, the soft start module 1 closes the soft start function, and the adjustment signal STG will be completely controlled by the error amplifier module 2.

[0095] Specifically, with reference toFigure 2 The specific circuit diagram of the soft start module 1 is shown, and the running flow of the soft start function is simply explained.

[0096] When the circuit is just started, the external enable signal EN is 0, at this time the first PMOS tube MP1, the third PMOS tube MP3 and the first NMOS tube MN1 are disconnected, and the fourth PMOS tube MP4 is turned on, so that the current of the second current source I2 flows to the second resistance R2 and the second NMOS tube MN2, and the voltage Va at the first node a is Va=I2R2+V GS_MN5 , at this time the voltage Va at the first node a is pulled up to a high voltage, which is enough to make the fourth NMOS tube MN4 conduct. And because the third PMOS tube MP3 is closed at this time, the voltage Vb at the second node b is pulled down to zero potential, so that the fifth PMOG tube is turned on, at this time the voltage value of the adjustment signal STG output by the source of the fifth PMOS tube MP5 is V STG =V b +V MP_5 =V MP_5 .

[0097] And when the high-level external enable signal EN comes, the first PMOS tube MP1 to the third PMOS tube MP3 of the soft start module 1, as well as the first NMOS tube MN1, the sixth NMOS tube MN6 and the seventh NMOS tube MN7 are turned on, and the fourth PMOS tube MP4 is turned off. Due to the pull-down effect of the third NMOS tube MN3 and the second NMOS tube MN2 and the pull-up effect of the third PMOS tube MP3, the voltage at the first node a gradually decreases, the voltage at the second node b gradually rises, and the voltage value V STG =V b +V GS_MP5Also gradually rises, namely, at this time, the adjustment signal STG is in the form of a gradually rising voltage signal, at this time, the output voltage VOUT of the error amplifier 2 gradually rises, the output voltage VOUT charges the first capacitor C1 to form a current, and as time goes on, the voltage at the first node a becomes lower and lower, causing the fourth NMOS transistor MN4 to gradually reduce the conduction state, and the current passing through becomes smaller and smaller, which causes the voltage at the second node b to become higher and higher. It should be noted that, in this process, although the voltage at the first node a gradually decreases, the degree of decrease of the voltage at the first node a is not sufficient to completely close the fourth NMOS transistor MN4. Similarly, although the voltage at the second node b also gradually increases in this process, the degree of increase is also not sufficient to completely close the fifth PMOS transistor MP5. Thus, the voltage value of the adjustment signal STG output by the fifth PMOS transistor MP5 is always increasing in this process, until the voltage value of the output voltage VOUT of the linear voltage stabilizer output by the error amplifier 2 is higher than the first reference voltage VREF1, the logic control module 3 outputs a high-level control signal to make the fifth NMOS transistor MN5 conduct, so as to pull down the voltage at the gate of the fourth NMOS transistor MN4 (i.e., the first node a) to zero level, so as to completely close the fourth NMOS transistor MN4, and the second node b is pulled up to the power supply voltage under the pull-up action of the third PMOS transistor MP3, so as to completely close the fifth PMOS transistor MP5, at this time, the adjustment signal STG is no longer controlled by the fifth PMOS transistor MP5, namely, the soft start function of the soft start module 1 is closed, and the adjustment signal STG is completely determined by the internal of the error amplifier 2.

[0098] In addition, in the output voltage VOUT rising stage, the rising speed can be adjusted by adjusting the sizes (resistance / capacitance) of the third NMOS transistor MN3, the second NMOS transistor MN2, the first capacitor C1 and the second resistor R2. Specifically as follows.

[0099] When the output voltage VOUT starts to rise, VOUT injects a current I to the first node a through the first capacitor C1, which satisfies:

[0100]

[0101] C1 is the capacitance value of the first capacitor C1, and Vout is the value of the output voltage VOUT.

[0102] In order to ensure the stability of the circuit, the third NMOS transistor MN3 and the second NMOS transistor MN2 are set, so that the current at the first node a is equal to the sum of the currents flowing through the third NMOS transistor MN3 and the second NMOS transistor MN2, namely, I = I MN4 +I MN5 Therefore, the rising slope (i.e., the rising speed) of the output voltage VOUT is:

[0103] The rising slope of the output voltage VOUT is basically a constant value, and the rising slope of the output voltage VOUT can be adjusted by adjusting the sizes (resistance / capacitance) of the second NMOS transistor MN2, the third NMOS transistor MN3, the first capacitor C1 and the second resistor R2.

[0104] Reference Figure 3 As shown, the error amplification module 2 includes a power transistor MP10, a current mirror load unit 21, a climbing unit 23, an input pair transistor 22, a bias current unit 25 and a switch unit 24.

[0105] Specifically, the drain of the power transistor MP10 is used to output the output voltage VOUT of the linear regulator, the gate is connected to the third node c, and the source is connected to the power supply end VIN; the current mirror load unit 21 includes the eighth PMOS transistor MP8 and the ninth PMOS transistor MP9 which are interconnected at the gate, and the input pair transistor 22 includes the eleventh NMOS transistor MN11 and the twelfth NMOS transistor MN12 which are interconnected at the source. Specifically, the gate of the eighth PMOS transistor MP8 is interconnected with its drain and connected to the drain of the eleventh NMOS transistor MN11 in the input pair transistor 22, the drain of the ninth PMOS transistor MP9 is connected to the drain of the twelfth NMOS transistor MN12 in the input pair transistor 22, and the sources of the eighth PMOS transistor MP8 and the ninth PMOS transistor MP9 are both connected to the power supply end VIN, and the current mirror load unit 21 is used to provide driving current to the input pair transistor 22 and other structures. The gate of the eleventh NMOS transistor MN11 is used to receive the second reference voltage VREF2, the source is connected to the drain of the eighth NMOS transistor MN8 in the bias current unit 25, and the gate of the twelfth NMOS transistor MN12 is used to receive the output voltage VOUT of the linear regulator. The input pair transistor 22 can realize that the output voltage VOUT of the linear regulator is stabilized at the second reference voltage VREF2 when the soft start module 1 stops working. Further, the gate of the eighth NMOS transistor MN8 is used to connect the bias voltage VBN in the soft start module 1, and the source is grounded, which is used to provide bias current for it.

[0106] The soft start module 1, the current mirror load unit 21 and the third node c are connected with the climbing unit 23 respectively, which is used to receive the adjusting signal STG and output the voltage VOUT to the third node c according to the adjusting signal STG to adjust the conduction state of the power tube MP10, so that the output voltage VOUT of the linear regulator gradually climbs. Specifically, the climbing unit 23 includes a seventh PMOS tube MP7, the gate of which is connected with the soft start module 1 to receive the adjusting signal STG, the source of which is connected with the power supply end VIN, and the drain of which is connected with the third node c. When the voltage of the adjusting signal STG gradually rises, the conduction state of the seventh PMOS tube MP7 gradually decreases, so that the voltage of the third node c gradually decreases under the pull-down action of the ninth NMOS tube MN9, thereby gradually increasing the conduction state of the power tube MP10, so that the output voltage VOUT of the linear regulator gradually climbs. When the output voltage VOUT exceeds the first reference voltage VREF1, the soft start function of the soft start module 1 is turned off, at this time, the adjusting signal STG is determined by the error amplifier module 2 internally, and through the clamping function of the error amplifier module 2 (i.e. under the action of the input pair tube 22), the output voltage VOUT of the linear regulator is stabilized at the second reference voltage VREF2. Specifically, the first reference voltage VREF1 is slightly less than the second reference voltage VREF2.

[0107] Further, the bias current unit 25 is connected with the power tube MP10, the climbing unit 23 and the input pair tube 22 respectively, which is used to provide a bias current. Specifically, the bias current unit 25 includes three NMOS tubes, the sources of which are all connected with the ground, and the gates of which are all connected with the bias voltage VBN output by the soft start module 1. Specifically, the three NMOS tubes are the eighth NMOS tube MN8, the ninth NMOS tube MN9 and the tenth NMOS tube MN10, wherein the drain of the eighth NMOS is connected with the source of the NMOS tube in the input pair tube 22, the drain of the ninth NMOS tube MN9 is connected with the drain of the seventh PMOS tube MP7, and the drain of the tenth NMOS tube MN10 is connected with the drain of the power tube MP10.

[0108] Further, the error amplifier module 2 further includes a switching unit 24, which is used to receive an external enable signal EN and control the on-off of the power tube MP10 according to the external enable signal EN. The switching unit 24 includes a sixth PMOS tube MP6, the gate of which is used to receive the external enable signal EN, the source of which is connected with the power supply end VIN, and the drain of which is connected with the third node c. When the external enable signal EN is a low-level signal, the sixth PMOS tube MP6 is turned on, so that the voltage at the third node c is pulled up to the power supply voltage, thereby turning off the power tube MP10, at this time, the output voltage VOUT of the linear regulator is 0.

[0109] The linear regulator of this application increases the range of device options when fabricating a linear regulator. Furthermore, using two NMOS transistors as the input pair 22 in the operational amplifier module 2 can also reduce the size of the linear regulator and improve its performance.

[0110] The soft-start module 1 adjusts the output signal to ensure that the input transistors 22 in the error amplifier module 2 can be driven during the initial startup phase, preventing the linear regulator from becoming unbalanced during the initial startup phase. Furthermore, the output voltage gradually increases from its initial value until it reaches the first reference voltage, ensuring a gradual increase in the output voltage VOUT.

[0111] Specifically, refer to Figure 4 The logic control module 3 includes a comparator, which is connected to the error amplifier module 2 and the soft-start module 1 respectively. The two input terminals of the comparator are used to receive the output voltage VOUT of the linear regulator and the first reference voltage VREF1 respectively. Its output terminal is connected to the gate of the sixth NMOS transistor in the soft-start module 1. When the output voltage VOUT of the linear regulator is higher than the first reference voltage VREF1, the logic control module 3 outputs a high-level control signal to the gate of the fifth NMOS transistor MN5 to turn on the fifth NMOS transistor MN5, thereby pulling down the voltage at the first node a to zero level.

[0112] Furthermore, the logic control module 3 may also include two inverters, such as... Figure 4 As shown, the second inverter INV2 and the third inverter INV3 are connected in series at the output of the comparator to rectify the signal output by the comparator and improve the stability of the signal.

[0113] The following is based on Figures 2 to 4 Taking the circuit structure of each module shown as an example, the working process of this linear regulator will be explained in detail.

[0114] When the circuit is first started, the external enable signal EN is 0. As mentioned above, at this time, the first PMOS transistor MP1, the third PMOS transistor MP3, and the first NMOS transistor MN1 are all turned off, while the fourth PMOS transistor MP4 is turned on, so that the current from the second current source I2 flows to the second resistor R2 and the second NMOS transistor MN2. The voltage Va at the first node a is Va = I2R2 + V GS_MN5 At this time, the voltage Va at the first node a is pulled up to a high voltage, sufficient to turn on the fourth NMOS transistor MN4. And since the third PMOS transistor MP3 is off at this time, the voltage Vb at the second node b is pulled down to zero, causing the fifth PMOS transistor MP5 to turn on. At this time, the voltage value of the adjustment signal STG output from the source of the fifth PMOS transistor MP5 is V. STG =V b +V MP_5 =VMP_5 In addition, since the external enable signal EN is 0, the sixth PMOS MP6 in the error amplifier module 2 is turned on, thereby pulling up the gate voltage of the power transistor MP10 to the power supply voltage, so that the power transistor MP10 is in the off state, and the output voltage VOUT of the linear regulator is 0.

[0115] When the high-level external enable signal EN arrives, the first PMOS MP1 to the third PMOS MP3 and the first NMOS MN1, the sixth NMOS MN6 and the seventh NMOS MN7 in the soft start module 1 are turned on, and the fourth PMOS MP4 is turned off. Due to the pull-down action of the third NMOS MN3 and the second NMOS MN2 and the pull-up action of the third PMOS MP3, the voltage Va at the first node a gradually decreases, the voltage Vb at the second node b gradually increases, and the voltage value VSTG of the adjustment signal STG gradually increases, that is, the adjustment signal STG at this time is in the form of a gradually rising level signal. At this time, the output voltage VOUT of the error amplifier module 2 gradually rises, and when the output voltage VOUT rises to the first reference voltage VREF1, the logic control module 3 outputs a high-level control signal CTRL, which turns on the fifth NMOS MN5 and pulls down the voltage Va at the first node a to zero level, causing the fourth NMOS MN4 to be turned off. The voltage Vb at the second node b is lifted to the power supply voltage by the pull-up action of the third PMOS MP3, thereby turning off the fifth PMOS MP5. Therefore, the voltage of the adjustment signal STG is completely determined by the error amplifier module 2, and through the clamping function of the error amplifier module 2, the value of the output voltage VOUT is stabilized at the second reference voltage VREF2. The first reference voltage VREF1 is slightly less than the second reference voltage VREF2. STG b GS_MP5

[0116] ​​​The linear voltage stabilizer provided in the application comprises a soft start module 1, an error amplification module 2 and a logic control module 3. The soft start module 1 makes the output voltage VOUT slowly rise when the power supply is started, thereby reducing the inrush current and the influence on the input power supply; the error amplification module 2 adjusts the gate of the power tube MP10, thereby suppressing the voltage ripple and realizing the stability of the output voltage VOUT; the logic control module 3 detects the output voltage VOUT and compares it with the first reference voltage VREF1, thereby determining whether the start is completed and outputting a logic control signal. That is, the linear voltage stabilizer in the application adopts a relatively simple circuit architecture, which not only can effectively prevent the inrush current and realize the smooth rise of the output voltage VOUT, but also can guarantee the stability and reliability of the circuit. In addition, the rising slope of the output voltage VOUT of the linear voltage stabilizer can be adjusted by adjusting the sizes of the third NMOS tube MN3, the second NMOS tube MN2, the first capacitor C1 and the second resistor R2, thereby improving the flexibility of the linear voltage stabilizer.

[0117] In the drawings, some structural or methodological features can be shown in a particular arrangement and / or order. However, it should be understood that such a particular arrangement and / or order can not be required. Rather, in some embodiments, these features can be arranged in a manner different from that shown in the illustrative drawings. Additionally, inclusion of a structural or methodological feature in a particular figure does not imply that such feature is required in all embodiments, and in some embodiments, such feature can not be included or can be combined with other features.

[0118] It should be noted that each unit / module mentioned in the device embodiments of the application is a logical unit / module, and in the physical aspect, one logical unit / module can be one physical unit / module, or a part of one physical unit / module, or a combination of multiple physical units / modules, and the physical implementation of the logical unit / module itself is not the most important, and the combination of the functions implemented by the logical unit / module is the key to solving the technical problems proposed in the application. In addition, in order to highlight the innovative part of the application, the above-mentioned device embodiments of the application do not introduce units / modules that are not closely related to solving the technical problems proposed in the application, which does not mean that the above-mentioned device embodiments do not have other units / modules.

[0119] It has to be noted that, in the description of the application and in the claims, terms such as first and second, etc. are used only for distinguishing between similar elements, not necessarily describing a chronological or sequential order. Furthermore, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises a", "comprising", or "includes a", does not, without more constraints, preclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[0120] While the application has been illustrated and described in detail in the drawings and foregoing description, the same is to be considered as illustrative and not restrictive in character, it being understood that only the preferred embodiments have been shown and described and that all changes and modifications that come within the spirit of the application are desired to be protected.

Claims

1. A linear voltage regulator, characterized in that, include: Soft-start module, used to output adjustment signal; An error amplification module, connected to the soft-start module, is used to adjust the output voltage of the linear regulator according to the adjustment signal; A logic control module is connected to the soft-start module and the error amplification module respectively, and is used to control the state of the soft-start module according to the output voltage of the linear regulator; When the adjustment signal is a gradually increasing voltage level signal, the output voltage of the linear regulator gradually increases, and when the output voltage of the linear regulator is higher than the first reference voltage, the logic control module controls the soft-start module to stop working, and the output voltage of the linear regulator follows the second reference voltage. The soft-start module includes: An output unit, connected to the second node, is used to output the adjustment signal according to the voltage of the second node; A pull-up unit is connected to the second node and is used to receive an external enable signal. When the external enable signal is a high-level signal, the pull-up unit boosts the voltage of the second node so that the adjustment signal appears as a gradually increasing voltage level signal. An adjustment unit, connected to the error amplification module, is used to adjust the ramp-up rate of the output voltage of the linear regulator; The fourth NMOS transistor has its gate connected to the adjustment unit and the pull-up unit at the first node, its drain connected to the second node, and its source grounded. A pull-down unit is connected to the first node and is used to receive the external enable signal. When the external enable signal is a low-level signal, the pull-down unit pulls up the voltage at the first node to turn on the fourth NMOS transistor, thereby pulling down the voltage of the second node to a second preset voltage value.

2. The linear regulator as described in claim 1, characterized in that, The soft-start module is also used to receive an external enable signal and output the adjustment signal according to the external enable signal.

3. The linear voltage regulator as described in claim 2, characterized in that, The soft-start module also includes: A bias unit is used to provide a bias voltage, and the bias unit is connected to the pull-up unit; A soft-start control unit is connected to the logic control module. The logic control module controls the soft-start control unit to raise the voltage of the second node to a first preset voltage value so that the output unit stops outputting the adjustment signal.

4. The linear regulator as described in claim 3, characterized in that, The pull-up unit includes: a first inverter, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, and a first NMOS transistor; The input terminal of the first inverter is used to receive the external enable signal. The output terminal of the first inverter is connected to the gate of the first PMOS transistor. The source of the first PMOS transistor is connected to the first current source. The drain of the first PMOS transistor and the gate of the first NMOS transistor are interconnected and connected to the bias unit. The drain and gate of the second PMOS transistor and the gate of the third PMOS transistor are interconnected and connected to the drain of the first NMOS transistor. The source of the second PMOS transistor and the source of the third PMOS transistor are connected to the power supply terminal. The drain of the third PMOS transistor is connected to the second node. The source of the first NMOS transistor is connected to the bias unit.

5. The linear regulator as described in claim 3, characterized in that, The adjustment unit includes: The first capacitor has one end connected to the error amplification module and is used to receive the output voltage of the linear regulator. The second NMOS transistor has its drain and gate interconnected and connected to the other end of the first capacitor through a second resistor, and its source is grounded.

6. The linear regulator as described in claim 5, characterized in that, The adjustment unit also includes a third NMOS transistor, whose gate is used to receive the bias voltage, whose drain is connected to the other end of the first capacitor, and whose source is grounded.

7. The linear regulator as described in claim 1, characterized in that, The adjustment unit is also used to adjust the conduction state of the fourth NMOS transistor according to the voltage of the first node, so that the pull-up unit can boost the voltage of the second node.

8. The linear regulator as described in claim 7, characterized in that, The pull-down unit includes: a fourth PMOS transistor, whose gate is used to receive the external enable signal, whose source is connected to a second current source, and whose drain is connected to the first node.

9. The linear regulator as described in claim 6, characterized in that, The soft-start control unit includes a fifth NMOS transistor, whose gate is connected to the logic control module, whose drain is connected to the gate of the fourth NMOS transistor, and whose source is grounded.

10. The linear regulator as described in claim 1, characterized in that, The output unit includes a fifth PMOS transistor, whose gate is connected to the second node, whose source is used to output the adjustment signal, and whose drain is grounded.

11. The linear regulator as described in claim 1, characterized in that, The error amplification module includes: The power transistor has its drain used to output the output voltage of the linear regulator, its gate connected to the third node, and its source connected to the power supply terminal. Current mirror load unit; The ramp-up unit is connected to the soft-start module, the current mirror load unit, and the third node, respectively. It is used to receive the adjustment signal and output voltage to the third node according to the adjustment signal to adjust the conduction state of the power transistor, so that the output voltage of the linear regulator gradually ramps up. The input pair is connected to the current mirror load unit to receive the second reference voltage and the output voltage of the linear regulator, so that when the soft-start module stops working, the output voltage of the linear regulator follows the second reference voltage. The bias current unit is connected to the power transistor, the ramp-up unit, and the input pair transistors, respectively, and is used to provide bias current.

12. The linear regulator as described in claim 11, characterized in that, It also includes a switching unit for receiving an external enable signal and controlling the switching on and off of the power transistor according to the external enable signal.

13. The linear regulator as described in claim 12, characterized in that, The switching unit includes a sixth PMOS transistor, whose gate is used to receive the external enable signal, its source is connected to the power supply terminal, and its drain is connected to the third node.

14. The linear regulator as described in claim 11, characterized in that, The climbing unit includes a seventh PMOS transistor, whose gate is connected to the soft-start module for receiving the adjustment signal, whose source is connected to the power supply terminal, and whose drain is connected to the third node.

15. The linear regulator as described in claim 1, characterized in that, The logic control module includes a comparator connected to the error amplification module and the soft-start module, respectively. The two input terminals of the comparator are used to receive the output voltage of the linear regulator and the first reference voltage, respectively. When the output voltage of the linear regulator is higher than the first reference voltage, the logic control module outputs a high-level control signal.

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