Method and apparatus for calculating frequency offset of network element clock in packet network

Abstract

The application discloses a method and device for calculating frequency deviation of network element clock in a packet network, and relates to the technical field of time synchronization. The method comprises the following steps: before a master device sends a first synchronization message for calculating clock frequency deviation, the master device and a slave device are brought into a frequency holdover state by stopping adjusting clock phase; after the slave device calculates the clock frequency deviation, the master device and the slave device are brought out of the frequency holdover state by resuming adjusting clock phase. In the process of calculating the frequency deviation, the application can ensure that the time of the master device and the slave device will not be adjusted, significantly improves the accuracy of the frequency deviation calculation result, and accordingly improves the accuracy of adjusting clock performance according to the calculation result.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of time synchronization, in particular to a method and device for calculating frequency deviation of network element clock in a packet network. BACKGROUND

[0002] Time synchronization technology is used to realize the synchronization of time between network elements, and is widely used in communication operator mobile backhaul scenarios to ensure normal communication between 4G and 5G base stations. When applied in the existing network, clock synchronization technology will be deployed before time synchronization technology is deployed. On the basis of ensuring consistency of the clock in the whole network, time synchronization will be deployed, that is, clock synchronization is the basis of time synchronization.

[0003] However, there is occasionally a clock "false locking" situation in the existing network, which mainly shows that the clock state is normal locking of the upstream, and the time synchronization cannot converge due to abnormal clock performance. Typical reasons include:

[0004] (1) Abnormal output clock performance of the upstream device (i.e. master device);

[0005] (2) Non-straight connection (intermediate through third-party devices, microwaves, etc.) between upstream and downstream devices (i.e. master and slave devices);

[0006] (3) Abnormal recovery of the clock performance of the downstream device (i.e. slave device) itself;

[0007] (4) The phase-locked loop locking bandwidth of the downstream device itself is configured too wide.

[0008] The above reasons will all cause abnormal clock locking performance of the downstream device, but the clock itself cannot perceive the abnormal clock performance. Based on the clock with abnormal performance, the time cannot be converged and locked.

[0009] Therefore, it is necessary to calculate the clock frequency deviation of the upstream and downstream based on the packet network, and then adjust and ensure the clock performance according to the frequency deviation.

[0010] The existing method for calculating clock frequency deviation is generally that the master device periodically sends synchronization messages to the slave device, and the slave device calculates the clock frequency deviation according to the sending timestamp, receiving timestamp and sending time interval of the synchronization message. After each calculation, the clock performance is adjusted according to the calculation result.

[0011] The above method has the following shortcomings: if the time of the master and slave devices is adjusted during the calculation of the frequency deviation, the time stamp will be abnormally jumped, which will greatly reduce the accuracy of the frequency deviation result calculated based on the time stamp, and even the result cannot be used, which will directly lead to the inability to adjust the clock performance according to the frequency deviation result. SUMMARY

[0012] In view of the defects in the prior art, the technical problem solved by the application is how to ensure that the time of the master and slave devices is not adjusted during the calculation of the frequency offset.

[0013] To achieve the above object, the application provides a method for calculating the frequency offset of a network element clock in a packet network, comprising the following steps: before a master device sends a first synchronization message for calculating the clock frequency offset, the master and slave devices are brought into a frequency holdover state by stopping adjusting the clock phase; after the slave device calculates the clock frequency offset, the master and slave devices are brought out of the frequency holdover state by resuming adjusting the clock phase.

[0014] On the basis of the above technical solution, after the master and slave devices enter the frequency holdover state and before the slave device calculates the clock frequency offset, the method further comprises a disordered message filtering process: after the slave device collects a plurality of synchronization messages, the receiving time stamps of all the synchronization messages received in the current round are sorted according to the sequence number order in each synchronization message to form a message data set, and the messages whose time order of the receiving time stamps does not correspond to the order of the sequence numbers are filtered from the message data set.

[0015] On the basis of the above technical solution, after the disordered message filtering process and before the slave device calculates the clock frequency offset, the method further comprises a time stamp abnormal message filtering process, which comprises a sending time stamp abnormal filtering process and a receiving time stamp abnormal filtering process.

[0016] The sending time stamp abnormal filtering process comprises: the slave device sequentially obtains the sending time stamp difference A and the sequence number difference B of two adjacent messages in the message data set, and obtains the sending time interval T according to the sending frequency parameter of the current two messages; when the difference between A and B*T exceeds the sending time error threshold, the current two messages are filtered from the message data set.

[0017] The receiving time stamp abnormal filtering process comprises: the slave device sequentially obtains the receiving time stamp difference of all adjacent messages in the message data set, and after filtering out the abnormal values, takes the average of the remaining differences as the message receiving interval E; the slave device sequentially obtains the sending time stamp difference C and the sequence number difference B of two adjacent messages in the message data set, and when the difference between C and B*E exceeds the sending time error threshold, the current two messages are filtered from the message data set.

[0018] On the basis of the above technical solution, the process of the slave device calculating the clock frequency offset comprises: in the message data set, two adjacent synchronization messages are taken as a group, the clock frequency offset of multiple groups is calculated, and the average of all the calculated clock frequency offsets is taken as the clock frequency offset calculation result.

[0019] The formula for calculating the clock frequency offset F is:

[0020] F=[(tn+12-tn2)-(tn+11-tn1)] / (tn+11-tn1);

[0021] Wherein, tn1 is the sending time stamp of the master device sending the synchronization message, and tn2 is the receiving time stamp of the slave device receiving the synchronization message.

[0022] On the basis of the above technical solution, the process of entering the frequency holdover state by stopping adjusting the clock phase includes: the slave device sends a frequency offset calculation request to the master device; the master device stops adjusting the clock phase after receiving the frequency offset calculation request, and responds to the slave device with a frequency holdover message; the slave device stops adjusting the clock phase after receiving the frequency holdover message; the process of exiting the frequency holdover state by resuming adjusting the clock phase includes: the slave device starts adjusting the clock phase, and sends a frequency offset calculation complete message to the master device; the master device starts adjusting the clock phase after receiving the frequency offset calculation complete message.

[0023] The application provides a device for calculating the frequency deviation of the clock of a network element in a packet network, which comprises a frequency holdover control module arranged on the master device and the slave device respectively, and a clock frequency deviation calculation module arranged on the slave device.

[0024] The frequency holdover control module is used for entering the frequency holdover state by stopping adjusting the clock phase before the master device sends the first synchronization message for calculating the clock frequency deviation; and the clock frequency deviation calculation module is used for exiting the frequency holdover state by resuming adjusting the clock phase after the clock frequency deviation calculation module is completed.

[0025] The clock frequency deviation calculation module is used for calculating the clock frequency deviation.

[0026] On the basis of the above technical solution, the device further comprises a message collecting module and a message filtering module arranged on the slave device.

[0027] The message collecting module is used for collecting a plurality of synchronization messages sent by the master device after the master device and the slave device enter the frequency holdover state.

[0028] The message filtering module comprises an out-of-order message filtering module, which is used for sorting the receiving time stamps of all the synchronization messages received in the current round according to the sequence number order in each synchronization message to form a message data set, and filtering the messages whose time order of the receiving time stamps does not correspond to the order of the message sequence numbers from the message data set.

[0029] On the basis of the above technical solution, the message filtering module further comprises a sending time stamp abnormality filtering module and a receiving time stamp abnormality filtering module.

[0030] The sending time stamp abnormality filtering module is configured to: after the out-of-order packet filtering module works, sequentially obtain the sending time stamp difference A and the sequence number difference B of two adjacent packets in the packet data set, and obtain the sending time interval T according to the sending frequency parameter of the current two packets; when the difference between A and B*T exceeds the sending time error threshold, filter the current two packets from the packet data set;

[0031] The receiving time stamp abnormality filtering module is configured to: after the out-of-order packet filtering module works, sequentially obtain the receiving time stamp difference of all adjacent packets in the packet data set, filter out the abnormal values, and take the average of the remaining differences as the packet receiving interval E; sequentially obtain the sending time stamp difference C and the sequence number difference B of two adjacent packets in the packet data set, and when the difference between C and B*E exceeds the sending time error threshold, filter the current two packets from the packet data set.

[0032] On the basis of the above technical solution, the working process of the clock frequency deviation calculation module includes: after the packet filtering module works, taking two adjacent synchronization packets as a group in the packet data set, calculating the clock frequency deviation of multiple groups, and taking the average of all calculated clock frequency deviations as the clock frequency deviation calculation result.

[0033] The formula for calculating the clock frequency deviation F is:

[0034] F=[(tn+12-tn2)-(tn+11-tn1)] / (tn+11-tn1);

[0035] Wherein, tn1 is the sending time stamp of the synchronization packet sent by the master device, and tn2 is the receiving time stamp of the synchronization packet received by the slave device.

[0036] On the basis of the above technical solution, the process in which the frequency time keeping control module lets the master-slave device enter the frequency time keeping state by stopping adjusting the clock phase includes: the slave device sends a frequency deviation calculation request to the master device; the master device stops adjusting the clock phase after receiving the frequency deviation calculation request, and sends a frequency time keeping packet to the slave device in response; the slave device stops adjusting the clock phase after receiving the frequency time keeping packet; the process in which the frequency time keeping control module lets the master-slave device exit the frequency time keeping state by resuming adjusting the clock phase includes: the slave device starts adjusting the clock phase, and sends a frequency deviation calculation complete packet to the master device; the master device starts adjusting the clock phase after receiving the frequency deviation calculation complete packet.

[0037] Compared with the prior art, the application has the following advantages:

[0038] (1) The application can make the master and slave devices enter the frequency time-keeping state by stopping adjusting the clock phase before calculating the frequency offset, thereby ensuring that the time of the master and slave devices will not be adjusted during the calculation of the frequency offset, significantly improving the accuracy of the frequency offset calculation result, and improving the accuracy of the subsequent clock adjustment performance according to the calculation result.

[0039] (2) Compared with the prior art which takes a single calculation result as the final clock frequency offset, the application calculates the clock frequency offset multiple times by taking the average of multiple sampled packet data as the final calculation result, further improving the accuracy.

[0040] (3) The application filters out out-of-order packets before calculating the clock frequency offset, thereby preventing the calculation result from being affected by out-of-order packets during the subsequent calculation of the frequency offset, further improving the accuracy of the calculation result.

[0041] (4) The application filters out synchronization packets with abnormal sending time stamps and / or receiving time stamps through the time stamp abnormal packet filtering process, further improving the accuracy of the calculation result. BRIEF DESCRIPTION OF DRAWINGS

[0042] In order to more clearly illustrate the technical solutions in the embodiments of the application, the following will briefly introduce the drawings needed to be used in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0043] Figure 1 The information interaction diagram of the synchronization packet in the embodiment of the application;

[0044] Figure 2 The information interaction diagram of the synchronization packet out-of-order in the embodiment of the application;

[0045] Figure 3 The flowchart of the calculation method of the frequency deviation of the clock of the network element in the packet network in the embodiment of the application;

[0046] Figure 4 The timing diagram of the calculation method of the frequency deviation of the clock of the network element in the packet network in the embodiment of the application. DETAILED DESCRIPTION

[0047] In order to make the purposes, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of the present application.

[0048] The flowchart shown in the drawings is only an example and does not necessarily include all the contents and operations / steps, nor does it have to be executed in the order described. For example, some operations / steps can be further decomposed, combined or partially merged, so that the actual execution order can be changed according to the actual situation.

[0049] The method for calculating the frequency deviation of the clock of a network element in a packet network in the embodiments of the present application comprises the following steps: before the master device sends a first synchronization message for calculating the clock frequency deviation, the master and slave devices are first brought into a frequency holdover state by stopping adjusting the clock phase; after the slave device calculates the clock frequency deviation, the master and slave devices are brought out of the frequency holdover state by resuming adjusting the clock phase.

[0050] Therefore, before calculating the frequency deviation, the master and slave devices are first brought into a frequency holdover state by stopping adjusting the clock phase, so that the time of the master and slave devices will not be adjusted during the calculation of the frequency deviation, which significantly improves the accuracy of the calculation result of the frequency deviation and the precision of the subsequent adjustment of the clock performance based on the calculation result.

[0051] Preferably, the process of bringing the master and slave devices into the frequency holdover state by stopping adjusting the clock phase in the method comprises: the slave device sends a frequency deviation calculation request to the master device; after receiving the frequency deviation calculation request, the master device stops adjusting the clock phase, enters the frequency holdover state and sends a frequency holdover entered message to the slave device; after receiving the frequency holdover entered message, the slave device stops adjusting the clock phase and enters the frequency holdover state.

[0052] The process of bringing the master and slave devices out of the frequency holdover state by resuming adjusting the clock phase in the method comprises: the slave device adjusts the clock phase and sends a frequency deviation calculation completed message to the master device; after receiving the frequency deviation calculation completed message, the master device resumes adjusting the clock phase.

[0053] Referring to Figure 1 The calculation formula of the clock frequency deviation in the method is:

[0054] The sending time interval of the message is defined as T, the clock frequency of the master device is f1, the sending time stamp of the synchronization message sent by the master device is t n1; the clock frequency of the slave device is f2, and the receiving time stamp of the slave device after receiving the synchronization message is t n 2, then the calculation formula of the clock frequency offset F is:

[0055] t21-t11 (i.e. t n+1 1-t n 1) = f1*T, t n+1 1 and t n 1 represent the sending time stamps of adjacent two messages, respectively;

[0056] t22-t12 (i.e. t n+1 2-t n 2) = f2*T, t n+1 2 and t n 2 represent the receiving time stamps of adjacent two messages, respectively;

[0057] Then F = (f2-f1) / f1 = [(t n+1 2-t n 2)-(t n+1 1-t n 1)] / (t n+1 1-t n 1);

[0058] The process of calculating the clock frequency offset of the slave device includes: taking adjacent two synchronization messages as a group in the message data set (in this embodiment, there are 32 messages in the message data set), calculating the clock frequency offset of multiple groups, and taking the average value of all calculated clock frequency offsets as the calculation result of the clock frequency offset.

[0059] Therefore, compared with the prior art in which a single calculation result is taken as the final clock frequency offset, the present application further improves the accuracy by calculating the clock frequency offset multiple times and taking the average value as the final calculation result through multiple sampled message data.

[0060] On this basis, the present application continues to develop and find that, since the clock frequency offset needs to be calculated according to the time stamps of multiple messages, if the messages are out of order (i.e. the later arrives first or the earlier arrives later, for example, referring to FIG. 1, the synchronization message with the receiving time t12 should arrive before the synchronization message with the receiving time t22, but actually it arrives after the message t22), the calculation result will be negative, which will lead to the calculation result being unavailable. Figure 1

[0061] ​To this end, the method further comprises an out-of-order message filtering process in the process of calculating the clock frequency offset, that is, before the slave device calculates the clock frequency offset after the master and slave devices enter the frequency time-keeping state, specifically: after the slave device collects a plurality of synchronization messages, according to the sequence number order marked by the master device in each synchronization message (the sequence number order is marked in the order of sending time), the receiving time stamps of all synchronization messages received in this round (all synchronization messages collected by the slave device before the slave device calculates the clock frequency offset after the master and slave devices enter the frequency time-keeping state) are sorted (in order or in reverse order) to form a message data set, and the messages whose time order of receiving time stamps do not correspond to the order of message sequence numbers are filtered (that is, deleted) from the message data set.

[0062] For example, as shown in the figure, the sequence number of the receiving time t12 is 1, the sequence number of the receiving time t22 is 2, t12 is after t22, that is, the message with sequence number 1 is sent first, but arrives after the message with sequence number 2; at this time, if the sequence numbers are arranged in ascending order, the time sequence of the receiving time is t12, t22, at this time, the time sequence is in descending order, that is, the time order of the receiving time stamps does not correspond to the order of the message sequence numbers, and the messages with sequence numbers 1 and 2 are deleted from the message data set. Figure 2

[0063] Therefore, after adding the out-of-order message filtering process, the out-of-order messages will be directly excluded, and then the subsequent calculation of the frequency offset will not be affected by the out-of-order messages, thereby further improving the accuracy of the calculation result.

[0064] Further, the present application further finds that if the message stamping is abnormal (for example, the sending time stamp and / or the receiving time stamp of the synchronization message is wrong when it is stamped), the calculation result is directly unusable.

[0065] Therefore, the method further comprises a time stamp abnormal message filtering process in the process of calculating the clock frequency offset, which is executed before the slave device calculates the clock frequency offset after the master and slave devices enter the frequency time-keeping state, and the time stamp abnormal message filtering process comprises a sending time stamp abnormal filtering process and a receiving time stamp abnormal filtering process, the execution time sequences of which need to be performed in sequence, but the execution order is not limited, that is, the two can be performed in sequence, but cannot be performed simultaneously.

[0066] The principle of the sending time stamp abnormal filtering process is that since the synchronization message sending interval of the master device is fixed, the sending time interval of adjacent messages can be calculated according to the message sending frequency parameter carried in the synchronization message; on this basis, if the difference between the sending time stamps of two adjacent messages (the difference between the sending time stamps, the actual difference (message interval time * the difference between the sequence numbers of adjacent messages)) is large (exceeds the stamping precision), it indicates that the two messages have sending time stamp stamping abnormality. ​

[0067] On this basis, the sending timestamp exception filtering process comprises: sequentially obtaining, from the device, a sending timestamp difference value A and a sequence number difference value B of two adjacent messages in a message data set, obtaining a sending time interval T according to a sending frequency parameter of the current two messages; judging whether a difference value of A and B*T exceeds a sending time error threshold G1, if yes, determining that the sending timestamp of the current two messages is abnormal, and filtering (i.e. deleting) the current two messages from the message data set, otherwise determining that it is normal.

[0068] The receiving timestamp exception filtering process comprises: sequentially obtaining, from the device, a receiving timestamp difference value of all adjacent messages in a message data set, taking an average value of the remaining difference values as a message receiving interval time E after filtering out abnormal values; sequentially obtaining, from the device, a sending timestamp difference value C and a sequence number difference value B of two adjacent messages in a message data set, judging whether a difference value of C and B*E exceeds a sending time error threshold G2, if yes, determining that the receiving timestamp of the current two messages is abnormal, and filtering (i.e. deleting) the current two messages from the message data set, otherwise determining that it is normal.

[0069] The value rule of G1 and G2 is 1000 / clock frequency, unit: ns, for example, if the clock frequency is 125MHZ, the value is 8ns, and if the clock frequency is 256MHZ, the value is 4ns; considering the actual situation, the threshold range can be appropriately enlarged.

[0070] Therefore, it can be known that the timestamp exception message filtering process filters out the synchronization message with abnormal sending timestamp and / or receiving timestamp, and further improves the accuracy of the calculation result.

[0071] Referring to FIGS. 1, 2 and 3, Figure 3 and Figure 4 the clock frequency offset calculation method will be specifically described below through a specific embodiment.

[0072] S1: the master and slave devices negotiate to enter the frequency holdover state at the same time, specifically:

[0073] The slave device uses the 1588 signaling message (i.e. synchronization message) to send a frequency offset calculation request to the master device; after receiving the frequency offset calculation request, the master device stops adjusting the clock phase, enters the frequency holdover state, and responds to the slave device with a message carrying information that it has entered the frequency holdover state. After receiving the message that it has entered the frequency holdover state, the slave device also stops adjusting the clock phase, enters the frequency holdover state, and responds to the master device with a message carrying information that it has entered the frequency holdover state; after receiving the message that it has entered the frequency holdover state, the master device starts periodically sending synchronization messages carrying sending timestamps, sequence numbers and message sending frequency parameters, and goes to S2.

[0074] S2: After the slave device receives a specified number (the specified number is greater than the pre-set minimum sample number) of synchronization messages, the slave device sorts all the received synchronization messages in the current round according to the sequence numbers in each synchronization message to form a message data set, the message data set includes the sequence number, the sending timestamp and the receiving timestamp of each message, and the process goes to S3.

[0075] S3: Message filtering process, specifically:

[0076] S301: The slave device compares the sequence numbers and receiving timestamps of two adjacent messages in sequence, and deletes the messages whose time sequence of receiving timestamps does not correspond to the sequence of message sequence numbers from the message data set, and the process goes to S302.

[0077] S302: The slave device compares the sending timestamp difference A and the sequence number difference B of two adjacent messages in the message data set in sequence; obtains the sending time interval T according to the sending frequency parameter of the current two messages; judges whether the difference between A and B*T exceeds the sending time error threshold G1: if yes, it is determined that the sending timestamps of the current two messages are abnormal, the current two messages are filtered (i.e. deleted) from the message data set, and the process goes to S303, otherwise it is determined to be normal, and the process goes to S303 directly.

[0078] S303: The slave device obtains the receiving timestamp difference of all adjacent messages in the message data set in sequence, and takes the average of the remaining differences as the message receiving interval E after filtering out abnormal values; obtains the sending timestamp difference C and the sequence number difference B of two adjacent messages in the message data set in sequence, judges whether the difference between C and B*E exceeds the sending time error threshold G2, if yes, it is determined that the receiving timestamps of the current two messages are abnormal, the current two messages are filtered (i.e. deleted) from the message data set, and the process goes to S4, otherwise it is determined to be normal, and the process goes to S4 directly.

[0079] S4: The slave device groups two adjacent synchronization messages in the message data set as a group, calculates the frequency deviation of multiple groups, and takes the average of all calculated clock frequency deviations as the clock frequency deviation calculation result, and the process goes to S5.

[0080] S5: The master and slave devices negotiate to exit the frequency time keeping state at the same time, specifically:

[0081] The slave device starts to adjust the clock phase and sends a frequency deviation calculation complete message to the master device, and the master device receives the frequency deviation calculation complete message and starts to adjust the clock phase again.

[0082] At this time, the master and slave devices start normal 1588 time synchronization phase adjustment, and after waiting for a fixed time, the slave device re-initiates negotiation and starts to calculate the frequency deviation again.

[0083] The application provides a device for calculating frequency deviation of network element clock in a packet network, characterized in that the device comprises a frequency holdover control module arranged on a master device and a slave device respectively, and a clock frequency deviation calculation module arranged on the slave device.

[0084] The frequency holdover control module is used for:

[0085] Before the master device sends a first synchronization message for calculating clock frequency deviation, the master device and the slave device enter a frequency holdover state by stopping adjusting clock phase, specifically, the slave device sends a frequency deviation calculation request to the master device, the master device stops adjusting clock phase after receiving the frequency deviation calculation request and sends a frequency holdover message to the slave device, and the slave device stops adjusting clock phase after receiving the frequency holdover message.

[0086] After the clock frequency deviation calculation module works, the master device and the slave device exit the frequency holdover state by resuming adjusting clock phase, specifically, the slave device starts adjusting clock phase and sends a frequency deviation calculation completion message to the master device, and the master device starts adjusting clock phase after receiving the frequency deviation calculation completion message.

[0087] The clock frequency deviation calculation module is used for calculating clock frequency deviation, specifically, after the message filtering module works, adjacent two synchronization messages in the message data set are taken as a group, and multiple groups of clock frequency deviation are calculated, and the average value of all calculated clock frequency deviations is taken as a clock frequency deviation calculation result.

[0088] The formula for calculating the clock frequency deviation F is:

[0089] F=[(t n+1 2-t n 2)-(t n+1 1-t n 1)] / (t n+1 1-t n 1);

[0090] Wherein t n 1 is a sending time stamp of the master device sending a synchronization message, and t n 2 is a receiving time stamp of the slave device receiving the synchronization message.

[0091] The device further comprises a message collecting module and a message filtering module arranged on the slave device.

[0092] The message collecting module is used for collecting a plurality of synchronization messages sent by the master device after the master device and the slave device enter the frequency holdover state.

[0093] The packet filtering module comprises a packet reordering filtering module, which is configured to: in all the packets collected by the packet collecting module, sort the receiving time stamps of all the synchronous packets received in the current round according to the sequence numbers in each synchronous packet to form a packet data set, and filter the packets whose time sequence of the receiving time stamps does not correspond to the sequence of the sequence numbers from the packet data set.

[0094] The packet filtering module further comprises a sending time stamp abnormality filtering module and a receiving time stamp abnormality filtering module.

[0095] The sending time stamp abnormality filtering module is configured to: after the packet reordering filtering module is worked, sequentially obtain the sending time stamp difference A and the sequence number difference B of two adjacent packets in the packet data set, obtain the sending time interval T according to the sending frequency parameter of the current two packets, and filter the current two packets from the packet data set when the difference between A and B*T exceeds the sending time error threshold.

[0096] The receiving time stamp abnormality filtering module is configured to: after the packet reordering filtering module is worked, sequentially obtain the receiving time stamp difference of all the adjacent packets in the packet data set, take the average of the remaining differences as the packet receiving interval time E after filtering out the abnormal values, and sequentially obtain the sending time stamp difference C and the sequence number difference B of two adjacent packets in the packet data set, and filter the current two packets from the packet data set when the difference between C and B*E exceeds the sending time error threshold.

[0097] Those skilled in the art can understand that all or some steps in the method disclosed above, the functions of the modules / units in the system and the device can be implemented as software, firmware, hardware and appropriate combinations thereof. In the hardware implementation, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component can have multiple functions, or one function or step can be performed by several physical components in cooperation. Some or all of the physical components can be implemented as software executed by a processor such as a central processing unit, a digital signal processor or a microprocessor, or as hardware, or as an integrated circuit such as an application specific integrated circuit. Such software can be distributed on a computer readable storage medium, which can include a computer readable storage medium (or non-transitory medium) and a communication medium (or transitory medium).

[0098] As is well known to those of ordinary skill in the art, the term computer readable storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data. Computer readable storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disks (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. Further, it is well known to those of ordinary skill in the art that communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media.

[0099] For example, the computer readable storage medium can be an internal storage unit of the electronic device of the foregoing embodiments, such as a hard disk or a memory of the electronic device. The computer readable storage medium can also be an external storage device of the electronic device, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, and the like.

[0100] The above merely describes specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of various equivalent modifications or replacements within the technical range disclosed by the present application, and these modifications or replacements shall be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A method for calculating the frequency offset of a network element clock in a packet network, characterized in that, The method comprises the following steps: before the master device sends a first synchronization message for calculating clock frequency offset, the master-slave devices enter a frequency holdover state by stopping adjusting clock phase; after the slave device calculates the clock frequency offset, the master-slave devices exit the frequency holdover state by resuming adjusting clock phase. The process of entering the frequency holdover state by stopping adjusting clock phase comprises: the slave device sends a frequency offset calculation request to the master device; the master device stops adjusting clock phase after receiving the frequency offset calculation request and responds to the slave device with a frequency holdover message; the slave device stops adjusting clock phase after receiving the frequency holdover message; the process of exiting the frequency holdover state by resuming adjusting clock phase comprises: the slave device starts adjusting clock phase and sends a frequency offset calculation completion message to the master device; the master device starts adjusting clock phase after receiving the frequency offset calculation completion message.

2. A method for calculating the frequency offset of a network element clock in a packet network according to claim 1, characterized in that: After the master-slave devices enter the frequency holdover state, before the slave device calculates the clock frequency offset, the method further comprises a disordered message filtering process: after the slave device collects a plurality of synchronization messages, the slave device sorts the receiving time stamps of all the synchronization messages received in the current round according to the sequence numbers in the synchronization messages to form a message data set, and filters the messages whose time sequence of receiving time stamps does not correspond to the sequence of message sequence numbers from the message data set.

3. The method for calculating the frequency offset of a network element clock in a packet network according to claim 2, characterized in that: After the disordered message filtering process, before the slave device calculates the clock frequency offset, the method further comprises a time stamp abnormal message filtering process, which comprises a sending time stamp abnormal filtering process and a receiving time stamp abnormal filtering process. The sending time stamp abnormal filtering process comprises: the slave device obtains, in the message data set, a sending time stamp difference A and a sequence number difference B of two adjacent messages in sequence, obtains a sending time interval T according to the sending frequency parameter of the current two messages, and filters the current two messages from the message data set when the difference between A and B*T exceeds a sending time error threshold. The receiving time stamp abnormal filtering process comprises: the slave device obtains, in the message data set, a receiving time stamp difference of all adjacent messages in sequence, filters out abnormal values, and takes the average of the remaining differences as a message receiving interval E; the slave device obtains, in the message data set, a sending time stamp difference C and a sequence number difference B of two adjacent messages in sequence, and filters the current two messages from the message data set when the difference between C and B*E exceeds a sending time error threshold.

4. The method for calculating the frequency offset of a network element clock in a packet network according to claim 3, characterized in that: The process of calculating the clock frequency offset by the slave device comprises: taking two adjacent synchronization messages in the message data set as a group, calculating the clock frequency offset of multiple groups, and taking the average of all calculated clock frequency offsets as a clock frequency offset calculation result. The formula for calculating the clock frequency offset F is: F=[(t n+1 2-t n 2)-(t n+1 1-t n 1)] / (t n+1 1-t n 1); Wherein t n 1 is the sending time stamp of the master device sending the synchronization message, t n+1 1 and t n 1 represent the sending time stamps of two adjacent messages respectively; t n 2 is the receiving time stamp of the slave device receiving the synchronization message, t n+1 2 and t n 2 represent the receiving time stamps of two adjacent messages respectively.

5. An apparatus for computing a frequency offset of a network element clock in a packet network, characterized by: The device comprises a frequency holdover control module arranged on the master-slave devices respectively, and a clock frequency offset calculation module arranged on the slave device. The frequency holdover control module is configured to: before the master device sends the first synchronization message for calculating the clock frequency offset, let the master and slave devices enter the frequency holdover state by stopping adjusting the clock phase; and after the clock frequency offset calculation module completes the work, let the master and slave devices exit the frequency holdover state by resuming adjusting the clock phase; The clock frequency offset calculation module is configured to: calculate the clock frequency offset; The process in which the frequency holdover control module lets the master and slave devices enter the frequency holdover state by stopping adjusting the clock phase includes: the slave device sends a frequency offset calculation request to the master device; the master device stops adjusting the clock phase after receiving the frequency offset calculation request, and sends a frequency holdover message to the slave device in response to having entered the frequency holdover state; and the slave device stops adjusting the clock phase after receiving the frequency holdover message; the process in which the frequency holdover control module lets the master and slave devices exit the frequency holdover state by resuming adjusting the clock phase includes: the slave device starts adjusting the clock phase, and sends a frequency offset calculation completion message to the master device; and the master device starts adjusting the clock phase after receiving the frequency offset calculation completion message.

6. The calculation device for frequency deviation of network element clocks in a packet network as described in claim 5, characterized in that: The device further includes a message collection module and a message filtering module arranged on the slave device; The message collection module is configured to: after the master and slave devices enter the frequency holdover state, collect a plurality of synchronization messages sent by the master device; The message filtering module includes an out-of-order message filtering module, which is configured to: among all the messages collected by the message collection module, sort the reception time stamps of all the synchronization messages received in the current round according to the sequence number order in each synchronization message to form a message data set, and filter the messages whose time order of the reception time stamps does not correspond to the order of the sequence numbers from the message data set.

7. The apparatus for calculating frequency offset of a network element clock in a packet network of claim 6, wherein: the first and second time stamps are received from a first node; the third and fourth time stamps are received from a second node; and the first and second time stamps are received from a third node. 5 The message filtering module further includes a sending time stamp exception filtering module and a reception time stamp exception filtering module; The sending time stamp exception filtering module is configured to: after the out-of-order message filtering module completes the work, sequentially obtain the sending time stamp difference A and the sequence number difference B of two adjacent messages in the message data set, obtain the sending time interval T according to the sending frequency parameter of the current two messages, and filter the current two messages from the message data set when the difference between A and B*T exceeds the sending time error threshold value; The reception time stamp exception filtering module is configured to: after the out-of-order message filtering module completes the work, sequentially obtain the reception time stamp difference of all adjacent messages in the message data set, take the average of the remaining differences as the message reception interval E after filtering out the abnormal values, and sequentially obtain the sending time stamp difference C and the sequence number difference B of two adjacent messages in the message data set, and filter the current two messages from the message data set when the difference between C and B*E exceeds the sending time error threshold value.

8. The apparatus for calculating frequency offset of a network element clock in a packet network of claim 7, wherein: the first and second time stamps are received from a first node; the third and fourth time stamps are received from a second node; and the first and second time stamps are received from a third node. 5 The working process of the clock frequency offset calculation module includes: after the message filtering module completes the work, take two adjacent synchronization messages in the message data set as a group, calculate the clock frequency offset of multiple groups, and take the average of all the calculated clock frequency offsets as the clock frequency offset calculation result; The formula for calculating the clock frequency offset F is: F=[(t n+1 2-t n 2)-(t n+1 1-t n 1)] / (t n+1 1-t n 1) Wherein t n 1 is the sending time stamp of the master device sending the synchronization message, t n+1 1 and t n 1 represent the sending time stamps of two adjacent messages respectively; t n 2 is the receiving time stamp of the slave device receiving the synchronization message, t n+1 2 and t n 2 represent the receiving time stamps of two adjacent messages respectively.

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