System and method for automatically identifying defect-based test coverage gaps in semiconductor devices

Abstract

Automatically identifying defect-based test coverage gaps in semiconductor devices includes: determining a plurality of apparent killer defects on the one or more semiconductor devices based on characterization measurements of the one or more semiconductor devices having a plurality of semiconductor dies acquired by one or more semiconductor manufacturing subsystems; determining at least one semiconductor die that passed at least one test based on test measurements acquired by one or more test tool subsystems; associating the characterization measurements with the test measurements to determine at least one apparent killer defect on the at least one semiconductor die that passed the at least one test; and determining one or more gap regions for defect-based test coverage on the one or more semiconductor devices based on the at least one apparent killer defect on the at least one semiconductor die that passed the at least one test.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Indian Provisional Application No. 202041055201, filed on December 18, 2020, and U.S. Provisional Application No. 63 / 144,997, filed on February 3, 2021, and the entire contents of both applications are incorporated herein by reference. Technical Field

[0003] The present disclosure relates generally to semiconductor devices, and more particularly, to systems and methods for automatically identifying defect-based test coverage gaps in semiconductor devices. Background Art

[0004] The manufacture of semiconductor devices may typically require hundreds or thousands of processing steps to form a functional device. During these processing steps, various inspection and / or metrology measurements may be performed to identify defects on the device and / or monitor various parameters on the device. Electrical testing may also be performed to verify or evaluate the functionality of the device. However, although some detected defects and metrology errors may be so obvious as to clearly indicate device failure, smaller variations may cause premature reliability failures of the device after exposure to its operating environment. Risk-averse users of semiconductor devices (such as automotive, military, aerospace, and medical applications) are beginning to seek failure rates in the parts per billion (PPB) range, exceeding current parts per million (PPM) levels. Identifying and controlling reliability defects is key to meeting the requirements of these industries as the demand for semiconductor devices in automotive, military, aerospace, and medical applications continues to increase. Therefore, it is desirable to provide systems and methods for reliability defect detection. Summary of the invention

[0005] According to one or more embodiments of the present disclosure, a system is disclosed. In one illustrative embodiment, the system includes a controller communicatively coupled to one or more semiconductor manufacturing subsystems and one or more test tool subsystems. In another illustrative embodiment, the controller includes one or more processors configured to execute program instructions, the program instructions causing the one or more processors to determine multiple obvious fatal defects on the one or more semiconductor devices via the characterization subsystem based on characterization measurements of the one or more semiconductor devices acquired by the one or more semiconductor manufacturing subsystems. In another illustrative embodiment, the one or more semiconductor devices include multiple semiconductor dies. In another illustrative embodiment, the controller includes one or more processors configured to execute program instructions, the program instructions causing the one or more processors to determine at least one semiconductor die of the multiple semiconductor dies that passed at least one of the multiple tests via the test subsystem based on test measurements acquired by the one or more test tool subsystems. In another illustrative embodiment, the controller includes one or more processors configured to execute program instructions, the program instructions causing the one or more processors to correlate the characterization measurements with the test measurements via a correlation subsystem to determine at least one of the plurality of clearly killer defects on the at least one semiconductor die of the plurality of semiconductor dies that passed the at least one of the plurality of tests. In another illustrative embodiment, the controller includes one or more processors configured to execute program instructions causing the one or more processors to determine, via a positioning subsystem, one or more gap regions covered for defect-based testing on the one or more semiconductor devices based on the at least one clearly killer defect on the at least one semiconductor die of the plurality of semiconductor dies that passed the at least one of the plurality of tests.

[0006] According to one or more embodiments of the present disclosure, a method is disclosed. In one illustrative embodiment, the method may include, but is not limited to, determining a plurality of obvious fatal defects on the one or more semiconductor devices via a characterization subsystem of a controller based on characterization measurements of the one or more semiconductor devices acquired by one or more semiconductor manufacturing subsystems. In another illustrative embodiment, the one or more semiconductor devices include a plurality of semiconductor dies. In another illustrative embodiment, the method may include, but is not limited to, determining at least one semiconductor die of the plurality of semiconductor dies that passed at least one of a plurality of tests via a test subsystem of the controller based on test measurements acquired by one or more test tool subsystems. In another illustrative embodiment, the method may include, but is not limited to, associating the characterization measurement with the test measurement via an association subsystem of the controller to determine at least one of the plurality of obvious fatal defects on the at least one semiconductor die of the plurality of semiconductor dies that passed at least one of the plurality of tests. In another illustrative embodiment, the method may include, but is not limited to, determining, via a positioning subsystem of the controller, one or more gap regions covered for defect-based testing on the one or more semiconductor devices based on the at least one clear killer defect on the at least one semiconductor die of the plurality of semiconductor dies that passed the at least one of the plurality of tests.

[0007] According to one or more embodiments of the present disclosure, a system is disclosed. In one illustrative embodiment, the system includes one or more semiconductor manufacturing subsystems. In another illustrative embodiment, the system includes one or more test tool subsystems. In another illustrative embodiment, the system includes a controller communicatively coupled to the one or more semiconductor manufacturing subsystems and the one or more test tool subsystems. In another illustrative embodiment, the controller includes one or more processors configured to execute program instructions, the program instructions causing the one or more processors to determine multiple obvious fatal defects on the one or more semiconductor devices via the characterization subsystem based on characterization measurements of the one or more semiconductor devices acquired by the one or more semiconductor manufacturing subsystems. In another illustrative embodiment, one or more semiconductor devices include multiple semiconductor dies. In another illustrative embodiment, the controller includes one or more processors configured to execute program instructions, the program instructions causing the one or more processors to determine at least one semiconductor die of the multiple semiconductor dies that passed at least one of the multiple tests via the test subsystem based on the test measurements acquired by the one or more test tool subsystems. In another illustrative embodiment, the controller includes one or more processors configured to execute program instructions, the program instructions causing the one or more processors to correlate the characterization measurements with the test measurements via a correlation subsystem to determine at least one of the plurality of clearly killer defects on the at least one semiconductor die of the plurality of semiconductor dies that passed the at least one of the plurality of tests. In another illustrative embodiment, the controller includes one or more processors configured to execute program instructions causing the one or more processors to determine, via a positioning subsystem, one or more gap regions covered for defect-based testing on the one or more semiconductor devices based on the at least one clearly killer defect on the at least one semiconductor die of the plurality of semiconductor dies that passed the at least one of the plurality of tests.

[0008] It should be understood that both the foregoing summary and the following detailed description are for illustration and explanation only and are not necessarily limiting of the invention as claimed.The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the summary, serve to explain the principles of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Those skilled in the art may better understand the many advantages of the present disclosure with reference to the accompanying drawings, in which:

[0010] Figure 1 is a flow chart illustrating steps performed in a method or process for automatically identifying defect-based test coverage gaps in a semiconductor device according to one or more embodiments of the present disclosure;

[0011] Figure 2 is a block diagram of a system for automatically identifying defect-based test coverage gaps in a semiconductor device according to one or more embodiments of the present disclosure;

[0012] Figure 3A is a conceptual illustration of a fatal defect in a semiconductor die that passed testing according to one or more embodiments of the present disclosure;

[0013] Figure 3B is a conceptual illustration of a fatal defect in a semiconductor die that passed testing according to one or more embodiments of the present disclosure;

[0014] Figure 3C is a conceptual illustration of a fatal defect in a semiconductor die that passed testing according to one or more embodiments of the present disclosure;

[0015] Figure 3D is a conceptual illustration of a fatal defect in a semiconductor die that passed testing according to one or more embodiments of the present disclosure;

[0016] Figure 4A is a conceptual illustration of a semiconductor die layout according to one or more embodiments of the present disclosure;

[0017] Figure 4B is a conceptual illustration of a semiconductor die layout having a fatal defect overlying the semiconductor die according to one or more embodiments of the present disclosure;

[0018] Figure 4C is a conceptual illustration of a semiconductor die layout overlying a killer defect including a potential defect-based test coverage gap region according to one or more embodiments of the present disclosure;

[0019] Figure 5A is a graph illustrating test coverage gap trends over time in accordance with one or more embodiments of the present disclosure;

[0020] Figure 5B is a chart illustrating test coverage gap trends by product according to one or more embodiments of the present disclosure;

[0021] Figure 6 is a flow chart illustrating steps performed in a method or process for manufacturing a semiconductor device according to one or more embodiments of the present disclosure;

[0022] Fig. 7A is a block diagram of a system for manufacturing a semiconductor device according to one or more embodiments of the present disclosure; and

[0023] Figure 7B is a block diagram of a system for manufacturing a semiconductor device according to one or more embodiments of the present disclosure. DETAILED DESCRIPTION

[0024] Reference will now be made in detail to the disclosed subject matter illustrated in the accompanying drawings. The present disclosure has been particularly shown and described with respect to certain embodiments and specific features thereof. The embodiments described herein are to be regarded as illustrative and not restrictive. It should be readily apparent to one of ordinary skill in the art that various changes and modifications in form and details may be made without departing from the spirit and scope of the present disclosure.

[0025] Defects that occur during the manufacturing process can have a wide range of effects on the performance of devices in the field. For example, a "fatal" defect can cause an immediate device failure. As another example, a small defect may have little or no effect on the performance of the device throughout the life of the device. As another example, a class of defects known as latent reliability defects (LRDs) may not cause failures during manufacturing / testing or may not cause immediate device failures during operation, but may cause premature failure of the device during operation when used in a working environment. It should be noted herein that for the purposes of this disclosure, the terms "manufacturing process" and "fabrication process" together with corresponding variations of the terms (such as "manufacturing line" and "fabrication line" and the like) may be considered equivalent.

[0026] Fatal defects can occur at known or unknown locations within the design. Unknown locations are particularly problematic because they are susceptible to reliability escapes from fatal defects in the test gap. Developments associated with the implementation of in-line defective partial average testing (I-PAT) have shown that a relatively large percentage of reliability escapes can be attributed to obvious fatal defects in the test coverage gap. In examples where there are reliability escapes, semiconductor devices may fail functionally after processing, but the device manufacturer is unable to make this determination due to testing limitations. Examples of implementing I-PAT can be found in U.S. Patent No. 10,761,128, issued on September 1, 2020, and U.S. Patent Application No. 17 / 101,856, filed on November 23, 2020, each of which is incorporated herein in its entirety.

[0027] Test coverage gaps may originate from one of several sources. For example, test coverage gaps may occur in areas of a semiconductor device that cannot be tested due to the logical layout of the device. As another example, test coverage gaps may occur in areas of a semiconductor device that are difficult to measure comprehensively (e.g., analog circuits or the like) due to the fact that fault identification consists of more than just being in the correct on / off state. As another example, test coverage gaps may occur in areas of a semiconductor device that are not tested due to cost considerations associated with increased testing expenses as test coverage increases.

[0028] Old methods or processes for identifying high risk areas of test coverage escape on semiconductor devices may generally allow semiconductor manufacturers to achieve a parts per million (PPM) level of baseline reliability defect control, depending on chip complexity and size. However, selected semiconductor manufacturers (e.g., automotive semiconductor manufacturers, military semiconductor manufacturers, aerospace semiconductor manufacturers, medical application semiconductor manufacturers, or the like) are actively seeking new and innovative methods to identify sources of reliability failures to achieve a parts per billion (PPB) level of baseline reliability defect control.

[0029] For example, older methods or processes include predictive methods such as testing analog software packages. However, predictive methods have varying degrees of effectiveness that are highly device dependent. For example, analog devices are much more difficult to predict than digital devices. In addition, certain areas of the circuit layout are often deemed "untestable" regardless of how much test time is allocated. Furthermore, predictive methods, by their nature, cannot identify undesirable areas of test coverage gaps.

[0030] As another example, the old method or process also includes population knowledge based on past semiconductor devices. Population knowledge based on past devices generally provides device manufacturers with a good starting point for designing an appropriate test strategy. However, this may not be comprehensive or quantitative.

[0031] As another example, the old method or process also includes physical failure analysis (PFA) from stress testing or field reliability feedback. For example, an automotive semiconductor manufacturer may need to perform PFA on a stress-tested die or field reliability feedback. The latter may be feedback from a Tier 1 component supplier, assembly from an automotive OEM, or warranty field feedback from an end consumer. Although a necessary task, PFA does not provide enough information to generate a full picture of the test coverage gap of the device. For example, statistical significance may be lacking because the PPM number of failures is too small, making it difficult to derive a comprehensive understanding of the baseline reliability Pareto from a few field feedbacks, which results in semiconductor manufacturers seeing only a few pieces of the puzzle. As another example, field feedback generally provides information reflecting the reliability problems of semiconductor manufacturers when manufacturing faulty devices, which may be several years ago and no longer relevant to the current design. As another example, physical failure analysis is expensive, time-consuming, and often uncertain or incorrect. As another example, the root cause of reliability failures is often destroyed by the activation of defects or collateral damage of PFA delay processes.

[0032] Embodiments of the present disclosure relate to systems and methods for automatically identifying defect-based test coverage gaps in semiconductor devices. In particular, embodiments of the present disclosure relate to allowing automatic identification of previously unknown locations within a design that have increased susceptibility to reliability escapes from killer defects in test gaps. In addition, embodiments of the present disclosure relate to using empirical defect data to systematically identify test coverage gaps. Furthermore, embodiments of the present disclosure relate to providing new metrics to quantify the risk of reliability escapes over time on a device-by-device basis or as improvements are made. Furthermore, embodiments of the present disclosure relate to providing new metrics and / or charts to demonstrate continuous improvement, evaluate the effectiveness of test program changes, and quantify test gap differences over time on a device-by-device basis or between different devices in a product portfolio as improvements are made.

[0033] Figure 1 A method or process 100 for automatically identifying defect-based test coverage gaps in a semiconductor device in accordance with one or more embodiments of the present disclosure is described. Figure 2 A block diagram of a system 200 for automatically identifying defect-based test coverage gaps in a semiconductor device according to one or more embodiments of the present disclosure is shown. Figure 2 However, it should be further recognized that the method or process 100 is not limited to Figure 2 The system 200 illustrated in FIG. 1 is described in detail because additional or alternative system-level embodiments may implement all or part of the steps of the method or process 100 .

[0034] In step 102, characterization measurements of one or more semiconductor devices are received. In some embodiments, the system 200 receives information output by one or more semiconductor manufacturing subsystems 202. The characterization measurements may be performed during the manufacture of the one or more semiconductor devices. For example, the one or more semiconductor manufacturing subsystems 202 may include, but are not limited to, one or more process tools configured to manufacture semiconductor devices comprising 1, 2, ... N layers manufactured after several (e.g., tens, hundreds, thousands) of steps performed by several manufacturing processes. As another example, the one or more semiconductor manufacturing subsystems 202 may include, but are not limited to, one or more in-line defect inspection and / or metrology tools configured to characterize the semiconductor devices. For example, one or more outputs may include, but are not limited to, baseline inspections (e.g., sampling-based inspections), screening inspections at major semiconductor device layers, or the like. For purposes of this disclosure, "characterization" may refer to in-line defect inspections or in-line metrology measurements.

[0035] In step 104, one or more apparent killer defects on one or more semiconductor devices are determined based on characterization measurements of the one or more semiconductor devices. In some embodiments, the system 200 includes a characterization subsystem 204 or subsystem A. The characterization subsystem 204 may receive information output by one or more semiconductor manufacturing subsystems 202 generated after characterization of the semiconductor devices. The characterization subsystem 204 may determine one or more apparent killer defects from the information by applying one or more processes to the received in-line defect data to separate defects that are apparent killer defects from defects with a lower probability of affecting device performance. For example, the characterization subsystem 204 may implement deterministic and / or statistical limit techniques. As another example, advanced deep learning or machine learning techniques may be implemented due to potential large data sets and / or potential defect rate variations. In general, machine learning techniques may be any technique known in the art, including (but not limited to) supervised learning, unsupervised learning, or other learning-based processes, such as (but not limited to) linear regression, neural networks or deep neural networks, heuristic-based models, or the like. It is noted herein that semiconductor dies or wafers without obvious killer defects may be flagged for further review (eg, for other types of defects).

[0036] In step 106, test measurements of one or more semiconductor devices are received. In some embodiments, the system 200 receives information output by one or more test tool subsystems 206. Test measurements for one or more semiconductor devices may be obtained. For example, the one or more test tool subsystems 206 may include (but are not limited to) one or more electrical test tools, one or more stress test tools, or the like. The one or more test tool subsystems 206 may be configured to test semiconductor devices manufactured by one or more semiconductor manufacturing processes performed by one or more semiconductor manufacturing subsystems 202. For the purposes of this disclosure, "testing" may be understood to refer to a process of electrically evaluating the functionality of a device at the end of a manufacturing process (e.g., an electrical wafer sorting (EWS) process or the like), the end of packaging (e.g., a unit detection process, a class detection process, or the like), and / or the end of final testing (e.g., after an aging process and other quality inspection processes). It should be noted herein that failed semiconductor dies or wafers may be isolated from passed semiconductor dies or wafers and / or identified for further testing.

[0037] In step 108, one or more semiconductor dies that pass one or more executed tests are determined based on test measurements of the one or more semiconductor devices. In some embodiments, the system 200 includes a test subsystem 208 or subsystem B. The test subsystem 208 may receive information output by the one or more test tool subsystems 206 after testing of semiconductor devices produced by one or more semiconductor manufacturing processes executed via the one or more semiconductor manufacturing subsystems 202. The test subsystem 208 may separate semiconductor dies that pass the executed tests from semiconductor dies that fail the executed tests (e.g., the executed tests include, but are not limited to, probing, electrical testing, stress testing, or the like). For example, the semiconductor dies may be assigned group numbers during manufacturing, and the subsystem B may separate semiconductor dies that pass the executed tests from semiconductor dies that fail the executed tests based on the group numbers. For example, only semiconductor dies that pass all executed tests may be accepted by the test subsystem 208. Alternatively, any semiconductor die that passes a selected subset of the executed tests, where the selected subset is less than the entire set of executed tests, may be accepted by the test subsystem 208. It should be noted herein that semiconductor die or wafers that fail may be disregarded (e.g., discarded) and / or identified for further testing.

[0038] In step 110, the characterization measurements are correlated with the test measurements to determine one or more significant killer defects on one or more semiconductor dies of one or more semiconductor devices that pass one or more tests performed. In some embodiments, the system 200 includes a correlation subsystem 210 or subsystem C. The correlation subsystem 210 may receive information output by the characterization subsystem 204 regarding significant killer defects. The correlation subsystem 210 may receive information output by the test subsystem 208 regarding semiconductor dies that pass a selected subset or all of the tests performed. The correlation subsystem 210 may correlate the information output by the characterization subsystem 204 with the information output by the test subsystem 208 to determine a subpopulation of significant killer defects present on the selected subset or all of the semiconductor dies that pass the tests performed.

[0039] Figures 3A to 3D A conceptual illustration of a killer defect in a semiconductor die that can be detected by a selected subset or all of the tests that can be performed by one or more test tool subsystems 206 in accordance with one or more embodiments of the present disclosure. Figure 3A In FIG. 3 , image 300 illustrates embedded particles 302 within a pattern 304. Figure 3B In FIG. 3 , image 310 illustrates a shorting bridge 312 within pattern 314. Figure 3C In FIG. 3 , image 320 illustrates an example 322 of insufficient copper plating polish near pattern 324. Figure 3D , image 330 illustrates surface voids 332 within pattern 334 .

[0040] In step 112, one or more gap regions of defect-based test coverage are determined based on one or more significant killer defects on one or more semiconductor dies of one or more semiconductor devices that pass one or more tests performed. In some embodiments, the system 200 includes a positioning subsystem 212 or subsystem D. The positioning subsystem 212 may receive information output by the correlation subsystem 210 regarding a subpopulation of significant killer defects present on a selected subset or all of the semiconductor dies that pass the tests performed. Gap regions in defect-based test coverage where the semiconductor dies are not sufficiently stressed to determine defects may be determined by the system 200. The positioning subsystem 212 may analyze the location and frequency of significant killer defects in the selected subset or all of the semiconductor dies that pass the tests performed. For example, the positioning subsystem 212 may determine a systematic spread of semiconductor dies that are one or more instances throughout the gap regions in the defect-based test coverage.

[0041] In step 114, one or more reports are generated for one or more gap regions in defect-based test coverage on one or more semiconductor devices. In some embodiments, system 200 includes a results subsystem 214 or subsystem E. Results subsystem 214 may receive information output by positioning subsystem 212 regarding the location and / or frequency of significant killer defects in semiconductor dies that passed a selected subset or all of the performed tests. Results subsystem 214 may prepare a report including one or more metrics and / or one or more graphical functions to present the results in a form configured to assist semiconductor manufacturers in taking corrective actions and / or evaluating the effectiveness of test program changes. For example, examples of corrective actions may include, but are not limited to, temporary relief of test gaps through inspection screening (e.g., I-PAT or the like), improvements resulting from adjusting the test program to provide greater coverage of determined gap regions in defect-based test coverage, or the like.

[0042] Examples of implementing I-PAT can be found in U.S. Patent No. 10,761,128, issued on September 1, 2020, and U.S. Patent Application No. 17 / 101,856, filed on November 23, 2020, each of which was previously incorporated herein in its entirety. The examples provided in the incorporated patents and applications focus on identifying specific dies at high risk for product handling (e.g., "screening") purposes to test coverage gaps. However, it should be noted herein that the present disclosure relates to automatically and systematically identifying risk areas of a semiconductor device to improve the inherent reliability of all chips of the semiconductor device and / or guide mitigation efforts, and screening data may not be required as input. In this regard, I-PAT may be implemented in the present disclosure, but is not required.

[0043] Figures 4A to 4C A conceptual illustration illustrating output from the results subsystem 214 in accordance with one or more embodiments of the present disclosure.

[0044] exist Figure 4A , image 400 illustrates one or more functional semiconductor die blocks 402 within a semiconductor die layout 404 .

[0045] exist Figure 4B 4, image 410 illustrates one or more apparent killer defects 412 from all semiconductor dies analyzed after a selected subset or all of the tests have been performed, wherein the one or more apparent killer defects 412 overlie one or more functional semiconductor die blocks 402 within semiconductor die layout 404. For example, image 410 may represent apparent killer defects as determined by characterization subsystem 204.

[0046] exist Figure 4C4, image 420 illustrates one or more significant killer defects 412 that pass a selected subset or all of the performed tests within a gap region 422 in defect-based test coverage, wherein the gap region 422 overlies one or more functional semiconductor die blocks 402 within semiconductor die layout 404. For example, image 420 may represent gap region 422 as determined by association subsystem 210.

[0047] It should be noted herein that the exact layout and / or configuration thereof in images 400, 410, 420 is for illustration purposes only. For example, the exact layout of semiconductor die block 402 may differ from Figures 4A to 4C As another example, the graphical illustration of the apparent fatal defect 412 and / or the gap area 422 may be different from that shown in FIG. Figure 4B and 4C Therefore, the above description should not be construed as limiting the scope of the present disclosure but is merely illustrative.

[0048] Figures 5A to 5B The generated metrics in the form of graphical output from the results subsystem 214 are illustrated for demonstrating improvements in semiconductor devices over time in accordance with one or more embodiments of the present disclosure.

[0049] exist Figure 5A , a graph 500 illustrates a particular tested semiconductor device design divided into a pass percentage 502 and a fail percentage 504 compared to a time frame, where the fail percentage may represent a potential gap area in defect-based test coverage. For example, the time frame may be quarterly, monthly, weekly, daily, or the like. Figure 5A As illustrated in , the test coverage gap trend over time may improve (eg, the ratio between the pass percentage 502 and the fail percentage 504 increases) as mitigation steps are taken to adjust the manufacturing, characterization, and / or testing of semiconductor devices.

[0050] exist Figure 5B , a graph 510 illustrates a plurality of different tested semiconductor device designs (1) through (5) across a product line or combination divided into pass percentages 502 and fail percentages 504 at a particular moment in time and / or within a time range, wherein the fail percentages may represent potential gap areas in defect-based test coverage. Figure 5B As illustrated in the figures, selected semiconductor devices (e.g., devices (2) to (4)) can be separated out for use in higher threshold environments (e.g., automobiles or the like requiring failure rates in the parts per billion (PPB) range), while other semiconductor devices (e.g., devices (1) and (5)) can be separated out for use in lower threshold environments (e.g., televisions, smart phones, or the like requiring failure rates in the parts per million (PPM) range).

[0051] It should be noted herein that the exact layout and / or configuration of the diagrams 500, 510 is for illustration purposes only. Figure 5A and 5B As another example, charts 500, 510 may provide a different type of data display tool than the bar chart described in Figure 5A and 5B Therefore, the above description should not be construed as limiting the scope of the present disclosure but is merely illustrative.

[0052] Although the embodiments of the present disclosure illustrate that subsystems 204, 208, 210, 212, 214 are separate or independent subsystems within system 200, it should be noted herein that one or more of subsystems 204, 208, 210, 212, 214 may be combined or integrated subsystems. Therefore, the above description should not be construed as limiting the scope of the present disclosure but is merely illustrative.

[0053] In step 116, one or more adjustments to at least one of manufacturing, characterization, or testing of semiconductor devices are determined based on one or more gap regions for defect-based test coverage on one or more semiconductor devices. In some embodiments, the system 200 may output information to an external system or subsystem, wherein the information includes corrective actions for modifying the manufacturing, characterization, and / or testing of the semiconductor devices. For example, a set of mitigation steps 216 may include calibrating areas of interest (e.g., I-PAT areas of interest or the like) provided to the external system or subsystem in a feed-forward loop. For example, the target areas of interest may include detailed or fine-tuned inspections of inkjet or scrap semiconductor dies (e.g., generated via one or more control signals). As another example, a set of mitigation steps 218 may include modifications to a manufacturing process or method, a characterization process or method, a testing process or method, or the like provided to the external system or subsystem in a feedback loop. For example, a manufacturing process or method, a characterization process or method, a testing process or method, or the like may be adjusted (e.g., via one or more control signals) based on the determined gap regions in defect-based test coverage. It should be noted herein that either or both of the set of mitigation steps 216, 218 may be performed separately as independent processes, the set of mitigation steps 216, 218 may be performed in any sequential order, or the set of mitigation steps 216, 218 may be performed simultaneously.

[0054] In some embodiments, for purposes of the present disclosure, system 200 , one or more semiconductor manufacturing subsystems 202 , and one or more test tool subsystems 206 are part of a semiconductor device manufacturing and defect-based test coverage gap identification system 220 .

[0055] Figure 6A method or process 600 for automatically identifying defect-based test coverage gaps in a semiconductor device is described in accordance with one or more embodiments of the present disclosure. Fig. 7A and 7B A block diagram illustrating a semiconductor device fabrication and defect-based test coverage gap identification system 220 or "system 220" according to one or more embodiments of the present disclosure. It should be noted herein that the system 220 may be configured to perform processing steps to fabricate and / or analyze semiconductor dies, as described throughout the present disclosure. Additionally, it should be noted herein that the steps of the method or process 600 may be implemented in whole or in part by the system 220 illustrated in FIG. 7. However, it should be further appreciated that the method or process 600 is not limited to the system 220 illustrated in FIG. 7, as additional or alternative system-level embodiments may implement all or part of the steps of the method or process 600.

[0056] In step 602 , characterization measurements are acquired for one or more semiconductor devices. In some embodiments, system 220 includes one or more semiconductor manufacturing subsystems 202 .

[0057] In one non-limiting example, one or more semiconductor manufacturing subsystems 202 may include at least one inspection tool 700 (e.g., an in-line sample analysis tool) for detecting defects in one or more layers of a sample 702. The system 220 may generally include any number or type of inspection tools 700. For example, the inspection tool 700 may include an optical inspection tool configured to detect defects based on interrogation of the sample 702 using light from any source, such as, but not limited to, a laser source, a lamp source, an X-ray source, or a broadband plasma source. As another example, the inspection tool 700 may include a particle beam inspection tool configured to detect defects based on interrogation of the sample using one or more particle beams, such as, but not limited to, an electron beam, an ion beam, or a neutral particle beam. For example, the inspection tool 700 may include a transmission electron microscope (TEM) or a scanning electron microscope (SEM). For the purposes of this disclosure, it should be noted herein that the at least one inspection tool 700 may be a single inspection tool 700 or may represent a group of inspection tools 700.

[0058] It is noted herein that the sample 702 may be a semiconductor wafer of a plurality of semiconductor wafers, wherein each semiconductor wafer of the plurality of semiconductor wafers includes a plurality of layers, wherein each layer of the plurality of layers includes a plurality of semiconductor dies, wherein each semiconductor die of the plurality of semiconductor dies includes a plurality of blocks. Additionally, it is noted herein that the sample 702 may be a semiconductor die package formed of a plurality of semiconductor dies arranged as a 2.5D lateral combination of dies on a substrate within an advanced die package or a 3D die package.

[0059] For the purposes of this disclosure, the term "defect" may refer to a physical defect found by an in-line inspection tool, a metric measurement outlier, or other physical characteristics of a semiconductor device that are considered abnormal. A defect may be considered any deviation from the designed characteristics of a manufactured layer or a manufactured pattern in a layer, including, but not limited to, physical, mechanical, chemical, or optical properties. In addition, a defect may be considered any deviation from the alignment or bonding of components in a manufactured semiconductor die package. In addition, a defect may have any size relative to a semiconductor die or a feature thereon. In this way, a defect may be smaller than a semiconductor die (e.g., in proportion to one or more patterned features), or may be larger than a semiconductor die (e.g., as part of a wafer-level scratch or pattern). For example, a defect may include a deviation in the thickness or composition of a sample layer before or after patterning. For another example, a defect may include a deviation in the size, shape, orientation, or position of a patterned feature. For another example, a defect may include defects associated with a lithography and / or etching step, such as, but not limited to, a bridge (or lack of a bridge), a pit, or a hole between adjacent structures. As another example, a defect may include a damaged portion of the sample 702, such as, but not limited to, a scratch or chip. For example, the severity of the defect (e.g., the length of the scratch, the depth of the pit, the measured magnitude or polarity of the defect, or the like) may be important and considered. As another example, a defect may include a foreign particle introduced into the sample 702. As another example, a defect may be a misalignment and / or mis-bonding of a package component on the sample 702. Therefore, it should be understood that the examples of defects in the present disclosure are for illustrative purposes only and should not be construed as limiting.

[0060] In another non-limiting example, the one or more semiconductor manufacturing subsystems 202 include at least one metrology tool 704 (e.g., an in-line sample analysis tool) for measuring one or more properties of the sample 702 or one or more layers thereof. For example, the metrology tool 704 may characterize properties such as, but not limited to, layer thickness, layer composition, critical dimension (CD), overlay, or lithography process parameters such as the intensity or dose of illumination during a lithography step. In this regard, the metrology tool 704 may provide information about the fabrication of the sample 702, one or more layers of the sample 702, or one or more dies of the sample 702 that may be related to the probability of manufacturing defects that may lead to reliability issues for the resulting manufactured devices. For purposes of this disclosure, it should be noted herein that the at least one metrology tool 704 may be a single metrology tool 704, or may represent a group of metrology tools 704.

[0061] In some embodiments, the one or more semiconductor manufacturing subsystems 202 include at least one semiconductor manufacturing tool or process tool 706. For example, the process tool 706 may include any tool known in the art, including, but not limited to, an etcher, a scanner, a stepper, a cleaner, or the like. For example, a manufacturing process may include manufacturing a plurality of dies distributed across a surface of a sample, such as a semiconductor wafer or the like, wherein each die includes a plurality of patterned material layers forming device components. Each patterned layer may be formed by the process tool 706 through a series of steps including material deposition, photolithography, etching to produce a pattern of interest, and / or one or more exposure steps, such as performed by a scanner, a stepper, or the like. As another example, the process tool 706 may include any tool known in the art configured to package and / or combine semiconductor dies into 2.5D and / or 3D semiconductor die packages. For example, a manufacturing process may include, but not limited to, aligning semiconductor dies and / or electrical components on semiconductor dies. Additionally, the manufacturing process may include, but is not limited to, bonding semiconductor dies and / or electrical components on the semiconductor dies via hybrid bonding (e.g., die-to-die, die-to-wafer, wafer-to-wafer, or the like), solder, adhesives, fasteners, or the like. For purposes of this disclosure, it should be noted herein that the at least one process tool 706 may be a single process tool 706, or may represent a group of process tools 706.

[0062] In step 604, test measurements are acquired for one or more semiconductor dies on one or more semiconductor devices. In some embodiments, system 220 includes one or more test tool subsystems 206 for testing functionality of one or more portions of a manufactured device.

[0063] In one non-limiting example, the one or more test tool subsystems 206 may include any number or type of electrical test tools 708 used to complete initial probing at the wafer level. For example, the initial probing may not be designed to attempt to force failures at the wafer level.

[0064] In another non-limiting example, the one or more test tool subsystems 206 may include any number or type of stress test tools 710 for testing, verifying, or otherwise characterizing properties of one or more portions of a manufactured device at any point in the manufacturing cycle. For example, the stress test tools 710 may include, but are not limited to, pre-burn-in electrical wafer sort and final testing (e.g., e-testing) or post-burn-in electrical testing configured to heat the sample 702 (e.g., an oven or other heat source), cool the sample 702 (e.g., a freezer or other cold source), operate the sample 702 at an inappropriate voltage (e.g., a power supply), or the like.

[0065] In some embodiments, defects are identified using any combination of characterization subsystem 204 (e.g., inspection tool 700, metrology tool 704, or the like), test tool subsystem 206 (e.g., including electrical test tool 708 and / or stress test tool 710, or the like) after one or more processing steps (e.g., lithography, etching, alignment, bonding, or the like) performed by one or more process tools 706 on a layer of interest in a semiconductor die and / or semiconductor die package. In this regard, defect detection at various stages of the manufacturing process may be referred to as in-line defect detection.

[0066] In step 606, the characterization measurements and the test measurements are automatically transmitted to a system for determining one or more gap regions in defect-based test coverage of one or more semiconductor devices.

[0067] In some embodiments, system 220 includes a controller 712. Controller 712 may include one or more processors 714 configured to execute program instructions maintained on a memory 716 (e.g., a memory medium, a memory device, or the like). Furthermore, controller 712 may be communicatively coupled with any of the components of system 220 including, but not limited to, an inspection tool 700, a metrology tool 704, a test tool 708 (including an electrical test tool 708 and / or a stress test tool 710), system 200, or the like.

[0068] One or more steps of the method or process 100 may be performed automatically. For example, one or more processors 714 of the controller 712 may be configured to: receive information for characterization measurements performed on a selected semiconductor device; determine one or more significant killer defects from the information of in-line inspection and metrology measurements; receive information for test measurements performed on a selected semiconductor device; determine one or more semiconductor dies that passed a selected test from the test measurements performed on the selected semiconductor device; correlate the information received for characterization measurements performed on the selected semiconductor device with the information received for test measurements performed on the selected semiconductor device; determine one or more gap regions of defect-based test coverage from the correlated information; and / or determine one or more adjustments to the manufacturing, characterization, and / or testing of the semiconductor device based on the determined one or more gap regions. It should be noted herein that one or more steps of the method or process 100 may be performed continuously as new data becomes available from the characterization measurements on an ongoing basis.

[0069] The one or more processors 714 of the controller 712 may include any processor or processing element known in the art. For the purposes of this disclosure, the term "processor" or "processing element" may be broadly defined to encompass any device having one or more processing or logic elements (e.g., one or more microprocessor devices, one or more application specific integrated circuit (ASIC) devices, one or more field programmable gate arrays (FPGAs), or one or more digital signal processors (DSPs)). In this sense, the one or more processors 714 of the controller 712 may include any device configured to execute algorithms and / or instructions (e.g., program instructions stored in a memory). In one embodiment, the one or more processors 714 of the controller 712 may be embodied as a desktop computer, a mainframe computer system, a workstation, an image computer, a parallel processor, a networked computer, or any other computer system configured to execute a program configured to operate components of the system 200 or operate in conjunction with components of the system 200, as described throughout this disclosure.

[0070] The memory 716 of the controller 712 may include any storage media known in the art suitable for storing program instructions that can be executed by the associated corresponding one or more processors 714 of the controller 712. For example, the memory 716 of the controller 712 may include a non-transitory memory medium. As another example, the memory 716 of the controller 712 may include, but is not limited to, a read-only memory (ROM), a random access memory (RAM), a magnetic or optical storage device (such as a disk), a tape, a solid-state drive, and the like. It should be further noted that the memory 716 of the controller 712 may be housed in a common controller housing along with the one or more processors 714. In one embodiment, the memory 716 of the controller 712 may be remotely located relative to the physical location of the corresponding one or more processors 714 of the controller 712. For example, the corresponding one or more processors 714 of the controller 712 may access a remote memory (such as a server) that is accessible via a network (such as the Internet, an intranet, and the like).

[0071] In another embodiment, the system 220 includes a user interface 718 coupled (e.g., physically coupled, electrically coupled, communicatively coupled, or the like) to the controller 712. For example, the user interface 718 can be a separate device coupled to the controller 712. As another example, the user interface 718 and the controller 712 can be located within a common or shared housing. However, it should be noted herein that the controller 712 may not include, require, or be coupled to the user interface 718.

[0072] The user interface 718 of the controller 712 may include, but is not limited to, one or more desktop computers, laptop computers, tablet computers, and the like. The user interface 718 of the controller 712 may include a display for displaying data of the system 200 to a user. The display of the user interface 718 of the controller 712 may include any display known in the art. For example, the display may include, but is not limited to, a liquid crystal display (LCD), an organic light emitting diode (OLED)-based display, or a CRT display. Those skilled in the art will recognize that any display device capable of being integrated with the user interface 718 of the controller 712 is suitable for implementation in the present disclosure. In another embodiment, a user may input selections and / or instructions via a user input device of the user interface 718 of the controller 712 in response to data displayed to the user.

[0073] In step 608, one or more control signals are generated for one or more adjustments to one or more gap regions in defect-based test coverage based on at least one of fabrication, characterization, or testing of the one or more semiconductor devices. For example, the one or more control signals may adjust the one or more semiconductor manufacturing subsystems 202 and / or one or more manufacturing processes or methods or one or more characterization processes or methods employed by the one or more semiconductor manufacturing subsystems 202 via a feed-forward loop (e.g., to correct a current semiconductor device) or a feedback loop (e.g., to adjust a future semiconductor device). As another example, the one or more control signals may adjust the one or more test tool subsystems 206 and / or one or more test processes or methods employed by the one or more test tool subsystems 206 via a feed-forward loop (e.g., to correct a current semiconductor device) or a feedback loop (e.g., to adjust a future semiconductor device).

[0074] Although the embodiments of the present disclosure illustrate the steps of the method or process 100, 600 as being performed by the controller 712, it should be noted herein that some or all of the steps of the method or process 100, 600 may be performed by a server or controller communicatively coupled to the controller 712. For example, the server or controller may include a processor and a memory and other communicatively coupled components described throughout the present disclosure.

[0075] It should be noted herein that for the purpose of this disclosure, Fig. 7A The embodiments described in Figure 7B The embodiments described in the may be considered as part of the same system 220, part of a different system 220, or part of a different subsystem of a different system 220. For example, where the system 220 includes in-line characterization, the characterization tools 700, 704, and / or the process tools 706 may be organized to receive the sample 702 at different stages during the manufacture of the sample 702. Additionally, it should be noted herein that Fig. 7A The components within the system 220 described in Figure 7B The components within the system 220 illustrated in FIG. 7 may communicate directly or may communicate through the controller 712 .

[0076] It should be noted herein that the methods or processes 100 and 600 are not limited to the steps and / or sub-steps provided. The methods or processes 100 and 600 may include more or fewer steps and / or sub-steps. The methods or processes 100 and 600 may perform the steps and / or sub-steps simultaneously. The methods or processes 100 and 600 may perform the steps and / or sub-steps sequentially (including in the order provided or in an order other than the order provided). Therefore, the above description should not be construed as limiting the scope of the present disclosure but is merely illustrative.

[0077] In this regard, the system 200 (and system 220) and method or process 100 can provide an economic trade-off between test time and the number of semiconductor die feedbacks attributable to gap areas in defect-based test coverage. Additionally, the system 200 (and system 220) and method or process 100 can provide semiconductor manufacturers with an accurate empirical map of semiconductor die areas at higher reliability risk and / or a quantitative comparison of the percentage area of ​​gaps in defect-based test coverage among semiconductor device designs.

[0078] For example, the improved insight into baseline test coverage gaps that system 200 (and system 220) and method or process 100 can provide will help enable automotive semiconductor device manufacturers to reduce reliability failures from the PPM to PPB range. Semiconductor failures are the number one failure item in automotive manufacturing, and the problem will become more prominent as automotive semiconductor content increases (e.g., with the implementation of autonomous driving and electric vehicles). Similarly, reliability issues are becoming increasingly important in industrial, biomedical, defense, aerospace, hyperscale data centers, and the like. Identifying test coverage gaps will make us aware of the limitations of electrical test methods and therefore drive the adoption of in-line defect screening inspection to mitigate these problems.

[0079] In one non-limiting example, inline characterization may be performed at selected (e.g., critical) layers. At user-selectable time intervals (e.g., quarterly, monthly, weekly, or the like), the system 200 may generate reports of all semiconductor devices monitored via one or more steps of the method or process 100 to provide a baseline of test coverage gaps across semiconductor devices. For example, a report may sound an alarm when a selected area of ​​a semiconductor device has a statistically elevated level of significant fatal defects in semiconductor dies that pass all tests. It should be noted herein that a report may be automatically triggered once a predetermined threshold is reached. In addition, it should be noted herein that for devices that are highly inspected for reliability issues, the reporting frequency may be increased to understand improvements over time. Furthermore, it should be noted herein that a design of experiments (DOE) study may be performed to reduce test coverage gaps by changing the test protocol. Furthermore, it should be noted herein that the system 200 may provide real-time feedback on the efficacy of such changes, thereby allowing the system 200 and the method or process 100 to be used when restricting new / future devices and / or during a "safety release" activity.

[0080] Advantages of the present disclosure relate to systems and methods for automatically identifying defect-based test coverage gaps in semiconductor devices. In particular, advantages of the present disclosure relate to allowing automatic identification of previously unknown locations within a design that have increased susceptibility to reliability escapes from killer defects in test gaps. Advantages of the present disclosure also relate to using empirical defect data to systematically identify test coverage gaps. Advantages of the present disclosure also relate to providing new metrics and / or graphs to demonstrate continuous improvement, evaluate the effectiveness of test program changes, and quantify test gap differences over time as improvements are made on a device-by-device basis or between different devices in a product portfolio.

[0081] The subject matter described herein sometimes illustrates different components contained within or connected to other components. It should be understood that such depicted architectures are for illustration only, and in fact, many other architectures that implement the same functionality can be implemented. In a conceptual sense, any arrangement of components that implement the same functionality is effectively "associated" so that the desired functionality is achieved. Therefore, any two components combined to achieve a specific functionality in this article can be considered to be "associated" with each other so that the desired functionality is achieved, regardless of the architecture or intermediate components. Similarly, any two components so associated can also be considered to be "connected" or "coupled" to each other to achieve the desired functionality, and any two components that can be so associated can also be considered to be "coupleable" to each other to achieve the desired functionality. Specific examples that can be coupled include (but are not limited to) physically interactive and / or physically interactive components and / or wirelessly interactive and / or wirelessly interactive components and / or logically interactive and / or logically interactive components.

[0082] It is believed that the present disclosure and many of its attendant advantages will be appreciated from the foregoing description, and it will be appreciated that various changes may be made in the form, construction, and arrangement of components without departing from the disclosed subject matter or sacrificing all of its significant advantages. The forms described are for illustrative purposes only and it is intended that such changes be encompassed and included by the following claims. Furthermore, it will be understood that the invention is defined by the appended claims.

Claims

1. An automatic identification system, comprising: A controller communicatively coupled to the one or more semiconductor manufacturing subsystems and the one or more test tool subsystems, the controller comprising one or more processors configured to execute program instructions that cause the one or more processors to: determining, via a characterization subsystem, a plurality of significant killer defects on the one or more semiconductor devices based on characterization measurements of the one or more semiconductor devices acquired by the one or more semiconductor manufacturing subsystems, wherein the one or more semiconductor devices include a plurality of semiconductor dies; determining, via a test subsystem, at least one semiconductor die of the plurality of semiconductor die that passes at least one of a plurality of tests based on test measurements acquired by the one or more test tool subsystems; correlating, via a correlation subsystem, the characterization measurements with the test measurements to determine at least one of the plurality of clear-killing defects on the at least one semiconductor die of the plurality of semiconductor dies that passed the at least one test of the plurality of tests; and One or more gap regions covered for defect-based testing on the one or more semiconductor devices are determined via a positioning subsystem based on the at least one significant killer defect on the at least one semiconductor die of the plurality of semiconductor dies that passed the at least one test of the plurality of tests.

2. The automatic identification system according to claim 1, wherein the one or more processors are further configured to execute the program instructions, which cause the one or more processors to: The characterization measurements acquired by the one or more semiconductor fabrication subsystems during fabrication of the one or more semiconductor devices are received via the characterization subsystem. 3 . The automatic identification system of claim 1 , wherein the characterization subsystem comprises one or more characterization tools configured to perform at least one of one or more in-line defect inspection processes or one or more metrology processes. 4 . The automatic identification system of claim 1 , wherein the characterization subsystem is configured to employ advanced deep learning techniques to determine the plurality of significant killer defects on the one or more semiconductor devices based on the characterization measurements. 5 . The automatic identification system of claim 1 , wherein the characterization subsystem is configured to employ machine learning techniques to determine the plurality of significant killer defects on the one or more semiconductor devices based on the characterization measurements.

6. The automatic identification system according to claim 1, wherein the one or more processors are further configured to execute the program instructions, which cause the one or more processors to: The test measurements for the one or more semiconductor devices acquired by the one or more test tool subsystems are received via the test subsystem.

7. The automatic identification system of claim 1, wherein the one or more test tool subsystems include one or more test tools configured to perform at least one of one or more electrical wafer sorting processes, unit detection processes, class detection processes, or final test processes. 8 . The automatic identification system of claim 1 , wherein the at least one semiconductor die of the plurality of semiconductor die passes all tests of the plurality of tests.

9. The automatic identification system of claim 1, wherein the positioning subsystem analyzes at least one of a location or a frequency of the at least one of the plurality of clear killer defects on the at least one of the plurality of semiconductor dies that passed the at least one of the plurality of tests.

10. The automatic identification system according to claim 1, wherein the one or more processors are further configured to execute the program instructions, which cause the one or more processors to: One or more reports are generated based on the one or more gap regions in defect-based test coverage on the one or more semiconductor devices.

11. An automatic identification system according to claim 10, wherein the one or more reports include at least one metric for adjusting at least one of the one or more semiconductor manufacturing subsystems or the one or more test tool subsystems to mitigate defect-based test coverage of the one or more gap regions on the one or more semiconductor devices.

12. The automatic identification system of claim 10, wherein the one or more reports include at least one graph configured to evaluate defect-based test coverage of the one or more interstitial regions on the one or more semiconductor devices.

13. The automatic identification system of claim 12, wherein the at least one graph is configured to compare test coverage gap trends over a time range for a particular semiconductor device design.

14. The automatic identification system of claim 12, wherein the at least one graph is configured to compare test coverage gaps of a plurality of semiconductor device designs.

15. The automatic identification system of claim 1, wherein the one or more processors are further configured to execute the program instructions, which cause the one or more processors to: One or more adjustments to at least one of manufacturing, characterization, or testing of the semiconductor devices are determined based on the one or more gap regions on the one or more semiconductor devices covered by the defect-based testing.

16. The automatic identification system of claim 15, wherein the one or more processors are further configured to execute the program instructions, which cause the one or more processors to: One or more control signals are generated based on the one or more adjustments to at least one of the manufacturing, characterization, or testing of the semiconductor device.

17. The automatic identification system of claim 16, wherein the one or more control signals are configured to target an In-Line Defect Partial Average Test (I-PAT) region of interest on the semiconductor device.

18. An automatic identification method, comprising: determining, via a characterization subsystem of a controller, a plurality of significant killer defects on one or more semiconductor devices based on characterization measurements of the one or more semiconductor devices acquired by one or more semiconductor manufacturing subsystems, wherein the one or more semiconductor devices include a plurality of semiconductor dies; determining, via a test subsystem of the controller, at least one semiconductor die of the plurality of semiconductor die that passes at least one of a plurality of tests based on test measurements acquired by one or more test tool subsystems; correlating, via a correlation subsystem of the controller, the characterization measurements with the test measurements to determine at least one of the plurality of clear-killing defects on the at least one semiconductor die of the plurality of semiconductor dies that passed the at least one test of the plurality of tests; and One or more gap regions covered for defect-based testing on the one or more semiconductor devices are determined via a positioning subsystem of the controller based on the at least one significant killer defect on the at least one semiconductor die of the plurality of semiconductor dies that passed the at least one test of the plurality of tests.

19. The automatic identification method according to claim 18, further comprising: The characterization measurements acquired by the one or more semiconductor fabrication subsystems during fabrication of the one or more semiconductor devices are received by the characterization subsystem via the controller.

20. The automatic identification method of claim 18, wherein the characterization subsystem comprises one or more characterization tools configured to perform at least one of one or more in-line defect inspection processes or one or more metrology processes.

21. The automatic identification method of claim 18, wherein the characterization subsystem is configured to employ advanced deep learning techniques to determine the plurality of significant killer defects on the one or more semiconductor devices based on the characterization measurements.

22. The automatic identification method of claim 18, wherein the characterization subsystem is configured to employ machine learning techniques to determine the plurality of significant killer defects on the one or more semiconductor devices based on the characterization measurements.

23. The automatic identification method according to claim 18, further comprising: The test measurements for the one or more semiconductor devices acquired by the one or more test tool subsystems are received by the test subsystem via the controller.

24. The automatic identification method of claim 18, wherein the one or more test tool subsystems include one or more test tools configured to perform at least one of one or more electrical wafer sorting processes, unit probing processes, class probing processes, or final test processes.

25. The automatic identification method of claim 18, wherein the at least one semiconductor die of the plurality of semiconductor dies passes all tests of the plurality of tests.

26. The automatic identification method of claim 18, wherein the positioning subsystem analyzes at least one of a location or a frequency of the at least one of the plurality of clear killer defects on the at least one of the plurality of semiconductor dies that passed the at least one of the plurality of tests.

27. The automatic identification method according to claim 18, further comprising: One or more reports are generated via the controller based on the one or more gap regions in defect-based test coverage on the one or more semiconductor devices.

28. An automatic identification method according to claim 27, wherein the one or more reports include at least one metric for adjusting the one or more semiconductor manufacturing subsystems or at least one of the one or more test tool subsystems to mitigate defect-based test coverage of the one or more gap regions on the one or more semiconductor devices.

29. The automatic identification method of claim 27, wherein the one or more reports include at least one graph configured to evaluate defect-based test coverage of the one or more interstitial regions on the one or more semiconductor devices.

30. The automatic identification method of claim 29, wherein the at least one graph is configured to compare test coverage gap trends over a time range for a particular semiconductor device design.

31. The automatic identification method of claim 29, wherein the at least one graph is configured to compare test coverage gaps of a plurality of semiconductor device designs.

32. The automatic identification method according to claim 18, further comprising: One or more adjustments to at least one of manufacturing, characterization, or testing of the semiconductor devices are determined via the controller based on the one or more gap regions on the one or more semiconductor devices covered by the defect-based test.

33. The automatic identification method according to claim 32, further comprising: One or more control signals are generated via the controller based on the one or more adjustments to at least one of the manufacturing, characterization, or testing of the semiconductor device.

34. The automatic identification method of claim 33, wherein the one or more control signals are configured to target an In-Line Defect Partial Average Test (I-PAT) region of interest on the semiconductor device.

35. An automatic identification system comprising: one or more semiconductor manufacturing subsystems; one or more test harness subsystems; and a controller communicatively coupled to the one or more semiconductor manufacturing subsystems and the one or more test tool subsystems, the controller comprising one or more processors configured to execute program instructions that cause the one or more processors to: determining, via a characterization subsystem, a plurality of significant killer defects on the one or more semiconductor devices based on characterization measurements of the one or more semiconductor devices acquired by the one or more semiconductor manufacturing subsystems, wherein the one or more semiconductor devices include a plurality of semiconductor dies; determining, via a test subsystem, at least one semiconductor die of the plurality of semiconductor die that passes at least one of a plurality of tests based on test measurements acquired by the one or more test tool subsystems; correlating, via a correlation subsystem, the characterization measurements with the test measurements to determine at least one of the plurality of clear-killing defects on the at least one semiconductor die of the plurality of semiconductor dies that passed the at least one test of the plurality of tests; and One or more gap regions covered for defect-based testing on the one or more semiconductor devices are determined via a positioning subsystem based on the at least one significant killer defect on the at least one semiconductor die of the plurality of semiconductor dies that passed the at least one test of the plurality of tests.

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