Through-silicon via fault detection circuit, apparatus, and detection method

Abstract

The application discloses a through silicon via (TSV) fault detection circuit, device and detection method, and relates to the field of integrated circuit testing. The application provides a technical scheme for solving the technical problems of low fault detection precision, long test time and large test structure cost in the prior art, and the technical scheme comprises the following steps: the TSV fault detection circuit is applied to a TSV array, and the circuit comprises an input end, a first inverter, a second inverter, a third inverter, a fourth inverter, a transmission gate, a TSPC flip-flop and a reference circuit; the input end is connected with the first inverter, the third inverter, the transmission gate and the D end of the TSPC flip-flop in sequence; the input end is also connected with the second inverter, the fourth inverter and the clock end of the TSPC flip-flop in sequence; the output end of the reference circuit is connected to the input end of the fourth inverter; and the input end of the third inverter is used for connecting the output end of the TSV array to be tested. The application is suitable for application in high-density TSV array fault detection work.

Description

Technical Field

[0001] This relates to the field of integrated circuit testing, specifically a method for detecting through-silicon via (TSPC) faults based on TSPC triggers. Background Technology

[0002] The emergence of Through Silicon Via (TSV) technology has brought a new turning point to the high integration of microsystems. TSV-based 3D integration is a key technology for realizing future high-performance integrated circuits; however, TSV testing is a bottleneck restricting the industrialization of 3D integrated circuits. First, defects or flaws can occur during TSV manufacturing due to process variations or contamination, leading to different types and degrees of circuit failures. However, existing technologies lack practical testing methods and tools for online detection of faulty TSVs. Second, as the integration density of 3D integrated circuits increases, TSV technology will continue to miniaturize in terms of the number of stacked layers in the vertical direction, silicon wafer thickness, TSV diameter, and pin spacing. For example, the number of stacked layers in the vertical direction will increase from 3-7 bare chip layers to 14 bare chip layers; the silicon wafer thickness will decrease from 20-50 μm to 8 μm; the TSV diameter will shrink from 4.0 μm to below 1.6 μm; and the pin spacing will decrease from 10 μm to 3.3 μm. Therefore, the increased integration density of 3D integrated circuits increases the difficulty of testing large-scale, high-density TSV arrays. Third, as TSV density increases, coupling between adjacent TSVs increases, especially when the operating frequency of 3D integrated circuits rises to the millimeter-wave or submillimeter-wave bands. The impact of TSV parasitic parameters becomes significant. As TSVs are crucial for signal integrity in high-speed channels, TSV testing needs to be more accurate and comprehensive. TSV technology has enabled the transformation of integrated circuits from two-dimensional to three-dimensional, and through-silicon via (TSV) technology provides a high-bandwidth, low-latency, and scalable solution. However, as an emerging process, TSV manufacturing may contain various defects that can lead to parametric failures. High-density TSV arrays necessitate consideration of testing time and cost. Therefore, effective TSV fault detection methods can improve chip reliability and production yield.

[0003] Through-Silicon Vias (TSVs) may suffer from voids, open circuits, and leakage faults during fabrication. These faults, especially those occurring before bonding, are characterized by weak features, making detection particularly difficult. Furthermore, when multiple faults coexist, the test structure may produce false readings. Although various fault detection methods have been proposed for TSV testing, such as ring oscillator-based and pulse reduction-based methods, these methods suffer from low detection accuracy, long testing times, and high test structure costs. Therefore, establishing a test structure with high accuracy and low area overhead is crucial for improving the yield and reliability of 3D integrated circuits. Summary of the Invention

[0004] To address the technical problems of low fault detection accuracy, long testing time, and high test structure cost in existing testing methods for through-silicon vias, the present invention provides the following technical solution:

[0005] A through-silicon via (TSV) fault detection circuit, applied to a TSV array, includes:

[0006] Input terminal, first inverter, second inverter, third inverter, fourth inverter, transmission gate, TSPC flip-flop and reference circuit;

[0007] The input terminal is connected in series with the D terminal of the first inverter, the second inverter, the transmission gate, and the TSPC flip-flop in sequence;

[0008] The input terminal is connected in series with the clock terminals of the third inverter, the fourth inverter, and the TSPC flip-flop in sequence.

[0009] The output of the reference circuit is connected to the input of the fourth inverter.

[0010] The input terminal of the third inverter is used to connect to the output terminal of the TSV array under test.

[0011] Furthermore, a preferred embodiment is provided, wherein the first inverter and the second inverter are respectively composed of a PMOS transistor and an NMOS transistor connected in parallel, and the PMOS transistor is connected to the power supply, while the NMOS transistor is grounded.

[0012] Furthermore, a preferred embodiment is provided in which the drains of the PMOS transistor and the NMOS transistor are connected together, and the source terminals are connected to the power supply and ground, respectively.

[0013] Furthermore, a preferred embodiment is provided in which the reference circuit includes a capacitor.

[0014] Furthermore, a preferred embodiment is provided in which the capacitor is equivalent to a fault-free TSV array.

[0015] Furthermore, a preferred embodiment is provided, wherein the device includes the aforementioned through-silicon via (TSV) fault detection circuit.

[0016] A through-silicon via (TSV) fault detection method is applied to a TSV array, and the method is implemented through the aforementioned TSV fault detection circuit.

[0017] The method includes:

[0018] The steps for outputting a low-level signal;

[0019] The steps for outputting a charging signal;

[0020] The steps to output a high-level signal;

[0021] The steps for outputting a discharge signal;

[0022] The steps for acquiring the output signal;

[0023] The judgment steps for determining whether a fault exists based on the output signal.

[0024] Furthermore, a preferred embodiment is provided, wherein the determination step specifically comprises:

[0025] The steps for acquiring the D terminal level of the TSPC flip-flop;

[0026] The step is to determine if a high level occurs at terminal D, and then output a fault result.

[0027] A computer storage medium for storing a computer program, which, when read by a computer, executes the through-silicon via (TSV) fault detection method.

[0028] A computer, including a processor and a storage medium, executes the through-silicon via (TSV) fault detection method when the processor reads a computer program stored in the storage medium.

[0029] Compared with the prior art, the advantages of the technical solution provided by the present invention are as follows:

[0030] The through-silicon via (TSV) fault detection method provided by this invention utilizes the principle of reduced discharge time of faulty TSVs. It compares the discharge time of the tested TSV with that of a reference TSV. When there is no difference in discharge time between the tested TSV and the reference TSV, the TSV is considered to be fault-free; otherwise, a fault exists. The discharge time comparison result is given by the fault detection circuit.

[0031] The through-silicon via (TSV) fault detection method provided by this invention can detect TSVs with void faults, open circuit faults, leakage faults, and two or more of these faults coexisting. It has high fault detection accuracy, wide coverage, and low testing cost.

[0032] Suitable for use in high-density TSV array fault detection. Attached Figure Description

[0033] Figure 1 A circuit diagram of the through-silicon via (TSV) fault detection device provided in Embodiment 1;

[0034] Figure 2 This is a schematic diagram of the electrical model of the fault TSV mentioned in Implementation Method Eleven;

[0035] Among them, (a) is a fault-free TSV, (b) is a void fault TSV, (c) is a leakage fault TSV, and (d) is an open circuit fault TSV.

[0036] Figure 3 This is a schematic diagram of the TSPC trigger output when the tested TSV is fault-free and faulty, as mentioned in Implementation Method Eleven;

[0037] Where (a) indicates that the TSV is fault-free, and (b) indicates that the TSV is faulty;

[0038] Figure 4 This is a schematic diagram illustrating the cavity detection accuracy mentioned in Implementation Method Eleven. Detailed Implementation

[0039] To make the advantages and benefits of the technical solution provided by the present invention clearer, the technical solution provided by the present invention will now be described in further detail with reference to the accompanying drawings, specifically:

[0040] Implementation Method 1: Combination Figure 1 This embodiment describes a through-silicon via (TSV) fault detection circuit applied to a TSV array. The circuit includes:

[0041] Input terminal, first inverter, second inverter, third inverter, fourth inverter, transmission gate, TSPC flip-flop and reference circuit;

[0042] The input terminal is connected in series with the D terminal of the first inverter, the second inverter, the transmission gate, and the TSPC flip-flop in sequence;

[0043] The input terminal is connected in series with the clock terminals of the third inverter, the fourth inverter, and the TSPC flip-flop in sequence.

[0044] The output of the reference circuit is connected to the input of the fourth inverter.

[0045] The input terminal of the third inverter is used to connect to the output terminal of the TSV array under test.

[0046] Specifically, in this embodiment, the detection circuit can be:

[0047] This includes a reference TSV module circuit, a TSV module circuit under test, a fault detection circuit, an input node IN, and an output node OUT, wherein:

[0048] The TSV module circuit under test consists of a first inverter, a TSV under test, and a second inverter. The input terminal of the first inverter is connected to node IN, the output terminal is connected to the upper end of the TSV under test, and the lower end of the TSV under test is left floating. The input terminal of the second inverter is cut off from the upper end of the TSV under test, and the output terminal is connected to the fault detection circuit.

[0049] The reference TSV module circuit consists of a third inverter, a first capacitor, and a fourth inverter. The third inverter is connected to node IN, and its output is connected to the first capacitor and ground. The input of the fourth inverter is connected to the output of the third inverter, and its output is connected to the fault detection circuit.

[0050] The fault detection circuit consists of a first transmission gate and a TSPC flip-flop. In the TSV circuit under test, the second inverter is connected to the input of the transmission gate, and the output of the transmission gate is connected to the D terminal of the TSPC flip-flop. In the reference TSV module circuit, the output of the fourth inverter is connected to the clock terminal of the TSPC flip-flop.

[0051] Implementation Method 2: This implementation method further defines the through-silicon via (TSV) fault detection circuit provided in Implementation Method 1. The first inverter and the second inverter are respectively composed of a PMOS transistor and an NMOS transistor connected in parallel, with the PMOS transistor connected to the power supply and the NMOS transistor grounded.

[0052] Implementation Method 3: This implementation method further defines the through-silicon via (TSV) fault detection circuit provided in Implementation Method 2. The drains of the PMOS transistor and the NMOS transistor are connected, and the power supply and ground are connected through the source stage, respectively.

[0053] Implementation Method 4: This implementation method further defines the through-silicon via (TSV) fault detection circuit provided in Implementation Method 1, wherein the reference circuit includes a capacitor.

[0054] Implementation Method 5: This implementation method further defines the through-silicon via (TSV) fault detection circuit provided in Implementation Method 4, wherein the capacitor is equivalent to a fault-free TSV array.

[0055] Implementation Method Six: This implementation method provides a through-silicon via (TSV) fault detection device, which includes a TSV fault detection circuit provided in any one of Implementation Methods One to Five.

[0056] Implementation Method Seven: This implementation method provides a through-silicon via (TSV) fault detection method, which is applied to a TSV array. The method is implemented by the through-silicon via fault detection circuit provided in any one of Implementation Methods One to Five.

[0057] The method includes:

[0058] The steps for outputting a low-level signal;

[0059] The steps for outputting a charging signal;

[0060] The steps to output a high-level signal;

[0061] The steps for outputting a discharge signal;

[0062] The steps for acquiring the output signal;

[0063] The judgment steps for determining whether a fault exists based on the output signal.

[0064] Implementation Method Eight: This implementation method further defines the through-silicon via (TSV) fault detection method provided in Implementation Method Seven. The judgment step specifically includes:

[0065] The steps for acquiring the D terminal level of the TSPC flip-flop;

[0066] The step is to determine if a high level occurs at terminal D, and then output a fault result.

[0067] Implementation Method Nine: This implementation method provides a computer storage medium for storing a computer program. When the computer program is read by the computer, the computer executes the through-silicon via (TSV) fault detection method provided in Implementation Method Seven.

[0068] Implementation Method 10: This implementation method provides a computer, including a processor and a storage medium. When the processor reads a computer program stored in the storage medium, the computer executes the through-silicon via (TSV) fault detection method provided in Implementation Method 7.

[0069] Implementation Method Eleven: Combination Figure 2-4 This embodiment describes a specific implementation of the through-silicon via (TSV) fault detection method provided in Embodiment Seven. Specifically:

[0070] The fault detection circuit mainly consists of TSPC flip-flops. When the rising edge of the clock signal of the TSPC flip-flop arrives, the OUT terminal will output the value of the TSPC flip-flop's D terminal acquired at this rising edge. The fault-free TSV is equivalent to the capacitance between the flip-flop and the substrate, therefore the fault-free TSV is replaced by a capacitor Cref. To avoid the unstable state that occurs when the clock signal and the flip-flop's D terminal signal arrive simultaneously, a transmission gate is added as a delay unit.

[0071] Combination Figure 2 The TSV under test is explained. When the TSV is fault-free, it can be considered equivalent to a capacitor. When the TSV has a hole fault, the hole resistance R... void The isolation effect divides the capacitance of the TSV into two parts; when there is a leakage fault in the TSV, there is a leakage resistance R. leak When the TSV has an open-circuit fault, the capacitance value of the TSV decreases to C. crack .

[0072] This test structure requires only one test input signal IN and one output signal OUT. The test steps are as follows: First, IN is placed at a low level for a sufficient time to charge the tested TSV and the reference TSV; next, IN is placed at a high level to discharge the tested TSV and the reference TSV; finally, the output of the fault detection circuit at the OUT terminal is observed. In the second step, the tested TSV and the reference TSV will transition from low to high levels, but the transition times will differ. The presence of a fault is detected based on the final level value at the OUT terminal. Figure 3 As shown, 1) When the tested TSV is fault-free, since the tested TSV is connected to a transmission gate unit with a delay function, when the signal of the reference TSV arrives at the clock terminal of the TSPC flip-flop, the D terminal of the flip-flop is still low, and the OUT output is low (e.g., Figure 3 (a) 2) When the TSV under test is faulty, even if it is connected to the transmission gate, the signal at the D terminal will first become high level. At this time, the clock terminal will collect a high level, indicating that the TSV is faulty (e.g. Figure 3 (b) In summary, an OUT value of 1 indicates a fault, while an OUT value of 0 indicates no fault.

[0073] Figure 4 The figure shows the detection accuracy of a TSV with a void fault when using a detection circuit.

[0074] The key feature of this invention is that when a TSV is faulty, a time difference arises in the discharge time between it and a fault-free TSV. The presence of a fault in the tested TSV is determined by comparing the high and low levels of the signal acquired at the trigger clock terminal. Since the discharge time decreases when a TSV has a hole fault, leakage fault, open circuit fault, or two or more faults simultaneously, this invention can detect different faults without false positives. This invention has the advantages of high fault testing accuracy, wide fault coverage, and low testing overhead.

[0075] The above description of several specific embodiments further details the technical solution provided by the present invention in order to highlight the advantages and benefits of the technical solution provided by the present invention. However, the above-described specific embodiments are not intended to limit the present invention. Any reasonable modifications and improvements to the present invention, combinations of embodiments, and equivalent substitutions based on the spirit and principles of the present invention should be included within the protection scope of the present invention.

[0076] In the description of this specification, only preferred embodiments of the present invention are described, and should not be construed as limiting the scope of the invention. Furthermore, the use of terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples" indicates that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or N embodiments or examples. Furthermore, those skilled in the art can combine and integrate the different embodiments or examples described in this specification and the features of different embodiments or examples without contradiction. Additionally, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of the present invention, "N" means at least two, such as two, three, etc., unless otherwise explicitly specified. Any process or method described in the flowcharts or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or more N executable instructions for implementing custom logical functions or processes, and the scope of preferred embodiments of the invention includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order according to the functions involved, as will be understood by those skilled in the art to which embodiments of the invention pertain. The logic and / or steps represented in the flowcharts or otherwise described herein, for example, can be considered as a ordered list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, a “computer-readable medium” can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include the following: an electrical connection having one or N wires (electronic device), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic device, and portable optical disc read-only memory (CDROM).Furthermore, the computer-readable medium can even be paper or other suitable media on which the program can be printed, since the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in a computer memory. It should be understood that various parts of the invention can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, the N steps or methods can be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0077] Those skilled in the art will understand that all or part of the steps of the methods in the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it includes one or a combination of the steps of the method embodiments. Furthermore, the functional units in the various embodiments of the present invention can be integrated into a processing module, or each unit can exist physically separately, or two or more units can be integrated into a module. The integrated module can be implemented in hardware or as a software functional module. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium.

Claims

1. A through-silicon via (TSV) fault detection circuit, applied to a TSV array, characterized in that, The circuit includes: Input terminal, first inverter, second inverter, third inverter, fourth inverter, transmission gate, TSPC flip-flop and reference circuit; The input terminal is connected in series with the D terminal of the first inverter, the second inverter, the transmission gate, and the TSPC flip-flop in sequence; The input terminal is connected in series with the clock terminals of the third inverter, the fourth inverter, and the TSPC flip-flop in sequence. The output of the reference circuit is connected to the input of the fourth inverter. It also includes a reference TSV module circuit, comprising: a third inverter, a first capacitor, and a fourth inverter. The input terminal of the third inverter is used to connect to the output terminal of the TSV array under test. The third inverter is connected to node IN, and its output terminal is connected to the first capacitor and ground. The input terminal of the fourth inverter is connected to the output terminal of the third inverter, and its output terminal is connected to the fault detection circuit. The fault detection circuit consists of a first transmission gate and a TSPC flip-flop. In the TSV circuit under test, the second inverter is connected to the input of the transmission gate, and the output of the transmission gate is connected to the D terminal of the TSPC flip-flop. In the reference TSV module circuit, the output of the fourth inverter is connected to the clock terminal of the TSPC flip-flop.

2. The through-silicon via (TSV) fault detection circuit according to claim 1, characterized in that, The first inverter and the second inverter are each composed of a PMOS transistor and an NMOS transistor connected in parallel, with the PMOS transistor connected to the power supply and the NMOS transistor grounded.

3. The through-silicon via (TSV) fault detection circuit according to claim 2, characterized in that, The drains of the PMOS and NMOS transistors are connected, and their sources are connected to the power supply and ground, respectively.

4. The through-silicon via (TSV) fault detection circuit according to claim 1, characterized in that, The reference circuit includes a capacitor.

5. The through-silicon via (TSV) fault detection circuit according to claim 4, characterized in that, The capacitor is equivalent to a fault-free TSV array.

6. A through-silicon via (TSV) fault detection device, characterized in that, The device includes the through-silicon via (TSV) fault detection circuit according to any one of claims 1-5.

7. A method for detecting faults in through-silicon vias (TSVs), applied to TSV arrays, characterized in that, The method is implemented using the through-silicon via (TSV) fault detection circuit as described in any one of claims 1-5; The method includes: The steps for outputting a low-level signal; The steps for outputting a charging signal; The steps to output a high-level signal; The steps for outputting a discharge signal; The steps for acquiring the output signal; The judgment steps for determining whether a fault exists based on the output signal.

8. The through-silicon via (TSV) fault detection method according to claim 7, characterized in that, The specific determination steps are as follows: The steps for acquiring the D terminal level of the TSPC flip-flop; The step is to determine if a high level occurs at terminal D, and then output a fault result.

9. A computer storage medium for storing computer programs, characterized in that, When the computer program is read by the computer, the computer executes the through-silicon via (TSV) fault detection method according to claim 7.

10. A computer, including a processor and a storage medium, characterized in that, When the processor reads the computer program stored in the storage medium, the computer executes the through-silicon via (TSV) fault detection method according to claim 7.

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