Cache Amplifier

Abstract

A cache amplifier includes an input stage that includes a first channel to receive a differential input and a second channel to receive the differential input; an intermediate stage that includes a first current source to receive the output of the second channel and is electrically connected to a power supply, a second current source to receive the output of the first channel and is electrically connected to ground, and a floating current source that is electrically connected between the first current source and the second current source; and an output stage that is coupled to the intermediate stage to generate an output voltage. A shunt circuit is electrically connected between the first current source and the second current source to bypass the floating current source. The present invention has the advantageous effect of improving the settling time.

Description

Technical Field

[0001] The present invention relates to an amplifier, and more particularly to a buffer amplifier. Background Art

[0002] A liquid crystal display (LCD) is a type of flat panel display that displays visual information by adjusting the liquid crystal in the liquid crystal panel. The liquid crystal panel of a liquid crystal display typically uses drivers to drive, such as a gate driver (or scan driver) and a source driver (or data driver), which are coordinated by a timing controller.

[0003] Rail-to-rail class-AB amplifiers are often used in the drivers of liquid crystal displays, as disclosed in "A compact power-efficient 3V CMOS rail-to-rail input / output operational amplifier for VLSI cell libraries", IEEE Journal of Solid-State Circuits, Vol. 29, No. 12, December 1994, the content of which is incorporated herein by reference. A low settling time is an important parameter for the driver of a liquid crystal display to ensure the performance of the liquid crystal display, especially for large or high-resolution liquid crystal displays. The settling time is defined as the time required for the amplifier to enter and maintain within a preset error range when an ideal instantaneous step input is applied.

[0004] Therefore, there is an urgent need to propose a novel mechanism to improve the settling time of buffer amplifiers applicable to liquid crystal displays. Summary of the Invention

[0005] In view of the above, one of the objectives of the embodiments of the present invention is to provide a buffer amplifier with improved settling time.

[0006] According to an embodiment of the present invention, a buffer amplifier includes an input stage, an intermediate stage, and an output stage. The input stage includes a first channel for receiving a differential input and a second channel for receiving the differential input. The intermediate stage includes a first current source for receiving the output of the second channel and electrically connected to a power supply, a second current source for receiving the output of the first channel and electrically connected to ground, and a floating current source electrically connected between the first current source and the second current source. The output stage is coupled to the intermediate stage to generate an output voltage. The intermediate stage includes a shunt circuit electrically connected between the first current source and the second current source for bypassing the floating current source.

[0007] Preferably, the first current source includes: a first current branch electrically connected between the power supply and a first connection node, the first current branch including a transistor connected to a first intermediate node; and a second current branch electrically connected between the power supply and a third connection node, the second current branch including a transistor connected to a second intermediate node.

[0008] Preferably, the second current source includes: a third current branch electrically connected between ground and a second connection node, the third current branch including a transistor connected to a third intermediate node; and a fourth current branch electrically connected between ground and a fourth connection node, the fourth current branch including a transistor connected to a fourth intermediate node.

[0009] Preferably, the floating current source includes: a first floating branch electrically connected between the first connection node and the second connection node; and a second floating branch electrically connected between the third connection node and the fourth connection node.

[0010] Preferably, the shunt circuit includes: a first shunt transistor having its source and drain connected to the second intermediate node and the fourth connection node respectively; and a second shunt transistor having its source and drain connected to the fourth intermediate node and the third connection node respectively.

[0011] Preferably, the first shunt transistor includes a P-type metal oxide semiconductor transistor, and the second shunt transistor includes an N-type metal oxide semiconductor transistor.

[0012] Preferably, the shunt circuit includes: a third shunt transistor having its source and drain connected to the first intermediate node and the second connection node respectively; and a fourth shunt transistor having its source and drain connected to the third intermediate node and the first connection node respectively.

[0013] Preferably, the third shunt transistor includes a P-type metal oxide semiconductor transistor, and the fourth shunt transistor includes an N-type metal oxide semiconductor transistor.

[0014] Preferably, the first channel includes: a first bias branch electrically connected to the power supply, the first bias branch including transistors connected in series; and a first source-coupled differential pair including transistors connected in parallel, the sources of which are connected together and connected to the first bias branch; wherein the drains of the first source-coupled differential pair are respectively connected to the third intermediate node and the fourth intermediate node.

[0015] Preferably, the second channel includes: a second bias branch electrically connected to the ground, the second bias branch including transistors connected in series; and a second source-coupled differential pair including transistors connected in parallel, the sources of which are connected together and connected to the second bias branch; wherein the drains of the second source-coupled differential pair are respectively connected to the first intermediate node and the second intermediate node.

[0016] By the above technical solution, the present invention has at least the advantageous effect of improving the settling time. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A block diagram showing a cache amplifier according to an embodiment of the present invention.

[0018] Figure 2 A circuit diagram showing a cache amplifier according to an embodiment of the present invention ( Figure 1 ).

[0019]

MAIN ELEMENT SYMBOL DESCRIPTION

[0020] 100: Cache amplifier 11: Input stage

[0021] 111: First channel 112: Second channel

[0022] 12: Intermediate stage 121: First current source

[0023] 122: Second current source 123: Floating current source

[0024] 124: Shunt circuit 13: Output stage

[0025] Vip, Vin: Differential input Vout: Output node

[0026] VDD: Power supply Vb1: First bias voltage

[0027] Vb2: Second bias voltage Vb3~Vb10: Bias voltages

[0028] M1~M20: Transistors M12x: First shunt transistor

[0029] M18x: Second shunt transistor M11x: Third shunt transistor

[0030] M17x: Fourth shunt transistor MpL1: First output transistor

[0031] MnL1: Second output transistor MpL2: Third output transistor

[0032] MnL2: Fourth output transistor n9: First intermediate node

[0033] n10: Second intermediate node n5: Third intermediate node

[0034] n6: Fourth intermediate node n13: First connection node

[0035] n14: Second connection node n12: Third connection node

[0036] n8: Fourth connection node n11: First coupling node

[0037] n7: Second coupling node Detailed implementation manner

[0038] Figure 1 The block diagram of the cache amplifier 100 showing an embodiment of the present invention Figure 2 The circuit diagram of the cache amplifier 100( Figure 1 ) showing an embodiment of the present invention

[0039] In this embodiment, the cache amplifier (hereinafter referred to as the amplifier) 100 may include an input stage 11, an intermediate stage 12, and an output stage 13

[0040] The input stage 11 of this embodiment may include a first channel 111, which receives differential inputs Vip and Vin, and includes first-type transistors (such as P-type metal oxide semiconductor (PMOS) transistors) M1-M4. Among them, transistors M1-M2 are connected in series (where transistor M1 is coupled to the power supply VDD) to form a first bias branch, whose bias is Vb3-Vb4. Transistors M3-M4 are connected in parallel and their sources are connected together to form a first source-coupled differential pair, and then connected to the first bias branch (transistor M2).

[0041] The input stage 11 of this embodiment may include a second channel 112 that receives differential inputs Vip and Vin and includes transistors of a second type (e.g., N-type metal oxide semiconductor (NMOS) transistors) M5 - M8. Among them, transistors M5 - M6 are connected in series (where transistor M5 is coupled to ground) to form a second bias branch with a bias voltage of Vb5 - Vb6. Transistors M7 - M8 are connected in parallel and their sources are connected together to form a second source-coupled differential pair, which is then connected to the second bias branch (transistor M6).

[0042] The intermediate stage 12 of this embodiment may include a first current source that receives the output of the second channel 112 and is electrically connected to the power supply VDD. The first current source 121 may include transistors of a first type M9 - M12. Among them, transistors M9, M11 are connected in series at a first intermediate node n9 (where transistor M9 is coupled to the power supply VDD) to form a first current branch; transistors M10, M12 are connected in series at a second intermediate node n10 (where transistor M10 is coupled to the power supply VDD) to form a second current branch. The gates of the corresponding transistors of the first current branch and the second current branch are coupled together. For example, the gates of transistors M9 - M10 adjacent to the power supply VDD are coupled to a first coupling node n11, which is then connected to the drain of transistor M11. The first intermediate node n9 and the second intermediate node n10 are respectively connected to the drains of the second source-coupled differential pair M7 - M8. The gates of transistors M11 - M12 are connected to a first bias voltage Vb1.

[0043] The intermediate stage 12 of this embodiment may include a second current source 122 that receives the output of the first channel 111 and is electrically connected to ground. The second current source 122 may include transistors of a second type M17 - M20. Among them, transistors M17, M19 are connected in series at a third intermediate node n5 (where transistor M19 is coupled to ground) to form a third current branch; transistors M18, M20 are connected in series at a fourth intermediate node n6 (where transistor M20 is coupled to ground) to form a fourth current branch. The gates of the corresponding transistors of the third current branch and the fourth current branch are coupled together. For example, the gates of transistors M19 - M20 adjacent to ground are coupled to a second coupling node n7, which is then connected to the drain of transistor M17. The third intermediate node n5 and the fourth intermediate node n6 are respectively connected to the drains of the first source-coupled differential pair M3 - M4. The gates of transistors M17 - M18 are connected to a second bias voltage Vb2.

[0044] The intermediate stage 12 of this embodiment may include a floating current source 123 (which includes first-type transistors M15-M16 and second-type transistors M13-M14), electrically connected between the first current source 121 and the second current source 122. Among them, transistors M13 and M15 are connected in parallel to form a first floating branch, which is connected between the first current branch M9 / M11 of the first current source 121 (at the first connection node n13) and the third current branch M17 / M19 of the second current source 122 (at the second connection node n14). Transistors M14 and M16 are connected in parallel to form a second floating branch, which is connected between the second current branch M10 / M12 of the first current source 121 (at the third connection node n12) and the fourth current branch M18 / M20 of the second current source 122 (at the fourth connection node n8). The gates of transistors M13-M16 are respectively connected to the bias voltages Vb7-Vb10. The gates of the same-type transistors M13-M14 / M15-M16 are generally connected to the same bias voltage.

[0045] It should be noted that the third connection node n12 and the fourth connection node n8 serve as the first output node and the second output node of the intermediate stage 12, respectively.

[0046] According to one of the features of this embodiment, the intermediate stage 12 may include a shunt circuit 124, which is electrically connected between the first current source 121 and the second current source 122 to bypass the floating current source 123. The shunt circuit 124 may include a first shunt transistor M12x (of the first type) and a second shunt transistor M18x (of the second type). Among them, the source and drain of the first shunt transistor M12x are respectively connected to the second intermediate node n10 and the fourth connection node n8, and its gate is connected to the first bias voltage Vb1; and the source and drain of the second shunt transistor M18x are respectively connected to the fourth intermediate node n6 and the third connection node n12, and its gate is connected to the second bias voltage Vb2. Furthermore, the shunt circuit 124 may include a third shunt transistor M11x (of the first type) and a fourth shunt transistor M17x (of the second type). Among them, the source and drain of the third shunt transistor M11x are respectively connected to the first intermediate node n9 and the second connection node n14, and its gate is connected to the first bias voltage Vb1; and the source and drain of the fourth shunt transistor M17x are respectively connected to the third intermediate node n5 and the first connection node n13, and its gate is connected to the second bias voltage Vb2.

[0047] In other words, the first shunt transistor M12x is in parallel with the transistor M12, but bypasses the second floating branch M14 / M16; and the second shunt transistor M18x is in parallel with the transistor M18, but bypasses the second floating branch M14 / M16. Furthermore, the third shunt transistor M11x is in parallel with the transistor M11, but bypasses the first floating branch M13 / M15; and the fourth shunt transistor M17x is in parallel with the transistor M17, but bypasses the first floating branch M13 / M15.

[0048] Since the drain of the first shunt transistor M12x is connected to the fourth connection node n8, rather than being connected to the third connection node n12 as in the case of the transistor M12, signals can bypass the transistors M12 and M16 and quickly affect the fourth connection node n8 (i.e., the second output node of the intermediate stage 12), thereby accelerating the response of the amplifier 100. Similarly, since the drain of the second shunt transistor M18x is connected to the third connection node n12, rather than being connected to the fourth connection node n8 as in the case of the transistor M18, signals can bypass the transistors M18 and M14 and quickly affect the third connection node n12 (i.e., the first output node of the intermediate stage 12), thereby accelerating the response of the amplifier 100.

[0049] The output stage 13 of this embodiment is coupled to the first output node and the second output node of the intermediate stage 12 for generating an output voltage at the output node Vout (of the output stage 13). The output stage 13 may include a first output branch, which includes a first output transistor MpL1 (of the first type) and a second output transistor MnL1 (of the second type), connected in series between the power supply VDD and the ground. The gates of the first output transistor MpL1 and the second output transistor MnL1 are respectively coupled to the first output node and the second output node of the intermediate stage 12.

[0050] The output stage 13 of this embodiment may include a second output branch, which includes a third output transistor MpL2 (of the first type) and a fourth output transistor MnL2 (of the second type), (at the output node Vout of the output stage 13) connected in series between the power supply VDD and the ground. The gates of the third output transistor MpL2 and the fourth output transistor MnL2 are respectively coupled to the first output node and the second output node of the intermediate stage 12.

[0051] During operation, when the differential input voltage between Vip and Vin increases, the voltage of the second intermediate node n10 decreases accordingly. Subsequently, the voltage of the third connection node n12 decreases, and the voltage of the fourth connection node n8 also decreases. Therefore, the output voltage of the output node Vout increases. It should be noted that, through the first shunt transistor M12x, some signals can bypass the transistors M12 and M16 and reach the fourth connection node n8 to quickly affect the output node Vout.

[0052] Conversely, when the differential input voltage between Vip and Vin decreases, the voltage of the fourth intermediate node n6 decreases accordingly. Subsequently, the voltage of the fourth connection node n8 decreases, and the voltage of the third connection node n12 also decreases. Therefore, the output voltage of the output node Vout decreases. It should be noted that through the second shunt transistor M18x, some signals can bypass transistors M18 and M14 and reach the third connection node n12 to quickly affect the output node Vout.

[0053] The above description is only a preferred embodiment of the present invention and does not impose any formal restrictions on the present invention. Although the present invention has been disclosed above with the preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make some changes or modifications to equivalent embodiments by using the above-disclosed technical content within the scope of the technical solution of the present invention. However, as long as it does not deviate from the content of the technical solution of the present invention, any simple modification, equivalent change, and modification made to the above embodiment based on the technical essence of the present invention still fall within the scope of the technical solution of the present invention.

Claims

1. A buffer amplifier, characterized in that, Comprising: An input stage, which includes a first channel for receiving a differential input and a second channel for receiving the differential input; An intermediate stage, which includes a first current source for receiving the output of the second channel and electrically connected to a power supply, a second current source for receiving the output of the first channel and electrically connected to ground, and a floating current source electrically connected between the first current source and the second current source; and An output stage, which is coupled to the intermediate stage to generate an output voltage; Wherein the intermediate stage includes a shunt circuit electrically connected between the first current source and the second current source for bypassing the floating current source, and the shunt circuit includes a first shunt transistor and a second shunt transistor; Wherein one end of the first shunt transistor is electrically connected to the output of the second channel, and the other end is electrically connected to a connection node between the second current source and the floating current source for bypassing the floating current source, and one end of the second shunt transistor is electrically connected to the output of the first channel, and the other end is electrically connected to a connection node between the first current source and the floating current source for bypassing the floating current source.

2. The cache amplifier according to claim 1, wherein The first current source includes: A first current branch electrically connected between the power supply and a first connection node, and the first current branch includes a transistor connected to a first intermediate node; and A second current branch electrically connected between the power supply and a third connection node, and the second current branch includes a transistor connected to a second intermediate node.

3. The cache amplifier according to claim 2, characterized in that, The second current source includes: A third current branch electrically connected between the ground and a second connection node, and the third current branch includes a transistor connected to a third intermediate node; and A fourth current branch electrically connected between the ground and a fourth connection node, and the fourth current branch includes a transistor connected to a fourth intermediate node.

4. The cache amplifier according to claim 3, characterized in that, The floating current source includes: A first floating branch electrically connected between the first connection node and the second connection node; and A second floating branch electrically connected between the third connection node and the fourth connection node.

5. The cache amplifier according to claim 4, wherein For the first shunt transistor, its source and drain are respectively connected to the second intermediate node and the fourth connection node; and For the second shunt transistor, its source and drain are respectively connected to the fourth intermediate node and the third connection node.

6. The cache amplifier according to claim 5, characterized in that The first shunt transistor includes a P-type metal oxide semiconductor transistor, and the second shunt transistor includes an N-type metal oxide semiconductor transistor.

7. The cache amplifier according to claim 4, wherein The shunt circuit includes: A third shunt transistor, whose source and drain are respectively connected to the first intermediate node and the second connection node; and A fourth shunt transistor, whose source and drain are respectively connected to the third intermediate node and the first connection node.

8. The cache amplifier according to claim 7, wherein The third shunt transistor includes a P-type metal oxide semiconductor transistor, and the fourth shunt transistor includes an N-type metal oxide semiconductor transistor.

9. The cache amplifier according to claim 3, characterized in that, The first channel includes: A first bias branch electrically connected to the power supply, and the first bias branch includes series-connected transistors; and A first source-coupled differential pair, including parallel-connected transistors, whose sources are connected together and connected to the first bias branch; The drains of the first source-coupled differential pair are respectively connected to the third intermediate node and the fourth intermediate node.

10. The cache amplifier according to claim 3, wherein The second channel includes: a second bias branch electrically connected to the ground, the second bias branch including transistors connected in series; and a second source-coupled differential pair including transistors connected in parallel, the sources of which are connected together and connected to the second bias branch; wherein the drains of the second source-coupled differential pair are respectively connected to the first intermediate node and the second intermediate node.

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