A GaN HEMT device based on in-situ SiNx and a method for preparing the same

Abstract

The present invention discloses a GaN HEMT device based on in-situ SiNx and a preparation method thereof, comprising: a substrate, and a GaN buffer layer, a high polarization strength thin barrier layer, and an in-situ SiNx layer sequentially arranged on the substrate; an isolation region, located at both ends of the device, and penetrating the in-situ SiNx layer and the high polarization strength thin barrier layer, until part of the GaN buffer layer; a passivation layer, located on the isolation region and the in-situ SiNx layer; a source and a drain electrode, located at both ends of the device near the isolation region, and penetrating the passivation layer until part of the in-situ SiNx layer; wherein the source and the drain electrode penetrate downward during the annealing process until part of the GaN buffer layer; a T-type gate electrode, penetrating the passivation layer and the in-situ SiNx layer until the upper surface of the high polarization strength thin barrier layer, and located on part of the passivation layer. The present invention can achieve low ohmic contact resistance at low cost, and design and prepare high-frequency GaN HEMT devices to meet 5G and 6G application requirements.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and in particular relates to a GaN HEMT device based on in-situ SiNx and a preparation method thereof. Background Art

[0002] Gallium nitride-based heterojunction materials have high 2DEG density due to strong polarization. At the same time, their large bandgap, high electron mobility and high breakdown field strength give them significant advantages in the fields of high frequency, high power, high efficiency and low noise. Therefore, GaN-based high electron mobility transistor (HEMT) devices with heterojunction as the core have broad application prospects in the field of high-power microwave and millimeter wave devices.

[0003] The fabrication of ohmic contact is one of the key technologies for preparing GaN-based HEMT devices. A good ohmic contact refers to one with low ohmic contact resistance and smooth surface morphology. The size of the ohmic contact resistance will directly affect the device performance. Low ohmic contact resistance will reduce the resistance of the source electrode and drain electrode, thereby increasing the saturation current and extrinsic transconductance of the device; the impact on the frequency characteristics is that low ohmic contact resistance reduces device loss and increases the device cutoff frequency. The impact of surface morphology on device characteristics is that the metal edge burrs increase the local peak electric field of the device, thereby reducing the device breakdown voltage. To form a good ohmic contact on a wide bandgap semiconductor material, it is generally necessary to utilize the mechanism of the tunnel effect, and use the source and drain regions to be heavily doped, so that the barrier region width is very narrow, and electrons tunnel through the barrier to generate tunneling current. To obtain a good ohmic contact, a low, thin barrier and a high doping concentration are required. However, the bandgap width of the barrier layer material of the GaN-based HEMT device is generally large, especially for the AlN barrier with a larger bandgap width. Compared with the traditional low Al component AlGaN / GaN heterojunction, it is more difficult to form a low ohmic contact. Low ohmic contact resistance is very important for obtaining high-quality and high-reliability microwave power devices.

[0004] The methods currently proposed to reduce ohmic contact resistance include the following:

[0005] 1) Ion implantation

[0006] The ion implantation method is used to directly perform n-type implantation doping on the source and drain electrode regions, thereby increasing the doping concentration of the contact layer, thereby increasing the tunneling probability and tunneling current, and achieving the purpose of reducing the ohmic contact resistance.

[0007] However, the process involves ion implantation, which is complex and costly, and the implantation of high-energy ions will also introduce new material surface damage. At the same time, the injected n-type doped ions require an annealing temperature of more than 1000°C to activate. This high-temperature activation process will cause thermal degradation of the device barrier layer, resulting in an increase in the device block resistance and affecting the device's DC characteristics.

[0008] 2) GaN regrowth method

[0009] The source-drain contact resistance is reduced by etching the source and drain regions and then growing n-type GaN. That is, the source and drain regions are first etched, and then n-type heavily doped GaN material is grown in the etched source and drain regions. + Ohmic metal is deposited on the GaN layer.

[0010] However, the regrowth method is a complex process, requiring both etching and secondary growth of n-type GaN.

[0011] 3) Surface pretreatment

[0012] The ohmic contact characteristics are improved by using a surface treatment process, that is, before the ohmic metal is deposited, the contact surface of the semiconductor is treated with an acid, alkaline solution, or plasma to remove the oxide layer and damage layer at the contact interface, so that a better ohmic contact effect can be obtained after the metal is deposited. This process can remove the oxide layer and damage layer, roughen the contact surface, and achieve a better metal-semiconductor contact effect, and may introduce N vacancies, which can play a role similar to a donor in GaN or AlGaN materials, thereby improving the ohmic contact effect.

[0013] Compared with other methods, surface pretreatment is simple and easy to operate, but the improvement of ohmic contact by this process is limited, and it is usually necessary to combine it with other methods to further reduce the ohmic contact resistance.

[0014] 4) Change the type and thickness of ohmic metal

[0015] The ohmic contact based on GaN-based HEMT devices initially adopted the Ti / Al metal system. On this basis, researchers have developed many different ohmic metal solutions, including the type, number and thickness ratio of metal layers.

[0016] After multi-layer metal deposition, high-temperature annealing is required to carry out interdiffusion reaction to form a balanced and thermally stable low-resistance compound. Annealing conditions, including annealing temperature and annealing time, are very important for the formation of metal alloys. Moreover, the Ti-based ohmic contact system often requires high-temperature annealing of up to 800°C to achieve good ohmic contact. High-temperature annealing will increase the surface roughness of the ohmic metal and even cause thermal degradation of the AlGaN barrier layer, which will have a great impact on device reliability.

[0017] 5) Barrier layer etching

[0018] Thinning the AlGaN barrier layer by dry etching can make the barrier at the metal / semiconductor interface of the AlGaN / GaN HEMT device thinner, thereby increasing the probability of electron tunneling, reducing the ohmic contact resistance, and enhancing the ohmic contact characteristics.

[0019] However, the overall etching depth of the source and drain regions is relatively large, which may damage the two-dimensional electron gas layer below the ohmic region, thereby reducing the device current and deteriorating the device characteristics.

[0020] It can be seen that the above existing methods for reducing ohmic contact resistance all have their own problems, which lead to other problems while reducing the ohmic contact resistance, thereby affecting the device performance. Summary of the invention

[0021] In order to solve the above problems existing in the prior art, the present invention provides a GaN HEMT device based on in-situ SiNx and a preparation method thereof. The technical problem to be solved by the present invention is achieved by the following technical solutions:

[0022] In a first aspect, an embodiment of the present invention provides a GaN HEMT device based on in-situ SiNx, including:

[0023] A substrate, and a GaN buffer layer, a high polarization strength thin barrier layer, and an in-situ SiNx layer sequentially disposed on the substrate;

[0024] An isolation region is located at both ends of the device and penetrates the in-situ SiNx layer and the high polarization strength thin barrier layer until it reaches part of the GaN buffer layer to achieve device isolation;

[0025] A passivation layer, located on the isolation region and the in-situ SiNx layer;

[0026] A source electrode and a drain electrode are located at two ends of the device near the isolation region and penetrate the passivation layer until part of the in-situ SiNx layer; wherein the source electrode and the drain electrode penetrate downward during the annealing process until part of the GaN buffer layer;

[0027] A T-shaped gate electrode, penetrating the passivation layer and the in-situ SiNx, reaching the upper surface of the high polarization strength thin barrier layer, and being located on a portion of the passivation layer;

[0028] The GaN HEMT device with low ohmic contact resistance is optimized by designing the high polarization strength thin barrier layer and the in-situ SiNx layer with different thicknesses.

[0029] In one embodiment of the present invention, the GaN buffer layer includes high-resistance GaN and UID-GaN, wherein:

[0030] The high-resistance GaN is disposed on the substrate;

[0031] The UID-GaN is disposed on the high-resistance GaN.

[0032] In one embodiment of the present invention, the thickness of the high-resistance GaN is 0.5 μm to 1 μm and is doped with Fe or C; the thickness of the UID-GaN is 0.1 μm to 0.5 μm.

[0033] In one embodiment of the present invention, the thickness of the high polarization strength thin barrier layer is 2.5 nm to 6 nm; the high polarization strength thin barrier layer includes AlN, ScAlN, InAlN, InAlGaN or high Al component AlGaN.

[0034] In one embodiment of the present invention, the thickness of the in-situ SiNx layer in the source and drain ohmic regions is 1 nm to 3 nm; the thickness of the in-situ SiNx layer outside the source and drain ohmic regions is 2 nm to 10 nm.

[0035] In a second aspect, an embodiment of the present invention provides a method for preparing a GaN HEMT device based on in-situ SiNx, comprising:

[0036] A GaN buffer layer, a high polarization strength thin barrier layer and an in-situ SiNx layer are sequentially grown on a substrate;

[0037] Photolithographically forming source and drain ohmic regions on the in-situ SiNx layer;

[0038] Etching away part of the SiNx layer in the source and drain ohmic regions to form an ohmic groove, and depositing a source metal and a drain metal in the ohmic groove to form a source electrode and a drain electrode respectively;

[0039] Annealing the entire device to form an ohmic contact;

[0040] Ion implantation is performed in the isolation regions at both ends of the device to form device isolation;

[0041] Depositing a passivation layer on the entire device surface except the source electrode and the drain electrode;

[0042] The passivation layer is etched in the gate region until the upper surface of the high polarization strength thin barrier layer forms a gate groove, and a gate metal is deposited on the gate groove and the passivation layer on both sides of the gate groove to form a T-shaped gate electrode.

[0043] In one embodiment of the present invention, a GaN buffer layer is sequentially grown on a substrate, comprising:

[0044] Growing Fe- or C-doped high-resistance GaN with a thickness of 0.5 μm to 1 μm on the substrate by using a MOCVD process;

[0045] A UID-GaN with a thickness of 0.1 μm to 0.5 μm is grown on the high-resistance GaN by using a MOCVD process; and the GaN buffer layer is composed of the high-resistance GaN and the UID-GaN.

[0046] In one embodiment of the present invention, a high polarization strength thin barrier layer is grown on a GaN buffer layer, comprising:

[0047] A high polarization strength thin barrier layer with a thickness of 2.5nm to 6nm is grown on the GaN buffer layer by using an MOCVD process; the high polarization strength thin barrier layer comprises AlN, ScAlN, InAlN, InAlGaN or high Al component AlGaN.

[0048] In one embodiment of the present invention, an in-situ SiNx layer is grown on a high polarization strength thin barrier layer, comprising:

[0049] An in-situ SiNx layer with a thickness of 2nm to 10nm is grown on the high polarization strength thin barrier layer by using a MOCVD process.

[0050] In one embodiment of the present invention, etching away part of the SiNx layer in the source and drain ohmic regions to form an ohmic groove includes:

[0051] The SiNx layer is etched away to a depth of 1 nm to 7 nm in the source and drain ohmic regions to form ohmic grooves.

[0052] Beneficial effects of the present invention:

[0053] The GaN HEMT device based on in-situ SiNx proposed by the present invention has a simple device structure design, but can achieve low ohmic contact resistance, specifically: a substrate, and a GaN buffer layer, a high polarization strength thin barrier layer, and an in-situ SiNx layer sequentially arranged on the substrate; an isolation region, located at both ends of the device, and penetrating the in-situ SiNx layer and the high polarization strength thin barrier layer until part of the GaN buffer layer; a passivation layer, located on the isolation region and the in-situ SiNx layer; a source electrode and a drain electrode, located at both ends of the device near the isolation region, and penetrating the passivation layer until part of the in-situ SiNx layer; wherein the source electrode and the drain electrode penetrate downward during the annealing process until part of the GaN buffer layer; a T-type gate electrode, penetrating the passivation layer and the in-situ SiNx layer until the upper surface of the high polarization strength thin barrier layer, and located on part of the passivation layer. Low ohmic contact resistance is achieved by designing in-situ SiNx layers of different thicknesses and high polarization strength thin barrier layers of different thicknesses. Compared with the traditional direct contact between the source and drain metal electrodes and the barrier layer, the barrier layer of the present invention adopts a strong polarization barrier material, which has a large bandgap width, and the presence of an in-situ SiNx layer between the source and drain electrodes and the high polarization strength thin barrier layer can enhance the ohmic contact. This is because the source and drain metals will infiltrate during the annealing process of the device, and may form a low-work function silicide. At the same time, the N atoms produced by the decomposition of the in-situ SiNx layer during the annealing process will react with the Ti in the source and drain metal electrodes to form a low-work function TiN. Ti and group III nitride materials can also react to form TiN, which can enhance the thermal electron emission transmission on the barrier layer and help to achieve good ohmic contact between the ohmic metal and the 2DEG. It can be seen that the present invention achieves low ohmic contact resistance at low cost by designing different SiNx thicknesses and different barrier layer thicknesses, and designs and prepares high-frequency GaN HEMT devices to meet the requirements of 5G and future 6G applications.

[0054] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] Figure 1 It is a schematic structural diagram of a GaN HEMT device based on in-situ SiNx provided by an embodiment of the present invention;

[0056] Figure 2 It is a schematic flow chart of a method for preparing a GaN HEMT device based on in-situ SiNx provided by an embodiment of the present invention;

[0057] Figure 3 (a) to 3(h) are schematic diagrams of the corresponding structures of the method for preparing a GaN HEMT device based on in-situ SiNx provided in an embodiment of the present invention.

[0058] Description of reference numerals:

[0059] 1-substrate; 2-GaN buffer layer; 3-high polarization strength thin barrier layer; 4-in-situ SiNx layer; 5-photoresist; 6-source electrode; 7-drain electrode; 8-isolation region; 9-passivation layer; 10-T-type gate electrode. DETAILED DESCRIPTION

[0060] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0061] To ensure low ohmic contact resistance and improved device performance, see Figure 1 , an embodiment of the present invention provides a GaN HEMT device based on in-situ SiNx, comprising:

[0062] A substrate 1, and a GaN buffer layer 2, a high polarization strength thin barrier layer 3, and an in-situ SiNx layer 4 sequentially arranged on the substrate 1;

[0063] The isolation region 8 is located at both ends of the device and penetrates the in-situ SiNx layer 4 and the high polarization strength thin barrier layer 3 until part of the GaN buffer layer 2 to achieve device isolation;

[0064] A passivation layer 9, located on the isolation region 8 and the in-situ SiNx layer 4;

[0065] The source electrode 6 and the drain electrode 7 are located at two ends of the device near the isolation region 8, and penetrate the passivation layer 9 until part of the in-situ SiNx layer 4; wherein the source electrode 6 and the drain electrode 7 penetrate downward during the annealing process until part of the GaN buffer layer 2;

[0066] A T-shaped gate electrode 10 penetrates the passivation layer 9 and the in-situ SiNx layer 4 to the upper surface of the high polarization strength thin barrier layer 3 and is located on a portion of the passivation layer 9;

[0067] The GaN HEMT device with low ohmic contact resistance is optimized by designing high polarization strength thin barrier layer 3 and in-situ SiNx layer 4 with different thicknesses.

[0068] In one embodiment of the present invention, the GaN buffer layer 2 includes high-resistance GaN and UID-GaN, wherein the high-resistance GaN is disposed on the substrate 1;

[0069] UID-GaN, set on high-resistance GaN.

[0070] In one embodiment of the present invention, the thickness of the high-resistance GaN is 0.5 μm to 1 μm and is doped with Fe or C; the thickness of the UID-GaN is 0.1 μm to 0.5 μm.

[0071] In one embodiment of the present invention, the thickness of the high polarization strength thin barrier layer 3 is 2.5 nm to 6 nm; the high polarization strength thin barrier layer 3 includes AlN, ScAlN, InAlN, InAlGaN or high Al component AlGaN.

[0072] In one embodiment of the present invention, the thickness of the in-situ SiNx layer 4 in the source and drain ohmic regions is 1 nm to 3 nm; the thickness of the in-situ SiNx layer 4 outside the source and drain ohmic regions is 2 nm to 10 nm.

[0073] Here, the in-situ SiNx layer 4 has a stress regulation function, which can enhance polarization, so that the 2DEG concentration in the GaN buffer layer 2 increases; the barrier layer adopts a strong polarization barrier material, and the strong polarization barrier material has a large bandgap width. After conventional stacked metal annealing, it is difficult to form a low ohmic contact resistance. The in-situ SiNx layer 4 introduced in the source and drain ohmic region according to the embodiment of the present invention can enhance the ohmic contact; the passivation layer 9 can effectively reduce the surface state density and reduce the probability of electrons being trapped, thereby reducing the current collapse effect.

[0074] In summary, the GaN HEMT device based on in-situ SiNx proposed in the embodiment of the present invention realizes low ohmic contact resistance by designing in-situ SiNx layer 4 of different thickness and high polarization strength thin barrier layer 3 of different thickness. Compared with the direct contact between the traditional source and drain metal electrodes and the barrier layer, the barrier layer in the embodiment of the present invention adopts a strong polarization barrier material, which has a large bandgap, and the ohmic contact can be enhanced due to the presence of the in-situ SiNx layer 4 between the source and drain electrodes and the high polarization strength thin barrier layer 3. This is because the source and drain metals will infiltrate during the annealing process of forming the device, and may form low work function silicides. At the same time, the N atoms generated by the decomposition of the in-situ SiNx layer 4 during the annealing process will react with Ti in the source and drain metal electrodes to form low work function TiN. Ti and group III nitride materials can also react to form TiN, which can enhance the thermal electron emission transmission on the barrier layer and help to achieve good ohmic contact between the ohmic metal and the 2DEG. Therefore, the embodiments of the present invention achieve low ohmic contact resistance at low cost by designing different SiNx thicknesses and different barrier layer thicknesses, and design and prepare high-frequency GaN HEMT devices to meet the application requirements of 5G and future 6G.

[0075] Second, see Figure 2 The embodiment of the present invention provides a method for preparing a GaN HEMT device based on in-situ SiNx, which specifically includes the following steps:

[0076] S10, sequentially growing a GaN buffer layer 2, a high polarization strength thin barrier layer 3 and an in-situ SiNx layer 4 on a substrate 1.

[0077] In one embodiment of the present invention, see Figure 3 (a) A GaN buffer layer 2 is sequentially grown on a substrate 1, including: using a Metal Organic Chemical Vapor Deposition (MOCVD) process to grow a high-resistance GaN doped with Fe or C with a thickness of 0.5 μm to 1 μm on the substrate 1; using a MOCVD process to grow a UID-GaN with a thickness of 0.1 μm to 0.5 μm on the high-resistance GaN; and forming a GaN buffer layer 2 with the high-resistance GaN and the UID-GaN.

[0078] In one embodiment of the present invention, a high polarization strength thin barrier layer 3 is grown on a GaN buffer layer 2, comprising: growing a high polarization strength thin barrier layer 3 with a thickness of 2.5 nm to 6 nm on the GaN buffer layer 2 using an MOCVD process; the high polarization strength thin barrier layer 3 comprises AlN, ScAlN, InAlN, InAlGaN or high Al component AlGaN.

[0079] In one embodiment of the present invention, growing an in-situ SiNx layer 4 on the high polarization strength thin barrier layer 3 includes: growing an in-situ SiNx layer 4 with a thickness of 2 nm to 10 nm on the high polarization strength thin barrier layer 3 using a MOCVD process.

[0080] S20 , forming source and drain ohmic regions on the in-situ SiNx layer 4 by photolithography.

[0081] In one embodiment of the present invention, see Figure 3 (b) Using an inductively coupled plasma etching device (ICP), using a photoresist 5 as a mask, the source and drain ohmic regions are formed on the in-situ SiNx layer 4 by photolithography. The specific etching process conditions are: etching gas is CF4 / O2, flow rate is 25 / 5sccm, chamber pressure is 5mTorr, ICP upper electrode power is 80W, and lower electrode power is 10W.

[0082] S30 , etching away a portion of the in-situ SiNx layer 4 in the source and drain ohmic regions to form ohmic grooves, and depositing source metal and drain metal in the ohmic grooves to form source electrodes 6 and drain electrodes 7 , respectively.

[0083] In one embodiment of the present invention, see Figure 3(c) Using ICP etching equipment and dry etching to thin the in-situ SiNx layer 4 in the source and drain ohmic region, an ohmic groove is formed in the in-situ SiNx layer 4. Control of the thinning amount is very important here. The inventors have found that during the subsequent device annealing process, the source and drain metals will infiltrate and may form low-work-function silicides. At the same time, during the annealing process, the N atoms generated by the decomposition of the in-situ SiNx layer 4 will react with Ti in the source and drain metal electrodes to form low-work-function TiN. Ti and group III nitride materials can also react to form TiN, which can enhance the thermal electron emission transmission on the barrier layer and help achieve good ohmic contact between the ohmic metal and the 2DEG. If the etching thinning amount is not enough, the source and drain metal electrodes are too far away from the barrier layer, and it is difficult to form an alloy. If the etching thinning amount is too large, the in-situ SiNx layer 4 does not contribute much to the formation of TiN, and it is difficult to achieve low ohmic contact resistance. Therefore, based on the above principle analysis, experiments show that the etching depth is 1nm~7nm, that is, 1nm~3nm of in-situ SiNx layer 4 is retained in the source and drain ohmic region, and combined with the designed high polarization strength thin barrier layer 3, a lower ohmic contact resistance can be obtained. The specific etching process conditions are: etching gas is CF4 / O2, flow rate is 25 / 5sccm, chamber pressure is 5mTorr, ICP upper electrode power is 80W, and lower electrode power is 10W.

[0084] Next, see Figure 3 (d) Using electron beam evaporation equipment to deposit source metal and drain metal in the ohmic groove to form source electrode 6 and drain electrode 7, respectively. Both the source metal and the drain metal can be Ti / Al / Ni / Au laminated metal.

[0085] Here, the design of the thickness of the high polarization strength thin barrier layer 3 and the in-situ SiNx layer 4 is critical, and the particular difficulty is the need to accurately control the etching amount of the in-situ SiNx layer 4 in the ohmic region. Generally, if there is a thicker in-situ SiNx layer 4 above the high polarization strength thin barrier layer 3, before forming the source-drain ohmic contact, it is generally necessary to etch away the in-situ SiNx layer 4 to reduce the distance between the ohmic metal and the 2DEG, so as to facilitate the penetration of the source-drain metal to achieve a lower ohmic contact resistance. However, considering that alloys such as TiSi and AlSi can be used as interconnects in the manufacture of silicon integrated circuits, the embodiment of the present invention considers thinning the in-situ SiNx layer 4 to form a similar alloy after annealing to achieve a lower ohmic contact resistance.

[0086] S40, performing annealing treatment on the entire device to form an ohmic contact.

[0087] In one embodiment of the present invention, see Figure 3 (e) The entire device is annealed in a nitrogen atmosphere at 860° C. for 60 seconds. During the annealing process, the source metal and the drain metal penetrate downward until an ohmic contact is formed in a portion of the GaN buffer layer 2 .

[0088] S50 , performing ion implantation at the isolation regions at both ends of the device to form isolation regions 8 .

[0089] In one embodiment of the present invention, see Figure 3 (f) Using ion implantation equipment, B or Ar ions are implanted into the isolation regions at both ends of the device to form isolation regions 8, thereby achieving device isolation.

[0090] S60 , depositing a passivation layer 9 on the entire device surface except the source electrode 6 and the drain electrode 7 .

[0091] In one embodiment of the present invention, see Figure 3 (g) A SiN passivation layer 9 is deposited by a plasma enhanced chemical vapor deposition (PECVD) device; and the SiN passivation layer 9 on the source electrode 6 and the drain electrode 7 is removed by dry etching using an ICP etching device. The specific etching process conditions are as follows: the etching gas is CF4 / O2, the flow rate is 25 / 5sccm, the chamber pressure is 5mTorr, the ICP upper electrode power is 80W, and the lower electrode power is 10W.

[0092] S70 , etching the passivation layer 9 in the gate region until the upper surface of the high polarization strength thin barrier layer 3 forms a gate groove, and depositing gate metal on the gate groove and the passivation layer 9 on both sides of the gate groove to form a T-shaped gate electrode 10 .

[0093] In one embodiment of the present invention, see Figure 3 (h) Using ICP etching equipment to remove the passivation layer 9 and the in-situ SiNx layer 4 in the gate area by dry etching, until a gate groove is formed on the upper surface of the high polarization strength thin barrier layer 3. The specific etching process conditions are: the etching gas is CF4 / O2, the flow rate is 25 / 5sccm, the chamber pressure is 5mTorr, the ICP upper electrode power is 80W, and the lower electrode power is 10W; then, an electron beam evaporation device is used to deposit a gate metal on the gate groove and the passivation layer 9 on both sides of the gate groove to form a T-shaped gate electrode 10. The gate metal can be a Ni / Au laminated metal.

[0094] In summary, the method for preparing a GaN HEMT device based on in-situ SiNx proposed in an embodiment of the present invention is different from the preparation of a conventional GaN-based HEMT device in that, before depositing the source and drain metal electrodes, the in-situ SiNx layer 4 in the source and drain ohmic regions is first etched and thinned, and then a series of conventional GaN HEMT device preparation processes are performed. Based on the source and drain ohmic region etching technology, low ohmic contact resistance can be achieved by etching and designing different in-situ SiNx thicknesses and different high polarization strength thin barrier layers 3. It can be seen that the embodiment of the present invention is based on a simple and easy source and drain ohmic region etching technology to achieve low ohmic contact resistance at low cost, and designs and prepares high-frequency GaN HEMT devices to meet the application requirements of 5G and future 6G.

[0095] In the description of the present invention, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0096] Although the present invention is described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art may understand and implement other variations of the disclosed embodiments by viewing the specification and its drawings. In the specification, the word "comprising" does not exclude other components or steps, and "a" or "one" does not exclude multiple situations. Certain measures are recorded in different embodiments, but this does not mean that these measures cannot be combined to produce good results.

[0097] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A GaN HEMT device based on in-situ SiNx, characterized in that: include: A substrate, and a GaN buffer layer, a high polarization strength thin barrier layer, and an in-situ SiNx layer sequentially disposed on the substrate; An isolation region is located at both ends of the device and penetrates the in-situ SiNx layer and the high polarization strength thin barrier layer until it reaches part of the GaN buffer layer to achieve device isolation; A passivation layer, located on the isolation region and the in-situ SiNx layer; A source electrode and a drain electrode are located at two ends of the device near the isolation region and penetrate the passivation layer until part of the in-situ SiNx layer; wherein the source electrode and the drain electrode penetrate downward during the annealing process until part of the GaN buffer layer; and during the annealing process, the source metal and the drain metal will penetrate downward to form a silicide with a low work function, and at the same time, during the annealing process, the N atoms generated by the decomposition of the in-situ SiNx layer will react with the source metal and the drain metal to form a metal nitride with a low work function, thereby enhancing the ohmic contact; A T-shaped gate electrode, penetrating the passivation layer and the in-situ SiNx layer, extending to the upper surface of the high polarization strength thin barrier layer, and located on a portion of the passivation layer; Among them, the GaN HEMT device with low ohmic contact resistance is optimized by designing the high polarization strength thin barrier layer and the in-situ SiNx layer with different thicknesses; the thickness of the high polarization strength thin barrier layer is 2.5nm~6nm; the thickness of the in-situ SiNx layer in the source and drain ohmic region is 1nm~3nm; the thickness of the in-situ SiNx layer except the source and drain ohmic region is 2nm~10nm.

2. The GaN HEMT device based on in-situ SiNx according to claim 1, characterized in that: The GaN buffer layer includes high-resistance GaN and UID-GaN, wherein: The high-resistance GaN is disposed on the substrate; The UID-GaN is disposed on the high-resistance GaN.

3. The GaN HEMT device based on in-situ SiNx according to claim 2, characterized in that: The thickness of the high-resistance GaN is 0.5 μm to 1 μm and is doped with Fe or C; the thickness of the UID-GaN is 0.1 μm to 0.5 μm.

4. The GaN HEMT device based on in-situ SiNx according to claim 1, characterized in that: The high polarization strength thin barrier layer includes AlN, ScAlN, InAlN, InAlGaN or high Al content AlGaN.

5. A method for preparing a GaN HEMT device based on in-situ SiNx, characterized in that: include: A GaN buffer layer, a high polarization strength thin barrier layer and an in-situ SiNx layer are sequentially grown on a substrate; Photolithographically forming source and drain ohmic regions on the in-situ SiNx layer; Etching away part of the SiNx layer in the source and drain ohmic regions to form an ohmic groove, and depositing a source metal and a drain metal in the ohmic groove to form a source electrode and a drain electrode respectively; The entire device is annealed to form an ohmic contact; during the annealing process, the source metal and the drain metal will penetrate to form a low work function silicide, and at the same time, the N atoms generated by the decomposition of the in-situ SiNx layer during the annealing process will react with the source metal and the drain metal to form a low work function metal nitride, thereby enhancing the ohmic contact; Ion implantation is performed in the isolation regions at both ends of the device to form device isolation; Depositing a passivation layer on the entire device surface except the source electrode and the drain electrode; The passivation layer is etched in the gate region until the upper surface of the high polarization strength thin barrier layer forms a gate groove, and a gate metal is deposited on the gate groove and the passivation layer on both sides of the gate groove to form a T-shaped gate electrode.

6. The method for preparing a GaN HEMT device based on in-situ SiNx according to claim 5, characterized in that: The GaN buffer layer is sequentially grown on the substrate, including: Growing Fe- or C-doped high-resistance GaN with a thickness of 0.5 μm to 1 μm on the substrate by using a MOCVD process; A UID-GaN with a thickness of 0.1 μm to 0.5 μm is grown on the high-resistance GaN by using a MOCVD process; and the GaN buffer layer is composed of the high-resistance GaN and the UID-GaN.

7. The method for preparing a GaN HEMT device based on in-situ SiNx according to claim 5, characterized in that: A high polarization strength thin barrier layer is grown on the GaN buffer layer, including: A high polarization strength thin barrier layer with a thickness of 2.5nm to 6nm is grown on the GaN buffer layer by using an MOCVD process; the high polarization strength thin barrier layer comprises AlN, ScAlN, InAlN, InAlGaN or high Al component AlGaN.

8. The method for preparing a GaN HEMT device based on in-situ SiNx according to claim 5, characterized in that: Growing an in-situ SiNx layer on a thin barrier layer with high polarization strength, including: An in-situ SiNx layer with a thickness of 2nm to 10nm is grown on the high polarization strength thin barrier layer by using a MOCVD process.

9. The method for preparing a GaN HEMT device based on in-situ SiNx according to claim 5, characterized in that: Etching away part of the SiNx layer in the source and drain ohmic regions to form an ohmic groove, comprising: The SiNx layer is etched away to a depth of 1 nm to 7 nm in the source and drain ohmic regions to form ohmic grooves.

Images