Drive control circuit board and display panel

Abstract

The application discloses a driving control circuit board and a display panel, comprising a first layout area, a second layout area and a third layout area which are sequentially and adjacently arranged along a first direction, the sizes of the first layout area, the second layout area and the third layout area along a second direction are sequentially reduced. The first layout area is used for arranging a first data driving circuit and a first number range of signal transmission lines, the second layout area is used for arranging a second data driving circuit and a second number range of signal transmission lines, and the third layout area is used for arranging a third data driving circuit and a third number range of signal transmission lines, the values of the first number range, the second number range and the third number range are sequentially reduced. By adjusting the areas of the first layout area, the second layout area and the third layout area, the wiring space around the second data driving circuit can be effectively increased, so as to eliminate the problems of heat generation and short circuit caused by space congestion.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a driving control circuit board and a display panel. BACKGROUND

[0002] At present, the driving control circuit board in the display panel is usually designed as a knife-shaped board frame, that is, the driving control circuit board has two rectangular regions with different lengths along the length direction, which are a first layout region and a second layout region respectively, the length of the first layout region is greater than that of the second layout region, the first layout region is used for laying signal lines and data driving ICs, and the second layout region is used for laying part of the signal lines, timing control circuits and power supply circuits.

[0003] However, since the length of the second layout region is less than that of the first layout region, the signal lines and the data driving ICs are arranged at the middle position of the first layout region, that is, the starting position of the excess part of the first layout region compared with the second layout region, which causes insufficient wiring space, leading to crowded arrangement of the signal lines and causing the risk of overheating of the lines and short circuit. Therefore, how to optimize the spatial layout of the signal lines and the driving ICs while ensuring small space occupation of the driving control circuit board is a problem to be solved. SUMMARY

[0004] In view of the above deficiencies of the prior art, the present application provides a driving control circuit board and a display panel which can effectively eliminate the problem of insufficient space at the critical position of the first layout region and the second layout region.

[0005] The present application provides a driving control circuit board applied to a display device for performing image display, comprising a first layout region, a second layout region and a third layout region arranged in sequence along a first direction, the sizes of the first layout region, the second layout region and the third layout region along a second direction decrease in sequence, and the second direction is perpendicular to the first direction. The first layout region is used for arranging a first data driving circuit and a first number range of signal transmission lines, the second layout region is used for arranging a second data driving circuit and a second number range of signal transmission lines, and the third layout region is used for arranging a third data driving circuit and a third number range of signal transmission lines, and the values of the first number range, the second number range and the third number range decrease in sequence.

[0006] Optionally, the first layout area is further provided with at least one functional circuit, the functional circuit being configured to control the first data driving circuit, the second data driving circuit and the third data driving circuit to output data signals, the first data driving circuit, the second data driving circuit and the third data driving circuit being arranged in sequence along the first direction and receiving data control signals from the timing control circuit through the signal transmission lines respectively and outputting data signals according to the data control signals, the data signals being used to be transmitted to pixel units in the image display area and drive the pixel units to perform image display.

[0007] Optionally, the first functional circuit comprises a timing control circuit and a power supply circuit, the timing control circuit being configured to output data control signals for image display, the power supply circuit being configured to provide a power supply voltage for the timing control circuit, the third functional circuit comprising a gamma circuit and a level conversion circuit, the gamma circuit being configured to correct gray scale voltages corresponding to the data signals output by the first data driving circuit, the second data driving circuit and the third data driving circuit, and the level conversion circuit being configured to output clock signals to adjust the timing of the display device receiving the data signals.

[0008] Optionally, the distance between the first data driving circuit and the second data driving circuit is equal to the distance between the second data driving circuit and the third data driving circuit.

[0009] Optionally, the size of the second layout area along the first direction is equal to the size of the second data driving circuit along the first direction.

[0010] Optionally, the difference between the size of the first layout area and the size of the second layout area along the second direction is equal to the difference between the size of the second layout area and the size of the third layout area along the second direction.

[0011] Optionally, the size of the first layout area along the first direction is equal to the size of the third layout area along the first direction, and the size of the first layout area along the first direction is greater than the size of the second layout area along the first direction.

[0012] Optionally, the first layout area is provided with at least one first functional circuit, and the second layout area or the third layout area is provided with at least one second functional circuit, the first functional circuit and the second functional circuit being used to control the first data driver circuit, the second data driver circuit, and the third data driver circuit to output data signals. The first data driver circuit, the second data driver circuit, and the third data driver circuit are arranged sequentially along the first direction, and each receives a data control signal from the timing control circuit via the signal transmission line, and outputs a data signal based on the data control signal, the data signal being used to transmit to the pixel units in the image display area and drive the pixel units to perform image display.

[0013] Optionally, the first layout area is provided with a timing control circuit, which is used to output a data control signal for image display; the second layout area is provided with a power supply circuit and a gamma circuit, the power supply circuit is used to provide a power supply voltage for the timing control circuit, and the gamma circuit is used to correct the grayscale voltage corresponding to the data signal output by the first data driving circuit, the second data driving circuit and the third data driving circuit; the third layout area is provided with a level conversion circuit, which is used to output a clock signal to adjust the timing of the display device receiving the data signal.

[0014] Optionally, the size of the first layout area along the first direction, the size of the second layout area along the first direction, and the size of the third layout area along the first direction are all equal, and the second data driving circuit is located at the midpoint of the second layout area along the first direction.

[0015] Optionally, a size difference between the first layout area and the second layout area along the second direction is twice a size difference between the second layout area and the third layout area along the second direction.

[0016] The present application also provides a display panel, comprising the aforementioned drive control circuit board, a scan drive circuit connected to the timing control circuit, a plurality of scan lines extending along a first direction and arranged sequentially along a second direction, a plurality of data lines extending along the second direction and arranged sequentially along the first direction, and pixel units arranged in an array, wherein the plurality of data lines are connected to the data drive circuit, the plurality of scan lines are connected to the scan drive circuit, the scan drive circuit outputs a scan signal under the control of the timing control circuit, the pixel unit is connected to the data line and the scan line, the pixel unit is used to receive a data signal from the data drive circuit in the drive control circuit board through the data line and to receive a scan signal from the scan drive circuit through the scan line, and to perform image display under the cooperation of the scan signal and the data signal.

[0017] Compared with the existing technology, by setting the first layout area, the second layout area and the third layout area and adjusting the areas of the first layout area, the second layout area and the third layout area, the wiring space around the data driving circuit in the second layout area is increased, thereby effectively optimizing the layout setting of the signal transmission lines and auxiliary circuits around the data driving circuit, eliminating the heat and short circuit problems caused by crowded signal transmission line space. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians, other drawings can be obtained based on these drawings without creative work.

[0019] Figure 1 A schematic diagram of the structure of a display terminal provided in the first embodiment of the present application

[0020] Figure 2 for Figure 1 A schematic diagram of the side structure of the display panel;

[0021] Figure 3 for Figure 2 Schematic diagram of the planar layout of the display panel;

[0022] Figure 4 for Figure 3 Schematic diagram of the structure of the middle drive control circuit board;

[0023] Figure 5 A second embodiment of the present application provides a Figure 3 Schematic diagram of the structure of the middle drive control circuit board;

[0024] Figure 6 for Figure 5 Schematic diagram of cutting and making the middle drive control circuit board;

[0025] Figure 7 A third embodiment of the present application provides a method as follows Figure 3 Schematic diagram of the structure of the drive control circuit board.

[0026] Reference numerals:

[0027] Display terminal-100, display panel-10, power module-20, support frame-30, display area-10a, non-display area-10b, m data lines-S1~Sm, n scan lines-G1~Gn, pixel unit-P, array substrate-10c, opposite substrate-10d, display medium layer-10e, timing control circuit-11, data drive circuit-12, scan drive circuit-13, backlight module-14, first direction-F1, second direction-F2, horizontal synchronization signal-Hsyn, vertical synchronization signal-Vsyn, scan control signal-Cg, data control signal-Cs, drive control circuit board-16, power circuit-17, gamma circuit-18, level conversion circuit-19, first layout area-161, second layout area-162, third layout area-163, first data drive circuit-12a, second data drive circuit-12b, third data drive circuit-12c, first length-d1, second length-d2, third length-d3, fourth length-d4, fifth length-d5, sixth length-d6. DETAILED DESCRIPTION

[0028] For the purposes of this application, the following description will be made with reference to the accompanying drawings. The preferred embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms, and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0029] The following description of the embodiments is made with reference to the accompanying drawings, which illustrate specific embodiments in which the present application can be implemented. The serial numbers of the components in this paper, such as "first", "second", etc., are only used to distinguish the described objects, and do not have any order or technical meaning. The "connection" and "coupling" mentioned in this application, unless otherwise specified, include direct and indirect connections (couplings). The direction terms mentioned in this application, such as "up", "down", "front", "back", "left", "right", "inside", "outside", "side" and the like, are only the direction of the attached drawings. Therefore, the direction terms used are to better, more clearly illustrate and understand the present application, and are not intended to indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application.

[0030] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection; it can be directly connected, or indirectly connected through an intermediate medium, or it can be internal communication between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances. It should be noted that the terms "first", "second", etc. in the description, claims, and drawings of this application are used to distinguish different objects, rather than to describe a specific order.

[0031] In addition, the terms "include", "may include", "include", or "may include" used in this application indicate the existence of the corresponding functions, operations, elements, etc. disclosed, and do not limit one or more other functions, operations, elements, etc. In addition, the terms "include" or "include" indicate the existence of the corresponding features, numbers, steps, operations, elements, components, or combinations thereof disclosed in the specification, and do not exclude the existence or addition of one or more other features, numbers, steps, operations, elements, components, or combinations thereof, and are intended to cover non-exclusive inclusions. In addition, when describing the embodiments of the present application, "may" is used to indicate "one or more embodiments of the present application". And, the term "exemplary" is intended to refer to an example or illustration.

[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0033] See also Figure 1 , Figure 1 This is a schematic diagram of the structure of a display terminal provided in the first embodiment of the present application. Figure 1 As shown, the display terminal 100 includes a display panel 10, a power module 20, and a support frame 30. The display panel 10 and the power module 20 are fixed to the support frame 30. The power module 20 is located on the back side of the display panel 10, which is also the non-display surface of the display panel 10. The power module 20 is used to provide power voltage for the display panel 10 to display images. The support frame 30 provides a secure connection and protection for the display panel 10 and the power module 20. In other embodiments of the present application, the display terminal 100 may not be provided with a support frame 30, for example, in the case of a portable electronic device such as a mobile phone or tablet computer.

[0034] See also Figure 2 , Figure 2 for Figure 1 Schematic diagram of the side structure of the display panel.

[0035] like Figure 2 As shown, Figure 2 As shown, the display panel 10 includes an array substrate (AS) 10c, an opposing substrate 10d, and a display medium layer 10e interposed between the array substrate 10c and the opposing substrate 10d. Driving elements are provided on the array substrate 10c and the opposing substrate 10d to generate corresponding electric fields based on data signals (Data), thereby driving the display medium layer 10e to emit light of corresponding brightness to display images.

[0036] In an exemplary embodiment, the display panel 10 may be a liquid crystal display panel or other types of display panels, which is not limited in this application.

[0037] Taking a liquid crystal display panel as an example, the display medium layer 10e contains liquid crystal molecules, which display images by deflecting and transmitting light of a preset brightness. The display panel 10 also includes a backlight module 14 (BM), which is used to provide light for display to the display area 10a of the display panel 10. The display panel 10 emits corresponding light according to the image signal to be displayed to perform image display. The display panel 10 also includes other elements or components, such as a signal processing module and a signal sensing module.

[0038] Please also refer to Figure 3 , Figure 3 for Figure 2 A schematic diagram of the floor plan layout of the display panel is shown in FIG.

[0039] like Figure 3 As shown, the display panel 10 further includes a data driving circuit 12, a scan driving circuit 13 and a timing control circuit 11. The timing control circuit 11, the data driving circuit 12 and the scan driving circuit 13 are arranged in the non-display area 10b.

[0040] The display area 10a of the display panel 10 is provided with m data lines (Source lines) S1 to Sm and n scan lines (Gate lines) G1 to Gn arranged in a grid pattern. The n scan lines G1 to Gn extend along a first direction F1 and are sequentially arranged along a second direction F2. The m data lines S1 to Sm extend along a second direction F2 and are sequentially arranged along the first direction F1. The first direction F1 and the second direction F2 are perpendicular to each other. Pixel units P are provided at the intersections of the n scan lines G1 to Gn and the data lines S1 to Sm.

[0041] The timing control circuit 11 receives image signals representing image information, horizontal synchronization signals Hsyn, and vertical synchronization signals Vsyn from an external signal source, and outputs data control signals Cs for controlling the data driver circuit 12, as well as clock signals and scan control signals Cg for controlling the scan driver circuit 13. m data lines S1 through Sm are connected to the data driver circuit 11 and receive and transmit data signals stored in the form of grayscale values ​​from the data driver circuit 12. n scan lines G1 through Gn are connected to the scan driver circuit 13 and receive scan signals from the scan driver circuit 13.

[0042] The scan driver circuit 13 receives the scan control signal Cg from the timing control circuit 11 and outputs scan signals to n scan lines G1-Gn. The data driver circuit 12 receives the data control signal Cs from the timing control circuit 11 and outputs it to each pixel unit P in the display area 10a via m data lines S1-Sm. The data signals provided to the display panel 10 are analog grayscale voltages. The scan driver circuit 13 outputs scan signals to control the pixel units P to receive the data signals from the data driver circuit 12, thereby controlling the pixel units P to display a corresponding image. Each pixel unit P is connected to a scan line and a data line. Under the control of the n scan lines G1-Gn, each pixel unit receives a data voltage corresponding to the grayscale value in the data signal provided by the data lines S1-Sm during a predetermined time period. Based on this data voltage, the display medium layer 10e is deflected by a corresponding angle, thereby causing the received backlight to emit light of a corresponding brightness according to the deflected angle, thereby emitting light of a corresponding brightness according to the image signal to display an image.

[0043] The display panel 10 further includes a drive control circuit board 16 ( Figure 4 ), the driving control circuit board 16 is arranged in the non-display area 10b of the display panel 10, and the timing control circuit 11, the data driving circuit 12 and other functional modules are arranged on the driving control circuit board 16.

[0044] In this embodiment, the circuit elements in the scan driving circuit 13 and the pixel units P in the array substrate 10 c are manufactured in the same process in the array substrate 10 c , which is also the GOA (Gate Driver on Array) technology.

[0045] See also Figure 4 , Figure 4 for Figure 3 Schematic diagram of the structure of the drive control circuit board.

[0046] The driving control circuit board 16 is arranged on the back of the array substrate 10c, that is, arranged in the non-display area 10b of the display panel 10, and is used to arrange the timing control circuit 11 and the data driving circuit 12, the power supply circuit 17, the gamma circuit 18 and the level conversion circuit 19 for driving the pixel units in the display area 10a to display images. The power supply circuit 17 is used to provide a power supply voltage for the timing control circuit 11, the gamma circuit is used to correct the grayscale corresponding to the data signal output by the data driving circuit 12, and the level conversion circuit 19 is used to output a clock signal to the scan driving circuit 13 ( Figure 3 ) to adjust the timing of scan signal output.

[0047] Among them, the drive control circuit board 16 includes a first layout area 161 and a second layout area 162 arranged adjacent to each other in sequence along the first direction F1. The first layout area 161 and the second layout area 162 are rectangular structures, and the first layout area 161 and the second layout area 162 have the same length along the first direction F1, and the length along the second direction F2 decreases successively.

[0048] The data driving circuit 12 includes a first data driving circuit 12a, a second data driving circuit 12b, and a third data driving circuit 12c, which are arranged in sequence along the first direction F1. The first layout area 161 is used to set the first data driving circuit 12a, a first number range of signal transmission lines, a timing control circuit 11, and a power supply circuit 17. The second data driving circuit 12b is set at the position where the first layout area 161 and the second layout area 162 contact along the first direction F1. The third data driving circuit 12c, a second number range of signal transmission lines, a gamma circuit 18, and a level conversion circuit 19 are set in the second layout area 162. The first number range is larger than the second number range, that is, the number of signal transmission lines set in the first layout area 161 is larger than the number of signal transmission lines set in the second layout area 162.

[0049] The first data driving circuit 12a, the second data driving circuit 12b and the third data driving circuit 12c respectively receive data control signals from the timing control circuit 11 through signal transmission lines, and output data signals to the pixel units P in the display area 10a according to the data control signals to control the pixel units P to display images.

[0050] The first layout area 161 , the second layout area 162 and the third layout area 163 are further provided with a plurality of auxiliary circuits RC. The auxiliary circuits RC may be voltage stabilizing circuits, filtering circuits, etc., for performing functions such as voltage stabilization and filtering when the timing control circuit 11 , the power supply circuit 17 and the level conversion circuit 19 are in operation.

[0051] The length of the first layout area 161 along the second direction F2 is a first length d1 , and the length of the second layout area 162 along the second direction F2 is a second length d2 , wherein the first length d1 is greater than the second length d2 .

[0052] By providing the driving control circuit board 16 with two first layout areas 161 and second layout areas 162 of different lengths, the space occupied by the driving control circuit board 16 can be effectively reduced, and the production cost of the driving control circuit board can be saved.

[0053] See also Figure 5 , Figure 5 A second embodiment of the present application provides a Figure 3 The schematic diagram of the structure of the drive control circuit board. Figure 5 As shown, the driving control circuit board 16 is arranged on the back of the array substrate 10c, that is, arranged in the non-display area 10b of the display panel 10, and is used to arrange the timing control circuit 11, the data driving circuit 12, the power supply circuit 17, the gamma circuit 18 and the level conversion circuit 19 for driving the pixel units in the display area 10a to display images. The power supply circuit 17 is used to provide a power supply voltage for the timing control circuit 11, the gamma circuit is used to correct the grayscale corresponding to the data signal output by the data driving circuit 12, and the level conversion circuit 19 is used to output a clock signal to the scan driving circuit 13 ( Figure 3 ) to adjust the timing of scan signal output.

[0054] Among them, the drive control circuit board 16 includes a first layout area 161, a second layout area 162 and a third layout area 163 which are arranged adjacent to each other in sequence along the first direction F1. The first layout area 161, the second layout area 162 and the third layout area 163 all have a rectangular structure, and the lengths of the first layout area 161, the second layout area 162 and the third layout area 163 along the second direction F2 decrease successively.

[0055] The data driver circuit 12 includes a first data driver circuit 12a, a second data driver circuit 12b, and a third data driver circuit 12c, sequentially arranged along a first direction F1. A first layout area 161 is used to arrange the first data driver circuit 12 and a first number of signal transmission lines. A second layout area 162 is used to arrange the second data driver circuit 12b and a second number of signal transmission lines. A third layout area 163 is used to arrange the third data driver circuit 12c and a third number of signal transmission lines. The first number range is greater than the second number range and the third number range. That is, the number of signal transmission lines arranged in the first layout area 161 is greater than the number of signal transmission lines arranged in the second layout area 162, and the number of signal transmission lines arranged in the second layout area 162 is greater than the number of signal transmission lines arranged in the third layout area 163. The first data driver circuit 12a, the second data driver circuit 12b, and the third data driver circuit 12c each receive data control signals from the timing control circuit 11 via signal transmission lines and output data signals to the pixel cells P in the display area 10a based on the data control signals to control the pixel cells P to display images.

[0056] Among them, the first layout area 161 is provided with a timing control circuit 11 and a power supply circuit 17, and the third layout area 163 is provided with a gamma circuit 18 and a level conversion circuit 19. Of course, the specific positions of the timing control circuit 11, the power supply circuit 17, the gamma circuit 18 and the level conversion circuit 19 can also be adjusted according to the specific sizes of the first layout area 161, the second layout area 162 and the third layout area 163 and the sizes of each functional circuit. For example, the timing control circuit 11, the power supply circuit 17 and the gamma circuit 18 can also be set in the first layout area 161, and the level conversion circuit 19 can be set in the third layout area 163. This application does not impose any restrictions on this.

[0057] The first layout area 161 , the second layout area 162 and the third layout area 163 are also respectively provided with a plurality of auxiliary circuits RC. The auxiliary circuits RC may be voltage stabilizing circuits, filtering circuits, etc., for performing functions such as voltage stabilization and filtering when the timing control circuit 11 , the power supply circuit 17 and the level conversion circuit 19 are in operation.

[0058] The length of the first layout area 161 along the second direction F2 is a first length d1, the length of the second layout area 162 along the second direction F2 is a second length d2, and the length of the third layout area 163 along the second direction F2 is a third length d3, wherein the first length d1 is greater than the second length d2, and the second length d2 is greater than the third length d3. The length of the first layout area 161 along the first direction F1 is equal to the length of the third layout area 163 along the first direction F1, and is greater than the length of the second layout area 162 along the first direction F1.

[0059] In an exemplary embodiment, the distance between the second data driving circuit 12b and the first data driving circuit 12a is equal to the distance between the second data driving circuit 12b and the third data driving circuit 12c, that is, the distances between the first data driving circuit 12a, the second data driving circuit 12b and the third data driving circuit 12c along the first direction F1 are equal. Of course, the spacing between the first data driving circuit 12a, the second data driving circuit 12b and the third data driving circuit 12c can also be set to other distances according to specific layout requirements, and this application does not impose any restrictions on this.

[0060] In an exemplary embodiment, the first data driving circuit 12a, the second data driving circuit 12b and the third data driving circuit 12c can be manufactured on a flexible circuit board using a chip on flex (COF) and connected to the driving control circuit board 16 and the array substrate 10c through the flexible circuit board to achieve signal transmission.

[0061] The second data driving circuit 12b is disposed in the second layout area 162. The length of the second data driving circuit 12b along the first direction F1 is the sixth length d6. The length of the second layout area 162 along the first direction F1 is also the sixth length d6. That is, the size of the second layout area 162 along the first direction F1 is equal to the size of the second data driving circuit 12b along the first direction F1.

[0062] By arranging the second data driving circuit 12b in the second layout area 162, that is, arranging the data driving circuit in the middle of the driving control circuit board 16 in the second layout area 162, the layout of the signal transmission lines and the auxiliary circuit RC around the second data driving circuit 12b can be effectively optimized, thereby eliminating the heating and short circuit problems caused by the crowding of the signal transmission lines and the auxiliary circuit RC.

[0063] In the exemplary embodiment, the difference in length between the first layout area 161 and the second layout area 162 along the second direction F2 is equal to the difference in length between the second layout area 162 and the third layout area along the second direction F2. That is, the difference between the first length d1 and the second length d2 is equal to the fourth length d4, the difference between the second length d2 and the third length d3 is equal to the fifth length d5, and the fourth length d4 is equal to the fifth length d5. Because the fourth length d4 is equal to the fifth length d5, the overall area of ​​the drive control circuit board 16 is the same as that of the drive control circuit board 16 in the first embodiment.

[0064] In an exemplary embodiment, the first length d1 can be 24 mm, the second length d2 can be 21 mm, and the third length d3 can be 18 mm. Therefore, the fourth length d4 is the difference between the first length d1 and the second length d2, which is equal to 3 mm, and the fifth length d5 ​​is the difference between the second length d2 and the third length d3, which is equal to 3 mm, that is, the fourth length d4 is equal to the fifth length d5. Of course, it can also be set to other sizes according to specific needs, and this application does not impose any restrictions on this.

[0065] By providing the first layout area 161, the second layout area 162, and the third layout area 163 and adjusting the areas of the first layout area 161, the second layout area 162, and the third layout area 163, the second data driving circuit 12b is located in the second layout area 162. This allows the wiring space around the second data driving circuit 12b to be increased while the area of ​​the driving control circuit board 16 remains unchanged, thereby effectively optimizing the layout of the signal transmission lines and the auxiliary circuit RC around the second data driving circuit 12b, and eliminating the problems of heating and short circuit caused by space crowding.

[0066] See also Figure 6 , Figure 6 for Figure 5 Schematic diagram of cutting and manufacturing the mid-drive control circuit board.

[0067] like Figure 6 As shown, two identical drive control circuit boards are formed by cutting a whole rectangular drive control circuit board. Compared with the "knife-shaped" drive control circuit board in the first embodiment, the drive control circuit board in this embodiment only changes the cutting process during the production and cutting process, and does not change the overall area of ​​the drive control circuit board. Therefore, while ensuring that the area of ​​the drive control circuit board remains unchanged, a second layout area is set to optimize the wiring space around the second data drive circuit, eliminating the heating and short circuit problems caused by the congestion of signal transmission lines and auxiliary circuits.

[0068] See also Figure 7 , Figure 7 A third embodiment of the present application provides a method as follows Figure 3 Schematic diagram of the structure of the drive control circuit board.

[0069] like Figure 7As shown, the driving control circuit board 16 is arranged on the back of the array substrate 10c, that is, arranged in the non-display area 10b of the display panel 10, and is used to arrange the timing control circuit 11, the data driving circuit 12, the power supply circuit 17, the gamma circuit 18 and the level conversion circuit 19 for driving the pixel units in the display area 10a to display images. The power supply circuit 17 is used to provide a power supply voltage for the timing control circuit 11, the gamma circuit is used to correct the grayscale corresponding to the data signal output by the data driving circuit 12, and the level conversion circuit 19 is used to output a clock signal to the scan driving circuit 13 ( Figure 3 ) to adjust the timing of scan signal output.

[0070] The drive control circuit board 16 includes a first layout area 161, a second layout area 162 and a third layout area 163 which are arranged adjacent to each other in sequence along the first direction F1. The first layout area 161, the second layout area 162 and the third layout area 163 all have a rectangular structure, and the lengths of the first layout area 161, the second layout area 162 and the third layout area 163 along the first direction F1 are equal, and the lengths along the second direction F2 decrease successively.

[0071] The data driving circuit 12 includes a first data driving circuit 12a, a second data driving circuit 12b and a third data driving circuit 12c, wherein the first layout area 161 is used to set the first data driving circuit 12a and a first number range of signal transmission lines, the second layout area 162 is used to set the second data driving circuit 12 and a second number range of signal transmission lines, and the third layout area 163 is used to set the third data driving circuit 12c and a third number range of signal transmission lines. The first number range is larger than the second number range and larger than the third number range, that is, the number of signal transmission lines set in the first layout area 161 is larger than the number of signal transmission lines set in the second layout area 162, and the number of signal transmission lines set in the second layout area 162 is larger than the number of signal transmission lines set in the third layout area 163. The first data driving circuit 12a, the second data driving circuit 12b, and the third data driving circuit 12c are sequentially arranged along the first direction F1, and each receives a data control signal from the timing control circuit 11 through a plurality of signal transmission lines, and outputs a data signal to the pixel units P in the display area 10a according to the data control signal, so as to control the pixel units P to display an image.

[0072] Among them, the first layout area 161 is provided with a timing control circuit 11 and a power supply circuit 17, the second layout area 162 is provided with a gamma circuit 18, and the third layout area 163 is provided with a level conversion circuit 19. The power supply circuit 17 can also be set in the first layout area 161 and the second layout area 162 at the same time, that is, the power supply circuit 17 is set in a position adjacent to the first layout area 161 and the second layout area 162, so that part of the power supply circuit 17 is located in the first layout area 161 and the other part is located in the second layout area 162. Of course, the layout can also be carried out according to specific needs, not limited to the above-mentioned arrangement, and this application does not impose any restrictions on this.

[0073] The first layout area 161 , the second layout area 162 and the third layout area 163 are further provided with a plurality of auxiliary circuits RC. The auxiliary circuits RC may be voltage stabilizing circuits, filtering circuits and the like, and are used to perform functions such as voltage stabilization and filtering when functional circuits such as the timing control circuit 11 , the power supply circuit 17 and the level conversion circuit 19 are in operation.

[0074] The length of the first layout area 161 along the second direction F2 is a first length d1, the length of the second layout area 162 along the second direction F2 is a second length d2, and the length of the third layout area 163 along the second direction F2 is a third length d3, wherein the first length d1 is greater than the second length d2, and the second length d2 is greater than the third length d3, that is, the first layout area 161, the second layout area 162, and the third layout area 163 are arranged in a stepped manner along the first direction F1.

[0075] In an exemplary embodiment, the distance between the first data driving circuit 12a and the second data driving circuit 12b is equal to the distance between the second data driving circuit 12b and the third data driving circuit 12c. That is, in the first direction F1, the first data driving circuit 12a, the second data driving circuit 12b and the third data driving circuit 12c are arranged at equal distances. Of course, the spacing between the first data driving circuit 12a, the second data driving circuit 12b and the third data driving circuit 12c can also be set to other distances according to specific layout requirements, and this application does not impose any restrictions on this.

[0076] The second data driving circuit 12b is disposed at the midpoint of the second layout area 162 along the first direction F1. That is, the distances from the second data driving circuit 12b to both sides of the second layout area 162 along the first direction F1 are equal. In other words, the distance from the second data driving circuit 12b to the contact position between the second layout area 162 and the first layout area 161 is equal to the distance from the second data driving circuit 12b to the contact position between the second layout area 162 and the third layout area 163.

[0077] By disposing the second data driving circuit 12 b in the second layout area 162 , that is, disposing the data driving circuit in the middle of the driving control circuit board 16 in the second layout area 162 , the signal transmission lines and the auxiliary circuit RC around the second data driving circuit 12 b can be effectively optimized, thereby eliminating heating and short circuit problems caused by crowded space between the signal transmission lines and the gamma circuit 18.

[0078] In an exemplary embodiment, the difference in length between the first layout area 161 and the second layout area 162 along the second direction F2 is equal to the fourth length d4, that is, the difference between the first length d1 and the second length d2 is the fourth length d4, and the difference in length between the second layout area 162 and the third layout area 163 along the second direction F2 is the fifth length d5, that is, the difference between the second length d2 and the third length d3 is equal to the fifth length d5, where the fifth length d5 ​​is twice the fourth length d4.

[0079] In an exemplary embodiment, the first length d1 can be 24 mm, the second length d2 can be 21 mm, and the third length d3 can be 15 mm. Therefore, the fourth length d4 is the difference between the first length d1 and the second length d2, which is equal to 3 mm, and the fifth length d5 ​​is the difference between the second length d2 and the third length d3, which is equal to 6 mm, that is, the fifth length d5 ​​is twice the fourth length d4. Of course, it can also be set to other sizes according to specific needs, and this application does not impose any restrictions on this.

[0080] By providing a first layout area 161, a second layout area 162, and a third layout area 163, and adjusting the areas of the first layout area 161, the second layout area 162, and the third layout area 163, the area of ​​the second layout area 162 is increased, thereby increasing the wiring space around the second data driver circuit 12b, and the gamma circuit in the third layout area 163 is arranged in the second layout area 162, thereby reducing the space occupied by the third layout area 163 and increasing the signal transmission line layout space in the third layout area 163, thereby effectively optimizing the layout of the signal transmission lines around the second data driver circuit 12b and the third data driver circuit 12c, and eliminating the heating and short circuit problems caused by the congestion of the signal transmission lines.

[0081] It should be understood that the application of the present invention is not limited to the above examples. For those skilled in the art, improvements or changes can be made based on the above description. All these improvements and changes should fall within the scope of protection of the claims attached to the present invention.

Claims

1. A drive control circuit board, used in a display device for performing image display, characterized in that: comprising a first layout area, a second layout area, and a third layout area sequentially arranged adjacent to each other along a first direction, wherein the sizes of the first layout area, the second layout area, and the third layout area sequentially decrease along a second direction, and the second direction is perpendicular to the first direction; The first layout area is used to set a first data driving circuit and a first number range of signal transmission lines, the second layout area is used to set a second data driving circuit and a second number range of signal transmission lines, and the third layout area is used to set a third data driving circuit and a third number range of signal transmission lines, and the values ​​of the first number range, the second number range, and the third number range decrease in sequence; The first layout area is further provided with at least one first functional circuit, and the third layout area is further provided with at least one second functional circuit, the first functional circuit and the second functional circuit are used to control the first data driving circuit, the second data driving circuit, and the third data driving circuit to output data signals, wherein the first functional circuit is a timing control circuit; The first data driving circuit, the second data driving circuit and the third data driving circuit are arranged in sequence along the first direction, and respectively receive data control signals from the timing control circuit through the signal transmission line, and output data signals based on the data control signals. The data signals are used to be transmitted to the pixel units in the image display area and drive the pixel units to perform image display.

2. The drive control circuit board according to claim 1, wherein: A distance between the first data driving circuit and the second data driving circuit is equal to a distance between the second data driving circuit and the third data driving circuit.

3. The drive control circuit board according to claim 2, wherein: A size of the second layout area along the first direction is equal to a size of the second data driving circuit along the first direction.

4. The drive control circuit board according to claim 3, wherein: A size difference between the first layout area and the second layout area along the second direction is equal to a size difference between the second layout area and the third layout area along the second direction.

5. The drive control circuit board according to any one of claims 1 to 4, characterized in that: The size of the first layout area along the first direction is equal to the size of the third layout area along the first direction; A size of the first layout area along the first direction is greater than a size of the second layout area along the first direction.

6. The drive control circuit board according to claim 1, wherein: The size of the first layout area along the first direction, the size of the second layout area along the first direction, and the size of the third layout area along the first direction are all equal, and the second data driving circuit is located at the midpoint of the second layout area along the first direction.

7. The drive control circuit board according to claim 6, wherein: A size difference between the first layout area and the second layout area along the second direction is twice a size difference between the second layout area and the third layout area along the second direction.

8. A display panel, characterized in that: It includes a driving control circuit board as described in any one of claims 2 to 7, a scanning driving circuit connected to the timing control circuit, a plurality of scanning lines extending along a first direction and arranged in sequence along a second direction, a plurality of data lines extending along the second direction and arranged in sequence along the first direction, and pixel units arranged in an array, a plurality of the data lines are connected to the data driving circuit, a plurality of the scanning lines are connected to the scanning driving circuit, the scanning driving circuit outputs a scanning signal under the control of the timing control circuit, the pixel unit is connected to the data line and the scanning line, the pixel unit is used to receive a data signal from the data driving circuit in the driving control circuit board through the data line and receive a scanning signal from the scanning driving circuit through the scanning line, and perform image display under the cooperation of the scanning signal and the data signal.

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