Ultrasonic detection circuit and driving method thereof, ultrasonic detection device
By designing a combination of reset module, acquisition module, drive transistor and compensation module in the ultrasonic detection circuit, the signal distortion problem caused by the difference in threshold voltage of thin film transistors is solved, and high-resolution and high-accuracy ultrasonic imaging and fingerprint recognition are achieved.
Patent Information
- Application Number
- CN202310611551.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2023-05-26
- Publication Date
- 2025-10-17
- Estimated Expiration
- 2043-05-26
AI Technical Summary
In existing ultrasonic detection circuits, large differences in the threshold voltages of thin-film transistors lead to distortion of the collected signals, affecting the resolution and accuracy of ultrasonic imaging.
A combination design of a reset module, an acquisition module, a driving transistor, a storage module and a compensation module is adopted. By writing the threshold voltage of the driving transistor to the second node in the reset and compensation stage and utilizing the bootstrap effect of the storage module, it is ensured that the voltage difference in the subsequent acquisition and reading stages is only related to the signal received by the ultrasonic sensor, eliminating the influence of the threshold voltage difference.
It improves the resolution and accuracy of ultrasonic imaging and reduces the error of ultrasonic signal detection, especially in large-area two-dimensional array ultrasonic imaging and fingerprint recognition.
Smart Images

Figure CN116643258B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present disclosure relates to the technical field of ultrasonic detection, and in particular to an ultrasonic detection circuit and a driving method thereof, and an ultrasonic detection device. BACKGROUND
[0002] Ultrasonic imaging is an important non-destructive testing method in medical treatment. With the update of technology, ultrasonic imaging develops towards faster, clearer and three-dimensional directions. High definition and high resolution are the goals that people have been exploring and pursuing, which is conducive to discovering diseases earlier so as to treat them in time. SUMMARY
[0003] The present disclosure provides an ultrasonic detection circuit, comprising a reset module, an acquisition module, a driving transistor, a storage module, a compensation module and a reading module.
[0004] The reset module is connected with a reset control end, a reset signal end and a first node respectively, and is configured to write a reset signal of the reset signal end into the first node in response to a reset control signal of the reset control end.
[0005] The acquisition module is connected with an acquisition control end, an ultrasonic sensor and the first node, and is configured to write a signal received by the ultrasonic sensor into the first node in response to an acquisition control signal of the acquisition control end.
[0006] The driving transistor has a control electrode connected with the first node, a first electrode connected with the compensation module, and a second electrode connected with a second node.
[0007] The storage module is connected with the first node and the second node respectively, and is configured to store a voltage between the first node and the second node.
[0008] The compensation module is further connected with a compensation control end and a first voltage end, and is configured to write a threshold voltage of the driving transistor into the second node in response to a compensation control signal of the compensation control end.
[0009] The reading module is connected with a reading control end, the second node and an output end respectively, and is configured to output a detection signal at the output end according to potentials of the first node and the second node in response to a reading control signal of the reading control end.
[0010] In some embodiments, the reset module is directly connected with the first node; or
[0011] The reset module is connected with the first node through the collection module, and the reset module is specifically configured to write the reset signal into the collection module in response to the reset control signal; and the collection module is further configured to write the reset signal into the first node in response to the collection control signal.
[0012] In some embodiments, the reset module comprises:
[0013] A second transistor, a control electrode of which is connected with the reset control terminal, a first electrode of which is connected with the reset signal terminal, and a second electrode of which is directly connected with the first node or connected with the first node through the collection module.
[0014] In some embodiments, the collection module comprises:
[0015] A third transistor, a control electrode of which is connected with the collection control terminal, a first electrode of which is connected with the ultrasonic sensor or connected with the ultrasonic sensor and the reset module respectively, and a second electrode of which is connected with the first node.
[0016] In some embodiments, the storage module comprises:
[0017] A first capacitor, a first electrode of which is connected with the first node, and a second electrode of which is connected with the second node.
[0018] In some embodiments, the compensation module comprises:
[0019] A fourth transistor, a control electrode of which is connected with the compensation control terminal, a first electrode of which is connected with the first voltage terminal, and a second electrode of which is connected with the first electrode of the driving transistor.
[0020] In some embodiments, the reading module comprises:
[0021] A fifth transistor, a control electrode of which is connected with the reading control terminal, a first electrode of which is connected with the second node, and a second electrode of which is connected with the output terminal.
[0022] In some embodiments, the ultrasonic detection circuit further comprises:
[0023] A control signal generation module, connected with the reset control terminal, the reading control terminal and the compensation control terminal respectively, configured to generate the compensation control signal at the compensation control terminal in response to the reset control signal and the reading control signal.
[0024] In some embodiments, the control signal generation module comprises:
[0025] A sixth transistor, a control electrode and a first electrode of which are connected with the reset control terminal, and a second electrode of which is connected with the compensation control terminal; and
[0026] The seventh transistor has a control electrode and a first electrode connected to the read control terminal, and a second electrode connected to the compensation control terminal.
[0027] The present disclosure provides an ultrasonic detection device, comprising:
[0028] A substrate;
[0029] A plurality of detection units arranged on one side of the substrate, each detection unit comprising an ultrasonic sensor and an ultrasonic detection circuit as described in any of the embodiments, the ultrasonic sensor being configured to receive a reflected ultrasonic signal and convert the received ultrasonic signal into an electrical signal.
[0030] In some embodiments, the plurality of detection units are arranged in a row direction and / or a column direction.
[0031] In some embodiments, the ultrasonic sensor is further configured to emit an ultrasonic signal in response to a first drive signal; or
[0032] The ultrasonic detection device further comprises an ultrasonic emitter configured to emit an ultrasonic signal in response to a second drive signal.
[0033] The present disclosure provides a driving method applied to an ultrasonic detection circuit as described in any of the embodiments, the driving method comprising:
[0034] A reset compensation phase, in which a reset control signal is provided to the reset control terminal and a compensation control signal is provided to the compensation control terminal, so as to turn on the reset module and the compensation module, write the reset signal to the first node, and write the threshold voltage of the drive transistor to the second node;
[0035] A collection phase, in which a collection control signal is provided to the collection control terminal, so as to turn on the collection module and write the signal received by the ultrasonic sensor to the first node;
[0036] A read phase, in which a compensation control signal is provided to the compensation control terminal and a read control signal is provided to the read control terminal, so as to turn on the compensation module and the read module, and output a detection signal at the output terminal according to the potentials of the first node and the second node.
[0037] In some embodiments, when the reset module is connected to the first node through the collection module, the reset compensation phase further comprises:
[0038] A collection control signal is provided to the collection control terminal, so as to turn on the collection module, and the reset signal is written to the first node through the reset module and the collection module in sequence.
[0039] In some embodiments, when the ultrasonic detection circuit further comprises a control signal generation module, and the control signal generation module is connected to the reset control end, the read control end and the compensation control end respectively, the step of providing a compensation control signal to the compensation control end comprises:
[0040] providing a reset control signal to the reset control end and a read control signal to the read control end to generate the compensation control signal at the compensation control end.
[0041] In some embodiments, after the last acquisition stage, before the next acquisition stage, further comprising:
[0042] a transmission stage, providing a first driving signal to the ultrasonic sensor to make the ultrasonic sensor emit an ultrasonic signal.
[0043] The above description is only a summary of the technical solutions of the present disclosure. In order to enable one skilled in the art to better understand the technical means of the present disclosure, the contents of the specification can be implemented, and in order to make the above and other purposes, features and advantages of the present disclosure more obvious and easy to understand, the following will specifically describe the embodiments of the present disclosure. BRIEF DESCRIPTION OF DRAWINGS
[0044] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the related art, the following will briefly introduce the drawings needed to be used in the embodiments or related art description. Obviously, the drawings in the following description are some embodiments of the present disclosure, and those skilled in the art can also obtain other drawings according to these drawings without creative labor. It should be noted that the proportions in the drawings are only for illustration and do not represent the actual proportions.
[0045] Figure 1 An exemplary structure diagram of an ultrasonic detection circuit in the related art is shown;
[0046] Figure 2 An exemplary structure diagram of a first ultrasonic detection circuit provided by the present disclosure is shown;
[0047] Figure 3 An exemplary structure diagram of a second ultrasonic detection circuit provided by the present disclosure is shown;
[0048] Figure 4 An exemplary equivalent circuit diagram of the first ultrasonic detection circuit in each stage is shown;
[0049] Figure 5 An exemplary equivalent circuit diagram of the second ultrasonic detection circuit in each stage is shown;
[0050] Figure 6 Fig. 3 shows a structural schematic diagram of a third ultrasonic detection circuit provided by the present disclosure;
[0051] Figure 7 Fig. 4 shows a structural schematic diagram of a fourth ultrasonic detection circuit provided by the present disclosure;
[0052] Figure 8 Fig. 5 shows a driving signal timing diagram of the first ultrasonic detection circuit;
[0053] Figure 9 Fig. 6 shows a driving signal timing diagram of the second ultrasonic detection circuit. DETAILED DESCRIPTION
[0054] In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only some, but not all of the embodiments of the present disclosure. Based on the embodiments in the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present disclosure.
[0055] The traditional ultrasonic imaging technology starts from the time distribution characteristics of waveforms, collects signals at all times, uses full-wave imaging algorithm, and mostly adopts one-dimensional array element design, and the identification resolution can reach 1 mm. Using acoustic imaging, starting from the spatial distribution characteristics of wavefronts, large-area two-dimensional array element design can realize the improvement of resolution, and the identification resolution can reach 0.5 mm-1 mm.
[0056] In the related art, the ultrasonic detection circuit in the array element adopts a 4T circuit as shown in Figure 1 Due to the poor uniformity of the performance of the thin film transistor in a large area range, such as a large difference in threshold voltage of the M3 transistor at different positions, the final collected signal is distorted.
[0057] In order to solve the above problems, with reference to Figure 2 and Figure 3 respectively, a structural schematic diagram of an ultrasonic detection circuit provided by the present disclosure is exemplarily shown, as shown in Figure 2 or Figure 3 The ultrasonic detection circuit includes a reset module 21, a collection module 22, a driving transistor T1, a storage module 23, a compensation module 24, and a reading module 25.
[0058] The reset module 21 is connected with a reset control end Rest, a reset signal end Vbias and a first node N1 respectively, and is configured to write a reset signal of the reset signal end Vbias into the first node N1 in response to a reset control signal of the reset control end Rest.
[0059] The collection module 22 is connected with a collection control end Close, an ultrasonic sensor Q and the first node N1, and is configured to write a signal received by the ultrasonic sensor Q into the first node N1 in response to a collection control signal of the collection control end Close.
[0060] A control pole of the driving transistor T1 is connected with the first node N1, a first pole of the driving transistor T1 is connected with the compensation module 24, and a second pole of the driving transistor T1 is connected with a second node N2.
[0061] The storage module 23 is connected with the first node N1 and the second node N2 respectively, and is configured to store a voltage between the first node N1 and the second node N2.
[0062] The compensation module 24 is further connected with a compensation control end VC and a first voltage end Vdd, and is configured to write a threshold voltage Vth of the driving transistor T1 into the second node N2 in response to a compensation control signal of the compensation control end VC.
[0063] The reading module 25 is connected with a reading control end Gate, the second node N2 and an output end Opt respectively, and is configured to output a detection signal at the output end Opt according to potentials of the first node N1 and the second node N2 in response to a reading control signal of the reading control end Gate.
[0064] Firstly, a reset control signal can be provided to the reset control end Rest and a compensation control signal can be provided to the compensation control end VC in a reset compensation stage t1, so that the reset module 21 and the compensation module 24 are turned on, the reset signal is written into the first node N1, and the threshold voltage Vth of the driving transistor T1 is written into the second node N2, as shown in a diagram of FIG. 1a. Figure 4 The equivalent circuit of the ultrasonic detection circuit shown in FIG. 1a in the stage is shown in a diagram of FIG. 1b. Figure 2 The voltage of the first node N1 is V1=Vbias, and the voltage of the second node N2 is V2=Vbias-Vth after the reset compensation stage t1 is completed.
[0065] Then, a collection control signal can be provided to the collection control end Close in a collection stage t2, so that the collection module 22 is turned on, and the signal received by the ultrasonic sensor Q is written into the first node N1, as shown in a diagram of FIG. 1c. Figure 4 The equivalent circuit of the ultrasonic detection circuit shown in FIG. 1c in the stage is shown in a diagram of FIG. 1d. Figure 2 Figure 5 Fig. 3c illustrates the equivalent circuit of the ultrasonic detection circuit in the read phase t3. Figure 3 Fig. 3c illustrates the equivalent circuit of the ultrasonic detection circuit in the read phase t3.
[0066] After that, in the read phase t3, a compensation control signal can be provided to the compensation control end VC, and a read control signal can be provided to the read control end Gate, so as to turn on the compensation module 24 and the read module 25, and output a detection signal at the output end Opt according to the potentials of the first node N1 and the second node N2. Referring to Fig. 3c, the equivalent circuit of the ultrasonic detection circuit in the read phase t3 is shown. Figure 4 Fig. 3c illustrates the equivalent circuit of the ultrasonic detection circuit in the read phase t3. Figure 2 Fig. 3c illustrates the equivalent circuit of the ultrasonic detection circuit in the read phase t3. Figure 5 Fig. 3c illustrates the equivalent circuit of the ultrasonic detection circuit in the read phase t3. Figure 3 Fig. 3c illustrates the equivalent circuit of the ultrasonic detection circuit in the read phase t3. In the read phase t3, the saturation current on the driving transistor T1 can be represented as:
[0067] Ids = 1 / 2*Cox*u*W / L*(Vgs-Vth)2
[0068] Where 1 / 2*Cox*u*W / L is a constant value, and the saturation current is related to the gate-source voltage difference Vgs and the threshold voltage Vth. If the threshold voltage Vth of the driving transistor T1 at different positions is quite different, it can cause a large difference in the output current at the output end Opt at different positions, and further cause a large error in ultrasonic detection.
[0069] In the present disclosure, the gate-source voltage difference Vgs is the voltage difference between the first node N1 and the second node N2, i.e. Vgs = V1-V2. Since in the reset and compensation phase t1, the second node N2 is written with the threshold voltage Vth of the driving transistor T1, and due to the bootstrap effect of the storage module 23, the voltage difference between the first node N1 and the second node N2 always contains the threshold voltage Vth of the driving transistor T1 in the subsequent acquisition phase t2 and the read phase t3, which can be substituted into the Ids formula to eliminate Vth, and finally make the saturation current Ids only related to Vbias and the signal U0 received by the ultrasonic sensor Q. Wherein, Vbias can be a constant level, so that the saturation current is only related to the signal U0 received by the ultrasonic sensor Q, and is independent of the threshold voltage Vth of the driving transistor T1, thereby eliminating the influence of the threshold voltage Vth of the driving transistor T1 at different positions on the output current, reducing the error of ultrasonic signal detection, and improving the detection accuracy.
[0070] It should be noted that in the read phase t3, since the compensation module 24, the driving transistor T1 and the read module 25 are connected in series, the saturation current of the driving transistor T1 can be considered as the readout current of the output end Opt.
[0071] The ultrasonic detection circuit provided by the present disclosure can be applied to ultrasonic imaging, facilitating the realization of high-resolution and high-precision ultrasonic imaging medical devices. For example, it can be applied to large-area two-dimensional array element ultrasonic imaging devices, facilitating improved recognition resolution and accuracy.
[0072] The ultrasonic detection circuit provided by the present disclosure can also be applied to fingerprint recognition, which is beneficial to improving the accuracy of fingerprint recognition.
[0073] In some embodiments, as Figure 2 As shown, the reset module 21 is directly connected to the first node N1.
[0074] In order to prevent the first node N1 from leaking, in some embodiments, as Figure 3 As shown, the reset module 21 is connected to the first node N1 via the acquisition module 22, and the reset module 21 and the ultrasonic sensor Q are connected to the same end of the acquisition module 22. Specifically, the reset module 21 is configured to write the reset signal into the acquisition module 22 in response to a reset control signal, and the acquisition module 22 is further configured to write the reset signal into the first node N1 in response to the acquisition control signal.
[0075] In the specific implementation, in the reset compensation phase t1, the acquisition control signal can also be provided to the acquisition control terminal Close to turn on the acquisition module 22, and the reset signal is sequentially passed through the reset module 21 and the acquisition module 22 and written into the first node N1. Figure 5 Figure a shows Figure 3 The equivalent circuit of the ultrasonic detection circuit at this stage is shown.
[0076] In some embodiments, as Figure 2 or Figure 3 As shown, the reset module 21 includes a second transistor T2, the control electrode of the second transistor T2 is connected to the reset control terminal Rest, the first electrode of the second transistor T2 is connected to the reset signal terminal Vbias, and the second electrode of the second transistor T2 is directly connected to the first node N1 (as shown in FIG. Figure 2 As shown), or the second electrode of the second transistor T2 and the first node N1 are connected through the acquisition module 22 (as shown Figure 3 (as shown). Figure 3 In the embodiment, the second electrode of the second transistor T2 and the ultrasonic sensor Q are connected to the same end of the acquisition module 22 .
[0077] In some embodiments, as Figure 2 or Figure 3 As shown, the acquisition module 22 includes a third transistor T3, the control electrode of the third transistor T3 is connected to the acquisition control terminal Close, and the first electrode of the third transistor T3 is connected to the ultrasonic sensor Q (as shown in FIG. Figure 2The first electrode of the third transistor T3 is connected with the reset module 21 and the ultrasonic sensor Q (as shown in the figure), or the first electrode of the third transistor T3 is connected with the first node N1 and the ultrasonic sensor Q (as shown in the figure). Figure 3 The second electrode of the third transistor T3 is connected with the first node N1.
[0078] In some embodiments, as shown in the figure, Figure 2 or Figure 3 The storage module 23 includes a first capacitor C1, the first electrode of the first capacitor C1 is connected with the first node N1, and the second electrode of the first capacitor C1 is connected with the second node N2.
[0079] In some embodiments, as shown in the figure, Figure 2 or Figure 3 The compensation module 24 includes a fourth transistor T4, the control electrode of the fourth transistor T4 is connected with the compensation control end VC, the first electrode of the fourth transistor T4 is connected with the first voltage end Vdd, and the second electrode of the fourth transistor T4 is connected with the first electrode of the driving transistor T1.
[0080] In some embodiments, as shown in the figure, Figure 2 or Figure 3 The read module 25 includes a fifth transistor T5, the control electrode of the fifth transistor T5 is connected with the read control end Gate, the first electrode of the fifth transistor T5 is connected with the second node N2, and the second electrode of the fifth transistor T5 is connected with the output end Opt.
[0081] In some embodiments, as shown in the figure, Figure 6 or Figure 7 The ultrasonic detection circuit further includes a control signal generation module 61, the control signal generation module 61 is connected with the reset control end Rest, the read control end Gate and the compensation control end VC respectively, and the control signal generation module 61 is used to generate a compensation control signal at the compensation control end VC in response to a reset control signal and a read control signal.
[0082] By setting the control signal generation module 61, the reset control signal of the reset control end Rest and the read control signal of the read control end Gate are multiplexed to generate the compensation control signal, so that a signal line for transmitting the compensation control signal is not needed, the number of signal lines is reduced, the wiring space is saved, and the cost is reduced.
[0083] In some embodiments, as shown in the figure, Figure 6 or Figure 7As shown, the control signal generation module 61 comprises a sixth transistor T6 and a seventh transistor T7, the control electrode and the first electrode of the sixth transistor T6 are connected with the reset control end Rest, the second electrode of the sixth transistor T6 is connected with the compensation control end VC, the control electrode and the first electrode of the seventh transistor T7 are connected with the read control end Gate, and the second electrode of the seventh transistor T7 is connected with the compensation control end VC.
[0084] The working process of the ultrasonic detection circuit will be described below with reference to the signal timing diagram shown in Figure 2 and Figure 8 The working process of the ultrasonic detection circuit will be described below with reference to the signal timing diagram shown in
[0085] In the reset compensation phase t1, the reset control signal Rest and the compensation control signal VC are high level, and the collection control signal Close and the read control signal Gate are low level, so the third transistor T3 and the fifth transistor T5 are closed, the driving transistor T1, the second transistor T2 and the fourth transistor T4 are opened, the reset signal Vbias is charged into the first node N1, so that the voltage of the first node N1 is Vbias, and the voltage of the second node N2 reaches Vbias-Vth, and then the driving transistor T1 is closed, so as to write the threshold voltage Vth of the driving transistor T1 into the second node N2, which plays a role of compensating the threshold voltage Vth difference in the read phase t3. It is shown in Figure 4 a diagram of Figure 2 the equivalent circuit of the ultrasonic detection circuit shown in FIG. 1.
[0086] In the collection phase t2, the collection control signal Close is high level, and the reset control signal Rest, the compensation control signal VC and the read control signal Gate are low level, so the driving transistor T1, the second transistor T2, the fourth transistor T4 and the fifth transistor T5 are closed, and the third transistor T3 is opened, the signal received by the ultrasonic sensor Q is written into the first node N1, and at the same time, due to the bootstrap effect of the first capacitor C1, the voltage of the second node N2 changes with the voltage of the first node N1. It is shown in Figure 4 b diagram of Figure 2 the equivalent circuit of the ultrasonic detection circuit shown in FIG. 1.
[0087] In the read stage t3, the compensation control signal VC and the read control signal Gate are high, and the reset control signal Rest and the collection control signal Close are low, so the second transistor T2 and the third transistor T3 are turned off, and the driving transistor T1, the fourth transistor T4 and the fifth transistor T5 are turned on. The initial voltage of the output terminal Opt is set to 0V, the fourth transistor T4, the driving transistor T1 and the fifth transistor T5 form a path, the voltage of the second node N2 jumps, and due to the bootstrap effect of the first capacitor C1, the voltage of the first node N1 changes with the voltage of the second node N2, and the output terminal Opt outputs the detection signal according to the potentials of the first node N1 and the second node N2. Referring to Figure 4 , the equivalent circuit of the ultrasonic detection circuit shown in Figure 2 in this stage is shown.
[0088] Since in the reset compensation stage t1, the second node N2 is written into the threshold voltage Vth of the driving transistor T1, and since the first node N1 and the second node N2 are respectively connected to the two plates of the first capacitor C1, and the first capacitor C1 has a bootstrap effect, in the subsequent collection stage t2 and the read stage t3, the voltage difference between the first node N1 and the second node N2 always contains the threshold voltage Vth of the driving transistor T1, which can be eliminated by substituting the Vth in the Ids formula, thereby eliminating the influence of the threshold voltage Vth difference, reducing the error of the ultrasonic signal detection, and improving the detection accuracy.
[0089] The working process of the ultrasonic detection circuit will be described below with reference to the signal timing diagrams shown in Figure 3 and Figure 9 , taking the N-type transistors as an example.
[0090] In the reset compensation stage t1, the reset control signal Rest, the collection control signal Close and the compensation control signal VC are high, and the read control signal Gate is low, so the fifth transistor T5 is turned off, and the driving transistor T1, the second transistor T2, the third transistor T3 and the fourth transistor T4 are turned on. The reset signal Vbias is charged into the first node N1, so that the voltage of the first node N1 is Vbias, and the voltage of the second node N2 reaches Vbias-Vth, and the driving transistor T1 is turned off, thereby realizing writing the threshold voltage Vth of the driving transistor T1 into the second node N2, and playing a role of compensating the threshold voltage Vth difference in the read stage t3. Referring to Figure 5 , the equivalent circuit of the ultrasonic detection circuit shown in Figure 3 in this stage is shown.
[0091] In the acquisition phase t2, the acquisition control signal Close is high, the reset control signal Rest, the compensation control signal VC and the read control signal Gate are low, thus the driving transistor T1, the second transistor T2, the fourth transistor T4 and the fifth transistor T5 are closed, the third transistor T3 is open, the signal received by the ultrasonic sensor Q is written to the first node N1, and the voltage of the second node N2 changes with the voltage of the first node N1 due to the bootstrap effect of the first capacitor C1. Referring to FIG. 1b, the equivalent circuit of the ultrasonic detection circuit shown in FIG. 1a in the acquisition phase t2 is shown. Figure 5 Figure 3 The equivalent circuit of the ultrasonic detection circuit shown in FIG. 1a in the acquisition phase t2 is shown.
[0092] In the read phase t3, the compensation control signal VC and the read control signal Gate are high, the reset control signal Rest and the acquisition control signal Close are low, thus the second transistor T2 and the third transistor T3 are closed, and the driving transistor T1, the fourth transistor T4 and the fifth transistor T5 are open. The initial voltage of the output terminal Opt is set to 0V, the fourth transistor T4, the driving transistor T1 and the fifth transistor T5 form a path, the voltage of the second node N2 jumps, the voltage of the first node N1 changes with the voltage of the second node N2 due to the bootstrap effect of the first capacitor C1, and the output terminal Opt outputs a detection signal according to the potentials of the first node N1 and the second node N2. Referring to FIG. 1c, the equivalent circuit of the ultrasonic detection circuit shown in FIG. 1a in the read phase t3 is shown. Figure 5 Figure 3 The equivalent circuit of the ultrasonic detection circuit shown in FIG. 1a in the read phase t3 is shown.
[0093] In the reset compensation phase t1, the second node N2 is written to the threshold voltage Vth of the driving transistor T1, and in the subsequent acquisition phase t2 and read phase t3, the voltage difference between the first node N1 and the second node N2 always contains the threshold voltage Vth of the driving transistor T1 due to the bootstrap effect of the first capacitor C1, which is substituted into the Ids formula to eliminate Vth, thereby eliminating the influence of the threshold voltage Vth difference, reducing the error of ultrasonic signal detection and improving the detection accuracy.
[0094] The ultrasonic detection device provided by the present disclosure comprises a substrate, a plurality of detection units on one side of the substrate, wherein each detection unit comprises an ultrasonic sensor Q and an ultrasonic detection circuit as provided in any of the embodiments, and the ultrasonic sensor Q is configured to receive a reflected ultrasonic signal and convert the received ultrasonic signal into an electrical signal.
[0095] Those skilled in the art can understand that the ultrasonic detection device provided by the present disclosure has the advantages of the ultrasonic detection circuit described above. The ultrasonic detection device provided by the present disclosure can be integrated into ultrasonic imaging devices, fingerprint recognition devices and other products.
[0096] The ultrasonic sensor Q receives the reflected ultrasonic signal and converts the received ultrasonic signal into an electrical signal, for example, in the range of 0V-2V.
[0097] In some embodiments, the plurality of detection units are arranged in a row direction and / or a column direction.
[0098] In some embodiments, the ultrasonic sensor Q is further configured to emit an ultrasonic signal in response to the first driving signal.
[0099] In a specific implementation, a transmission phase is set after the last acquisition phase t2 and before the next acquisition phase t2, and the first driving signal is provided to the ultrasonic sensor Q to make the ultrasonic sensor Q emit an ultrasonic signal.
[0100] In this embodiment, the ultrasonic sensor Q completes the emission and reception of the ultrasonic signal in time periods, and a separate ultrasonic transmitter is not needed, which can simplify the structure of the ultrasonic detection device.
[0101] In some embodiments, the ultrasonic detection device further comprises an ultrasonic transmitter configured to emit an ultrasonic signal in response to a second driving signal.
[0102] In this embodiment, the emission and reception of the ultrasonic signal are completed by different devices, i.e., the ultrasonic transmitter is configured to emit an ultrasonic signal, and the ultrasonic sensor Q is configured to receive an ultrasonic signal, which is conducive to improving the detection efficiency and accuracy.
[0103] The present disclosure provides a driving method applied to the ultrasonic detection circuit as provided in any of the embodiments, and the driving method comprises the following steps. Figures 2 to 9 The driving method comprises the following steps.
[0104] In the reset compensation phase t1, a reset control signal is provided to the reset control end Rest, and a compensation control signal is provided to the compensation control end VC, so that the reset module 21 and the compensation module 24 are turned on, the reset signal is written to the first node N1, and the threshold voltage Vth of the driving transistor T1 is written to the second node N2.
[0105] In the acquisition phase t2, an acquisition control signal is provided to the acquisition control end Close, so that the acquisition module 22 is turned on, and the signal received by the ultrasonic sensor Q is written to the first node N1.
[0106] In the reading phase t3, a compensation control signal is provided to the compensation control end VC, and a reading control signal is provided to the reading control end Gate, so that the compensation module 24 and the reading module 25 are turned on, and the detection signal is output from the output end Opt according to the potentials of the first node N1 and the second node N2.
[0107] In some embodiments, when the reset module 21 is connected with the first node N1 through the collection module 22, the reset compensation stage t1 further includes:
[0108] A collection control signal is provided to the collection control end Close to make the collection module 22 conductive, and the reset signal is written into the first node N1 through the reset module 21 and the collection module 22 in sequence.
[0109] In some embodiments, when the ultrasonic detection circuit further includes a control signal generation module 61, and the control signal generation module 61 is connected with the reset control end Rest, the reading control end Gate and the compensation control end VC respectively, the step of providing the compensation control signal to the compensation control end VC includes:
[0110] A reset control signal is provided to the reset control end Rest, and a reading control signal is provided to the reading control end Gate to generate a compensation control signal at the compensation control end VC.
[0111] In some embodiments, after the last collection stage t2, before the next collection stage t2, further includes:
[0112] A transmission stage, in which a first driving signal is provided to the ultrasonic sensor Q to make the ultrasonic sensor Q emit an ultrasonic signal.
[0113] It should be noted that the driving method can further include more steps, which can be determined according to actual needs, and the present disclosure does not limit this. For detailed description and technical effects of the driving method, reference can be made to the description of the ultrasonic detection circuit embodiment in the foregoing, which will not be described here.
[0114] In the present disclosure, the meaning of "multiple" is two or more, and the meaning of "at least one" is one or more, unless otherwise explicitly and specifically limited.
[0115] In the present disclosure, the terms "upper", "lower", and the like indicate the orientation or positional relationship shown in the drawings, which is only for the convenience of describing the present disclosure and simplifying the description, and does not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure.
[0116] As used herein, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the presence of additional identical elements in the process, method, article, or apparatus that comprises the element.
[0117] As used herein, the terms "one embodiment," "some embodiments," "certain embodiments," "one or more embodiments," "some examples," "one example," "an example," "embodiment," "exemplary embodiment," and the like, are intended to mean that a particular feature, structure, material, or characteristic is included in at least one embodiment or example of the present disclosure, and that is used in certain ones of the examples and / or embodiments but is not necessarily included or used in all examples and / or embodiments. Such terminology used in the context of the examples and / or embodiments disclosed herein is not necessarily intended to be construed to mean that particular feature, structure, material, or characteristic is essential to every embodiment or example of the present disclosure.
[0118] As used herein, the terms "first," "second," "third," etc. are used merely to identify one of a number of entities or operations, and are not intended to imply any actual relationship or order between the entities or operations.
[0119] In describing some embodiments, the expressions "coupled" and "connected" can be used. For example, the term "connected" can be used to indicate that two or more elements are in direct physical or electrical contact with each other. As another example, the term "coupled" can be used to indicate that two or more elements are in direct physical or electrical contact with each other. However, the terms "coupled" or "communicatively coupled" can also mean that two or more elements are not in direct contact with each other, but yet are still in cooperation or interaction with each other. The embodiments disclosed herein are not necessarily limited in scope to the terms used herein.
[0120] "at least one of A, B, and C" has the same meaning as "at least one of A, B, or C" and includes the following combinations: only A, only B, only C, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B, and C.
[0121] "A and / or B" includes the following three combinations: only A, only B, and a combination of A and B.
[0122] As used herein, the term "if' is optionally interpreted as meaning "when" or "while" or "in response to a determination" or "in response to a detection" depending on the context. Similarly, the phrase "if it is determined" or "if [stated condition or event] is detected" is optionally interpreted as meaning "upon a determination" or "in response to a determination" or "upon detecting [stated condition or event]" or "in response to detecting [stated condition or event]" depending on the context.
[0123] The use of "for" or "configured to" herein means open and inclusive language that does not exclude additional devices or steps for performing additional tasks or steps.
[0124] The use of "based on" or "according to" herein means open and inclusive. A process, step, calculation, or other action that is based on one or more stated conditions or values can in practice be based on other conditions or values beyond those stated. A process, step, calculation, or other action that is according to one or more stated conditions or values can in practice be according to other conditions or values beyond those stated.
[0125] As used herein, "about," "approximately," or "around" includes the recited value and the average value within an acceptable range of deviation from the particular value, as determined by one of ordinary skill in the art considering the measurement in question and the error in measuring the particular quantity (i.e., the limitations of the measurement system).
[0126] As used herein, "parallel," "perpendicular," "equal," "flush" includes the recited condition and conditions that approximate the recited condition within an acceptable range of deviation, where the acceptable range of deviation is as determined by one of ordinary skill in the art considering the measurement in question and the error in measuring the particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallel and near parallel, where the acceptable range of deviation for near parallel can be, for example, within 5°; "perpendicular" includes absolute perpendicular and near perpendicular, where the acceptable range of deviation for near perpendicular can also be, for example, within 5°. "Equal" includes absolute equality and near equality, where the acceptable range of deviation for near equality can be, for example, a difference between the two that is less than or equal to 5% of either. "Flush" includes absolute flush and near flush, where the acceptable range of deviation for near flush can be, for example, a distance between the two that is less than or equal to 5% of either dimension.
[0127] It will be appreciated that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers can also be present.
[0128] Exemplary embodiments are described herein with reference to cross-sectional and / or plan view illustrations that are idealized illustrations. In the interest of clarity, not all of the layer and regions are shown in the drawings with the same thickness. Thus, the dimensions of the layers and regions depicted in the drawings can be exaggerated relative to each other for clarity. Accordingly, exemplary embodiments should not be construed as limited to the shapes of regions illustrated in the drawings, which are schematic representations.
[0129] Finally, it should be noted that the above-mentioned embodiments are merely used to illustrate the technical solutions of the present disclosure, rather than limit the present disclosure; even though the present disclosure has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand: the technical solutions recorded in the foregoing embodiments can still be modified, or some technical features can be replaced by equivalent replacements; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present disclosure.
Claims
1. An ultrasonic detection circuit, comprising: Reset module, acquisition module, driving transistor, storage module, compensation module and reading module; The reset module is connected to the reset control terminal, the reset signal terminal and the first node respectively, and is used to write the reset signal of the reset signal terminal into the first node in response to the reset control signal of the reset control terminal; The acquisition module is connected to the acquisition control end, the ultrasonic sensor and the first node, and is used to write the signal received by the ultrasonic sensor into the first node in response to the acquisition control signal of the acquisition control end; The driving transistor has a control electrode connected to the first node, a first electrode connected to the compensation module, and a second electrode connected to the second node; The storage module is connected to the first node and the second node respectively, and is used to store the voltage between the first node and the second node; The compensation module is further connected to the compensation control terminal and the first voltage terminal, and is configured to write the threshold voltage of the driving transistor into the second node in response to a compensation control signal from the compensation control terminal; The read module is connected to the read control terminal, the second node and the output terminal respectively, and is used to respond to the read control signal of the read control terminal and output a detection signal at the output terminal according to the potentials of the first node and the second node.
2. The ultrasonic detection circuit according to claim 1, wherein: The reset module is directly connected to the first node; or The reset module is connected to the first node through the acquisition module. The reset module is specifically used to write the reset signal into the acquisition module in response to the reset control signal. The acquisition module is also used to write the reset signal into the first node in response to the acquisition control signal.
3. The ultrasonic detection circuit according to claim 2, wherein: The reset module includes: The second transistor has a control electrode connected to the reset control terminal, a first electrode connected to the reset signal terminal, and a second electrode directly connected to the first node or connected through the acquisition module.
4. The ultrasonic detection circuit according to claim 2, wherein: The acquisition module includes: A third transistor has a control electrode connected to the acquisition control end, a first electrode connected to the ultrasonic sensor, or a first electrode connected to the ultrasonic sensor and the reset module respectively, and a second electrode connected to the first node.
5. The ultrasonic detection circuit according to claim 1, wherein: The storage module includes: A first capacitor has a first electrode connected to the first node and a second electrode connected to the second node. The ultrasonic detection circuit according to claim 1 , wherein: The compensation module includes: A fourth transistor has a control electrode connected to the compensation control terminal, a first electrode connected to the first voltage terminal, and a second electrode connected to the first electrode of the driving transistor.
7. The ultrasonic detection circuit according to claim 1, wherein: The reading module includes: A fifth transistor has a control electrode connected to the read control terminal, a first electrode connected to the second node, and a second electrode connected to the output terminal.
8. The ultrasonic detection circuit according to any one of claims 1 to 7, wherein: The ultrasonic detection circuit further includes: The control signal generating module is connected to the reset control terminal, the read control terminal and the compensation control terminal respectively, and is used to generate the compensation control signal at the compensation control terminal in response to the reset control signal and the read control signal.
9. The ultrasonic detection circuit according to claim 8, wherein: The control signal generating module includes: a sixth transistor, wherein the control electrode and the first electrode are both connected to the reset control terminal, and the second electrode is connected to the compensation control terminal; and The seventh transistor has a control electrode and a first electrode both connected to the read control terminal, and a second electrode connected to the compensation control terminal.
10. An ultrasonic detection device comprising: substrate; Multiple detection units are located on one side of the substrate, the detection units include ultrasonic sensors and the ultrasonic detection circuit according to any one of claims 1 to 9, the ultrasonic sensors are used to receive reflected ultrasonic signals and convert the received ultrasonic signals into electrical signals.
11. The ultrasonic detection device according to claim 10, wherein: The plurality of detection units are arranged in an array along a row direction and / or a column direction.
12. The ultrasonic detection device according to claim 10 or 11, wherein: The ultrasonic sensor is further configured to transmit an ultrasonic signal in response to the first driving signal; or The ultrasonic detection device further includes an ultrasonic transmitter, which is configured to transmit an ultrasonic signal in response to a second driving signal.
13. A driving method, applied to the ultrasonic detection circuit according to any one of claims 1 to 9, the driving method comprising: In a reset and compensation phase, a reset control signal is provided to the reset control terminal and a compensation control signal is provided to the compensation control terminal to turn on the reset module and the compensation module, write the reset signal to the first node, and write the threshold voltage of the driving transistor to the second node; In the acquisition phase, an acquisition control signal is provided to the acquisition control terminal to turn on the acquisition module and write the signal received by the ultrasonic sensor into the first node; In the reading phase, a compensation control signal is provided to the compensation control terminal, and a reading control signal is provided to the reading control terminal to turn on the compensation module and the reading module, and output a detection signal at the output terminal according to the potentials of the first node and the second node.
14. The driving method according to claim 13, wherein: When the reset module is connected to the first node through the acquisition module, the reset compensation stage further includes: An acquisition control signal is provided to the acquisition control terminal to turn on the acquisition module, and the reset signal is sequentially written into the first node through the reset module and the acquisition module.
15. The driving method according to claim 13, wherein: When the ultrasonic detection circuit further includes a control signal generating module, and the control signal generating module is connected to the reset control terminal, the read control terminal, and the compensation control terminal respectively, the step of providing the compensation control signal to the compensation control terminal includes: A reset control signal is provided to the reset control terminal, and a read control signal is provided to the read control terminal, so as to generate the compensation control signal at the compensation control terminal.
16. The driving method according to any one of claims 13 to 15, wherein: After the last acquisition phase and before the next acquisition phase, the method further includes: In the transmitting stage, a first driving signal is provided to the ultrasonic sensor so that the ultrasonic sensor transmits an ultrasonic signal.
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