Brain-inspired on-chip learning spiking neural network and edge neural morphic processor

Abstract

The application discloses a brain biomimetic on-chip learning pulse neural network and an edge terminal neural morphological processor, which comprises an encoding layer, a feature extraction layer and a decision layer; the encoding layer is used for pulse coding of an input image; if the input is data generated by a dynamic vision sensor, the data is directly sent to the feature extraction layer, and the encoding layer does not work; if the input is a static image, pixel values of the static image are coded into a pulse sequence and then input to the feature extraction layer; the feature extraction layer extracts and selects features from the pulse output by the encoding layer, and the feature extraction method supported by the feature extraction layer comprises a pulse extreme learning machine, a space-time compression sensing, a liquid state machine and local / partial connection; the decision layer is used for receiving the pulse from the feature extraction layer and performing on-chip learning training on the weight of the decision layer. The application can flexibly configure different on-chip learning algorithms, reduce resource consumption and lower the power consumption of the chip.

Description

Brain-inspired on-chip learning spiking neural network and edge neuromorphic processor Technical Field

[0001] This invention belongs to the fields of artificial intelligence and brain-like intelligent chip technology, specifically relating to a brain-inspired on-chip learning spiking neural network and an edge neuromorphic processor. Background Technology

[0002] Spiking neural networks (SNNs) exchange information based on discrete pulses, lacking continuity and differentiability. Therefore, they struggle to achieve the training and recognition rates of artificial neural networks (ANNs). SNN-based algorithms are still immature and are continuously being researched and optimized. Achieving high recognition rates on top of shallow SNNs remains a challenge. Deeper networks typically achieve higher recognition rates, but also consume more hardware resources. Therefore, it is necessary to design suitable SNN models to find a balance between classification accuracy and cost-effectiveness, enabling implementation on platforms with limited hardware resources. Summary of the Invention

[0003] The purpose of this invention is to provide a brain-inspired on-chip learning spiking neural network to implement different on-chip learning algorithms to adapt to different application scenarios.

[0004] Another objective of this invention is to provide an edge-side neuromorphic processor that can be flexibly configured to execute different on-chip learning algorithms in order to reduce resource consumption and lower chip power consumption.

[0005] In a first aspect, the present invention provides a brain-inspired on-chip learning spiking neural network, comprising an encoding layer, a feature extraction layer, and a decision layer;

[0006] The encoding layer is used to perform pulse coding on the input image. If the input is data generated by a dynamic vision sensor, it is directly sent to the feature extraction layer, and the encoding layer does not work. If the input is a static image, the pixel values ​​of the static image are encoded into a pulse sequence before being input to the feature extraction layer. The pulse coding methods supported by the encoding layer include rate coding, first pulse time coding, pulse interval coding, and phase coding.

[0007] The feature extraction layer extracts and selects features from the pulses output by the coding layer. The feature extraction methods supported by the feature extraction layer include pulse limit learning machine, spatiotemporal compressed sensing, liquid state machine, and local / partial connectivity.

[0008] The decision layer is used to receive pulses from the feature extraction layer and to perform on-chip learning training on the weights of the decision layer; wherein, the on-chip learning training method supports learning rules including unsupervised pulse temporal dependent plasticity learning rules, reward-modulated pulse temporal dependent plasticity reinforcement learning rules, supervised Tempotron learning rules, supervised remote supervision ReSuMe learning rules, Tempotron-like Resume learning rules, and 1-2 layer error backpropagation STDP learning rules.

[0009] Optionally, the weight precision of the feature extraction layer can be configured to be 1, 2, 4, or 8 bits.

[0010] Optionally, the spiking neuron models of the encoding layer, feature extraction layer, and decision layer all adopt the leakage integral ignition spiking neuron model. This spiking neuron model has the functions of whether the neuron has charge leakage, whether there is decay current, the way the neuron's potential recovers to the resting potential after firing a pulse, and whether the neuron enters the refractory period after firing a pulse.

[0011] Secondly, the edge neuromorphic processor of the present invention employs a brain-inspired on-chip learning spiking neural network as described in the present invention.

[0012] The edge-end neuromorphic processor includes a global controller, and a pulse-coding neural computation kernel, a feature extraction neural computation kernel, and a decision execution neural computation kernel, which are respectively connected to the global controller;

[0013] The global controller is used for overall architecture control, data scheduling, and data initialization.

[0014] The feature extraction neural computation kernel includes multiple feature extraction neural computation slices, and each feature extraction neural computation slice runs a thousand spiking neurons;

[0015] The decision execution neural computation kernel includes multiple learning and reasoning neural computation slices, each of which runs several spiking neurons;

[0016] A first FIFO module is set between the pulse coding neural computation kernel and the feature extraction neural computation kernel, a second FIFO module is set between the feature extraction neural computation kernel and the decision execution neural computation kernel, and a third FIFO module is set for the output of each decision execution neural computation kernel. Each FIFO module is used to buffer the pulse information input by other kernels, as well as the sequence number of the neuron that emitted the pulse.

[0017] Optionally, the pulse-coded neural computation kernel includes an encoding processor, and a first multiplexer, a rate encoding unit, a TTFS encoding unit, an ISI encoding unit, a phase encoding unit, and a second multiplexer, all connected to the encoding processor. The first multiplexer is connected to the rate encoding unit, the TTFS encoding unit, the ISI encoding unit, and the phase encoding unit, respectively; the rate encoding unit, the TTFS encoding unit, the ISI encoding unit, and the phase encoding unit are all connected to the second multiplexer.

[0018] The encoding processor determines whether to enable the pulse coding neural computing kernel and whether to execute the pulse coding function for the image based on the data to be processed. If the input sample is a static image, the pixel values ​​are pulse-coded according to the encoding method and cached in the first FIFO module. If the input sample is a pulse event generated by a dynamic visual sensor, the pulse event is directly cached in the first FIFO module. When encoding a static image, the pulse coding neural computing kernel selects the corresponding pulse coding method through configuration and caches the corresponding pulse event data in the first FIFO module. The pulse event data is expressed in AER format.

[0019] Optionally, the feature extraction neural computing core includes a feature extraction controller, a first AER arbitrator, a connection mode information storage, and multiple parallel feature extraction neural computing chips, all connected to the feature extraction controller. Each feature extraction neural computing chip is connected to the first AER arbitrator and also to the connection mode information storage.

[0020] The feature extraction neural computation chip includes a feature extraction neural computation chip controller, a cross matrix, a cross matrix encoding and decoding unit, a feature extraction layer neuron computation unit, and a feature extraction layer neuron state storage unit.

[0021] The cross matrix can flexibly configure any connection relationship between neurons;

[0022] The feature extraction controller is used to determine which implementation method to use: impulse limit learning machine, liquid state machine, spatiotemporal compressed sensing, and fixed local connectivity.

[0023] The first AER arbitrator is used to arbitrate the pulse events output by the neural computing chips with different features and cache them into the second FIFO module;

[0024] The connection method information storage device is used to store connection relationships;

[0025] Before the feature extraction neural computation kernel is executed, the data in the first FIFO module of the input buffer is first detected to determine whether to start the feature extraction neural computation kernel; the corresponding feature extraction method is executed according to the configuration information; when the AER data in the first FIFO module is received, the feature extraction controller encodes the AER data and inputs it into the cross matrix to determine the connection relationship, obtains the weight according to the connection relationship, calculates and updates the neuron state; if the neuron emits a pulse, it outputs a pulse event, and the pulse events output by different feature extraction neural computation chips are buffered into the second FIFO module through the first AER arbitrator.

[0026] Optionally, the decision execution neural computing core includes a decision layer controller, a second AER arbitrator, a PreTrace memory, and multiple parallel learning and inference neural computing chips, all connected to the decision layer controller; each learning and inference neural computing chip is connected to the second AER arbitrator and also to the PreTrace memory.

[0027] The PreTrace memory is used to store the pulse trajectories of presynaptic neurons, and the pulse trajectories are used for weight updates;

[0028] The learning and reasoning neural computing chip includes a learning and reasoning neural computing chip controller, and decision layer neuron units, decision layer synaptic units, decision layer neuron memory, postsynaptic Trace memory, decision layer synaptic memory and Vmax&tmax memory connected to the learning and reasoning neural computing chip controller via a data bus; the decision layer synaptic units execute corresponding learning rules according to the configuration.

[0029] The decision execution neural computation kernel receives pulse events from the second FIFO module. During training, it updates the connection weights in the decision execution neural computation kernel according to the corresponding learning rules executed by the decision layer controller, and makes decisions during inference. The output pulses of neurons in the decision execution learning inference neural computation chip are cached in FIFO_3 through the second AER arbitrator, and the winning neuron is determined to make a decision based on the number of pulses emitted by the neuron.

[0030] The beneficial effects of this invention are:

[0031] (1) The lightweight brain-inspired bionic on-chip learning spiking neural network algorithm proposed in this invention has a network structure consisting of three layers: an encoding layer, a feature extraction layer, and a decision layer. Each layer can be flexibly configured and can support different spiking neuron models to implement different on-chip learning algorithms to adapt to different application scenarios. It also provides a reference for further research on spiking neural networks that flexibly support multiple on-chip learning rules.

[0032] (2) The edge neuromorphic processor architecture proposed in this invention can be flexibly configured to execute different on-chip learning algorithms, thereby reducing resource consumption and effectively reducing chip power consumption.

[0033] (3) The edge neuromorphic processor proposed in this invention supports on-chip learning and is easy to integrate into edge devices or miniaturized devices, meeting the needs of multiple edge application scenarios. Attached Figure Description

[0034] Figure 1 is a general design diagram of the present invention;

[0035] Figure 2 is an architecture diagram of the edge neuromorphic processor in this invention. Detailed Implementation

[0036] This embodiment proposes an edge neuromorphic processor. The overall design scheme is shown in Figure 1. It includes software verification of recognition rate and SystemVerilog design and simulation, FPGA prototype verification process, brain-inspired on-chip learning spiking neural network and configurable edge neuromorphic processing architecture design.

[0037] In this embodiment, a brain-inspired on-chip learning spiking neural network is provided, which can flexibly support edge-end on-chip learning.

[0038] The brain-inspired on-chip learning spiking neural network consists of three layers: an encoding layer, a feature extraction layer, and a decision layer. Each layer can be flexibly configured. This flexible configuration refers to using different enable signals to achieve different data flow directions and switch to specific computational circuits, thereby implementing different on-chip learning rules and supporting different spiking neuron models. These different neuron models are implemented by using different enable signals to achieve different data flow directions and switch to specific computational circuits, thereby implementing neuron models with different functions to achieve different on-chip learning algorithms.

[0039] The following provides a detailed explanation of the encoding layer, feature extraction layer, and decision layer:

[0040] 1. Coding layer:

[0041] The coding layer mainly performs pulse coding on the input image. If the input is data generated by a dynamic vision sensor (DVS), it is directly sent to the feature extraction layer and the coding layer does not work. If the input is a static image, the pixel values ​​of the static image are encoded into a pulse sequence before being input to the feature extraction layer. The coding layer can support different pulse coding methods, including rate coding, first pulse time coding, pulse interval coding, and phase coding.

[0042] 2. Feature extraction layer:

[0043] The feature extraction layer is used to extract and select features from the pulses output by the coding layer. Its role is to reduce data redundancy, extract more effective features, improve subsequent learning and decision-making capabilities, and achieve a higher recognition rate. To reduce computational complexity and better match the hardware requirements of edge computing, the weight precision of the feature extraction layer is set to be configurable with 1, 2, 4, and 8 bits. This configurability allows it to accommodate various feature extraction methods, including pulse extreme learning machine, spatiotemporal compressed sensing, liquid state machine (LSM), and local / partial connectivity.

[0044] 1) The Impulse Extreme Learning Machine (IEM) is an algorithm based on a feedforward neural network structure that uses arbitrary input weights to extract features from the input signal. The feature extraction method involves randomly initializing the weights at the beginning of the network and keeping them fixed throughout the training and inference process. The thresholds of the neurons in this feature extraction layer are also randomly set and then fixed, requiring no adjustment. Therefore, only the number of neurons in this feature extraction layer needs to be set.

[0045] 2) Spatiotemporal compressed sensing is an extension of classical spatial domain compressed features to the pulse-time domain. Pulse-domain compressed sensing features can be extracted from the pulse sequence encoded in the input layer. Each spiking neuron in the feature extraction layer that satisfies spatiotemporal compressed sensing corresponds to a feature element. Each neuron corresponds to four randomly selected fixed regions on the image. Each region contains three attributes: position, size, and polarity (±1). The position and size of these four regions are randomly set, and two regions are randomly selected and assigned as positive polarity, while the other two regions are assigned as negative polarity. The initial neuron membrane potential V(t) is... i ) is the resting potential V rest =0, when the neuron is at t i When pulses are received from these regions at any time, V(t) i It will be updated as follows:

[0046]

[0047] Among them, t pre It is the presynaptic pulse time, V(t) pre ) is t pre At time τ, the neuron membrane potential m Let t be the membrane potential decay time constant. i This is the current membrane potential update time; S p It is the area of ​​the region multiplied by its polarity (+1 / -1, corresponding to positive / negative regions respectively).

[0048] 3) The liquid state machine is a recursive spiking neural network that uses a reservoir computing method. It mainly extracts input features through a Reservoir layer (or Liquid layer). The neurons between the input and the Reservoir layer are randomly connected with fixed weights. The Reservoir layer is a recursive network composed of excitatory neurons and inhibitory neurons with random fixed weights. It can nonlinearly improve the features of different input sequences to a higher dimension and can record past input information to form a multidimensional dynamic representation of the input stream.

[0049] 4) Local / partial connectivity means that each neuron receives pulse input from only a few neighboring pixels of the input image and is configured as a local random connection or a local random Gabor filter. This local connectivity is similar to the local receptive field in a convolutional neural network and is configured through training by local unsupervised learning rules.

[0050] 3. Decision-making level:

[0051] The decision layer receives impulses from the feature extraction layer and performs on-chip learning training on the weights of the decision layer. The training method can be flexibly configured with various learning rules, including unsupervised impulse temporal dependent plasticity learning rule (STDP), reward-modulated impulse temporal dependent plasticity reinforcement learning rule (R-STDP), supervised Tempotron learning rule, supervised long-range supervised ReSuMe learning rule, Tempotron-like Resume learning rule, and 1-2 layer error backpropagation STDP learning rule (BP-STDP).

[0052] 1) Unsupervised impulse temporal dependence plasticity learning rule:

[0053] Unsupervised impulse timing-dependent plasticity learning rules are a type of rule that simulates the unsupervised plasticity learning of biological neurons. Their synaptic weights are updated based on the time interval between presynaptic (input) neuron impulses and postsynaptic (output) neuron impulses.

[0054]

[0055] Among them: A + A - These represent the learning rate and τ, respectively. + τ - These are the time constants, when the presynaptic pulse time t pre Earlier than the postsynaptic pulse time t post At this time, the synaptic weight increases, and learning enters a long-term reinforcement process; if the presynaptic pulse time t pre Later than the postsynaptic pulse time t postIf this happens, the synaptic weights decrease, and learning enters a long-term inhibitory process.

[0056] 2) Reward-modulated impulse temporally dependent plasticity reinforcement learning rules:

[0057] The human brain's reward system plays a crucial role in decision-making and behavioral performance. Building upon the STDP (Simultaneous Transmission Difference) model, which simulates biological learning, adding a reward-punishment mechanism creates the reward-modulated R-STDP (Reinforcement Learning Difference) rule. R-STDP ensures biological feasibility and accelerates the learning rate. It guides synaptic adjustments by determining whether the output neuron has fired correctly based on the current input.

[0058]

[0059]

[0060] Among them: A r + A r - The learning rate, A, under reward and penalty scenarios, respectively. p + A p - The learning rate τ represents the learning rate under reward and penalty scenarios, respectively. + τ - These are the time constants. If a neuron fires correctly, the corresponding synapse is rewarded, and the STDP rule is executed; if the firing is incorrect, the anti-STDP rule is executed.

[0061] 3) Supervised Tempotron learning rules

[0062] Supervised Tempotron learning is a type of supervised learning rule where labeled data is fed into a neural network, each neuron is uniquely assigned a class label, and the weights are modified as each training sample receives its input pulse sequence. If a neuron belongs to the corresponding input class but does not fire any pulse, the synaptic weight increases; conversely, if a neuron does not belong to the class but fires an incorrect pulse, the corresponding synaptic weight decreases. The mathematical representation of this supervised Tempotron learning rule is as follows:

[0063]

[0064] Where λ is the learning rate, τ mt is the time constant, and p is a flag indicating whether the neuron responded correctly. p = 1 when the neuron did not respond to an input belonging to its category; p = -1 when the neuron incorrectly responded to an input of another category; otherwise, p = 0, and the weights remain unchanged. i It is the moment when the i-th synapse receives an input pulse, t max All previously received input pulses will affect the update of synaptic weights.

[0065] 4) Supervised remote supervision of ReSuMe learning rules

[0066] Supervised remote ReSuMe learning rules describe the learning process performed by spiking neurons based on precise pulse timing. This process learns the temporal sequence of pulse firing, with weights determined by the target output S. d (t) and actual output S o The difference in (t) is modified:

[0067]

[0068] Where λ is the learning rate, a d a is a constant. di (s) is an exponential window function, S i (t) represents the input pulse sequence. The supervised long-range supervision ReSuMe learning rule is applicable to different neuron models.

[0069] 5) Tempotron-like ReSuMe learning rules

[0070] Like the supervised Tempotron learning rule, the Tempotron-like Resume learning rule only allows neurons to fire a single impulse. However, the biggest difference between the Tempotron-like Resume learning rule and the supervised Tempotron learning rule is that the Tempotron-like Resume learning rule can train neurons to fire a specified impulse response corresponding to the input category.

[0071] 6) Layer 1-2 error backpropagation STDP learning rule

[0072] The 1-2 layer error backpropagation STDP learning rule is a learning rule that combines efficient bio-inspired STDP learning with high-performance error backpropagation (gradient descent). It treats the error value as a signal and backpropagates it to stimulate or inhibit neurons.

[0073] In the STDP learning rule for backpropagation of errors in layers 1-2, the error is calculated as follows:

[0074]

[0075] The synaptic weight update rule is as follows:

[0076] w t+ =w t +μξ i (t)∑ t (s t (8)

[0077] Where, ξ i (t) represents the error corresponding to neuron i, μ is the learning rate, and w t The weights before the update, w t+ For the updated weights, ∑ t (s t ) represents the number of pulses emitted by the neuron.

[0078] In this embodiment, a flexibly configurable spiking neuron model is used. The Leaky Integrate & Fire (LIF) spiking neuron model offers a good balance between brain-like biomimicry and computational efficiency due to its low computational complexity and full preservation of the core characteristics of biological neurons, making it suitable for hardware implementation. The LIF neuron integrates and accumulates the synaptic weights corresponding to the input presynaptic pulses onto the membrane potential. If the neuron's membrane potential reaches a threshold, it fires a pulse and then resets to a resting state. The dynamic characteristics of the LIF neuron model can be described as follows:

[0079]

[0080] Where V(t) represents the neuron membrane potential, w i s represents the synaptic weight value connected to neuron i. i (t) represents the presynaptic pulse sequence connected to this neuron, i.e., when a presynaptic pulse occurs at time t, s i (t) = 1, otherwise s i (t) = 0. τ m Let V(t) be the decay time constant. According to the formula, the membrane potential V(t) increases after receiving the presynaptic pulse and decays exponentially at other times.

[0081] LIF neurons can be configured to perform different functions, including whether the neuron has charge leakage, whether it has decaying current, how the neuron's potential recovers to its resting potential after firing a pulse, and whether the neuron enters a refractory period after firing a pulse.

[0082] 1) Whether the neuron leaks: By configuring whether the neuron model has leakage, "Integrate-and-Fire" (IF) neurons and LIF neurons can be realized, which can realize resource configurability in different application scenarios.

[0083] 2) Decaying current: The presence or absence of decaying current in the neuron model can be set, allowing for flexible configuration of brain-like biomimicry and computational complexity based on the specific algorithm.

[0084] 3) Resting potential: After a neuron fires a pulse, its membrane potential returns to the resting potential. The resting potential can be set in several ways: directly setting the membrane potential to the resting potential, proportionally reducing the membrane potential to zero, or subtracting a threshold from the membrane potential. Multiple configuration methods are supported to enhance the algorithm's adaptability in different application scenarios.

[0085] 4) Refractory period: The refractory period of a neuron refers to the time during which the neuron ignores the remaining input pulses after firing a pulse. The refractory period can be flexibly configured to 0 or other values ​​greater than 0. That is, when the refractory period is 0, the neuron is indiscriminately driven; when the refractory period is greater than 0, the neuron ignores input pulses within that time value.

[0086] As shown in Figure 2, in this embodiment, an edge-end neuromorphic processor employs a brain-inspired on-chip learning spiking neural network as described in this embodiment.

[0087] 1. Configurable edge neuromorphic processor architecture design:

[0088] As shown in Figure 2, the configurable edge-end neuromorphic processing architecture includes a global controller, a pulse-coding neural computation kernel, a feature extraction neural computation kernel, and a decision execution neural computation kernel. The global controller is connected to each of these kernels, and is used for overall architecture control and data scheduling. The feature extraction neural computation kernel includes multiple feature extraction neural computation slices, each running several spiking neurons. The decision execution neural computation kernel includes multiple learning and inference neural computation slices, each running several spiking neurons. A first FIFO module (FIFO_1) is set between the pulse-coding neural computation kernel and the feature extraction neural computation kernel, and a second FIFO module (FIFO_2) is set between the feature extraction neural computation kernel and the decision execution neural computation kernel. The outputs of each decision execution neural computation kernel are equipped with a third FIFO module (FIFO_3). FIFO_1, FIFO_2, and FIFO_3 are used to buffer pulse information input from other kernels, as well as the sequence number of the neuron that emitted the pulse.

[0089] 2. Design of pulse-code neural computational kernels:

[0090] The pulse-code neural computation kernel includes an encoding processor, and a first multiplexer (MUX-1), a rate encoding unit, a TTFS encoding unit, an ISI encoding unit, a phase encoding unit, and a second multiplexer (MUX-2) connected to the encoding processor. The first multiplexer is connected to the rate encoding unit, TTFS encoding unit, ISI encoding unit, and phase encoding unit, respectively. The rate encoding unit, TTFS encoding unit, ISI encoding unit, and phase encoding unit are connected to the second multiplexer. The second multiplexer is connected to a first FIFO module via a third multiplexer (MUX-3). The encoding processor determines whether to activate the pulse-code neural computation kernel and whether to perform pulse coding of the image based on the data to be processed. If the input sample is a static image, the pixel values ​​are pulse-coded according to the encoding method and cached in the first FIFO module; if the input sample is a pulse event generated by a dynamic visual sensor, the pulse event is directly cached in the first FIFO module. When encoding still images, the pulse coding neural computation kernel selects the corresponding pulse coding mode by configuration and caches the corresponding pulse event data in the first FIFO module. This pulse event data is expressed in a format called Address-Event Representation (AER). AER data packets typically contain the pixel address or neuron index of the emitted pulse and the pulse emission timestamp. The corresponding AER data is cached in the first FIFO module and then sent to the feature extraction neural computation kernel for processing.

[0091] 3. Design of the feature extraction neural computation kernel:

[0092] The feature extraction neural computation kernel includes a feature extraction controller, a first AER arbitrator, a connection mode information memory, and multiple parallel feature extraction neural computation slices, all connected to the feature extraction controller. Each feature extraction neural computation slice is connected to the first AER arbitrator and also to the connection mode information memory. The number of feature extraction neural computation slices can be configured according to actual application requirements. Each feature extraction neural computation slice includes a feature extraction neural computation slice controller, a cross matrix, a cross matrix encoding / decoding unit, a feature extraction layer neuron computation unit, and a feature extraction layer neuron state storage unit. The cross matrix can flexibly configure arbitrary connection relationships between neurons. The feature extraction controller determines which implementation method—spurious extreme learning machine, liquid state machine, spatiotemporal compressed sensing, or fixed local connectivity—to use. The first AER arbitrator arbitrates the pulse events output by different feature extraction neural computation slices and caches them in a second FIFO module. The connection mode information memory stores connection relationships.

[0093] Before the feature extraction neural computation kernel executes, the data in the first FIFO input buffer is first checked to determine whether to activate the kernel. Different feature extraction methods are executed based on different configurations. Upon receiving AER data from the first FIFO, the feature extraction controller encodes the AER data and inputs it into a cross-matrix to determine connectivity. Weights are obtained based on these connectivity relationships, and the neuron state is calculated and updated. If a neuron fires a pulse, it outputs a pulse event. Pulse events output by different feature extraction neural computation chips are buffered in the second FIFO module through the first AER arbitrator.

[0094] 4. Classification decision neural computation kernel design.

[0095] The decision execution neural computation kernel includes a decision layer controller, a second AER arbitrator, a PreTrace memory, and multiple parallel learning and inference neural computation slices, all connected to the decision layer controller. Each learning and inference neural computation slice is connected to the second AER arbitrator and also to the PreTrace memory. The PreTrace memory stores the pulse trajectories of presynaptic neurons, which are used for weight updates. The main difference between the decision execution neural computation kernel and the feature extraction neural computation kernel is that the decision execution neural computation kernel needs to update the synaptic weight information during the learning process. Therefore, the learning and inference neural computation slice includes a learning and inference neural computation slice controller, and decision layer neuron units, decision layer synaptic units, decision layer neuron memories, postsynaptic Trace memories, decision layer synaptic memories, and V connected to the learning and inference neural computation slice controller via a data bus. max &t max The memory is consistent with the neural computation kernel in the decision layer. The decision layer synaptic units can execute different learning rules according to their configuration. These learning rules include unsupervised impulse temporal dependent plasticity learning rules, reward-modulated impulse temporal dependent plasticity reinforcement learning rules, supervised Tempotron learning rules, supervised remote supervision ReSuMe learning rules, Tempotron-like Resume learning rules, and 1-2 layer error backpropagation STDP learning rules.

[0096] The decision execution neural computation kernel receives pulse events from the second FIFO module. During training, it updates the connection weights in the kernel according to the corresponding learning rules executed by the decision layer controller, and makes decisions during inference. The output pulses of neurons in the decision execution learning inference neural computation chip are cached in FIFO_3 by the second AER arbitrator. The winning neuron makes a decision based on the number of pulses emitted by each neuron.

[0097] The above embodiments are merely preferred embodiments provided to fully illustrate the present invention, and the scope of protection of the present invention is not limited thereto. Equivalent substitutions or modifications made by those skilled in the art based on the present invention are all within the scope of protection of the present invention.

Claims

1. A brain-inspired on-chip learning spiking neural network, characterized in that: It includes an encoding layer, a feature extraction layer, and a decision layer; the encoding layer is used to perform pulse coding on the input image; If the input is data generated by a dynamic vision sensor, it is directly sent to the feature extraction layer, and the encoding layer does not operate. If the input is a static image, the pixel values ​​of the static image are encoded into a pulse sequence before being input to the feature extraction layer. The pulse encoding layer supports pulse encoding methods including rate encoding, first pulse time encoding, pulse interval encoding, and phase encoding. The feature extraction layer extracts and selects features from the pulses output by the encoding layer. The feature extraction methods supported by the feature extraction layer include impulse extreme learning machine, spatiotemporal compressed sensing, liquid state machine, and local / partial connectivity. The decision layer receives pulses from the feature extraction layer and performs on-chip learning training on the weights of the decision layer. The on-chip learning training methods support learning rules including unsupervised impulse temporal dependent plasticity learning rules, reward-modulated impulse temporal dependent plasticity reinforcement learning rules, supervised Tempotron learning rules, supervised remote supervision ReSuMe learning rules, and Tempotron-like rules. The Resume learning rule and the STDP learning rule for backpropagation of error in layers 1-2; the spiking neuron model of the encoding layer, feature extraction layer and decision layer all adopt the leakage integral ignition spiking neuron model, which has the functions of whether the neuron has charge leakage, whether there is decay current, the way the potential of the neuron recovers to the resting potential after the neuron emits a pulse, and whether the neuron enters the refractory period after emitting a pulse.

2. The brain-inspired on-chip learning spiking neural network according to claim 1, characterized in that: The weight precision of the feature extraction layer can be configured to be 1, 2, 4, or 8 bits.

3. An edge-end neuromorphic processor, characterized in that: The brain-inspired on-chip learning spiking neural network as described in claim 1 or 2 is employed; the edge-end neuromorphic processor includes a global controller, and a spiking coding neural computation kernel, a feature extraction neural computation kernel, and a decision execution neural computation kernel respectively connected to the global controller; the global controller is used for overall architecture control, data scheduling, and data initialization; the feature extraction neural computation kernel includes multiple feature extraction neural computation slices, each of which runs several spiking neurons; The decision execution neural computation core includes multiple learning and reasoning neural computation slices, each of which runs several spiking neurons. A first FIFO module is set between the spiking encoding neural computation core and the feature extraction neural computation core, and a second FIFO module is set between the feature extraction neural computation core and the decision execution neural computation core. The output of each decision execution neural computation core is equipped with a third FIFO module. Each FIFO module is used to buffer the spiking information input from other cores, as well as the sequence number of the neuron that emitted the spiking signal.

4. The edge-end neuromorphic processor according to claim 3, characterized in that: The pulse-code neural computation kernel includes an encoding processor, and a first multiplexer, a rate encoding unit, a TTFS encoding unit, an ISI encoding unit, a phase encoding unit, and a second multiplexer, all connected to the encoding processor. The first multiplexer is connected to the rate encoding unit, the TTFS encoding unit, the ISI encoding unit, and the phase encoding unit, respectively. The rate encoding unit, the TTFS encoding unit, the ISI encoding unit, and the phase encoding unit are all connected to the second multiplexer. The encoding processor determines whether to enable the pulse-code neural computation kernel and whether to perform pulse coding of the image based on the data to be processed. If the input sample is a static image, the pixel values ​​are pulse-coded according to the encoding method and cached in the first FIFO module. If the input sample is a pulse event generated by a dynamic visual sensor, the pulse event is directly cached in the first FIFO module; when encoding a static image, the pulse coding neural computation kernel selects the corresponding pulse coding method through configuration and caches the corresponding pulse event data in the first FIFO module; the pulse event data is expressed in AER format.

5. The edge-end neuromorphic processor according to claim 4, characterized in that: The feature extraction neural computation kernel includes a feature extraction controller, a first AER arbitrator, a connection mode information memory, and multiple parallel feature extraction neural computation chips connected to the feature extraction controller. Each feature extraction neural computation chip is connected to the first AER arbitrator and also to the connection mode information memory. Each feature extraction neural computation chip includes a feature extraction neural computation chip controller, a cross matrix, a cross matrix encoding / decoding unit, a feature extraction layer neuron computation unit, and a feature extraction layer neuron state storage unit. The cross matrix can flexibly configure arbitrary connection relationships between neurons. The feature extraction controller is used to determine which implementation method—spiking limit learning machine, liquid state machine, spatiotemporal compressed sensing, or fixed local connectivity—to use. The first AER... An arbitrator is used to arbitrate the pulse events output by different feature extraction neural computing chips and cache them in the second FIFO module; the connection information storage is used to store connection relationships; before the feature extraction neural computing core is executed, the data in the input cache first FIFO module is first detected to determine whether to start the feature extraction neural computing core; the corresponding feature extraction method is executed according to the configuration information; when the AER data in the first FIFO module is received, the feature extraction controller encodes the AER data and inputs it into the cross matrix to determine the connection relationship, obtains the weights according to the connection relationship, calculates and updates the neuron state; if the neuron emits a pulse, it outputs a pulse event, and the pulse events output by different feature extraction neural computing chips are cached in the second FIFO module through the first AER arbitrator.

6. The edge-end neuromorphic processor according to claim 5, characterized in that: The decision execution neural computation core includes a decision layer controller, a second AER arbitrator, a PreTrace memory, and multiple parallel learning and inference neural computation slices, all connected to the decision layer controller. Each learning and inference neural computation slice is connected to the second AER arbitrator and also to the PreTrace memory. The PreTrace memory stores the pulse trajectories of presynaptic neurons, which are used for weight updates. Each learning and inference neural computation slice includes a learning and inference neural computation slice controller, and decision layer neuron units, decision layer synaptic units, a decision layer neuron memory, a postsynaptic Trace memory, a decision layer synaptic memory, and a Vmax & tmax memory, all connected to the learning and inference neural computation slice controller via a data bus. The decision layer synaptic units execute corresponding learning rules according to their configuration. The decision execution neural computation core receives pulse events from the second FIFO module, updates the connection weights in the decision execution neural computation core according to the corresponding learning rules executed by the decision layer controller during training, and makes decisions during inference. In the decision-making, execution, learning, and reasoning neural computation chip, the output pulses of neurons are buffered in FIFO_3 through the second AER arbitrator. The winning neuron is determined by the number of pulses emitted by each neuron.

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