P-type laterally diffused metal oxide semiconductor device and manufacturing method thereof

Abstract

The present invention relates to a P-type laterally diffused metal oxide semiconductor device and a manufacturing method thereof, the method comprising: obtaining a substrate; patterning a mask layer to form at least two injection windows; performing N-type ion implantation through each injection window to form a high-voltage N-well doped region and a low-voltage N-well doped region in a P-type region; forming an oxide layer on the surface of each injection window; removing the mask layer; performing P-type ion general implantation into the P-type region, wherein the implantation of the P-type ions is blocked at the oxide layer; and thermally annealing is performed to diffuse the implanted P-type ions to form a drift region and a P-type well region. The patterned mask layer of the present invention forms segmented implantation windows, and after the N-type ions are implanted, an oxide layer is covered on the surface of the implantation window, and when the P-type ions are subsequently implanted, the oxide layer serves as an implantation blocking layer, so that the P-type ion implantation does not require a separate photolithography plate to be prepared, effectively simplifying the manufacturing process of the PLDMOS device, making it compatible with the manufacturing process of the NLDMOS.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor integrated circuits, and in particular to a P-type laterally diffused metal oxide semiconductor device, and also to a method for manufacturing the P-type laterally diffused metal oxide semiconductor device. Background Art

[0002] High-voltage integrated circuits are an important field of power electronics. They integrate high-voltage power devices with signal processing systems, as well as peripheral interface circuits, protection circuits, and detection circuits on a single chip, which not only improves the reliability and stability of the system, but also reduces the power consumption, volume, weight, and cost of the system. In high-voltage integrated circuits, when the potential of the high-side circuit is high voltage, level shifting technology is required to transmit the low-voltage signal to the high-voltage part to drive the high-voltage power device. The level shifting circuit is a bridge connecting high and low voltage circuits. It raises the low-voltage signal output by the previous dead zone generating circuit to a high-voltage signal for use by the subsequent high-voltage circuit to prevent the high and low voltage signals from generating crosstalk between the previous and subsequent stages. The high-voltage power conversion device LDMOS is the key to the level shifting circuit. Its gate terminal receives the signal of the low-side circuit and outputs the high-voltage signal through its drain terminal. Therefore, LDMOS needs to withstand the voltage of the high-side circuit. The breakdown voltage is an important parameter for measuring LDMOS devices. The breakdown voltage refers to the maximum voltage that the drain terminal can withstand when a high voltage is applied to the drain terminal of LDMOS and the gate and source are at zero potential. When the voltage at the drain exceeds the breakdown voltage of the device, the device will undergo avalanche breakdown. If the device is in a state of avalanche breakdown for a long time, it will burn out. LDMOS is widely used in high-voltage power integrated circuits because of its good switching characteristics and high breakdown voltage.

[0003] PLDMOS is a type of LDMOS, and has the excellent performance of LDMOS. At the same time, PLDMOS as a high-side driver can simplify the complexity of power integrated circuits and reduce chip area. However, unlike the conventional NLDMOS manufacturing process, the exemplary PLDMOS manufacturing process is more complicated. Summary of the invention

[0004] Based on this, it is necessary to provide a simplified method for manufacturing a P-type laterally diffused metal oxide semiconductor device.

[0005] A method for manufacturing a P-type laterally diffused metal oxide semiconductor device, comprising: obtaining a substrate; the substrate comprising an N-type buried layer and a P-type region on the N-type buried layer, wherein a mask layer is formed on the P-type region; patterning the mask layer to form at least two injection windows; performing N-type ion injection through each of the injection windows to form a high-voltage N-well doping region and a low-voltage N-well doping region in the P-type region; the doping concentration of the low-voltage N-well doping region is higher than the doping concentration of the high-voltage N-well doping region; forming an oxide layer on the surface of each of the injection windows; removing the mask layer; performing P-type ion injection into the P-type region, wherein the injection of the P-type ions is blocked at the oxide layer; and performing thermal annealing to diffuse the injected P-type ions to form A drift region and a P-type well region, the high-voltage N-well doped region diffuses to form a high-voltage N-type well region, and the low-voltage N-well doped region diffuses to form a low-voltage N-type well region; the drift region is located between the high-voltage N-type well region and the low-voltage N-type well region, the P-type well region is located on both sides of the high-voltage N-type well region, and the P-type well region on one side is located between the high-voltage N-type well region and the drift region; a source doped region, a drain doped region and a gate are formed; the source doped region is located in the low-voltage N-type well region, the drain doped region is located in the P-type well region and is located between the high-voltage N-type well region and the drift region, the gate is located on the substrate between the source doped region and the drain doped region, and the source doped region and the drain doped region have P-type doping.

[0006] In the manufacturing method of the above-mentioned P-type laterally diffused metal oxide semiconductor device, the patterned mask layer forms a segmented injection window, and after the N-type ions are injected, an oxide layer is covered on the surface of the injection window. When the P-type ions are subsequently injected, the oxide layer serves as an injection barrier layer. Therefore, there is no need to prepare a separate photolithography plate for the P-type ion injection, which effectively simplifies the manufacturing process of the PLDMOS device and makes it compatible with the manufacturing process of the NLDMOS.

[0007] In one of the embodiments, each of the injection windows includes a high-voltage N-well injection window and a low-voltage N-well injection window; the step of performing N-type ion implantation through each of the injection windows to form a high-voltage N-well doped region and a low-voltage N-well doped region in the P-type region includes: performing a first N-type ion implantation through the high-voltage N-well injection window and the low-voltage N-well injection window; forming a photoresist layer covering the high-voltage N-well injection window and exposing the low-voltage N-well injection window on the P-type region by photolithography; and performing a second N-type ion implantation, wherein the N-type ion implantation is blocked at a position covered by the photoresist layer.

[0008] In one of the embodiments, each of the injection windows also includes a plurality of N-type ion injection windows located between the high-voltage N-well injection window and the low-voltage N-well injection window; the first N-type ion injection includes forming a corresponding number of N-type drift region doping adjustment regions in the P-type region through each of the N-type ion injection windows; and the position covered by the photoresist layer includes each of the N-type ion injection windows.

[0009] In one embodiment, the interval between adjacent windows in the N-type ion implantation windows is 1.0 to 2.0 microns.

[0010] In one embodiment, the width of each N-type ion implantation window is 2.0-4.0 microns.

[0011] In one embodiment, the mask layer includes a silicon oxide layer and a silicon nitride layer, and the step of removing the mask layer is to remove the silicon nitride layer.

[0012] In one embodiment, the material of the silicon oxide layer includes a silicon dioxide layer.

[0013] In one embodiment, the material of the silicon nitride layer includes silicon nitride.

[0014] In one embodiment, the manufacturing method further includes: forming a field effect oxide layer on the drift region; the field effect oxide layer is located between the source doping region and the drain doping region; forming a source metal electrode, a drain metal electrode and a gate metal electrode; the source metal electrode is located on the source doping region and is electrically connected to the source doping region, the drain metal electrode is located on the drain doping region and is electrically connected to the drain doping region, the gate metal electrode is located on the gate and is electrically connected to the gate, the portion of the drain metal electrode located above the field effect oxide layer serves as a drain metal field plate, and the portion of the gate metal electrode located above the field effect oxide layer serves as a gate metal field plate; wherein the gate is a polysilicon gate, and the polysilicon gate extends onto the field effect oxide layer.

[0015] In one embodiment, the manufacturing method also includes the steps of forming a substrate lead-out region and a body region; the substrate lead-out region is formed in the P-type well region on the side of the high-voltage N-type well region away from the drift region, and the substrate lead-out region has P-type doping, the body region is formed in the low-voltage N-type well region, and the body region has N-type doping, and the source doping region is located between the body region and the drift region.

[0016] In one embodiment, forming a field effect oxide layer on the drift region includes forming a field effect oxide layer on the substrate surface between the substrate lead-out region and the drain doping region, and forming a field effect oxide layer on the substrate surface on both sides of the body region.

[0017] In one embodiment, the manufacturing method is used to form a PLDMOS for a high voltage integrated circuit with a breakdown voltage of 600V.

[0018] In one embodiment, the N-type ion source of the high-pressure N-type well region and the low-pressure N-type well region is phosphorus.

[0019] In one embodiment, the doping concentration of the high voltage N-type well region and the low voltage N-type well region is 1e 11 cm -2 ~1e 13 cm -2 .

[0020] In one of the embodiments, the P-type ion source of the drift region and the P-type well region is boron.

[0021] In one embodiment, the doping concentration of the drift region and the P-type well region is 1e 11 cm -2 ~1e 13 cm -2 .

[0022] It is also necessary to provide a P-type laterally diffused metal oxide semiconductor device, which is manufactured by the manufacturing method described in any of the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to better describe and illustrate the embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more drawings. The additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the embodiments and / or examples currently described, and the best modes of these inventions currently understood.

[0024] Figure 1 is a flow chart of a method for manufacturing a P-type laterally diffused metal oxide semiconductor device in one embodiment;

[0025] Figure 2a is a schematic cross-sectional view of a device structure after step S120 is completed in one embodiment, Figure 2b is a schematic cross-sectional view of a device structure after the first step of implantation in step S130 is completed in one embodiment. Figure 2c is a schematic cross-sectional view of the device structure after the second step of implantation in step S130 is completed in one embodiment, Figure 2d is a schematic cross-sectional view of a device structure after step S140 is completed in one embodiment, Figure 2e is a schematic cross-sectional view of a device structure after step S160 is completed in one embodiment, Figure 2fIt is a schematic diagram of the structure of the drift region, the P-type well region, the high-voltage N-type well region and the low-voltage N-type well region after the second thermal annealing in one embodiment;

[0026] Figure 3 It is a cross-sectional schematic diagram of a P-type laterally diffused metal oxide semiconductor device in one embodiment. DETAILED DESCRIPTION

[0027] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.

[0028] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0029] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there may be no intervening elements or layers. It should be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below may be represented as a second element, component, region, layer or part.

[0030] Spatially relative terms such as "under," "below," "below," "under," "above," "above," etc., may be used herein for ease of description to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatially relative terms are intended to include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, then the elements or features described as "under other elements" or "under" or "under" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" may include both upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0031] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present invention. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0032] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic diagrams of ideal embodiments (and intermediate structures) of the invention. Thus, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the invention should not be limited to the specific shapes of the zones shown herein, but include shape deviations due to, for example, manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to show the actual shape of the region of the device and are not intended to limit the scope of the invention.

[0033] The semiconductor field vocabulary used in this article is technical vocabulary commonly used by technical personnel in this field. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type represents P-type with heavy doping concentration, P-type represents P-type with medium doping concentration, P-type represents P-type with light doping concentration, N+ type represents N-type with heavy doping concentration, N-type represents N-type with medium doping concentration, and N-type represents N-type with light doping concentration.

[0034] In order to simplify the manufacturing process of PLDMOS and make it compatible with the manufacturing process of NLDMOS, the present application proposes a manufacturing method of a P-type laterally diffused metal oxide semiconductor device, referring to Figure 1 , including the following steps:

[0035] S110, obtaining a substrate, the substrate comprising an N-type buried layer and a P-type region on the N-type buried layer, and a mask layer formed on the P-type region.

[0036] See also Figure 2a In one embodiment of the present application, an N-type buried layer 220 is disposed in a substrate 210, a P-type region is specifically an epitaxial layer 230, and a mask layer 240 includes a silicon oxide layer 246 and a silicon nitride layer 248 on the silicon oxide layer 246; specifically, the silicon oxide layer 246 may be made of silicon dioxide, and the silicon nitride layer 248 may be made of silicon nitride. The substrate 210 is a semiconductor substrate, and its material may be undoped single crystal silicon, single crystal silicon doped with impurities, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanium on insulator (S-SiGeOI), silicon germanium on insulator (SiGeOI), and germanium on insulator (GeOI), etc. Figure 2a In the illustrated embodiment, the constituent material of the substrate 210 is single crystal silicon, ie, a P-type silicon substrate.

[0037] In one embodiment of the present application, an N-type buried layer 220 may be first formed in the substrate 210 , and then an epitaxial layer 230 may be formed on the N-type buried layer 220 , and then a mask layer 240 may be deposited on the epitaxial layer 230 .

[0038] S120, patterning the mask layer to form at least two injection windows.

[0039] In one embodiment of the present application, a photoresist is coated on the mask layer 240, and then the photoresist is exposed through an N-well photomask, and after development, a Figure 2a The photoresist layer 292 is shown, and the mask layer 240 is etched with the photoresist layer 292 as an etching barrier layer, and the excess mask layer 240 is removed to form a Figure 2a The multiple injection windows shown. These injection windows at least include a high-voltage N-well injection window 241 and a low-voltage N-well injection window 243, and may also include multiple N-type ion injection windows located between the high-voltage N-well injection window 241 and the low-voltage N-well injection window 243. Figure 2a In one embodiment of the present application, the interval d between adjacent windows in each N-type ion implantation window is 1.0 to 2.0 microns, and the width w of each N-type ion implantation window is 2.0 to 4.0 microns.

[0040] In one embodiment of the present application, a thin oxide layer 242 is further formed on the surface of the epitaxial layer 230 at each implantation window.

[0041] S130, performing N-type ion implantation through the implantation window to form a high-voltage N-well doping region and a low-voltage N-well doping region in the P-type region.

[0042] In one embodiment of the present application, the N-type ion implantation in step S130 is a two-step implantation (two implantations). Figure 2b In the first step, the doped regions are formed in the epitaxial layer 230 below each injection window, including the high-voltage N-well doped region 231. Before the second step of injection, the photoresist layer 292 is removed, and then the photoresist is coated again. The photoresist is exposed through the low-voltage N-well photomask. The exposed photoresist layer covers the high-voltage N-well injection window 241 and each N-type ion injection window, but exposes the low-voltage N-well injection window 243. The second step of injection is injected into the epitaxial layer 230 below through the low-voltage N-well injection window 243, and the N-type ions injected in the first step are superimposed to form the low-voltage N-well doped region 233, see Figure 2c In one embodiment of the present application, the N-type ion implantation dose of the second step is higher than the N-type ion implantation dose of the first step; accordingly, the doping concentration of the low-voltage N-well doping region 233 is higher than the doping concentration of the high-voltage N-well doping region 231 .

[0043] See also Figure 2b In this embodiment, the first step is to implant a drift region doping adjustment region 232 below each N-type ion implantation window. The N-type doped drift region doping adjustment region 232 can adjust the doping concentration of the drift region formed in subsequent steps.

[0044] In one embodiment of the present application, the ion source of the two N-type ion implantations in step S130 is phosphorus.

[0045] S140, forming an oxide layer on the surface of each implantation window.

[0046] In one embodiment of the present application, the thin oxide layer 242 on the surface of each implant window is thickened by high temperature oxidation to form an oxide layer 244, see Figure 2d The high temperature oxidation is thermal annealing with oxygen or other high temperature treatment with oxygen. The N-type ions implanted in step S130 diffuse during the annealing process.

[0047] S150, removing the mask layer.

[0048] The subsequent P-type ion implantation is implanted from the position of the mask layer 240, so in this step, the mask layer 240 is removed. In one embodiment of the present application, step S150 is to remove the silicon nitride layer 248 in the mask layer 240.

[0049] S160, performing P-type ion general injection into the P-type region.

[0050] See also Figure 2e , P-type ions are generally injected into the epitaxial layer 230, and the oxide layer 244 blocks the injection of P-type ions. The P-type ions are injected from the position covered by the mask layer 240 in the previous step to form a P-type doped region 234. If P-type ions diffuse into the region of the epitaxial layer 230 where N-type ions are injected, they will be neutralized by the N-type ions.

[0051] In one embodiment of the present application, the ion source of the P-type ion implantation in step S160 is boron.

[0052] S170, thermal annealing.

[0053] Thermal annealing is performed again to promote the diffusion of the high-voltage N-well doping region 231, the low-voltage N-well doping region 233 and the P-type doping region 234, so that their bottoms reach the N-type buried layer 220; the high-voltage N-well doping region 231 forms a high-voltage N-type well region 235 after thermal annealing, the low-voltage N-well doping region 233 forms a low-voltage N-type well region 237 after thermal annealing, and the P-type doping region 234 forms a drift region 236 and a P-type well region 238 after thermal annealing. The P-type well region 238 is formed on both sides of the high-voltage N-type well region 235, and the drift region 236 is formed between the P-type well region 238 and the low-voltage N-type well region 237 on the side of the high-voltage N-type well region 235 close to the low-voltage N-type well region 237. Since an N-type drift region doping adjustment region 232 is formed in advance in the area where the drift region 236 is located, in the process of forming the drift region 236 after the thermal annealing of the P-type doping region 234 in step S170, the N-type drift region doping adjustment region 232 will neutralize a portion of the P-type ions in the drift region 236, so that the doping concentration of the drift region 236 is lower than the doping concentration of the P-type well region 238. In addition, the dose of the P-type ion implantation in step S160 can be made greater than the dose of the first N-type ion implantation in step S130, so as to effectively ensure that the P-type drift region 236 is formed after the thermal annealing in step S170.

[0054] In one embodiment of the present application, the doping concentration of the high voltage N-type well region 235 is lower than the doping concentration of the low voltage N-type well region 237; the doping concentration range of the high voltage N-type well region 235 and the low voltage N-type well region 237 is 1e 11 cm -2 ~1e 13 cm -2 .

[0055] In one embodiment of the present application, the doping concentration range of the drift region 236 and the P-type well region 238 is 1e 11 cm -2 ~1e 13 cm -2 .

[0056] S180, forming a source doping region, a drain doping region and a gate.

[0057] In one embodiment of the present application, a source doping region 252 is formed in the low voltage N-type well region 237 by photolithography and ion implantation processes, and a drain doping region 254 is formed in the P-type well region 238 (the P-type well region 238 between the high voltage N-type well region 235 and the drift region 236) by photolithography and ion implantation processes. A gate 260 is formed on the substrate between the source doping region 252 and the drain doping region 254 by deposition, photolithography and etching processes. In one embodiment of the present application, before forming the gate 260, a step of forming a field effect oxide layer 250 on the drift region is also included. The polysilicon gate 260 extends from the edge of the source doping region 252 (extending in the direction of the drain doping region 254) to the field effect oxide layer 250. The source doping region 252 and the drain doping region 254 have P-type doping, specifically, the source doping region 252 and the drain doping region 254 are P+ regions.

[0058] In the manufacturing method of the above-mentioned P-type laterally diffused metal oxide semiconductor device, the patterned mask layer forms a segmented injection window, and after the N-type ions are injected, the oxide layer 244 is covered on the surface of the injection window. When the P-type ions are subsequently injected, the oxide layer 244 serves as an injection barrier layer. Therefore, there is no need to prepare a separate photolithography plate for the P-type ion injection, which effectively simplifies the manufacturing process of the PLDMOS device and makes it compatible with the manufacturing process of the NLDMOS.

[0059] In one embodiment of the present application, after step S180, the step of forming a source metal electrode S, a drain metal electrode D and a gate metal electrode G is also included. The source metal electrode S is located on the source doping region 252 and is electrically connected to the source doping region 252. The drain metal electrode D is located on the drain doping region 254 and is electrically connected to the drain doping region 254. The gate metal electrode G is located on the gate 260 and is electrically connected to the gate 260. The portion of the drain metal electrode D located above the field effect oxide layer 250 serves as a drain metal field plate, and the portion of the gate metal electrode G located above the field effect oxide layer 250 serves as a gate metal field plate.

[0060] In one embodiment of the present application, the manufacturing method of the above-mentioned P-type laterally diffused metal oxide semiconductor device further includes the steps of forming a substrate lead-out region 256 and a body region 258. The substrate lead-out region 256 is formed in the P-type well region 238 on the side of the high-voltage N-type well region 235 away from the drift region 236, and the substrate lead-out region 256 has a P-type doping. The body region 258 is formed in the low-voltage N-type well region 237, and the body region 258 has an N-type doping. The source doping region 252 is located between the body region 258 and the drift region 236. In one embodiment of the present application, the substrate lead-out region 256 is a P+ region, and the body region 258 is an N+ region.

[0061] In one embodiment of the present application, the aforementioned step of forming the field effect oxide layer 250 simultaneously forms a field effect oxide layer 250 on the substrate surface between the substrate lead-out region 256 and the drain doping region 254 , and forms a field effect oxide layer 250 on the substrate surface on both sides of the body region 258 .

[0062] The present application accordingly provides a PLDMOS for high voltage integrated circuits with a breakdown voltage of 600V, which can be manufactured by the manufacturing method of a P-type laterally diffused metal oxide semiconductor device of any of the above embodiments. Figure 3 The PLDMOS includes a P-type substrate 210, an N-type buried layer 220 is provided in the substrate 210, and a P-type epitaxial layer is provided on the N-type buried layer 210 and the substrate 210. A high-voltage N-type well region 235, a low-voltage N-type well region 237, a P-type doped drift region 236, and a P-type well region 238 are provided in the P-type epitaxial layer. A field effect oxide layer 250 is provided on the P-type epitaxial layer, and a gate 260 is provided on the field effect oxide layer 250, which can be a polysilicon gate, and the gate 260 is located above the low-voltage N-type well region 237 and the field effect oxide layer 250. A cathode N-type heavily doped region (as a body region 258) and a cathode P-type heavily doped region (as a source doped region 252) are provided in the low-voltage N-type well region 237, and the body region 258 is connected to the body region metal electrode bulk. The source doping region 252 is located between the gate 260 and the body region 258 and is connected to the source metal electrode S. An anode P-type heavily doped region (as a substrate lead-out region 256) is provided in the P-type well region 238, and the substrate lead-out region 256 is connected to the substrate lead-out region metal electrode Sub. An anode P-type heavily doped region (as a drain doping region 254) is provided in the P-type well region 238, and the drain doping region 254 is located between the high-voltage N-type well region 235 and the drift region 236 and is connected to the drain metal electrode D.

[0063] See also Figure 3 The first side of the front metal layer of the drain (i.e., the drain metal electrode D) is located above the field effect oxide layer 250 between the drain doping region 254 and the substrate lead-out region 256, and the second side is located above the field effect oxide layer 250 on the drift region 236, and the second side extends toward the drift region 236 to form a drain metal field plate. The first side of the front metal layer of the gate (i.e., the gate metal electrode G) is located above the field effect oxide layer 250 on the drift region 236, and the second side is located above the gate 260, and the first side extends above the drift region 236 to form a gate metal field plate.

[0064] It should be understood that, although the various steps in the flowchart of the present application are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowchart of the present application may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0065] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0066] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0067] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A method for manufacturing a P-type laterally diffused metal oxide semiconductor device, comprising: Obtaining a substrate; The substrate comprises an N-type buried layer and a P-type region on the N-type buried layer, and a mask layer is formed on the P-type region; patterning the mask layer to form at least two injection windows; Performing N-type ion implantation through each of the implantation windows to form a high-voltage N-well doping region and a low-voltage N-well doping region in the P-type region; the doping concentration of the low-voltage N-well doping region is higher than the doping concentration of the high-voltage N-well doping region; forming an oxide layer on the surface of each of the injection windows; removing the mask layer; Performing a general P-type ion injection into the P-type region, wherein the injection of the P-type ions is blocked at the oxide layer; The injected P-type ions are diffused to form a drift region and a P-type well region by thermal annealing, the high-voltage N-well doped region is diffused to form a high-voltage N-type well region, and the low-voltage N-well doped region is diffused to form a low-voltage N-type well region; the drift region is located between the high-voltage N-type well region and the low-voltage N-type well region, the P-type well region is located on both sides of the high-voltage N-type well region, and the P-type well region on one side is located between the high-voltage N-type well region and the drift region; A source doping region, a drain doping region and a gate are formed; the source doping region is located in the low voltage N-type well region, the drain doping region is located in the P-type well region and between the high voltage N-type well region and the drift region, the gate is located on the substrate between the source doping region and the drain doping region, and the source doping region and the drain doping region have P-type doping.

2. The method for manufacturing a P-type laterally diffused metal oxide semiconductor device according to claim 1, characterized in that: Each of the injection windows includes a high-voltage N-well injection window and a low-voltage N-well injection window; The step of performing N-type ion implantation through each of the implantation windows to form a high-voltage N-well doped region and a low-voltage N-well doped region in the P-type region comprises: Performing a first N-type ion implantation through the high-voltage N-well implantation window and the low-voltage N-well implantation window; Forming a photoresist layer covering the high-voltage N-well injection window and exposing the low-voltage N-well injection window on the P-type region by photolithography; A second N-type ion implantation is performed, and the N-type ion implantation at the position covered by the photoresist layer is blocked.

3. The method for manufacturing a P-type laterally diffused metal oxide semiconductor device according to claim 2, characterized in that: Each of the injection windows further comprises a plurality of N-type ion injection windows located between the high-voltage N-well injection window and the low-voltage N-well injection window; The first N-type ion implantation includes forming a corresponding number of N-type drift region doping adjustment regions in the P-type region through each of the N-type ion implantation windows; The positions covered by the photoresist layer include the N-type ion implantation windows.

4. The method for manufacturing a P-type laterally diffused metal oxide semiconductor device according to claim 3, characterized in that: The interval between adjacent windows in the N-type ion implantation windows is 1.0 to 2.0 micrometers, and / or The width of each N-type ion implantation window is 2.0 to 4.0 microns.

5. The method for manufacturing a P-type laterally diffused metal oxide semiconductor device according to claim 1, characterized in that: The mask layer includes a silicon dioxide layer and a silicon nitride layer on the silicon dioxide layer, and the step of removing the mask layer is to remove the silicon nitride layer.

6. The method for manufacturing a P-type laterally diffused metal oxide semiconductor device according to claim 1, characterized in that: Also includes: forming a field effect oxide layer on the drift region; The field effect oxide layer is located between the source doping region and the drain doping region; A source metal electrode, a drain metal electrode and a gate metal electrode are formed; the source metal electrode is located on the source doped region and is electrically connected to the source doped region, the drain metal electrode is located on the drain doped region and is electrically connected to the drain doped region, the gate metal electrode is located on the gate and is electrically connected to the gate, the portion of the drain metal electrode located above the field effect oxide layer serves as a drain metal field plate, and the portion of the gate metal electrode located above the field effect oxide layer serves as a gate metal field plate; Wherein, the gate is a polysilicon gate, and the polysilicon gate extends onto the field effect oxide layer.

7. The method for manufacturing a P-type laterally diffused metal oxide semiconductor device according to claim 1, characterized in that: It also includes the steps of forming a substrate lead-out region and a body region; the substrate lead-out region is formed in the P-type well region on the side of the high-voltage N-type well region away from the drift region, the substrate lead-out region has P-type doping, the body region is formed in the low-voltage N-type well region, the body region has N-type doping, and the source doping region is located between the body region and the drift region.

8. The method for manufacturing a P-type laterally diffused metal oxide semiconductor device according to claim 1, characterized in that: Used to form PLDMOS for high-voltage integrated circuits with a breakdown voltage of 600V.

9. The method for manufacturing a P-type laterally diffused metal oxide semiconductor device according to claim 1, characterized in that: The N-type ion source of the high-voltage N-type well region and the low-voltage N-type well region is phosphorus, and the doping concentration is 1e 11 cm -2 ~1e 13 cm -2 The P-type ion source of the drift region and the P-type well region is boron, and the doping concentration is 1e 11 cm -2 ~1e 13 cm -2 .

10. A P-type laterally diffused metal oxide semiconductor device, characterized in that: Produced by the method according to any one of claims 1 to 9.

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