IGBT device manufacturing method and IGBT device

Abstract

The present invention proposes a method for manufacturing an IGBT device and an IGBT device, the manufacturing method comprising: providing a first silicon wafer and a second silicon wafer; manufacturing a MOSFET on the front side of the first silicon wafer (IGBT front side process), depositing an interlayer dielectric layer, a first metal layer and a first hard mask; depositing a second hard mask on the front side of the second silicon wafer, and bonding the front side of the first silicon wafer to the front side of the second silicon wafer. The manufacturing method of the IGBT device provided in the present application performs a back side process on the first silicon wafer after the first silicon wafer and the second silicon wafer are bonded. At this time, the first silicon wafer is no longer a thin wafer, and the IGBT device can be made thinner. A thinner IGBT device can effectively solve the heat dissipation problem of high-power devices; at the same time, the stability of the manufacturing process of the field termination FS region and the collector P-type region performed on the back side of the first silicon wafer is higher.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor manufacturing methods, and in particular relates to a manufacturing method of an IGBT device and an IGBT device. Background Art

[0002] The IGBT (insulated gate bipolar transistor) with field stop (FS) structure has low conduction loss and positive conduction voltage drop temperature coefficient, so that high-power devices can be used in parallel. The FS-type IGBT has a FS region, which is an N-type doped region with a higher doping concentration than the N-region in the IGBT. Its function is to rapidly reduce the electric field intensity in this layer under high voltage to achieve electric field termination. The FS-type IGBT includes: the silicon substrate N-region of the IGBT, the FS region, the back P-type region, the back metal layer and the front MOSFET (metal-oxide-semiconductor field effect transistor). The current method for making FS-type IGBT is generally: first, MOSFET devices are made on the silicon substrate, and then the residual layer and part of the silicon substrate left when making MOSFET are removed from the back of the silicon wafer by grinding, and then N-type and P-type impurities are injected from the back of the silicon wafer by an ion implanter, and the injected impurities are activated by thermal annealing or laser annealing to form the FS region and the collector region (P-type region); a metal layer is deposited on the lower surface of the P-type region. The IGBT itself is relatively thin. The existing back-side processing uses a special thin-film machine to grind the back of the IGBT. The ground thin film is easy to break in the subsequent process, which makes the stability of the subsequent process poor and affects the product yield. Summary of the invention

[0003] To overcome one of the defects of the prior art, the present invention provides a method for manufacturing an IGBT device and an IGBT device.

[0004] The technical solution adopted by the present invention is:

[0005] A method for manufacturing an IGBT device comprises the following steps:

[0006] Providing a first silicon wafer;

[0007] Manufacturing MOSFET on the front side of the first silicon wafer, and depositing an interlayer dielectric layer on the MOSFET;

[0008] forming a first metal connection portion in the interlayer dielectric layer;

[0009] forming a first metal layer on the interlayer dielectric layer;

[0010] forming a first hard mask on the first metal layer;

[0011] forming a second metal connection in the first hard mask;

[0012] Providing a second silicon wafer;

[0013] Depositing a second hard mask on the front side of the second silicon wafer;

[0014] forming a third metal connection in the second hard mask;

[0015] Bonding the front side of the first silicon wafer to the front side of the second silicon wafer;

[0016] Forming a field termination FS region on the back side of the first silicon wafer;

[0017] Making a collector P-type region on the back side of the first silicon wafer;

[0018] A back metal is formed on the back side of the first silicon wafer.

[0019] In some embodiments of the present application, the method for manufacturing the IGBT device further includes:

[0020] performing chemical mechanical polishing on the back side of the second silicon wafer;

[0021] forming a hole on the back side of the second silicon wafer to expose the third metal connection portion in the second hard mask;

[0022] Depositing a conductive layer on the back side of the second silicon wafer and in the hole;

[0023] A passivation layer is formed on the conductive layer.

[0024] In some embodiments of the present application, the method for manufacturing the IGBT device further includes:

[0025] performing chemical mechanical polishing on the back side of the second silicon wafer;

[0026] forming a hole on the back side of the second silicon wafer to expose the third metal connection portion in the second hard mask;

[0027] forming a barrier layer along the sidewalls of the hole;

[0028] removing the barrier layer at the bottom of the hole to expose the third metal connection portion;

[0029] Depositing a conductive layer on the back side of the second silicon wafer and in the hole;

[0030] A passivation layer is formed on the conductive layer.

[0031] In some embodiments of the present application, the back side of the second silicon wafer is ground to a thickness of 5-600 μm.

[0032] In some embodiments of the present application, chemical mechanical polishing is performed on the back side of the first silicon wafer before the field stop FS region is formed on the back side of the first silicon wafer.

[0033] In some embodiments of the present application, the back side of the first silicon wafer is ground to a thickness of 5-400 μm.

[0034] In some embodiments of the present application, the thickness of the second silicon wafer is 40-800 μm.

[0035] In some embodiments of the present application, bonding the front side of the first silicon wafer to the front side of the second silicon wafer includes: aligning and bonding the second metal connection portion on the front side of the first silicon wafer to the third metal connection portion on the front side of the second silicon wafer.

[0036] In some embodiments of the present application, the front side of the first silicon wafer and the front side of the second silicon wafer are bonded by an annealing process, and the annealing conditions are: temperature below 600° C. and time from 30 min to 3 hrs.

[0037] On the other hand, the present application provides an IGBT device, including:

[0038] A first silicon wafer, wherein the back side of the first silicon wafer has, from outside to inside: a back side metal, a collector P-type region and a field stop FS region, and the front side of the first silicon wafer has, from outside to inside: an interlayer dielectric layer and a MOSFET;

[0039] A first metal layer and a first hard mask are sequentially formed on the front side of the first silicon wafer and the interlayer dielectric layer; a first metal connection portion is provided in the interlayer dielectric layer, and the first metal connection portion is electrically connected to the first metal layer; a second metal connection portion is provided in the first hard mask, and the second metal connection portion is electrically connected to the first metal layer;

[0040] A second silicon wafer, wherein a second hard mask is formed on the front side of the second silicon wafer, and a third metal connection portion is formed in the second hard mask; the third metal connection portion is electrically connected to the second metal connection portion;

[0041] The front side of the second silicon wafer is bonded to the front side of the first silicon wafer.

[0042] In some embodiments of the present application, a hole is opened on the back side of the second silicon wafer, and the hole exposes the third metal connection portion;

[0043] A conductive layer is formed in the hole and on the back side of the second silicon wafer;

[0044] A passivation layer is formed on the conductive layer.

[0045] In some embodiments of the present application, a barrier layer is further provided on the sidewall of the hole, between the conductive layer and the second silicon wafer.

[0046] In some embodiments of the present application, in addition to the hole, a protective layer is formed between the conductive layer and the second silicon wafer.

[0047] Compared with the prior art, the advantages and positive effects of the present invention are: the manufacturing method of the IGBT device provided by the present application performs the back process of the first silicon wafer after the first silicon wafer and the second silicon wafer are bonded. At this time, the first silicon wafer is no longer a thin slice, and the IGBT device can be made thinner. For example, for large-size IGBT devices (above 12 inches), the chip thickness can be reduced to less than 100μm. Thinner IGBT devices can effectively solve the heat dissipation problem of high-power devices. At the same time, the stability of the field termination FS region and the collector P-type region manufacturing process performed on the back of the first silicon wafer is higher. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 Schematic cross-sectional view of the steps of a method for manufacturing an IGBT device in one embodiment of the present invention, wherein an interlayer dielectric layer and a first metal layer are formed on the front side of a first silicon wafer;

[0049] Figure 2 Schematic cross-sectional view of the steps of a method for manufacturing an IGBT device in one embodiment of the present invention, wherein a first hard mask is formed on a first metal layer;

[0050] Figure 3 Schematic cross-sectional view of the steps of a method for manufacturing an IGBT device in an embodiment of the present invention, wherein a second metal connection portion is formed in a first hard mask;

[0051] Figure 4 is a schematic cross-sectional view of steps of a method for manufacturing an IGBT device in an embodiment of the present invention, wherein a second hard mask is formed on a second silicon wafer;

[0052] Figure 5 Schematic cross-sectional view of the steps of a method for manufacturing an IGBT device in one embodiment of the present invention, wherein the second hard mask has an opening;

[0053] Figure 6 Schematic cross-sectional view of the steps of a method for manufacturing an IGBT device in an embodiment of the present invention, wherein a third metal connection portion is formed in the second hard mask;

[0054] Figure 7 It is a schematic cross-sectional view of the steps of a method for manufacturing an IGBT device in one embodiment of the present invention, wherein the front side of a first silicon wafer is bonded to the front side of a second silicon wafer;

[0055] Figure 8Schematic cross-sectional view of the steps of a method for manufacturing an IGBT device in one embodiment of the present invention, wherein the back side of the second silicon wafer is thinned;

[0056] Fig. 9 Schematic cross-sectional view of the steps of a method for manufacturing an IGBT device in one embodiment of the present invention, wherein a through hole is opened on the back side of the second silicon wafer;

[0057] Fig.10 Schematic cross-sectional view of the steps of a method for manufacturing an IGBT device in one embodiment of the present invention, wherein a conductive layer on the back side of a second silicon wafer is formed;

[0058] Fig.11 Schematic diagram of the cross-section of the steps of a method for manufacturing an IGBT device in one embodiment of the present invention, wherein a passivation layer is formed;

[0059] Fig.12 1 is a schematic flow chart of steps of a method for manufacturing an IGBT device in another embodiment of the present invention, wherein a barrier layer is formed on the sidewall of the hole;

[0060] Fig.13 is a schematic cross-sectional view of steps of a method for manufacturing an IGBT device in another embodiment of the present invention, wherein a conductive layer is formed;

[0061] Fig.14 is a schematic cross-sectional view of steps of a method for manufacturing an IGBT device in another embodiment of the present invention, wherein a passivation layer is formed;

[0062] Fig.15 Schematic cross-sectional view of the steps of a method for manufacturing an IGBT device in one embodiment of the present invention, wherein the front side of the first silicon wafer is thinned;

[0063] Fig.16 Schematic diagram of the cross-section of the steps of a method for manufacturing an IGBT device in one embodiment of the present invention, wherein N-type ions are implanted into the back side of a first silicon wafer;

[0064] Fig.17 Schematic diagram of the cross-section of the steps of a method for manufacturing an IGBT device in one embodiment of the present invention, wherein P-type ions are implanted into the back side of a first silicon wafer;

[0065] Fig.18 Schematic diagram of the cross-section of the steps of a method for manufacturing an IGBT device in one embodiment of the present invention, wherein a back metal is formed;

[0066] Fig.19 is a schematic cross-sectional view of steps of a method for manufacturing an IGBT device in another embodiment of the present invention, wherein a back metal is formed;

[0067] Fig. 20 Schematic diagram of a process for manufacturing an IGBT device in one embodiment of the present invention;

[0068] Fig.21 A schematic flow chart of the steps of a method for manufacturing an IGBT device provided in another embodiment of the present application;

[0069] Fig. 22 A schematic flow chart of the steps of a method for manufacturing an IGBT device provided in yet another embodiment of the present application.

[0070] In the figure:

[0071] 100, first silicon wafer; 101, field stop FS region; 102, collector P-type region; 110, MOSFET; 120, interlayer dielectric layer; 121, first metal connection; 130, first metal layer; 140, first hard mask; 141, second metal connection; 150, back metal; 200, second silicon wafer; 201, hole; 210, second hard mask; 211, third metal connection; 212, barrier layer; 220, protective layer; 230, conductive layer; 240, passivation layer. DETAILED DESCRIPTION

[0072] The technical solutions in the embodiments of the present invention are described clearly and completely below. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0073] An embodiment of the present invention provides a method for manufacturing an IGBT device, comprising the following steps:

[0074] Providing a first silicon wafer;

[0075] Fabricate a MOSFET on the front side of the first silicon wafer, and deposit an interlayer dielectric layer on the MOSFET;

[0076] forming a first metal connection portion in the interlayer dielectric layer;

[0077] forming a first metal layer on the interlayer dielectric layer;

[0078] forming a first hard mask on the first metal layer, and forming a second metal connection portion in the first hard mask;

[0079] Providing a second silicon wafer;

[0080] Depositing a second hard mask on the front side of the second silicon wafer;

[0081] forming a third metal connection in the second hard mask;

[0082] bonding the front side of the first silicon wafer to the front side of the second silicon wafer;

[0083] Forming a field termination FS region on the back side of the first silicon wafer;

[0084] Producing a collector P-type region on the back side of the first silicon wafer;

[0085] A back metal is formed on the back side of the first silicon wafer.

[0086] The manufacturing method of the IGBT device provided in the present application performs a back process on the first silicon wafer after the first silicon wafer and the second silicon wafer are bonded. At this time, the first silicon wafer is no longer a thin slice, and the IGBT device can be made thinner. For example, for large-size IGBT devices (over 12 inches), the chip thickness can be reduced to less than 100μm. Thinner IGBT devices can effectively solve the heat dissipation problem of high-power devices. At the same time, the stability of the field termination FS region and the collector P-type region manufacturing process performed on the back of the first silicon wafer is higher.

[0087] Figures 1 to 19 FIG. 1 is a cross-sectional diagram of a method for manufacturing an IGBT device according to an embodiment of the present invention. First, Figure 1 As shown, a first silicon wafer 100 is provided, and a MOSFET 110 is manufactured on the front side of the first silicon wafer, that is, an IGBT front side process. The first silicon wafer 100 may be a semiconductor substrate such as a silicon substrate, a silicon-containing substrate or a silicon-covered insulating substrate. The method for manufacturing a MOSFET on the front side of the first silicon wafer may be a known method. For example, an interlayer dielectric layer is formed on the front side of the first silicon wafer, and a gate trench is formed in the interlayer dielectric layer; a gate dielectric layer is formed in the gate trench; a gate electrode is formed on the gate dielectric layer; and a planarization process is performed to remove the gate dielectric layer material and the gate electrode material located on the interlayer dielectric layer. In order to adjust the threshold voltage of the MOSFET, the method for manufacturing the MOSFET may also include a process for adjusting the threshold voltage, such as a work function layer formation process, a channel region doping process, etc. The method for manufacturing the MOSFET may also include a source and drain epitaxial process, a gate sidewall oxide layer manufacturing process, etc.

[0088] Figure 1 1 and 2 also show an interlayer dielectric layer 120. The interlayer dielectric layer 120 is formed on the MOSFET 110, and can be formed of a low-K dielectric material, such as phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), SiOxCy, silicon carbide, silicon nitride, aluminum nitride, aluminum oxide, etc., by any suitable method known in the art, such as spin coating, chemical vapor deposition (CVD) and plasma enhanced CVD (PECVD).

[0089] Next, a first metal connection 121 is formed in the interlayer dielectric layer 120. The first metal connection is formed of a metal material or a metal compound material, such as copper (Cu), cobalt (Co), aluminum (Al), tungsten (W), titanium (Ti), titanium nitride (TiN), thallium (Ta), thallium nitride (TaN), etc. Specifically, the method for forming the first metal connection in the interlayer dielectric layer is: first forming a patterned mask on the interlayer dielectric layer, then performing an etching process to form a through groove on the interlayer dielectric layer, then depositing the first metal connection material in the through groove, and then performing chemical mechanical polishing to remove the first metal connection material on the surface of the interlayer dielectric layer. The first metal connection formed in the interlayer dielectric layer is electrically connected to the transistor circuit below the interlayer dielectric layer.

[0090] Figure 1 It is also shown that a first metal layer 130 is formed on the interlayer dielectric layer 120. The first metal layer 130 is electrically connected to the first metal connection portion 121. The first metal layer is formed of a metal material or a metal compound material, such as copper (Cu), cobalt (Co), aluminum (Al), tungsten (W), titanium (Ti), titanium nitride (TiN), thallium (Ta), thallium nitride (TaN), etc. The first metal layer can be formed by physical vapor deposition and chemical vapor deposition, or by electroplating. The first metal connection portion is made of metal or a metal compound, such as copper (Cu), cobalt (Co), aluminum (Al), tungsten (W), titanium (Ti), titanium nitride (TiN), thallium (Ta), thallium nitride (TaN).

[0091] Then, refer to Figure 2 and Figure 3 , a first hard mask 140 is formed on the first metal layer 130, and a second metal connection portion 141 is formed in the first hard mask 140. The second metal connection portion 141 is electrically connected to the first metal layer 130. The first hard mask is formed of materials such as silicon nitride (SiN), silicon dioxide (SiO2), silicon carbide (SiC), aluminum nitride (AlN), aluminum oxide (AlO), etc. The method for forming the first hard mask can be a chemical vapor deposition method, such as a plasma-assisted chemical vapor deposition method or a low-pressure chemical vapor deposition method. The second metal connection portion can be formed in the first hard mask by the same method as the first metal connection portion in the interlayer dielectric layer. The second metal connection portion can be made of the same material as the first metal connection portion.

[0092] like Figure 4 As shown, a second silicon wafer 200 is provided. The second silicon wafer 200 may be a semiconductor substrate such as a silicon substrate, a silicon-containing substrate, or a silicon-covered insulating substrate. The thickness of the second silicon wafer may be 40-800 μm. Then, referring to Figure 5 and Figure 6, a second hard mask 210 is formed on the front side of the second silicon wafer 200, and a third metal connection portion 211 is formed in the second hard mask 210. The second hard mask is formed of materials such as silicon nitride (SiN), silicon dioxide (SiO2), silicon carbide (SiC), aluminum nitride (AlN), aluminum oxide (AlO), etc. The method for forming the second hard mask can be a chemical vapor deposition method, such as a plasma-assisted chemical vapor deposition method or a low-pressure chemical vapor deposition method. The third metal connection portion can be formed in the second hard mask by the same method as the first metal connection portion formed in the interlayer dielectric layer. The third metal connection portion can be made of the same material as the first metal connection portion.

[0093] Next, refer to Figure 7 , bonding the front side of the first silicon wafer 100 to the front side of the second silicon wafer 200. Specifically, the first hard mask 140 located at the outermost layer of the front side of the first silicon wafer 100 is used as one of the bonding surfaces; the second hard mask 210 located at the outermost layer of the front side of the second silicon wafer 200 is used as the other bonding surface to achieve bonding between the front side of the first silicon wafer 100 and the front side of the second silicon wafer 200. The bonding between the front side of the first silicon wafer and the front side of the second silicon wafer adopts an annealing process, and the annealing conditions are: temperature below 600°C, time 30min to 3hrs.

[0094] Before bonding the front side of the first silicon wafer 100 and the front side of the second silicon wafer 200, the first hard mask 140 on the front side of the first silicon wafer and the second hard mask 210 on the front side of the second silicon wafer are firstly subjected to chemical mechanical polishing. On the one hand, the second metal connection part 141 and the third metal connection part 211 are exposed, and on the other hand, the flatness of the bonding surface is controlled, which is beneficial to the subsequent bonding process. Then, the second metal connection part 141 on the front side of the first silicon wafer 100 and the third metal connection part 211 on the front side of the second silicon wafer 200 are aligned and bonded. Metal-metal bonding is formed between the second metal connection part 141 and the third metal connection part 211, and an electrical connection is formed. In addition, a dielectric-dielectric bonding is formed between the first hard mask 140 and the second hard mask 210.

[0095] Next, a through-hole process is performed on the back side of the second silicon wafer to connect the transistor circuit on the front side of the first silicon wafer to the back side of the second silicon wafer through the conductive material filled in the through-hole. Figures 8 to 11 As shown, the process for forming a through hole on the back side of the second silicon wafer includes: performing chemical mechanical polishing on the back side of the second silicon wafer 200; forming a hole 201 on the back side of the second silicon wafer 200 to expose the third metal connection portion 211 located in the second hard mask 210; depositing a conductive layer 230 on the back side of the second silicon wafer 200 and the hole 201; and forming a passivation layer 240 on the conductive layer 230.

[0096] refer to Figure 8 , Fig. 9 , Figures 12 to 14As shown in FIG. 1 , the process flow of the second silicon wafer backside through hole is shown. First, Figure 8 As shown, the back side of the second silicon wafer 200 is subjected to chemical mechanical grinding. The second silicon wafer is ground to a thickness of 5-600 μm. Then, as Fig. 9 As shown, optionally, a protective layer 220 is deposited on the back of the second silicon wafer 200 to protect the second silicon wafer 200 covered by the protective layer from being etched in subsequent processes. Fig. 9 As shown, a patterned hard mask layer is formed on the back of the second silicon wafer 200, and then the hard mask layer is used as a mask to etch the back of the second silicon wafer 200 to remove the protective layer 220 used to form the hole 201 part later, and then the etching gas and the protective gas are alternately introduced to alternately etch the back of the second silicon wafer 200 and protect the sidewall formed after etching until the hole 201 of a predetermined size is formed. Alternatively, before the hole 201 is formed, the protective layer 220 is not deposited first, and after the hole 201 is formed, a protective layer 220 is deposited on the back of the second silicon wafer 200 except the hole. The material of the protective layer can be Si C, Si N, Si CN or a mixture thereof. The method of etching to form the hole can adopt a deep reactive ion etching process.

[0097] Then, if Fig.12 As shown, a barrier layer 212 is formed on the back of the second silicon wafer 200 and on the surface of the hole 201. The barrier layer can improve the elimination of stress around the hole and prevent stress from causing structural defects. The material of the barrier layer may include silicon oxide and silicon nitride. In this embodiment, the method for forming the barrier layer may be plasma-assisted chemical vapor deposition or low-pressure chemical vapor deposition. In this embodiment, the barrier layer is formed on the surface of the hole, and the surface of the hole includes both the bottom surface of the hole and the inner sidewall surface of the hole.

[0098] Then, if Fig.12 As shown, the barrier layer 212 at the bottom of the hole 201 is removed to expose the third metal connection portion 211. Specifically, the back of the second silicon wafer is wet-etched to improve the uniformity and roughness of the back of the second silicon wafer, and the second silicon wafer is further thinned until the second hard mask at the bottom of the hole is exposed, thereby exposing the third metal connection portion, which facilitates the electrical connection between the third metal connection portion and the subsequently formed through hole. The wet etching etchant can be selected, for example, a mixture of KOH, HF and nitric acid, or a TMAH solvent.

[0099] refer to Fig.13, a conductive layer 230 is formed on the back of the second silicon wafer 200 and in the hole 201. In this embodiment, the material of the conductive layer is copper. The conductive layer can be formed by physical vapor deposition and chemical vapor deposition, or by electroplating. It should be noted that in other embodiments of the present application, the material of the conductive layer can be other metals or metal compounds, such as cobalt (Co), aluminum (Al), tungsten (W), titanium (Ti), titanium nitride (TiN), thallium (Ta), thallium nitride (TaN), etc.

[0100] After the barrier layer is formed, the barrier layer may be subjected to a planarization process to maintain a certain flatness between the barrier layer and the back side of the second silicon wafer; after the conductive layer is formed, the conductive layer may be subjected to a planarization process. In this embodiment, chemical mechanical polishing may be used to planarize the conductive layer and the barrier layer, and chemical mechanical polishing can accurately and uniformly planarize the corresponding structure to the required thickness and flatness. For the back side of the second silicon wafer formed with a protective layer, the protective layer may also be subjected to a planarization process to maintain a corresponding flatness on its surface.

[0101] like Fig.14 As shown, a passivation layer 240 is formed on the conductive layer 230. Specifically, it can be formed by the following steps: a patterned mask layer is formed on the back of the second silicon wafer, and then a passivation layer is deposited on the conductive layer in the hole using the mask layer as a mask. Then, the mask layer is removed, and the passivation layer is deposited on the back of the second silicon wafer. The material of the passivation layer can be silicon oxide or silicon carbon nitride.

[0102] refer to Fig.15 In the method for manufacturing an IGBT device provided in this embodiment, before manufacturing the field stop FS region on the back side of the first silicon wafer 100, chemical mechanical polishing is performed on the back side of the first silicon wafer 100. The first silicon wafer is polished to a thickness of 5-400μm. The first silicon wafer is bonded to the second silicon wafer, so it can be thinned by chemical mechanical polishing; at the same time, the degree to which the first silicon wafer can be thinned by the thinning process is improved, and a thinner first silicon wafer can be obtained, and finally a thinner IGBT device is obtained. In addition, the phenomenon of chip breakage caused by the thinning process is greatly reduced. The thinning process of the first silicon wafer does not require an additional wafer machine, saving the manufacturing cost of the IGBT device.

[0103] Next, refer to Fig.16 , a field stop FS region is formed on the back side of the first silicon wafer 100. In this embodiment, the field stop FS region is formed by implanting N-type ions on the back side of the first silicon wafer and subsequent high temperature diffusion. N-type ions, such as phosphorus (P), arsenic (As), antimony (Sb), sulfur (S) or selenium (Se), are implanted on the back side of the first silicon wafer.

[0104] Then, refer to Fig.17A collector P-type region is formed on the back of the first silicon wafer 100. Ion implantation of R-type impurities required for the collector is performed on the back of the first silicon wafer. Ion implantation of R-type impurities required for the collector is performed on the back of the first silicon wafer, such as boron (B), boron difluoride (BF2), and indium (In).

[0105] Next, low temperature annealing is performed to complete the diffusion of N-type impurities and P-type impurities. Adjust the temperature and time to diffuse the N-type impurities to the required thickness. Fig.18 , forming the field stop FS region 101 and the collector P-type region 102, and completing the activation of the N-type impurities and the Р-type impurities at the same time. The annealing temperature is selected between 300℃-600℃, and the annealing time is 0.5h-4h.

[0106] Then, refer to Fig.18 , a back metal process is performed on the back of the first silicon wafer 100 to form a back metal 150. The back metal 150 is deposited on the back of the first silicon wafer 100, that is, a back metal of aluminum (Al), titanium (Ti), nickel (Ni) and silver (Ag) is formed. The thickness of the back metal finally formed is 2000 angstroms to 8000 angstroms.

[0107] like Fig.18 and 19 As shown, the second embodiment of the present application provides an IGBT device, including:

[0108] A first silicon wafer 100, the back side of the first silicon wafer 100 from outside to inside sequentially comprises: a back side metal 150, a collector P-type region 102 and a field stop FS region 101, and the front side of the first silicon wafer from outside to inside sequentially comprises: an interlayer dielectric layer 120 and a MOSFET 110;

[0109] The second silicon wafer 200 has its front surface bonded to the front surface of the first silicon wafer 100 .

[0110] In this embodiment, the back side of the first silicon wafer can be ground to a thickness of 5-400 μm. In the IGBT device provided by the present application, a bond is formed between the first silicon wafer and the second silicon wafer, and the thickness of the first silicon wafer can be thinner, so the IGBT device can be made thinner. For example, for large-size IGBT devices (over 12 inches), the chip thickness can be reduced to less than 100 μm. Thinner IGBT devices can effectively solve the heat dissipation problem of high-power devices. At the same time, the field termination FS region and the collector P-type region manufacturing process performed on the back side of the first silicon wafer have higher stability.

[0111] In this embodiment, the back side of the second silicon wafer is ground to a thickness of 5-600 μm. The second silicon wafer can be a semiconductor substrate such as a silicon substrate, a silicon-containing substrate or a silicon-coated insulating substrate.

[0112] like Fig.18 and Fig.19As shown, a first metal layer 130 and a first hard mask 140 are sequentially formed on the front side of the first silicon wafer 100 and the interlayer dielectric layer 120; a first metal connection portion 121 is provided in the interlayer dielectric layer 120, and the first metal connection portion 121 is electrically connected to the first metal layer 130; a second metal connection portion 141 is provided in the first hard mask 140, and the second metal connection portion 141 is electrically connected to the first metal layer 130;

[0113] A second hard mask 210 is formed on the front side of the second silicon wafer 200 . A third metal connection portion 211 is formed in the second hard mask 210 . The third metal connection portion 211 is electrically connected to the second metal connection portion 141 .

[0114] The front side of the first silicon wafer is bonded to the front side of the second silicon wafer by aligning the second metal connection portion on the front side of the first silicon wafer with the third metal connection portion on the front side of the second silicon wafer and then bonding. In addition, a dielectric-to-dielectric bond can also be formed between the first hard mask and the second hard mask. Therefore, a metal-to-metal and dielectric-to-dielectric dual bond is formed on the front side of the first silicon wafer and the second silicon wafer.

[0115] The first hard mask and the second hard mask are formed of materials such as silicon nitride (SiN), silicon dioxide (SiO2), silicon carbide (SiC), aluminum nitride (AlN), aluminum oxide (AlO), etc. The first metal connection part, the second metal connection part and the third metal connection part are made of metal or metal compound, for example, copper (Cu), cobalt (Co), aluminum (Al), tungsten (W), titanium (Ti), titanium nitride (TiN), thallium (Ta), thallium nitride (TaN).

[0116] like Fig. 9 , 18 As shown in FIG. 19 , a hole 201 is opened on the back of the second silicon wafer 200 , and the hole 201 exposes the third metal connection portion 211 ; a conductive layer 230 is formed in the hole 201 and on the back of the second silicon wafer 200 ; and a passivation layer 240 is formed on the conductive layer 230 .

[0117] like Fig.19 As shown, a barrier layer 212 is provided on the sidewall of the hole 201 between the conductive layer 230 and the second silicon wafer 200. The barrier layer can improve the elimination of stress around the hole and reduce structural defects caused by stress.

[0118] like Fig.18 and Fig.19 As shown, outside the hole 201, a protective layer 220 is formed between the conductive layer 230 and the second silicon wafer 200. A protective layer 220 is deposited on the back of the second silicon wafer 200 to protect the covered second silicon wafer 200 from being etched again during the IGBT manufacturing process.

[0119] like Fig. 20 FIG. 1 is a flow chart of the steps of a method for manufacturing an IGBT device provided in an embodiment of the present application. The method comprises the following steps:

[0120] Providing a first silicon wafer, manufacturing a MOSFET on the front side of the first silicon wafer, depositing an interlayer dielectric layer on the MOSFET; forming a first metal connection portion in the interlayer dielectric layer; and forming a first metal layer on the interlayer dielectric layer;

[0121] forming a first hard mask on the first metal layer, and forming a second metal connection portion in the first hard mask;

[0122] Providing a second silicon wafer; depositing a second hard mask on the front side of the second silicon wafer;

[0123] forming a third metal connection in the second hard mask;

[0124] performing chemical mechanical polishing on the front side of the first silicon wafer;

[0125] Chemical mechanical polishing of the front side of the second silicon wafer

[0126] bonding the front side of the first silicon wafer to the front side of the second silicon wafer;

[0127] performing chemical mechanical polishing on the back side of the second silicon wafer;

[0128] forming a hole on the back side of the second silicon wafer;

[0129] Depositing a conductive layer on the back side of the second silicon wafer;

[0130] performing chemical mechanical polishing on the conductive layer;

[0131] depositing a passivation layer on the conductive layer;

[0132] performing chemical mechanical polishing on the back side of the first silicon wafer;

[0133] Implanting N-type ions required for the field stop FS region and P-type ions required for the collector P-type region on the back side of the first silicon wafer; then, annealing to form the field stop FS region and the collector P-type region;

[0134] A backside metal process is performed on the backside of the first silicon wafer.

[0135] like Fig.21 FIG. 1 is a flow chart of steps of a method for manufacturing an IGBT device provided by another embodiment of the present application. The method comprises the following steps:

[0136] Providing a first silicon wafer, manufacturing a MOSFET on the front side of the first silicon wafer, depositing an interlayer dielectric layer on the MOSFET; forming a first metal connection portion in the interlayer dielectric layer; and forming a first metal layer on the interlayer dielectric layer;

[0137] forming a first hard mask on the first metal layer, and forming a second metal connection portion in the first hard mask;

[0138] Providing a second silicon wafer; depositing a second hard mask on the front side of the second silicon wafer;

[0139] forming a third metal connection in the second hard mask;

[0140] performing chemical mechanical polishing on the front side of the first silicon wafer;

[0141] Chemical mechanical polishing of the front side of the second silicon wafer

[0142] bonding the front side of the first silicon wafer to the front side of the second silicon wafer;

[0143] performing chemical mechanical polishing on the back side of the first silicon wafer;

[0144] Implanting N-type ions required for the field stop FS region and P-type ions required for the collector P-type region on the back side of the first silicon wafer; then, annealing to form the field stop FS region and the collector P-type region;

[0145] Performing a back metal process on the back side of the first silicon wafer;

[0146] performing chemical mechanical polishing on the back side of the second silicon wafer;

[0147] forming a hole on the back side of the second silicon wafer;

[0148] Depositing a conductive layer on the back side of the second silicon wafer;

[0149] performing chemical mechanical polishing on the conductive layer;

[0150] A passivation layer is deposited on the conductive layer.

[0151] like Fig. 22 FIG. 1 is a flow chart of steps of a method for manufacturing an IGBT device provided by another embodiment of the present application. The method comprises the following steps:

[0152] Providing a first silicon wafer, manufacturing a MOSFET on the front side of the first silicon wafer, depositing an interlayer dielectric layer on the MOSFET; forming a first metal connection portion in the interlayer dielectric layer; and forming a first metal layer on the interlayer dielectric layer;

[0153] forming a first hard mask on the first metal layer, and forming a second metal connection portion in the first hard mask;

[0154] Providing a second silicon wafer; depositing a second hard mask on the front side of the second silicon wafer;

[0155] forming a third metal connection in the second hard mask;

[0156] performing chemical mechanical polishing on the front side of the first silicon wafer;

[0157] Chemical mechanical polishing of the front side of the second silicon wafer

[0158] bonding the front side of the first silicon wafer to the front side of the second silicon wafer;

[0159] performing chemical mechanical polishing on the back side of the first silicon wafer;

[0160] Implanting N-type ions required for the field stop FS region and P-type ions required for the collector P-type region on the back side of the first silicon wafer; then, annealing to form the field stop FS region and the collector P-type region;

[0161] performing chemical mechanical polishing on the back side of the second silicon wafer;

[0162] forming a hole on the back side of the second silicon wafer;

[0163] Depositing a conductive layer on the back side of the second silicon wafer;

[0164] performing chemical mechanical polishing on the conductive layer;

[0165] depositing a passivation layer on the conductive layer;

[0166] A backside metal process is performed on the backside of the first silicon wafer.

Claims

1. A method for manufacturing an IGBT device, characterized in that: The following steps are involved: Providing a first silicon wafer; Fabricate a MOSFET on the front side of the first silicon wafer, and deposit an interlayer dielectric layer on the MOSFET; forming a first metal connection portion in the interlayer dielectric layer; forming a first metal layer on the interlayer dielectric layer; forming a first hard mask on the first metal layer; forming a second metal connection in the first hard mask; Providing a second silicon wafer; Depositing a second hard mask on the front side of the second silicon wafer; forming a third metal connection in the second hard mask; Bonding the front side of the first silicon wafer to the front side of the second silicon wafer; Forming a field termination FS region on the back side of the first silicon wafer; Making a collector P-type region on the back side of the first silicon wafer; A back metal is formed on the back side of the first silicon wafer.

2. The method for manufacturing an IGBT device according to claim 1, characterized in that: Also includes: Performing chemical mechanical polishing on the back side of the second silicon wafer; forming a hole on the back side of the second silicon wafer to expose the third metal connection portion located in the second hard mask; Depositing a conductive layer on the back side of the second silicon wafer and in the hole; A passivation layer is formed on the conductive layer.

3. The method for manufacturing an IGBT device according to claim 1, wherein: Also includes: Performing chemical mechanical polishing on the back side of the second silicon wafer; forming a hole on the back side of the second silicon wafer to expose the third metal connection portion located in the second hard mask; forming a barrier layer along the sidewalls of the hole; removing the barrier layer at the bottom of the hole to expose the third metal connection portion; Depositing a conductive layer on the back side of the second silicon wafer and in the hole; A passivation layer is formed on the conductive layer.

4. The method for manufacturing an IGBT device according to claim 2 or 3, characterized in that: The back side of the second silicon wafer is ground to a thickness of 5-600 μm.

5. The method for manufacturing an IGBT device according to claim 1, wherein: Before forming the field stop FS region on the back side of the first silicon wafer, chemical mechanical polishing is performed on the back side of the first silicon wafer.

6. The method for manufacturing an IGBT device according to claim 5, characterized in that: The back side of the first silicon wafer is ground to a thickness of 5-400 μm.

7. The method for manufacturing an IGBT device according to claim 1, characterized in that: The second silicon wafer has a thickness of 40-800 μm.

8. The method for manufacturing an IGBT device according to claim 1, wherein: The bonding of the front side of the first silicon wafer to the front side of the second silicon wafer includes: aligning the second metal connection portion on the front side of the first silicon wafer and the third metal connection portion on the front side of the second silicon wafer for bonding.

9. The method for manufacturing an IGBT device according to claim 1, characterized in that: The front side of the first silicon wafer and the front side of the second silicon wafer are bonded by an annealing process, and the annealing conditions are: temperature below 600° C. and time from 30 minutes to 3 hours.

10. An IGBT device, characterized in that: include: A first silicon wafer, wherein the back side of the first silicon wafer has, from outside to inside: a back side metal, a collector P-type region, and a field stop FS region, and the front side of the first silicon wafer has, from outside to inside: an interlayer dielectric layer and a MOSFET; A first metal layer and a first hard mask are sequentially formed on the front side of the first silicon wafer and the interlayer dielectric layer; a first metal connection portion is provided in the interlayer dielectric layer, and the first metal connection portion is electrically connected to the first metal layer; a second metal connection portion is provided in the first hard mask, and the second metal connection portion is electrically connected to the first metal layer; A second silicon wafer, wherein a second hard mask is formed on the front side of the second silicon wafer, and a third metal connection portion is formed in the second hard mask; the third metal connection portion is electrically connected to the second metal connection portion; The front side of the second silicon wafer is bonded to the front side of the first silicon wafer.

11. The IGBT device according to claim 10, characterized in that: A hole is formed on the back of the second silicon wafer, and the hole exposes the third metal connecting portion; a conductive layer is formed in the hole and on the back of the second silicon wafer; A passivation layer is formed on the conductive layer.

12. The IGBT device according to claim 11, characterized in that: A barrier layer is also provided on the side wall of the hole and between the conductive layer and the second silicon wafer.

13. The IGBT device according to claim 11 or 12, characterized in that: Outside the hole, a protection layer is formed between the conductive layer and the second silicon wafer.

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