A method for obtaining network card information, a server board card, a device and a medium

Abstract

The application relates to the technical field of servers and discloses a method for acquiring network card information, a server board card, equipment and a medium, the method for acquiring network card information comprises the following steps: outputting a clock signal and a data loading enable signal to a network card through a complex programmable logic device, and reading a data signal sent by the network card by using the clock signal and the loading enable signal; processing the data signal sent by the network card through the complex programmable logic device, generating internal register data, and transmitting the internal register data to a baseboard management controller; and updating a log file based on the internal register data through the baseboard management controller; wherein the log file stores the data signal sent by the network card. The application enriches the read data signal sent by the network card, increases the flexibility and practicality of network card management, and reduces the difficulty of network card problem processing.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of servers, and particularly relates to a method for obtaining network card information, a server board card, equipment and a medium. BACKGROUND

[0002] In a server machine, a network card is an important component peripheral device for connecting the machine to the Internet, which improves the efficiency of data transmission between the server and the outside. The OCP 3.0 network card is increasingly widely used in the server field due to its direct plug-in characteristics without opening the case. The acquisition of the OCP network card state is crucial for the debugging and maintenance of the server.

[0003] However, the OCP network card state acquired by the related equipment is relatively single, which leads to inflexible management of the OCP card and increases the difficulty of OCP card problem processing. SUMMARY

[0004] Therefore, the present application provides a method for obtaining network card information, a server board card, equipment and a medium to solve the problem of single network card state acquired by the related equipment.

[0005] In a first aspect, the present application provides a method for obtaining network card information, which is applied to a server board card, the server board card comprising a complex programmable logic device and a baseboard management controller, the complex programmable logic device being connected with the network card, and the baseboard management controller being connected with the complex programmable logic device; the method comprising:

[0006] outputting a clock signal and a data load enable signal to the network card through the complex programmable logic device, reading the data signal sent by the network card by using the clock signal and the load enable signal, processing the data signal sent by the network card, generating internal register data, and transmitting the internal register data to the baseboard management controller;

[0007] updating a log file based on the internal register data through the baseboard management controller; wherein the log file stores network card information.

[0008] The method for obtaining network card information provided in the embodiment actively reads the data signal sent by the network card by using the clock signal and the load enable signal, enriches the obtained network card information, increases the flexibility and practicality of network card management, and reduces the difficulty of network card problem processing.

[0009] In an alternative embodiment, the complex programmable logic device comprises a data load enable signal control module, a clock generation module, a clock output enable module, a shift register module and a logic calculation module; wherein the clock output enable module is connected with the data load enable signal control module, the clock generation module and the shift register module respectively, and the shift register module is connected with the logic calculation module; the data signal sent by the network card is read by using the clock signal and the load enable signal, comprising:

[0010] The data load enable signal is output by the data load enable signal control module, and the data load enable signal is pulled up or pulled down to trigger the network card to load the data signal;

[0011] The clock signal is pulled up or pulled down by the clock output enable module within a preset signal period; wherein the clock signal is output by the clock generation module;

[0012] The bit value in the data signal sent by the network card is read by the shift register module, and the type of the in-place signal is determined based on the bit value;

[0013] The in-place signal is logically calculated by the logic calculation module to generate internal register data, and the internal register data is transmitted to the baseboard management controller.

[0014] The method for obtaining network card information provided in this embodiment directly accesses the network card by using the complex programmable logic device, obtains the bit value in the data signal sent by the network card and the type of the in-place signal, and can quickly detect and alarm the fault of the server board card.

[0015] In an alternative embodiment, the data load enable signal is output by the data load enable signal control module, and the data load enable signal is pulled up or pulled down to trigger the network card to load the data signal, comprising:

[0016] After obtaining the power-on signal of the network card, the data load enable signal control module pulls down the data load enable signal, generates a low pulse signal with a preset width, and then pulls up the data load enable signal to trigger the network card to load the data signal.

[0017] The method for obtaining network card information provided in this embodiment controls the data load enable signal, ensures that the output data load enable signal can trigger the network card to load the data signal, and ensures the integrity of the data signal sent by the network card.

[0018] In an alternative embodiment, the bit value in the data signal sent by the network card is read by the shift register module, and the type of the in-place signal is determined based on the bit value, comprising:

[0019] The shift register module starts reading the data signal sent by the network card when the clock signal output by the clock output enable module is at the rising edge, and ends reading the data signal sent by the network card when the clock signal is at the falling edge;

[0020] The shift register module reads the bit value in the data signal sent by the network card, and generates the type of the in-place signal based on the mapping relationship between the bit value and the in-place signal, wherein the type of the in-place signal includes the first network card in-place signal, the second network card in-place signal, the third network card in-place signal, the fourth network card in-place signal, the wake-up signal, the first network card overheating warning signal, the second network card overheating warning signal, and the network card fan request signal.

[0021] The method for obtaining network card information provided by the embodiment can orderly and completely read the data signal sent by the network card by pulling up and pulling down the clock signal, and can quickly and accurately obtain various in-place information and temperature warning information of the network card by using the mapping relationship between the bit value and the in-place signal.

[0022] In an optional implementation, the logic calculation module is used to perform logic calculation on the in-place signal to generate internal register data, and the internal register data is transmitted to the baseboard management controller, including:

[0023] The logic calculation module is used to perform logic AND calculation on the first network card in-place signal, the second network card in-place signal, the third network card in-place signal, and the fourth network card in-place signal to generate a total in-place signal;

[0024] The logic calculation module is used to generate internal register data based on the total in-place signal, the wake-up signal, the first network card overheating warning signal, the second network card overheating warning signal, and the network card fan request signal, and the internal register data is transmitted to the baseboard management controller.

[0025] The method for obtaining network card information provided by the embodiment uses the logic calculation module to perform logic calculation on the internal register information, thereby laying a foundation for the baseboard management controller to judge whether the network card is well connected.

[0026] In an optional implementation, the baseboard management controller is used to update a log file based on the internal register data, including:

[0027] The baseboard management controller is used to read the first network card overheating warning signal, the second network card overheating warning signal, and the network card fan request signal in the internal register data, and the baseboard management controller is used to update a log file based on the first network card overheating warning signal, the second network card overheating warning signal, and the network card fan request signal;

[0028] The first network card overheating warning signal and the second network card overheating warning signal are determined as network card overheating warning levels by the baseboard management controller, and the fan rotating speed is controlled based on the overheating warning levels.

[0029] The method for obtaining network card information provided in the embodiment can further record logs and manage heat dissipation based on the obtained internal register data, so that the network card can be regulated in time, and normal operation of the server is ensured.

[0030] In an optional embodiment, the internal register data is used to update the log file by the baseboard management controller, and the method further includes:

[0031] The baseboard management controller reads the overall in-place signal in the internal register data, and judges the connection state of the network card based on the level state of the overall in-place signal.

[0032] The method for obtaining network card information provided in the embodiment can further record logs and manage heat dissipation based on the obtained internal register data, so that the network card can be regulated in time, and normal operation of the server is ensured.

[0033] In a second aspect, the present application provides a server board card, which includes:

[0034] The complex programmable logic device is connected with the network card, and is used to output a clock signal and a data loading enable signal to the network card, read data signals sent by the network card by using the clock signal and the loading enable signal, and process the data signals sent by the network card to generate internal register data.

[0035] The baseboard management controller is connected with the complex programmable logic device, and is used to update a log file based on the internal register data; wherein the log file stores network card information.

[0036] In a third aspect, the present application provides a computer device, which includes a memory and a processor, the memory and the processor are communicatively connected with each other, the memory stores computer instructions, and the processor executes the computer instructions to perform the method for obtaining network card information according to the first aspect or any one of the corresponding embodiments.

[0037] In a fourth aspect, the present application provides a computer readable storage medium, which stores computer instructions, and the computer instructions are used to make a computer execute the method for obtaining network card information according to the first aspect or any one of the corresponding embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the specific embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the specific embodiments or prior art description. Obviously, the drawings described below are some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor on the basis of these drawings.

[0039] Figure 1 is a connection block diagram of an OCP3.0 network card and a mainboard according to the related art;

[0040] Figure 2 is a flowchart of a method for obtaining network card information according to an embodiment of the present application;

[0041] Figure 3 is a hardware connection block diagram of data signal reading of network card sending by CPLD according to an embodiment of the present application;

[0042] Figure 4 is a structural block diagram of a complex programmable logic device according to an embodiment of the present application;

[0043] Figure 5 is a flowchart of another method for obtaining network card information according to an embodiment of the present application;

[0044] Figure 6 is a data signal analysis timing diagram of network card sending according to an embodiment of the present application;

[0045] Figure 7 is a flowchart of still another method for obtaining network card information according to an embodiment of the present application;

[0046] Figure 8 is a hardware structure schematic diagram of a computer device of an embodiment of the present application. DETAILED DESCRIPTION

[0047] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the following will combine the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the protection scope of the present application.

[0048] The embodiments of the present application are applied to the application scenarios of network card control access, such as Figure 1As shown, the in-situ signals (PRSNTB0~3_N) of the OCP3.0 card in the related art are transmitted to the mainboard through the connector between the card and the mainboard, and then the overall in-situ signal OCP_PSNT_N is generated on the mainboard through a logic and gate chip and then transmitted to the CPLD (Complex Programmable Logic Device) and the BMC (Baseboard Manager Controller), that is, if one of the four signals is low, then the OCP_PSNT_N is low. At the same time, the BMC on the mainboard accesses the card through the SMBus (System Management Bus) to obtain the card temperature and other information, and performs unified case heat dissipation management.

[0049] The in-situ signals (PRSNTB0~3_N) are located at different positions of the connector between the OCP3.0 card and the mainboard, and can indicate the connection status of different positions. If the card is inserted obliquely, for example, PRSNTB0_N and PRSNTB1_N are low, and PRSNTB2_N is high, then the OCP_PSNT_N is still low, and the mainboard end cannot detect this fault.

[0050] Moreover, the BMC can only obtain the card temperature information through the SMBus, and cannot obtain the temperature alarm and heat dissipation demand information on the card, causing heat dissipation regulation lag.

[0051] According to the embodiment of the present application, a method for obtaining card information is provided. It should be noted that the steps shown in the flowchart of the drawings can be executed in a computer system such as a group of computer executable instructions, and although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0052] In the embodiment, a method for obtaining card information is provided, which is applied to a server card, the server card comprising a CPLD (Complex Programmable Logic Device) and a BMC (Baseboard Manager Controller), the CPLD is connected with a card, and the BMC is connected with the CPLD, Figure 2 As shown in the flowchart of the method for obtaining card information according to the embodiment of the present application, the flowchart comprises the following steps: Figure 2 As shown in the flowchart of the method for obtaining card information according to the embodiment of the present application, the flowchart comprises the following steps:

[0053] In step S201, the complex programmable logic device 1 outputs a clock signal and a data load enable signal to the network card 3. The clock signal and the load enable signal are used to read the data signal sent by the network card 3, and the data signal sent by the network card 3 is processed to generate internal register data. The internal register data is then transmitted to the baseboard management controller 2.

[0054] In this embodiment, the network card 3 is, for example, an OCP card, such as an OCP3.0 network card. The OCP3.0 network card includes a series of OCP cards of version 3.0, which have advantages over the OCP2.0 network card, such as supporting remote direct data access, low CPU load, and high network throughput.

[0055] Specifically, such as Figure 3 As shown, the CPLD uses CLK (clock signal), LD_N (data load enable signal), and DATA_N (data signal) signals to connect to network card 3 and acts as the MASTER to drive this set of signals and read OCP information; where CLK is the clock signal sent by the CPLD, LD_N is the data load enable signal sent by the CPLD, and DATA_N is the data signal sent by network card 3.

[0056] Furthermore, based on the read presence information (i.e., the data signal sent by network card 3), the CPLD sends the OCP_PSNT_N signal (overall presence signal) to the BMC according to the original motherboard's AND logic, thus ensuring compatibility with the existing BMC detection process.

[0057] Furthermore, the CPLD generates internal register data based on the data signal sent by the network card 3, which is then read by the BMC via the I2C bus (Inter-Integrated Circuit).

[0058] Step S202: Update the log file through the baseboard management controller 2 based on the internal register data; wherein, the log file stores network card information.

[0059] This embodiment provides a method for obtaining network card information. By outputting a clock signal and a data load enable signal to the network card through a CPLD, the method actively reads the data signals sent by the network card using the clock signal and the load enable signal. While retaining the functionality of existing solutions, this method reduces the number of traces on the PCB and the use of logic AND gate chips, thereby reducing hardware costs. Furthermore, it can obtain more data signals sent by the network card than existing solutions, increasing the flexibility and practicality of network card management and reducing the difficulty of handling network card problems.

[0060] This embodiment provides a method for obtaining network card information, such as... Figure 4As shown, the complex programmable logic device 1 described above includes a data load enable signal control module 4, a clock generation module 5, a clock output enable module 6, a shift register module 7, and a logic calculation module 8; wherein, the clock output enable module 6 is connected to the data load enable signal control module 4, the clock generation module 5, and the shift register module 7, respectively, and the shift register module 7 is connected to the logic calculation module 8. Figure 5 This is a flowchart of a method for obtaining network interface card (NIC) information according to an embodiment of the present invention, such as... Figure 5 As shown, the process includes the following steps:

[0061] In step S501, the complex programmable logic device 1 outputs a clock signal and a data load enable signal to the network card 3. The clock signal and the load enable signal are used to read the data signal sent by the network card 3, and the data signal sent by the network card 3 is processed to generate internal register data. The internal register data is then transmitted to the baseboard management controller 2.

[0062] Specifically, step S201 includes:

[0063] Step S5011: The data loading enable signal is output by the data loading enable signal control module 4, and the data loading enable signal is pulled high or low to trigger the network card 3 to load the data signal.

[0064] Specifically, after receiving the power-on signal of the network card 3, the data loading enable signal control module 4 pulls the data loading enable signal low, generates a low pulse signal of preset width, and then pulls the data loading enable signal high to trigger the network card 3 to load the data signal.

[0065] Furthermore, such as Figure 6 As shown, in the initial state, LD_N is high level, CLK is low level, and the clock period output by clock generation module 5 is T.

[0066] Furthermore, after the network card 3 is powered on, the data loading enable signal control module 4 pulls LD_N low to generate a low pulse signal with a pulse width of T (i.e., the preset width) and then pulls it high to trigger the network card 3 to load the latest status information (i.e., the data signal sent by the network card 3); during the period when LD_N is pulled low, the CLK signal remains at a low level.

[0067] In step S5012, within a preset signal period, the clock signal is pulled high or pulled low by the clock output enable module 6; wherein, the clock signal is output by the clock generation module 5.

[0068] Step S5013: Read the bit values ​​in the data signal sent by the network card 3 through the shift register module 7, and determine the type of the signal in place based on the bit values.

[0069] In some optional embodiments, the step S2013 comprises:

[0070] Step a1, the shift register module 7 starts reading the data signal sent by the network card 3 when the clock signal output by the clock output enable module 6 is at the rising edge, and ends reading the data signal sent by the network card 3 when the clock signal is at the falling edge.

[0071] Specifically, the step of reading the data signal sent by the network card 3 is as follows: after the data load enable signal LD_N is at the rising edge, after T / 2, the clock output enable module 6 pulls up CLK to generate a rising edge, and the network card 3 sends internal data to the DATA_IN signal at the rising edge of CLK, and after T / 2, the CPLD pulls down CLK to generate a falling edge, at this time, the data sent by the network card 3 to the DATA_IN signal has been stable, and the shift register module 7 samples the data on the DATA_IN signal line as the highest bit Bit7 (bit value is 7) in a frame of data.

[0072] Further, the above steps are repeated 8 times, that is, 8 CLKs are generated in turn, and Bit7-Bit0 are received in turn.

[0073] Further, at the falling edge of the 8th CLK, the CPLD generates an LD_N signal low pulse signal again while completing the Bit0 data reception, and repeats the steps S5011-S5013 to start the latest reading of the data signal sent by the network card 3.

[0074] Step a2, the shift register module 7 reads the bit value in the data signal sent by the network card 3, and generates the type of in-place signal based on the mapping relationship between the bit value and the in-place signal; wherein the type of in-place signal includes the first network card in-place signal, the second network card in-place signal, the third network card in-place signal, the fourth network card in-place signal, the wake-up signal, the first network card overheat warning signal, the second network card overheat warning signal and the network card fan request signal.

[0075] Specifically, the mapping relationship between the bit value and the in-place signal is shown in Table 1 as follows:

[0076] Table 1:

[0077]

[0078] In Table 1, Bit0-Bit3 correspond to the in-place signals PRSNTB0_N-PRSNTB3_N (i.e. the first in-place signal to the fourth in-place signal) of the network card respectively; WAKE_N represents a wake-up signal, which is used to wake up the mainboard and provide power supply for the network card 3 by the mainboard; TEMP_WARN_N represents a first network card overheat warning signal, when the signal is valid (i.e. the signal is in a low level state), the network card 3 is used at a reduced frequency; TEMP_CRIT_N represents a second network card overheat warning signal, the overheat level is higher than TEMP_WARN_N, when the signal is valid, the network card 3 should be stopped and the power supply of the network card 3 should be turned off; FAN_ON_AUX represents a network card fan request signal, when the signal is valid (i.e. the signal is in a low level state), the network card 3 is provided with a fan for heat dissipation during shutdown.

[0079] In the optional embodiment, the CPLD is used to directly access the network card, to obtain the in-place information and temperature warning information of the network card 3, and to rely on the advantage of parallel processing of the internal module of the CPLD to quickly respond to the heat dissipation warning.

[0080] In step S5014, the logic calculation module 8 is used to perform logic calculation on the in-place signals to generate internal register data, and the internal register data is transmitted to the baseboard management controller 2.

[0081] In some optional embodiments, the step S5014 includes:

[0082] In step b1, the logic calculation module 8 is used to perform logic AND calculation on the first in-place signal, the second in-place signal, the third in-place signal and the fourth in-place signal of the network card to generate a total in-place signal.

[0083] Specifically, according to the following logic, the OCP_PSNT_N signal (i.e. the total in-place signal) is sent to the BMC for compatibility with the original in-place detection process of the BMC:

[0084] OCP_PSNT_N

[0085] = PRSNTB0_N && PRSNTB1_N && PRSNTB2_N && PRSNTB3_N

[0086] For example, when PRSNTB0_N, PRSNTB1_N, PRSNTB2_N and PRSNTB3_N are all low (i.e. 0), OCP_PSNT_N is 0; when PRSNTB0_N, PRSNTB1_N, PRSNTB2_N and PRSNTB3_N are all high (i.e. 1), OCP_PSNT_N is 1; when PRSNTB0_N, PRSNTB1_N, PRSNTB2_N and PRSNTB3_N have both low and high, OCP_PSNT_N is 0.

[0087] In step b2, the logic calculation module 8 generates internal register data based on the overall in-place signal, the wake-up signal, the first network card overheating warning signal, the second network card overheating warning signal and the network card fan request signal, and sends the internal register data to the baseboard management controller 2.

[0088] In the above optional embodiment, the logic calculation module is used to perform logic calculation on the internal register information, which lays a foundation for the baseboard management controller to determine whether the network card 3 is well connected.

[0089] In step S502, the baseboard management controller 2 updates a log file based on the internal register data; wherein the log file stores network card information. For details, please refer to Figure 2 The step S202 of the embodiment shown will not be repeated here.

[0090] The method for obtaining network card information provided in the embodiment uses the CPLD to directly access the network card, obtains various in-place information and temperature warning information of the network card, and relies on the advantage of parallel processing of the internal module of the CPLD to quickly respond to the heat dissipation warning.

[0091] In the embodiment, a method for obtaining network card information is provided, which can be used in a complex programmable logic device 1 including a data loading enable signal control module 4, a clock generation module 5, a clock output enable module 6, a shift register module 7 and a logic calculation module 8; wherein the clock output enable module 6 is connected with the data loading enable signal control module 4, the clock generation module 5 and the shift register module 7 respectively, the shift register module 7 is connected with the logic calculation module 8, Figure 7 is a flowchart of a method for obtaining network card information according to an embodiment of the application, as shown in the figure, the flowchart includes the following steps: Figure 7

[0092] ​Step S701, output clock signal and data load enable signal to the network card 3 through the complex programmable logic device 1, read the data signal sent by the network card 3 using the clock signal and the load enable signal, and process the data signal sent by the network card 3 to generate internal register data, and transmit the internal register data to the baseboard management controller 2. For details, please refer to Figure 5 Step S501 of the embodiment shown will not be described here.

[0093] Step S702, based on the internal register data, update the log file through the baseboard management controller 2; wherein the log file stores network card information.

[0094] Specifically, the above step S702 includes:

[0095] Step S7021, read the first network card overheating warning signal, the second network card overheating warning signal and the network card fan request signal in the internal register data through the baseboard management controller 2.

[0096] Step S7022, based on the first network card overheating warning signal, the second network card overheating warning signal and the network card fan request signal, update the log file through the baseboard management controller 2.

[0097] Specifically, after reading the above TEMP_WARN_N, TEMP_CRIT_N and FAN_ON_AUX through the BMC, record them in the log file of the BMC.

[0098] Further, the baseboard management controller 2 determines the network card overheating warning level of the first network card overheating warning signal and the second network card overheating warning signal respectively, and controls the fan speed based on the overheating warning level.

[0099] Further, according to FAN_ON_AUX, it is judged whether to start fan control when shutting down, and according to TEMP_WARN_N and TEMP_CRIT_N signals, the different speeds of the fan are controlled according to the different overheating warning levels.

[0100] Further, the baseboard management controller 2 reads the overall in-place signal in the internal register data, and judges the connection state of the network card 3 based on the level state of the overall in-place signal.

[0101] Further, when OCP_PSNT_N is 1, it indicates that the server board card is not connected with the network card 3; when OCP_PSNT_N is 0, it indicates that the server board card is connected with the network card 3, and further, when PRSNTB0_N-PRSNTB3_N are all low, it indicates that the contact with the network card 3 is good, when PRSNTB0_N-PRSNTB3_N have both high and low, it indicates that the contact with the network card 3 is poor, and when PRSNTB0_N-PRSNTB3_N are all high, it indicates that there is no contact with the network card 3.

[0102] The method for obtaining network card information provided in the embodiment can make further log recording, heat dissipation management and contact good judgment according to the obtained internal register data, can timely regulate and control the network card, and ensures the normal operation of the server.

[0103] The method for obtaining network card information is described below through a specific embodiment.

[0104] Embodiment 1

[0105] 1) In the initial state, LD_N is high and CLK is low. The period of the clock is set as T.

[0106] 2) Data reading starts, the CPLD pulls down LD_N, generates a low pulse with a pulse width of T, and then pulls up, triggering the OCP to load the latest state information once. During the period of pulling down LD_N, the CLK signal remains low.

[0107] 3) After T / 2, the CPLD pulls up CLK, generates a rising edge, and the OCP card sends the internal data to the DATA_IN signal on the rising edge of CLK. After T / 2, the CPLD pulls down CLK, generates a falling edge, at this time, the data sent by the OCP card to the DATA_IN signal has been stable, and the CPLD samples the data on the DATA_IN signal line as the highest bit Bit7 in a frame of data.

[0108] 4) The CPLD repeats step 3) for 8 times, that is, generates 8 CLKs in turn, and receives Bit7-Bit0 in turn.

[0109] 5) On the falling edge of the 8th CLK, the CPLD completes the reception of bit0 data, and re-generates the LD_N signal low pulse signal, repeats steps 2)-4), and starts to read new data.

[0110] 6) In a frame of data, Bit0~Bit3, respectively corresponding to OCP card in-signal PRSNTB0_N~PRSNTB3_N, CPLD controls output OCP_PSNT_N signal to send to BMC according to the following logic, for compatibility with the original BMC OCP card in-signal detection process.

[0111] OCP_PSNT_N

[0112] = PRSNTB0_N && PRSNTB1_N && PRSNTB2_N && PRSNTB3_N

[0113] At the same time, send the 4bit data through I2C interface to internal register data for BMC to judge whether the OCP card is well connected.

[0114] 7) In a frame of data, Bit5~Bit7 for OCP card temperature alarm and heat request signal, CPLD generates I2C interface internal register data for BMC to read for the judgment and log record of the whole machine heat control.

[0115] 8) After BMC reads the above temperature alarm and heat request signal, record it to the BMC log file, and judge whether to start the fan control when shutting down according to the FAN_ON_AUX, and control the different speed of the fan according to the TEMP_WARN_N and TEMP_CRIT_N signal to judge the different levels of overheat alarm.

[0116] In the embodiment, a server board card is also provided, which is used to implement the above embodiments and preferred embodiments, and has been described above. As used below, the term "module" can be a combination of software and / or hardware that implements a predetermined function. Although the apparatus described in the following embodiments is preferably implemented in software, hardware, or a combination of software and hardware is also possible and contemplated.

[0117] The embodiment provides a server board card, as shown in the following formula: Figure 3 The server board card comprises:

[0118] A complex programmable logic device 1 is connected with a network card 3, used to output clock signal and data load enable signal to the network card, read data signal sent by the network card 3 by using the clock signal and the load enable signal, and process the data signal sent by the network card 3 to generate internal register data.

[0119] A baseboard management controller 2 is connected with the complex programmable logic device 11, used to update a log file based on the internal register data; wherein the log file stores network card information.

[0120] In some optional implementations, the complex programmable logic device 1 includes: a data load enable signal control module 4, a clock generation module 5, a clock output enable module 6, a shift register module 7, and a logic calculation module 8; wherein the clock output enable module 6 is connected to the data load enable signal control module 4, the clock generation module 5, and the shift register module 7, respectively, and the shift register module 7 is connected to the logic calculation module 8.

[0121] Further functional descriptions of the above modules and units are the same as those in the corresponding embodiments described above, and will not be repeated here.

[0122] In this embodiment, the device for acquiring data signals sent by the network card 3 is presented in the form of a functional unit. Here, a unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that execute one or more software or fixed programs, and / or other devices that can provide the above-mentioned functions.

[0123] This invention also provides a computer device having the above-described features. Figure 3 The image shows a server board.

[0124] Please see Figure 8 , Figure 8 This is a schematic diagram of the structure of a computer device provided in an optional embodiment of the present invention, such as... Figure 8 As shown, the computer device includes one or more processors 10, memory 20, and interfaces for connecting the components, including high-speed interfaces and low-speed interfaces. The components communicate with each other via different buses and can be mounted on a common motherboard or otherwise installed as needed. The processors can process instructions executed within the computer device, including instructions stored in or on memory to display graphical information of a GUI on external input / output devices (such as display devices coupled to the interfaces). In some alternative implementations, multiple processors and / or multiple buses can be used with multiple memories and multiple memory modules, if desired. Similarly, multiple computer devices can be connected, each providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system). Figure 8 Take a processor 10 as an example.

[0125] The processor 10 can be a central processing unit, a network processing unit, or a combination thereof. The processor 10 can further include a hardware chip. The hardware chip can be an application specific integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device can be a complex programmable logic device, a field programmable logic gate array, a generic array logic, or any combination thereof.

[0126] The memory 20 stores instructions executable by the at least one processor 10 to cause the at least one processor 10 to perform the methods illustrated in the above embodiments.

[0127] The memory 20 can include a program storage area and a data storage area. The program storage area can store an operating system and application programs required by at least one function. The data storage area can store data created according to the use of the computer device, and the like. In addition, the memory 20 can include a high-speed random access memory, and can further include a non-transitory memory, such as at least one magnetic disk storage device, a flash memory device, or other non-transitory solid-state memory device. In some alternative embodiments, the memory 20 can optionally include a memory disposed remotely from the processor 10, which can be connected to the computer device through a network. Examples of the network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and a combination thereof.

[0128] The memory 20 can include a volatile memory, such as a random access memory, and can also include a non-volatile memory, such as a flash memory, a hard disk, or a solid state disk. The memory 20 can further include a combination of the above-mentioned types of memories.

[0129] The computer device further includes an input device 30 and an output device 40. The processor 10, the memory 20, the input device 30, and the output device 40 can be connected by a bus or other means, Figure 8 For example, by a bus connection.

[0130] The input device 30 can receive input digital or character information, and generate key signal inputs related to the user settings and function controls of the computer device, such as a touch screen, a keypad, a mouse, a trackpad, a touchpad, a pointing stick, one or more mouse buttons, a trackball, a joystick, and the like. The output device 40 can include a display device, an auxiliary lighting device (e.g., an LED), a tactile feedback device (e.g., a vibration motor), and the like. The display device includes, but is not limited to, a liquid crystal display, a light emitting diode, a display, and a plasma display. In some alternative embodiments, the display device can be a touch screen.

[0131] The embodiments of the present application further provide a computer readable storage medium, and the method according to the embodiments of the present application can be implemented in hardware, firmware, or recorded in a storage medium, or be implemented as computer codes stored in a remote storage medium or a non-transitory machine readable storage medium and downloaded through a network and stored in a local storage medium, so that the method described herein can be processed by such software on a storage medium using a general purpose computer, a special purpose processor, or programmable or special hardware. The storage medium can be a magnetic disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk, or a solid state disk, etc. Further, the storage medium can also include a combination of the above-mentioned types of memories. It can be understood that the computer, the processor, the microprocessor controller, or the programmable hardware includes a storage component that can store or receive software or computer codes, when the software or computer codes are accessed and executed by the computer, the processor, or the hardware, the method shown in the above embodiments is implemented.

[0132] Although the embodiments of the present application are described in conjunction with the accompanying drawings, various modifications and changes can be made by those skilled in the art without departing from the spirit and scope of the present application, and such modifications and changes fall within the scope defined by the appended claims.

Claims

1. A method for obtaining network card information, the method comprising: The application is applied to a server board card, the server board card includes a complex programmable logic device and a baseboard management controller, the complex programmable logic device and a network card are connected, the baseboard management controller and the complex programmable logic device are connected;The method comprises: Through the complex programmable logic device, a clock signal and a data load enable signal are output to the network card, the clock signal and the load enable signal are used to read the data signal sent by the network card, the data signal sent by the network card is processed, internal register data is generated, and the internal register data is transmitted to the baseboard management controller; Based on the internal register data, the baseboard management controller updates a log file;Wherein, the log file stores network card information; The complex programmable logic device includes a data load enable signal control module, a clock generation module, a clock output enable module, a shift register module and a logic calculation module;Wherein, the clock output enable module is connected with the data load enable signal control module, the clock generation module and the shift register module respectively, and the shift register module is connected with the logic calculation module;The clock signal and the data load enable signal are output to the network card through the complex programmable logic device, the clock signal and the load enable signal are used to read the data signal sent by the network card, the data signal sent by the network card is processed, internal register data is generated, and the internal register data is transmitted to the baseboard management controller, which comprises: The data load enable signal is output through the data load enable signal control module, and the data load enable signal is pulled up or pulled down to trigger the network card to load the data signal; Within a preset signal period, the clock signal is pulled up or pulled down through the clock output enable module;Wherein, the clock signal is output through the clock generation module; The bit value in the data signal sent by the network card is read through the shift register module, and the type of in-bit signal is determined based on the bit value; The in-bit signal is logically calculated through the logic calculation module, the internal register data is generated, and the internal register data is transmitted to the baseboard management controller; The bit value in the data signal sent by the network card is read through the shift register module, and the type of in-bit signal is determined based on the bit value, which comprises: When the clock signal output by the clock output enable module is at the rising edge, the shift register module starts to read the data signal sent by the network card, and when the clock signal is at the falling edge, the shift register module ends to read the data signal sent by the network card. The shift register module reads the bit value of the data signal sent by the network card, and generates the type of the in-bit signal based on the bit value by using the mapping relationship between the bit value and the in-bit signal; wherein, the type of the in-bit signal includes the first network card in-bit signal, the second network card in-bit signal, the third network card in-bit signal, the fourth network card in-bit signal, the wake-up signal, the first network card overheat warning signal, the second network card overheat warning signal and the network card fan request signal.

2. The method of claim 1, wherein, The data load enable signal control module outputs the data load enable signal and performs pull-up operation or pull-down operation on the data load enable signal to trigger the network card to load the data signal, including: After the data load enable signal control module obtains the power-on signal of the network card, it pulls down the data load enable signal, generates a low pulse signal with a preset width, and then pulls up the data load enable signal to trigger the network card to load the data signal.

3. The method of claim 1, wherein, The logic calculation module performs logic calculation on the in-bit signal to generate the internal register data and transmits the internal register data to the baseboard management controller, including: The logic calculation module performs logic AND calculation on the first network card in-bit signal, the second network card in-bit signal, the third network card in-bit signal and the fourth network card in-bit signal to generate the overall in-bit signal; The logic calculation module generates the internal register data based on the overall in-bit signal, the wake-up signal, the first network card overheat warning signal, the second network card overheat warning signal and the network card fan request signal, and sends the internal register data to the baseboard management controller.

4. The method of claim 3, wherein, The baseboard management controller updates the log file based on the internal register data, including: The baseboard management controller reads the first network card overheat warning signal, the second network card overheat warning signal and the network card fan request signal in the internal register data; The baseboard management controller updates the log file based on the first network card overheat warning signal, the second network card overheat warning signal and the network card fan request signal.

5. The method of claim 3, wherein, Further comprising: The baseboard management controller determines the network card overheat warning level of the first network card overheat warning signal and the second network card overheat warning signal respectively, and controls the fan speed based on the overheat warning level.

6. A server board card for implementing the method of obtaining network card information according to any one of claims 1 to 5, characterized in that, Comprise: A complex programmable logic device connected with the network card, used to output clock signal and data load enable signal to the network card, read the data signal sent by the network card by using the clock signal and the load enable signal, and process the data signal sent by the network card to generate internal register data; A baseboard management controller connected with the complex programmable logic device, used to update the log file based on the internal register data; wherein, the log file stores network card information; The complex programmable logic device comprises a data loading enable signal control module, a clock generation module, a clock output enable module, a shift register module and a logic calculation module; wherein the clock output enable module is connected with the data loading enable signal control module, the clock generation module and the shift register module respectively, and the shift register module is connected with the logic calculation module.

7. A computer device, characterized by Comprise: A memory and a processor, which are connected in communication with each other, and the memory stores computer instructions, and the processor executes the computer instructions to perform the method for acquiring network card information according to any one of claims 1 to 5.

8. A computer-readable storage medium, characterized in that, The computer readable storage medium stores computer instructions, and the computer instructions are used to make the computer execute the method for acquiring network card information according to any one of claims 1 to 5.

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