Patch adhesive and patching process thereof

Abstract

The present application belongs to the technical field of packaging process, and particularly relates to a patch adhesive and a patch process thereof. The patch adhesive comprises the following components in percentage by weight: solvent 20-70%, resin 1-20%, and activator 20-70%. The patch adhesive prepared by the present application has good adhesive force and wettability, and the prepared adhesive has the characteristics of complete volatilization and decomposition at low temperature (220 DEG C), and will not remain on the adhesive surface, thereby avoiding the adverse effects on the conductivity, thermal conductivity, shear strength and reliability of metal bonding. The application of the patch adhesive in the patch process of the joining technology can effectively expand the volatilization channel of the nano sintering paste, and realize the improvement of the conductivity, thermal conductivity, shear strength and reliability of metal bonding.

Description

Technical Field

[0001] This invention belongs to the field of packaging technology, specifically relating to a surface mount adhesive and its surface mount process. Background Technology

[0002] Electronic interconnects, as crucial components in electronic devices, play multiple roles including signal transmission, heat dissipation, mechanical support, and environmental protection, significantly impacting the performance of the entire electronic circuit and device. With the rise of wide-bandgap semiconductors such as SiC and GaN, the power density and operating temperature of power electronic modules are continuously increasing, placing ever higher demands on the reliability of electronic interconnects. Currently, traditional soft soldering processes have reached their application limits, necessitating the replacement with new packaging processes and materials. The creep temperature of traditional solder is generally below 120℃; if the application temperature exceeds 150-200℃, the performance of its interconnect layer degrades drastically, affecting the reliability and lifespan of the module.

[0003] As a highly reliable interconnect technology, sintered nano-paste (adhesive) technology, represented by sintered silver nanoparticles, has promising application prospects in third-generation semiconductors, such as SiC. In the early 1990s, researchers developed sintered silver nanoparticle interconnect technology. This process involves the interdiffusion of atoms on the surface of silver nanoparticles under relatively low temperature and pressure, forming a dense silver layer. The sintered silver layer exhibits excellent thermal and electrical conductivity, and its high melting point of 961℃ significantly improves its reliability. Furthermore, the sintering temperature is similar to that of traditional solders, and its lead-free nature makes it particularly environmentally friendly. Current methods for interconnecting electronic devices / substrates using sintered silver / copper nanoparticles generally employ dry-mount and wet-mount processes. The dry-mount process involves four steps: printing nano-paste onto the substrate / heat sink, drying the nano-paste, pre-attaching the electronic device to the dried nano-paste, and sintering the metal bond using a sintering machine. However, this method, which involves pre-attaching the electronic device to the dried nano-paste, suffers from low reliability and issues such as easy detachment or displacement. The wet mount process involves pre-bonding bare chips / devices or substrates using the adhesive properties of the nano-sintering paste before baking, and then placing the pre-bonded electronic devices in an oven for baking. However, because the devices cover the surface of the nano-paste, the solvent evaporation channels in the nano-paste are drastically reduced, and a large amount of solvent is trapped inside the paste, beneath the devices or substrate, forming numerous voids. This leads to reduced sintered interconnect strength, decreased electrical and thermal conductivity, and other performance degradation after sintering. Therefore, there is an urgent need to develop a mounting method that can effectively reduce the mounting pressure requirements of the pick-and-place machine, reduce sintering voids, and improve interconnect performance. Summary of the Invention

[0004] This invention aims to provide a patch adhesive and its patching process. The patch adhesive prepared by this invention has good adhesion and wettability. When applied to the patching process, it can effectively expand the volatilization channels of the nano-sintering paste, thereby improving the conductivity, thermal conductivity, shear strength, and reliability of the metal bond. At the same time, the patch adhesive prepared by this invention has the characteristic of complete volatilization and decomposition at low temperature (220℃), and will not remain on the bonding surface, thus avoiding adverse effects on the conductivity, thermal conductivity, shear strength, and reliability of the metal bond.

[0005] To achieve the above objectives, the present invention adopts the following technical solution: a patch adhesive comprising the following components by weight percentage: solvent 20-70%, resin 1-20%, and activator 20-70%.

[0006] Preferably, the patch adhesive comprises the following components by weight percentage: solvent 40-60%, resin 5-10%, and activator 30-55%.

[0007] The adhesive of this invention is suitable for patches of different sizes, but it is more effective for large-area patches.

[0008] Preferably, the solvent includes at least one selected from butyl acetate, tetrahydrofurfuryl alcohol, terpineol, butyl ether, and diethyl ether.

[0009] Preferably, the solvent is butyl acetate and terpineol, and the content ratio of butyl acetate to terpineol is 1:1.

[0010] Preferably, the resin includes at least one selected from polyvinylpyrrolidone, polyvinyl alcohol, ethyl cellulose, cellulose acetate, and carboxymethyl cellulose.

[0011] Preferably, the activator includes at least one of hexamethyldisiloxane, octamethylcyclotetrasiloxane, decamethylcyclopentasiloxane, and dodecylcyclohexasiloxane.

[0012] A patch mounting process using the aforementioned patch adhesive includes the following steps:

[0013] S1. Print nano-sintering paste onto the substrate / heat sink;

[0014] S2. Dry the substrate / heat sink containing the nano sintering paste;

[0015] S3. Apply the patch adhesive to the back of the bare chip / device or substrate, and then bond it to the substrate / heat sink obtained in step S2 to complete the pre-bonding.

[0016] S4. Sinter the pre-bonded products to complete the mechanical and electrical interconnection.

[0017] Preferably, the drying temperature in step S2 is 80-140°C, and the drying time is 0.1-2 hours.

[0018] Preferably, the adhesive coating thickness of the patch adhesive in step S3 is 1-20 μm.

[0019] Preferably, the bonding temperature in step S3 is 120-140°C, and the bonding pressure is 5-100 kg.

[0020] The sintering step in the patch process of this invention is applicable to all sintering processes on the market.

[0021] Compared with the prior art, the present invention has the following beneficial effects:

[0022] (1) Through the interaction between the components, the present invention can effectively improve the wettability and adhesion of the adhesive. When applied to bonding technology, it can better wet the dried nano-sintering paste and chip surface, which is beneficial to subsequent bonding and sintering. At the same time, the resulting patch adhesive has the properties of low-temperature volatilization and decomposition, and will not affect the metal bonding process in the bonding technology.

[0023] (2) The present invention introduces adhesive components into the bonding technology, which can achieve bonding under lower bonding pressure and temperature conditions. Compared with the existing wet bonding technology, it can significantly reduce voids in the sintering paste interconnect, improve sintering strength, and increase electrical and thermal conductivity. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the patch process (b) of the present invention and the existing process (a). Detailed Implementation

[0025] The technical solutions of the present invention will be clearly and completely described below with reference to the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0026] Unless otherwise specified, the experimental methods used in the examples and comparative examples are conventional methods, and the materials and reagents used are commercially available unless otherwise specified.

[0027] Examples 1-14, Comparative Examples 1-8

[0028] The components and weight percentages of the patch adhesives of Examples 1-14 and Comparative Examples 1-8 are shown in Tables 1-2.

[0029] The preparation methods of the patch adhesives of Examples 1-14 and Comparative Examples 1-8 include the following steps:

[0030] A measured amount of resin is added to a solvent and stirred until the resin is completely dissolved in the solvent. An activator is then added and stirred until homogeneous to obtain the patch adhesive.

[0031] Table 1 shows the component dosages (by weight) in the examples.

[0032]

[0033]

[0034] Table 2 shows the component dosage (by weight) in the comparative examples.

[0035]

[0036]

[0037] Performance testing

[0038] The adhesives prepared in Examples 1-14 and Comparative Examples 1-8 were applied to the sintering nano-paste interconnection process for small-sized chips, devices, or substrates described below. Comparative Example 9 used a conventional wet bonding process. The resistivity, thermal conductivity, shear strength, and thermal shock resistance of the corresponding products were measured. The performance testing standards are shown in Table 3, and the performance test results are shown in Table 4.

[0039] The specific steps of the sintering nano-paste interconnection process for small-sized chips, devices, or substrates are as follows:

[0040] S1. Using a stencil and printing press, and by calling the appropriate program, nano silver paste (Heraesche silver paste ASP338) is printed onto the heat sink (100×100mm).

[0041] S2. Dry the heat sink containing 100um silver paste in an oven at 120℃ for 1 hour.

[0042] S3. Use the pick-and-place head to pick up the copper substrate (50×50mm) to be interconnected (or it can be a chip, device or ceramic substrate, etc.). By controlling the drop height of the pick-and-place head (or by using the micro pressure sensor of the pick-and-place head), the pick-and-place head is moved to the appropriate position to move the copper substrate to the glue pool, so that the back of the copper substrate is evenly coated with the glue and bonded to the heat sink dried in step S2 to complete the pre-bonding.

[0043] S4. Transfer the pre-bonded product to the sintering machine to sinter the copper substrate onto the substrate / heat sink to achieve reliable mechanical and electrical interconnection. The sintering pressure is 15MPa and the sintering time is 5 minutes.

[0044] Comparative Example 9: Specific steps of the traditional wet-laying process:

[0045] The copper substrate (50×50mm) is attached to the heat sink (100×100mm) printed with 100um silver paste (Heraesche silver paste ASP338). The product is then placed in an oven to dry. After baking at 120℃ for 1 hour, the product is transferred to a sintering machine and sintered at 15MPa for 5 minutes.

[0046] Table 3 Performance Testing Standards

[0047]

[0048]

[0049] Table 4 Performance Test Results

[0050]

[0051] The experimental data in Table 4 show that the adhesive prepared according to the embodiments of this invention can effectively improve the thermal conductivity, shear strength, and thermal shock resistance of small-sized chips, devices, or substrates in the sintering nano-paste interconnect process, while reducing the resistivity of the product, which can be maintained at 2.4 × 10⁻⁶. -6 ~4.2×10 -6 The thermal conductivity can be maintained at 138–245 W / m·K, the shear strength is 71–102 MPa, and the number of thermal shock cycles is 2309–4306.

[0052] In Comparative Example 1, no activator was added to the adhesive component, resulting in a product with high resistivity after sintering, and inferior thermal conductivity, shear strength, and thermal shock resistance compared to the Example. In Comparative Examples 2-5, the resin components used in the adhesive components were unsuitable, leading to poor resistivity, thermal conductivity, shear strength, and thermal shock resistance in the resulting products. In Comparative Examples 6 and 7, the activator used in the adhesive components was unsuitable, and in Comparative Example 8, the solvent component was unsuitable, resulting in final products with inferior resistivity, thermal conductivity, shear strength, and thermal shock resistance compared to the Example. Comparative Example 9, using a traditional wet-lay process, achieved a final product with a resistivity of 15.4 × 10⁻⁶. -6 The thermal conductivity is only 46 W / m·K, the shear strength is only 18 MPa, and the thermal shock cycle is only 543 times, which is significantly worse than the example.

[0053] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A patch adhesive, characterized in that, It includes the following components by weight percentage: solvent 20-70%, resin 1-20%, activator 20-70%; The solvent is at least one selected from butyl acetate, tetrahydrofurfuryl alcohol, terpineol, butyl ether, and diethyl ether. The resin is at least one of polyvinylpyrrolidone, polyvinyl alcohol, ethyl cellulose, cellulose acetate, and carboxymethyl cellulose; The activator is at least one of hexamethyldisiloxane, octamethylcyclotetrasiloxane, decamethylcyclopentasiloxane, and dodecylcyclohexasiloxane; The process of applying the patch adhesive includes the following steps: S1. Print nano-sintering paste onto the substrate / heat sink; S2. Dry the substrate / heat sink containing the nano sintering paste; S3. Apply the patch adhesive to the back of the bare chip / device or substrate, and then bond it to the substrate / heat sink obtained in step S2 to complete the pre-bonding. S4. Sinter the pre-bonded products to complete the mechanical and electrical interconnection.

2. The patch adhesive as described in claim 1, characterized in that, It includes the following components by weight percentage: solvent 40-60%, resin 5-10%, activator 30-55%.

3. The patch adhesive as described in claim 1, characterized in that, In the process of applying adhesive, the drying temperature in step S2 is 80-140℃, and the drying time is 0.1-2 hours.

4. The patch adhesive as described in claim 1, characterized in that, In the process of applying the patch adhesive, the thickness of the patch adhesive in step S3 is 1-20 μm.

5. The patch adhesive as described in claim 1, characterized in that, In the process of applying adhesive, the bonding temperature in step S3 is 120~140℃, and the bonding pressure is 5~100kg.

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