A multi-section curvature compensation bandgap reference voltage source with trimming function

Abstract

Disclose a kind of multi-segment curvature compensation band gap reference voltage source with trimming function, including multi-segment curvature compensation circuit, temperature coefficient trimming circuit, voltage precision trimming circuit and V REF The generating circuit adopts multi-segment curvature current compensation traditional BGR, and the output reference voltage of BGR can be trimmed to about 1ppm / ℃ under most process angles by the method of digital trimming (temperature coefficient trimming and voltage precision trimming). The circuit does not use trimming resistance matrix to trim BGR, avoiding the problem of complex circuit structure caused by the large circuit area occupied by resistance.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of circuit design, in particular to a multi-segment curvature compensation bandgap reference voltage source with trimming function. BACKGROUND

[0002] In integrated circuits, bandgap reference voltage source (BGR) is an indispensable unit module, which provides a high-precision, high-stability reference voltage for circuits that does not change with device technology, temperature and power voltage, and is widely used in high-performance analog, digital-analog hybrid, digital and power management systems and other chip circuits. The precision and stability of the BGR will determine the performance of the subsequent circuit, and it plays an extremely important role. The output reference voltage of the traditional BGR is obtained by summing the emitter-base voltage (VBE) of the bipolar transistor and the thermal voltage VT. Since the VBE of the bipolar transistor has the characteristic of temperature nonlinearity, the output reference voltage of the traditional first-order temperature compensation BGR has a relatively high temperature coefficient, generally reaching 20-100ppm / ℃. SUMMARY

[0003] In order to solve the above technical problems existing in the prior art, the present application provides a multi-segment curvature compensation bandgap reference voltage source with trimming function, which comprises a multi-segment curvature compensation circuit, a temperature coefficient trimming circuit, a voltage precision trimming circuit and a V REF generating circuit;

[0004] The multi-segment curvature compensation circuit comprises a low-temperature compensation circuit and a high-temperature compensation circuit, and the low-temperature compensation circuit and the high-temperature compensation circuit are used to generate a low-temperature curvature compensation current and a high-temperature curvature compensation current, and the low-temperature curvature compensation current and the high-temperature curvature compensation current are added to obtain a multi-segment curvature compensation current;

[0005] The temperature coefficient trimming circuit comprises a low-temperature coefficient trimming circuit and a high-temperature coefficient trimming circuit, the low-temperature coefficient trimming circuit comprises a first current mirror circuit composed of field effect transistors with a preset aspect ratio, a first subtraction circuit, a first weighting circuit and a first digital switch circuit, the high-temperature coefficient trimming circuit comprises a second current mirror circuit composed of field effect transistors with a preset aspect ratio, a second subtraction circuit, a second weighting circuit and a second digital switch circuit, the low-temperature coefficient trimming circuit processes the pre-generated bias current I CTAT with negative temperature correlation through the first current mirror circuit and the first subtraction circuit to obtain a low-temperature coefficient trimming current, and the high-temperature coefficient trimming circuit processes the pre-generated bias current I PTATThe low-temperature coefficient trimming circuit and the high-temperature coefficient trimming circuit control the turn-on of field effect transistors of the first digital switch circuit and the second digital switch circuit respectively based on binary coding to obtain the low-temperature coefficient trimming current weighted by the first weighting circuit and the high-temperature coefficient trimming current weighted by the second weighting circuit respectively, and the low-temperature coefficient trimming current weighted and the high-temperature coefficient trimming current weighted are added to obtain a temperature coefficient trimming current;

[0006] The voltage precision trimming circuit comprises a low-temperature reference current generating circuit, a high-temperature reference current generating circuit, a third weighting circuit and a third digital switch circuit, the low-temperature reference current generating circuit comprises a third current mirror circuit and a third subtraction circuit, the high-temperature reference current generating circuit comprises a fourth current mirror circuit and a fourth subtraction circuit, the low-temperature reference current generating circuit outputs a low-temperature reference current I CTAT The high-temperature reference current generating circuit outputs a high-temperature reference current I PTAT The low-temperature reference current and the high-temperature reference current are added, and the turn-on of field effect transistors of the third digital switch circuit is controlled based on binary coding to obtain the added current of the low-temperature reference current weighted by the third weighting circuit and the high-temperature reference current, thereby obtaining a voltage precision trimming current;

[0007] The V REF The generating circuit injects the multi-segment curvature compensation current generated by the multi-segment curvature compensation circuit, the temperature coefficient trimming current generated by the temperature coefficient trimming current circuit, and the voltage precision trimming current generated by the voltage precision trimming circuit to obtain an output reference voltage V REF .

[0008] In some specific embodiments, a pre-generated bias current I CTAT with negative temperature correlation and a pre-generated bias current I PTAT with positive temperature correlation are obtained respectively based on I CTAT The generating circuit and I PTAT The generating circuit, I PTAT The generating circuit outputs a bias current I PTAT through the drain of field effect transistor M1, I CTAT The generating circuit outputs a bias current I CTAT through the drain of field effect transistor M4, I PTAT The generating circuit, field effect transistor M1 of I CTATThe field-effect transistors M1 and M4 in the generation circuit have the same width-to-length ratio. By setting the same width-to-length ratio for field-effect transistors M1 and M4, and connecting them to the gates of the field-effect transistors corresponding to the multi-segment curvature circuit, temperature coefficient adjustment circuit, and voltage accuracy adjustment circuit, the bias current I is obtained through the drain output of the field-effect transistors. CTAT With bias current I PTAT .

[0009] In some specific embodiments, the low-temperature compensation circuit of the multi-segment curvature compensation circuit is connected to the gate of the field-effect transistor M5, M... 11 gate and I CTAT The gates of the field-effect transistor M4 in the generating circuit are connected, and the drains of M5 and M are respectively connected. 11 The drain is connected to M6-M7 and M 12 -M 13 The current mirror circuit consists of M7-M9 and M 13 -M 15 The subtraction circuit is constructed to generate two segments of low-temperature curvature compensation current I. CP_L1 and I CP_L2 ;

[0010] The high-temperature compensation circuit of the multi-segment curvature compensation circuit uses a field-effect transistor M. 17 gate, M 20 gate and I PTAT The gates of the field-effect transistor M1 in the generating circuit are connected, respectively based on M 17 The drain and M 23 The drain is through M 18 -M 19 With M 24 -M 25 The current mirror circuit is constructed by M 19 -M 21 With M 25 -M 27 The constructed subtraction circuit generates two high-temperature curvature compensation currents I. CP_H1 and I CP_H2 The low-temperature curvature compensation current and the high-temperature curvature compensation current are added together to obtain a multi-segment curvature compensation current, which is then output to V. REF The generation circuit outputs a reference voltage V for the BGR at each temperature range. REF Compensation is performed to reduce its temperature coefficient.

[0011] In some specific embodiments, the multi-segment curvature compensation circuit includes field-effect transistors M5-M7, M... 11 -M 13 M 17 -M 19 and M 24 -M 26It has the same width-to-length ratio and operates in the saturation region across the entire temperature range. It accurately replicates the temperature-inversely correlated bias current I. PTAT Bias current I that is positively correlated with temperature CTAT .

[0012] In some specific embodiments, the low-temperature coefficient adjustment circuit of the temperature coefficient adjustment circuit uses a field-effect transistor M. 29 gate and I CTAT The gates of the field-effect transistor M4 in the generating circuit are connected, and based on M... 30 and M 31 Constructing the first current mirror circuit and M 29 The drain connection is used to replicate the bias current I. CTAT Through field-effect transistor M 32 gate and I PTAT The gates of the field-effect transistor M1 in the generation circuit are connected, based on M 31 M 32 and M 33 The first subtraction circuit will construct the bias current I CTAT With M 32 The bias current I at the drain output PTAT The low-temperature coefficient adjustment current is obtained by performing a subtraction operation and then passed through the field-effect transistor M. 34 -M 41 The gates of the transistors are connected to form the first weighting circuit, which is connected to the field-effect transistor M. C0 -M C7 The gate of the circuit is connected to the binary code input terminal to form the first digital switch circuit. M in the first weighting circuit... 34 -M 41 The drain of the first digital switch circuit is connected to the M terminal. C0 -M C7 The source connection is used to control the turn-on of the corresponding field-effect transistor based on binary code to obtain a weighted low-temperature coefficient adjustment current;

[0013] The high-temperature coefficient adjustment circuit of the temperature coefficient adjustment circuit uses a field-effect transistor M. 42 gate and I PTAT The gates of the field-effect transistor M1 in the generating circuit are connected, and based on M 43 and M 44 Constructing the second current mirror circuit and M 42 The drain connection is used to replicate the bias current I. PTAT Through field-effect transistor M 45 gate and I CTAT The gates of the field-effect transistor M4 in the generation circuit are connected, based on M 44 M 45 and M 46The second subtraction circuit will construct the bias current I PTAT With M 45 The bias current I at the drain output CTAT The high-temperature coefficient adjustment current is obtained by performing a subtraction operation, and then passed through the field-effect transistor M. 47 -M 54 The gates of the transistors are connected to form a second weighting circuit, which is achieved through a field-effect transistor M. P0 -M P7 The gate of the circuit is connected to the binary code input terminal to form a second digital switch circuit. M in the second weighting circuit... 47 -M 54 The drain of the second digital switch circuit and M P0 -M P7 The source connection is used to control the turn-on of the corresponding field-effect transistor based on binary code to obtain a weighted high-temperature coefficient adjustment current.

[0014] In some specific embodiments, the temperature coefficient adjustment circuit uses a field-effect transistor M. 29 M 30 M 42 M 43 and I PTAT The aspect ratio of M1 in the generation circuit is the same, and the field-effect transistor M... 31 M 32 M 44 and M 45 The aspect ratios of the two components are respectively those of the I. PTAT The width-to-length ratio of the generation circuit M1 is α1-α4 times, and the field-effect transistor M... 34 and M 47 The aspect ratios of the M and M are respectively those of the field-effect transistor M 33 and M 46 A field-effect transistor M with a width-to-length ratio of α5 and α6 times. 29 -M 33 and M 42 -M 46 It operates in the saturation region across the entire temperature range. Low-temperature and high-temperature adjustment currents can be obtained by setting appropriate α1-α6.

[0015] In some specific embodiments, the temperature coefficient adjustment circuit uses a field-effect transistor M. C0 -M C7 and M P0 -M P7 Each is subject to 8-bit binary code C <0> -C <7> and P <0> -P <7> The control uses binary codes 0 and 1 to correspond to the on and off states of the field-effect transistor, respectively. When the BGR outputs the reference voltage V... REFWhen the temperature coefficient is relatively large due to process variation, device mismatch and other factors, the temperature coefficient trimming current with positive temperature characteristic and negative temperature characteristic is injected into the BGR voltage output node respectively through the digital switch control mode, so as to perform temperature coefficient trimming on the BGR output reference voltage V REF .

[0016] In some specific embodiments, the low-temperature reference current generating circuit of the voltage accuracy trimming circuit is connected with the gate of the field effect transistor M 55 and the gate of the field effect transistor M1 of the current generating circuit, and is connected with the drain of the field effect transistor M CTAT based on M 56 and M 57 to copy the bias current I 55 . The gate of the field effect transistor M CTAT is connected with the gate of the field effect transistor M1 of the current generating circuit, and is connected with the drain of the field effect transistor M 58 based on M PTAT , M 57 and M 58 to perform subtraction operation on the bias current I 59 output by the drain of M CTAT and the bias current I 58 output by the drain of M PTAT to obtain the low-temperature reference current, and outputs the low-temperature reference current based on the drain of M 60 to the third weighting circuit.

[0017] The high-temperature reference current generating circuit of the voltage accuracy trimming circuit is connected with the gate of the field effect transistor M 61 and the gate of the field effect transistor M1 of the current generating circuit, and is connected with the drain of the field effect transistor M PTAT based on M 62 and M 63 to copy the bias current I 61 . The gate of the field effect transistor M PTAT is connected with the gate of the field effect transistor M4 of the current generating circuit, and is connected with the drain of the field effect transistor M 64 based on M CTAT , M 63 and M 64 to perform subtraction operation on the bias current I 65 output by the drain of M PTAT and the bias current I 64 output by the drain of M CTAT to obtain the high-temperature reference current, and outputs the high-temperature reference current based on the drain of M 66 to the third weighting circuit.

[0018] The low-temperature reference current and the high-temperature reference current are output to the field effect transistor M67 The gate and the drain of the field effect transistor M 67 -M 71 The gate of the field effect transistor M V0 -M V7 The gate of the field effect transistor M 67 -M 71 The drain of the field effect transistor M V0 -M V7 The source of the field effect transistor M

[0019] In some specific embodiments, the width-length ratio of the field effect transistor M 68 -M 71 is respectively M 67 times of the width-length ratio of the field effect transistor M

[0020] In some specific embodiments, the width-length ratio of the field effect transistor M V0 -M V3 is controlled by the 4-bit binary code V REF <0>-V REF <3>, and the binary codes 0 and 1 respectively correspond to the opening and closing of the field effect transistor.

[0021] The present application provides a multi-segment curvature compensation bandgap reference voltage source with a trimming function, which has the technical effect that: the conventional BGR is compensated by multi-segment curvature current, and the output reference voltage of the BGR is trimmed by the method of digital trimming (temperature coefficient trimming and voltage precision trimming), so that the temperature coefficient of the output reference voltage of the BGR can be trimmed to about 1ppm / ℃ under most process angles, and the circuit does not use the trimming resistance matrix to trim the BGR, thereby avoiding the problem of complex circuit structure caused by the fact that the resistance occupies a large circuit area. BRIEF DESCRIPTION OF DRAWINGS

[0022] The accompanying drawings are included to provide a further understanding of embodiments and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments and, together with the description, serve to explain the principles of the application. Other embodiments and many of the intended advantages of the present application will be readily appreciated as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings. The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts.

[0023] Figure 1 A complete circuit diagram of the multi-segment curvature compensation bandgap reference voltage source with trimming function according to one embodiment of the present application is shown;

[0024] Figure 2 A working principle diagram of the multi-segment curvature compensation bandgap reference voltage source with trimming function according to one specific embodiment of the present application is shown;

[0025] Figure 3 A circuit diagram of the multi-segment curvature compensation circuit according to one specific embodiment of the present application is shown;

[0026] Figure 4 A graph showing the variation of the currents I0, I1 and I2 with temperature in the multi-segment curvature compensation circuit according to one specific embodiment of the present application is shown;

[0027] Figure 5 A simulation result of the curvature compensation currents I CP_L1 , I CP_L2 , I CP_H1 and I CP_H2 in the multi-segment curvature compensation circuit according to one specific embodiment of the present application is shown;

[0028] Figure 6 A comparison diagram of the conventional BGR output reference voltage before and after compensation according to one specific embodiment of the present application is shown;

[0029] Figure 7 A circuit diagram of the temperature coefficient trimming circuit according to one specific embodiment of the present application is shown;

[0030] Figure 8 A circuit diagram of the voltage precision trimming circuit according to one specific embodiment of the present application is shown;

[0031] Figure 9 A simulation result of the reference current I REF in the voltage precision trimming circuit according to one specific embodiment of the present application is shown;

[0032] Figure 10 A trimming process diagram of the multi-segment curvature compensation BGR output reference voltage according to one specific embodiment of the present application is shown;

[0033] Figure 11 A binary-coded C-to-BGR output reference voltage temperature coefficient trimming process diagram is shown according to one specific embodiment of the present application;

[0034] Figure 12 A multi-segment curvature compensation BGR output reference voltage untrimmed simulation result diagram under multiple process corners is shown according to one specific embodiment of the present application.

[0035] Figure 13 A multi-segment curvature compensation BGR output reference voltage trimmed simulation result diagram under multiple process corners is shown according to one specific embodiment of the present application. DETAILED DESCRIPTION

[0036] The present application will be further described below in conjunction with the accompanying drawings and embodiments. It can be understood that the specific embodiments described herein are only used to explain the related application, and are not a limitation on the application. In addition, it should be noted that only the parts related to the application are shown in the drawings for ease of description.

[0037] It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict. The present application will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.

[0038] The multi-segment curvature compensation bandgap reference voltage source with trimming function according to one embodiment of the present application, the specific circuit is as shown in Figure 1 The multi-segment curvature compensation bandgap reference voltage source with trimming function according to one embodiment of the present application, the specific circuit is as shown in REF The multi-segment curvature compensation bandgap reference voltage source with trimming function according to one embodiment of the present application, the specific circuit is as shown in

[0039] The multi-segment curvature compensation circuit includes a low-temperature compensation circuit and a high-temperature compensation circuit, and the low-temperature compensation circuit and the high-temperature compensation circuit are used to generate a low-temperature curvature compensation current and a high-temperature curvature compensation current, and the low-temperature curvature compensation current and the high-temperature curvature compensation current are added to obtain a multi-segment curvature compensation current;

[0040] The temperature coefficient trimming circuit includes a low-temperature coefficient trimming circuit and a high-temperature coefficient trimming circuit, the low-temperature coefficient trimming circuit has a first current mirror circuit composed of field effect transistors with a preset aspect ratio, a first subtraction circuit, a first weighting circuit and a first digital switch circuit, the high-temperature coefficient trimming circuit has a second current mirror circuit composed of field effect transistors with a preset aspect ratio, a second subtraction circuit, a second weighting circuit and a second digital switch circuit, the low-temperature coefficient trimming circuit generates a bias current I CTATThe low-temperature coefficient trimming current is obtained by processing, and the high-temperature coefficient trimming circuit obtains a high-temperature coefficient trimming current by processing the pre-generated bias current I PTAT The low-temperature coefficient trimming circuit and the high-temperature coefficient trimming circuit control the turn-on of field effect transistors of the first digital switch circuit and the second digital switch circuit respectively based on binary coding to obtain the low-temperature coefficient trimming current weighted by the first weighting circuit and the high-temperature coefficient trimming current weighted by the second weighting circuit respectively, and the temperature coefficient trimming current is obtained by adding the weighted low-temperature coefficient trimming current and the weighted high-temperature coefficient trimming current.

[0041] The voltage accuracy trimming circuit includes a low-temperature reference current generating circuit, a high-temperature reference current generating circuit, a third weighting circuit and a third digital switch circuit, the low-temperature reference current generating circuit includes a third current mirror circuit and a third subtraction circuit, the high-temperature reference current generating circuit includes a fourth current mirror circuit and a fourth subtraction circuit, the low-temperature reference current generating circuit obtains a low-temperature reference current by processing the bias current I CTAT The high-temperature reference current generating circuit obtains a high-temperature reference current by processing the bias current I PTAT The low-temperature reference current and the high-temperature reference current are added, and the turn-on of field effect transistors of the third digital switch circuit is controlled based on binary coding to obtain the addition current of the low-temperature reference current weighted by the third weighting circuit and the high-temperature reference current, thereby obtaining the voltage accuracy trimming current.

[0042] The V REF The generating circuit injects the multi-segment curvature compensation current generated by the multi-segment curvature compensation circuit, the temperature coefficient trimming current generated by the temperature coefficient trimming current circuit, and the voltage accuracy trimming current generated by the voltage accuracy trimming circuit to obtain an output reference voltage V REF .

[0043] In some specific embodiments, the main working principle of a multi-segment curvature compensation bandgap reference voltage source with trimming function proposed by the present application is as shown in Figure 2 The circuit proposed by the present application injects a multi-segment curvature compensation current I REF at the A node of the branch where the output reference voltage V COPM of the BGR is located, compensates and reduces the temperature coefficient of the BGR output reference voltage V REF for each temperature segment. When the BGR output reference voltage V REFWhen the temperature coefficient is large due to factors such as process variations and component mismatch, temperature coefficient adjustment currents with positive and negative temperature characteristics are injected into the BGR voltage output node via digital switch control to adjust the BGR output reference voltage V. REF Perform temperature coefficient adjustment. When the BGR outputs the reference voltage V... REF When the accuracy does not meet the requirements, a voltage accuracy adjustment current I is injected into the BGR voltage output node via digital switch control. REF For the BGR output reference voltage V REF Perform precision adjustments.

[0044] In some specific embodiments, a pre-generated bias current I that is negatively correlated with temperature is used. CTAT and the pre-generated temperature-dependent bias current I PTAT Based on I respectively CTAT Generation circuit and I PTAT I is obtained by the generation circuit. PTAT The generating circuit outputs a bias current I through the drain of the field-effect transistor M1. PTAT I CTAT The generating circuit outputs a bias current I through the drain of the effect transistor M4. CTAT I PTAT The field-effect transistors M1 and I in the generating circuit CTAT The field-effect transistors M1 and M4 in the generation circuit have the same width-to-length ratio. By setting the same width-to-length ratio for field-effect transistors M1 and M4, and connecting them to the gates of the field-effect transistors corresponding to the multi-segment curvature circuit, temperature coefficient adjustment circuit, and voltage accuracy adjustment circuit, the bias current I is obtained through the drain output of the field-effect transistors. CTAT With bias current I PTAT .

[0045] In some specific embodiments, I PTAT The generating circuit includes a first field-effect transistor M1, a second field-effect transistor M2, a resistor R1, transistors Q1 and Q2, and a first differential amplifier A1. The source of M1 and the source of M2 are connected to VDD. The gate of M1 is connected to the output terminal of the first differential amplifier A1 and the gate of M2. The drain of M1 is connected to the negative input terminal of A1 and the emitter of Q1. The drain of M2 is connected to the positive input terminal of A1 and one end of R1. The other end of R1 is connected to the emitter of Q2. The base of Q1 and the base of Q2 are connected to GND. The collector of Q1 is connected to GND, and the collector of Q2 is connected to GND.

[0046] In some specific embodiments, I CTATThe generating circuit includes a fourth field-effect transistor M4, a resistor R2, and a second differential amplifier A2; the source of the field-effect transistor M4 is connected to VDD, and the gate of M4 is connected to the output terminal of the second differential amplifier A2, I... PTAT The drain of M1 in the generation circuit, I PTAT The emitter of Q1 in the generating circuit, I PTAT The negative input terminal of amplifier A1 in the generation circuit is connected to the positive input terminal of the second differential amplifier A2, and one end of resistor R2 is connected to the positive input terminal of the second differential amplifier A2. The other end of resistor R2 is connected to GND. The negative input terminal of the second differential amplifier A2 is connected to I. PTAT The drain of M1 in the generation circuit, I PTAT The emitter of Q1 in the generating circuit, I PTAT Connect it to the negative input terminal of A1 in the generating circuit.

[0047] In some specific embodiments, the multi-segment curvature compensation circuit diagram is as follows: Figure 3 As shown. This multi-segment curvature compensation circuit includes a low-temperature compensation circuit and a high-temperature compensation circuit. The low-temperature compensation circuit includes the fifth field-effect transistor M5, the sixth field-effect transistor M6, the seventh field-effect transistor M7, the eighth field-effect transistor M8, the ninth field-effect transistor M9, and the tenth field-effect transistor M10. 10 Eleventh field-effect transistor M 11 The twelfth field-effect transistor M 12 Thirteenth Field-Effect Transistor M 13 The fourteenth field-effect transistor M 14 The fifteenth field-effect transistor M 15 The sixteenth field-effect transistor M 16 The high-temperature compensation circuit includes a seventeenth field-effect transistor M. 17 The eighteenth field-effect transistor M 18 The nineteenth field-effect transistor M 19 20th Field-Effect Transistor M 20 21st Field Effect Transistor M 21 22nd Field-Effect Transistor M 22 23rd Field Effect Transistor M 23 24th Field-Effect Transistor M 24 25th Field Effect Transistor M 25 The twenty-sixth field-effect transistor M 26 The twenty-seventh field-effect transistor M 27 The twenty-eighth field-effect transistor M 28 29th Field-Effect Transistor M 29 In the aforementioned low-temperature compensation circuit, the source of M5 is connected to the source of M8, the source of M9, and M... 10 The source, M11 source of M 14 source of M 15 source of M 16 source of M 17 source of M 20 source of M 21 source of M 22 source of M 23 source of M 26 source of M 27 source of M 28 source of M 11 gate of M 20 gate of M 26 gate of M CTAT gate of M4 of the generating circuit and the output terminal of the second differential amplifier A2 are connected, the drain of M5 and the gate of M6, the source of M6, the gate of M7 are connected, the source of M6 and the source of M7, the drain of M7 are connected, the drain of M7 and the drain of M8, the gate of M9, the drain of M9 are connected 12 source of M 13 source of M 18 source of M 19 source of M 24 source of M 25 source of M are connected to GND, the drain of M7 and the drain of M8, the gate of M9, the drain of M9 are connected 10 gate of M 14 gate of M 17 gate of M 23 gate of M PTAT gate of M1 of the generating circuit and the output terminal of the first differential amplifier A1 are connected, the drain of M 10 drain of M 16 drain of M 22 drain of M 28 drain of M are connected, the drain of M 11 drain of M 12 gate of M 12 drain of M 13 gate of M are connected, the drain of M 13 drain of M 14 drain of M 15 drain of M 15 gate of M 16 gate of M are connected; in the high-temperature compensation circuit, the drain of M 17 drain of M 18 gate of M 18 drain of M 19 gate of M are connected, the drain of M 19 drain of M 20 drain of M 21Drain, M 21 gate, M 22 The gates are connected, M 23 The drain and M 24 gate, M 24 Drain, M 25 The gates are connected, M 25 The drain and M 26 Drain, M 27 Drain, M 27 gate, M 28 The gate is connected.

[0048] In some specific embodiments, the low-temperature compensation circuit of the multi-segment curvature compensation circuit is connected to the gate of the field-effect transistor M5, M... 11 gate and I CTAT The gates of the field-effect transistor M4 in the generating circuit are connected, and the gates are connected to the drains of M5 and M6 respectively. 11 The drain is connected to M6-M7 and M 12 -M 13 The current mirror circuit consists of M7-M9 and M 13 -M 15 The subtraction circuit is constructed to generate two segments of low-temperature curvature compensation current I. CP_L1 and I CP_L2 Furthermore, the circuit operates within the nanoampere power consumption range; the high-temperature compensation circuit of the multi-segment curvature compensation circuit utilizes a field-effect transistor M. 17 gate, M 20 gate and I PTAT The gates of the field-effect transistor M1 in the generating circuit are connected, respectively based on M 17 The drain and M 23 The drain is through M 18 -M 19 With M 24 -M 25 The current mirror circuit is constructed by M 19 -M 21 With M 25 -M 27 The constructed subtraction circuit generates two high-temperature curvature compensation currents I. CP_H1 and I CP_H2 The field-effect transistors M5-M7 and M... 11 -M 13 M 17 -M 19 and M 24 -M 26 Having the same width-to-length ratio and operating in the saturation region across the entire temperature range, it accurately replicates the temperature-inversely correlated bias current I. PTAT Bias current I that is positively correlated with temperature CTAT.

[0049] wherein at low temperature, the current I1>I0(I CTAT >I PTAT ) and I1=I0+I2, therefore the field effect transistors M9 and M 10 are turned on to generate the compensation current I CP_L1 . However, as the temperature rises, the current I1decreases and the current I0increases until I1=I0, M9 and M 10 are turned off, the curves of the currents I0, I1and I2versus temperature are shown in Figure 4 . The principle of generating the high-temperature compensation current is the same as that of generating the low-temperature compensation current, and the simulation results of the curvature compensation currents I CP_L1 , I CP_L2 , I CP_H1 and I CP_H2 are shown in Figure 5 . At low temperature, M9, M 10 , M 15 and M 16 are turned on to generate two segments of low-temperature compensation currents I CP_L1 and I CP_L2 , at intermediate temperature, none of them are turned on to generate no compensation current, and at high temperature, M 21 , M 22 , M 27 and M 28 are turned on to generate two segments of high-temperature compensation currents I CP_H1 and I CP_H2 .

[0050] In some specific embodiments, the comparison of the conventional BGR output reference voltage before and after compensation is shown in Figure 6 . The output reference voltage after compensation is in the form of multiple steps, and within the working temperature range of -40-120℃, the maximum value (V MAX -V MIN ) of the BGR output reference voltage varying with temperature is significantly reduced, and the average value V MEAN of the output slightly rises. According to the temperature coefficient calculation formula of the output reference voltage:

[0051]

[0052] wherein T MAX and T MIN are the maximum and minimum temperatures of the circuit working. The temperature coefficient of the conventional BGR output reference voltage after compensation is significantly reduced.

[0053] In some specific embodiments, the temperature coefficient trimming circuit is shown in Figure 7 . The temperature trimming circuit includes a twenty-ninth field effect transistor M 29 , a thirtieth field effect transistor M30 , a thirty-first field effect transistor M 31 , a thirty-second field effect transistor M 32 , a thirty-third field effect transistor M 33 , thirty-fourth to forty-first field effect transistors M 34 -M 41 , a forty-second field effect transistor M 42 , a forty-third field effect transistor M 43 , a forty-fourth field effect transistor M 44 , a forty-fifth field effect transistor M 45 , a forty-sixth field effect transistor M 46 , forty-seventh to fifty-fourth field effect transistors M 47 -M 54 , C0 to C7 field effect transistors M C0 -M C7 , P0 to P7 field effect transistors M P0 -M P7 ; M 29 of the source of M 32 of the source of M 33 of the source of M 34 -M 41 of the source of M 42 of the source of M 45 of the source of M 46 of the source of M 47 -M 54 of the source of M 29 of the gate of M 45 of the gate of M CTAT of the gate of M4 of the output terminal of the second differential amplifier A2, M 29 of the drain of M 30 of the gate of M 30 of the drain of M 31 of the gate of M 30 of the source of M 31 of the source of M 43 of the source of M 44 of the source of M 31 of the drain of M 32 of the drain of M 33 of the gate of M 33 of the drain of M 34 -M 41 of the gate of M 32 of the gate of M 42 of the gate of M PTAT of the gate of M1 of the output terminal of the first differential amplifier A1, M 34 -M41 The drains are respectively connected to M C0 -M C7 The source terminals are connected, M C0 -M C7 The drain and M P0 -M P7 The drains are connected, M 42 The drain and M 43 gate, M 43 Drain, M 44 The gates are connected, M 44 The drain and M 45 Drain, M 46 Drain, M 46 gate, M 47 -M 54 The gates are connected, M 47 -M 54 The drains are respectively connected to M P0 -M P7 The source poles are connected.

[0054] In some specific embodiments, the low-temperature coefficient adjustment circuit of the temperature coefficient adjustment circuit uses a field-effect transistor M. 29 gate and I CTAT The gates of the field-effect transistor M4 in the generating circuit are connected, and based on M... 30 and M 31 Constructing the first current mirror circuit and M 29 The drain connection is used to replicate the bias current I. CTAT Through field-effect transistor M 32 gate and I PTAT The gate of the field-effect transistor M1 in the generation circuit is connected, based on M 31 M 32 and M 33 The first subtraction circuit will construct the bias current I CTAT With M 32 The bias current I at the drain output PTAT The low-temperature coefficient adjustment current is obtained by performing a subtraction operation and then passed through the field-effect transistor M. 34 -M 41 The gates of the transistors are connected to form the first weighting circuit, which is connected to the field-effect transistor M. C0 -M C7 The gate of the circuit is connected to the binary code input terminal to form the first digital switch circuit. M in the first weighting circuit... 34 -M 41 The drain of the first digital switch circuit is connected to the M... C0 -M C7 The source connection is used to control the turn-on of the corresponding field-effect transistor based on binary code to obtain a weighted low-temperature coefficient adjustment current;

[0055] The high-temperature coefficient adjustment circuit of the temperature coefficient adjustment circuit uses a field-effect transistor M. 42 gate and I PTAT The gates of the field-effect transistor M1 in the generating circuit are connected, and based on M 43 and M 44 Constructing the second current mirror circuit and M 42 The drain connection is used to replicate the bias current I. PTAT Through field-effect transistor M 45 gate and I CTAT The gates of the field-effect transistor M4 in the generation circuit are connected, based on M 44 M 45 and M 46 The second subtraction circuit will convert the bias current I PTAT With M 45 The bias current I at the drain output CTAT The high-temperature coefficient adjustment current is obtained by performing a subtraction operation, and then passed through the field-effect transistor M. 47 -M 54 The gates of the transistors are connected to form a second weighting circuit, which is achieved through a field-effect transistor M. P0 -M P7 The gate of the circuit is connected to the binary code input terminal to form a second digital switch circuit. M in the second weighting circuit... 47 -M 54 The drain of the second digital switch circuit and M P0 -M P7 The source connection is used to control the turn-on of the corresponding field-effect transistor based on binary code to obtain a weighted high-temperature coefficient adjustment current.

[0056] The temperature coefficient adjustment circuit is used to improve the situation where the temperature coefficient of the BGR output reference voltage deteriorates due to device mismatch and process angle variations. In the temperature coefficient adjustment circuit, field-effect transistors M1 and M2 are used. 29 M 30 M 42 and M 43 They have the same width-to-length ratio. Field-effect transistor M 31 M 32 M 44 and M 45 The aspect ratios of the two transistors are α1-α4 times that of transistor M1, respectively. (The last part, "Field-effect transistor M...", appears to be a typo and can be left as is.) 34 and M 47 The aspect ratios are M and M respectively. 33 and M 46 A field-effect transistor M with a width-to-length ratio of α5 and α6 times. 29 -M 33 M 42 -M46 All work in the saturation region in the full temperature range. In combination with software simulation, set appropriate a1-a6 to obtain low temperature coefficient adjustment current and high temperature coefficient adjustment current I C 、 P . Field effect transistor M C0 -M C7 and M P0 -M P7 are controlled by 8-bit binary codes C<0>-C<7> and P<0>-P<7>, respectively, and binary codes 0 and 1 correspond to the opening and closing of the field effect transistor, respectively. When the temperature coefficient of the BGR output reference voltage is poor, the corresponding field effect transistor is turned on by the corresponding binary codes 0 and 1 to inject the weighted temperature coefficient adjustment current XI C +YI P , which ultimately plays a role in improving the temperature coefficient of the BGR output reference voltage.

[0057] In some specific embodiments, the voltage precision adjustment circuit is as shown in Figure 8 , which includes the fifty-fifth field effect transistor M 55 , the fifty-sixth field effect transistor M 56 , the fifty-seventh field effect transistor M 57 , the fifty-eighth field effect transistor M 58 , the fifty-ninth field effect transistor M 59 , the sixtieth field effect transistor M 60 , the sixty-first field effect transistor M 61 , the sixty-second field effect transistor M 62 , the sixty-third field effect transistor M 63 , the sixty-fourth field effect transistor M 64 , the sixty-fifth field effect transistor M 65 , the sixty-sixth field effect transistor M 66 , the sixty-seventh field effect transistor M 67 , the sixty-eighth field effect transistor to the seventy-first field effect transistor M 68 -M 71 , the V0 to V3 field effect transistor M V0 -M V3 ; the gate of M 55 , the gate of M 64 and the gate of M4 of the I CTAT generation circuit and the output terminal of the second differential amplifier A2 are connected, the source of M 55 , the source of M 58 , the source of M 59 , the source of M 60 , the source of M 61 , the source of M 64source of M 65 source of M 66 source of M 55 drain of M 56 gate of M 56 drain of M 57 gate of M 56 source of M 57 source of M 62 source of M 63 source of M 67 source of M 68 -M 71 source of M 57 drain of M 58 drain of M 59 gate of M 59 drain of M 60 gate of M 58 gate of M 61 gate of M PTAT gate of M1 and output of first differential amplifier A1 of the generating circuit are connected, M 60 drain of M 66 drain of M 67 drain of M 67 gate of M 68 -M 71 gate of M 61 drain of M 62 gate of M 62 drain of M 63 gate of M 63 drain of M 64 drain of M 65 gate of M 65 drain of M 66 gate of M 68 -M 71 drains of M V0 -M V3 source of M V0 -M V3 drains of M are connected.

[0058] In some specific embodiments, the low temperature reference current generating circuit of the voltage precision trimming circuit comprises a field effect transistor M 55 gate of M CTAT gate of field effect transistor M4 of the generating circuit is connected, and is based on M 56 and M 57 comprise a third current mirror circuit connected with the drain of M 55 to copy the bias current ICTAT Through field-effect transistor M 58 gate and I PTAT The gates of the field-effect transistor M1 in the generation circuit are connected, based on M 57 M 58 and M 59 The third subtraction circuit will construct the bias current I CTAT With M 58 The bias current I at the drain output PTAT The low-temperature reference current is obtained by subtraction, based on M. 60 The drain outputs the low-temperature reference current to the third weighting circuit;

[0059] The high-temperature reference current generation circuit of the voltage accuracy adjustment circuit uses a field-effect transistor M. 61 gate and I PTAT The gates of the field-effect transistor M1 in the generating circuit are connected, and based on M 62 and M 63 Constructing the fourth current mirror circuit and M 61 The drain connection is used to replicate the bias current I. PTAT Through field-effect transistor M 64 gate and I CTAT The gates of the field-effect transistor M4 in the generation circuit are connected, based on M 63 M 64 and M 65 The fourth subtraction circuit will convert the bias current I PTAT With M 64 The bias current I at the drain output CTAT The high-temperature reference current is obtained by subtraction, based on M. 66 The high-temperature reference current is output from the drain to the third weighting circuit;

[0060] The low-temperature reference current and the high-temperature reference current are respectively output to the field-effect transistor M. 67 The gate and drain are added together, based on the field-effect transistor M. 67 -M 71 The gates of the transistors are connected to form a third weighting circuit, which is achieved through a field-effect transistor M. V0 -M V7 The gate of the circuit is connected to the binary code input terminal to form a third digital switch circuit. M in the third weighting circuit... 67 -M 71 The drain of the third digital switch circuit and M V0 -M V7 The source connection is used to control the turn-on of the corresponding field-effect transistor based on binary code to obtain the sum of the low-temperature reference current and the high-temperature reference current after being weighted by the third weighting circuit.

[0061] Among them, the voltage accuracy adjustment circuit uses a field-effect transistor M. 57 -M 59 and M 63 -M 65 These constitute two subtraction circuits, and a field-effect transistor M. 55 M 56 M 61 and M 62 The constructed current mirror circuit obtains the low-temperature reference current I. RC and high temperature reference current I RP Current I RC and I RP The temperature coefficient and the average value over the entire temperature range are basically the same. Reference current I REF From current I RC and I RP The summation and weighting yielded a very low temperature coefficient of only 48.4 ppm / ℃, with a reference current I. REF The simulation results are as follows Figure 9 As shown. Field-effect transistor M 68 -M 71 The aspect ratios are M and M respectively. 67 Aspect ratios of γ, 2γ, 4γ, and 8γ times. Field-effect transistor M. V0 -M V3 Subject to 4-bit binary code V <0> -V <3> The control uses binary codes 1 and 0 to correspond to the on and off states of the field-effect transistor, respectively. When the BGR output reference voltage accuracy is insufficient, the transistor is turned on using the corresponding binary codes 0 and 1, and the weighted voltage accuracy adjustment current ZI is extracted. REF To improve the accuracy of the BGR output reference voltage.

[0062] In some specific embodiments, V REF The generating circuit includes a field-effect transistor M3, resistors R3 and R4, a transistor Q3, and the source of the field-effect transistor M3 is connected to VDD. The gate of M3 is connected to the voltage precision adjustment circuit M. 61 Connected, the drain of M3 is connected to the M of the temperature coefficient adjustment circuit. C0 -M C7 The drain and M P0 -M P7 The drain and voltage accuracy adjustment circuit of M V0 -M V3 The drain of Q3 is connected to one end of resistor R3, the other end of R3 is connected to the emitter of Q3, and the base and collector of Q3 are connected to GND.

[0063] In some specific embodiments, the adjustment process of the multi-segment curvature compensation BGR output reference voltage is as follows: Figure 10The untrimmed BGR output reference voltage increases continuously with the temperature rising, and the temperature coefficient is as high as 10.66ppm / ℃. The binary codes C<0>-C<7> and P<0>-P<7> are used to control the turn-on of transistors M C0 -M C7 and M P0 -M P7 , and inject the weighted temperature coefficient trimming current XI C +YI P , so that the BGR output reference voltage is stabilized at about 1.2247V, and the temperature coefficient is reduced to 1.386ppm / ℃. When the BGR is applied to a circuit with high precision requirements, the precision of the BGR output reference voltage needs to be trimmed. The binary codes V<0>-V<3> are used to control the turn-on of transistors M V0 -M V3 , and extract the weighted reference current ZI REF The precision of the BGR output reference voltage is trimmed, and finally the BGR output reference voltage is trimmed to 1.2V and the temperature coefficient is 0.959ppm / ℃, which meets the performance requirements of the circuit for the precision and temperature coefficient of the BGR output reference voltage.

[0064] In some specific embodiments, the trimming process of the binary code C for the temperature coefficient of the BGR output reference voltage is as shown in Figure 11 The trimming of the temperature coefficient of the BGR output reference voltage needs to be performed at-40℃ and 125℃ to determine the optimal trimming binary code C<0>-C<7>. At-40℃ and 125℃, the size of the BGR output reference voltage is measured when the binary code C<0:7> is FFH and 00H respectively, and a straight line graph is drawn. The binary code at the intersection of the two straight lines is 7FH, and the temperature coefficient of the BGR output reference voltage under this code is the smallest.

[0065] In order to highlight the effect of the proposed multi-segment curvature compensation bandgap reference voltage source circuit with trimming function, Figure 12 a plurality of process angles are provided for the simulation results of the untrimmed multi-segment curvature compensation BGR output reference voltage, Figure 13 a plurality of process angles are provided for the simulation results of the trimmed multi-segment curvature compensation BGR output reference voltage. The temperature coefficient of the reference voltage trimmed by the circuit proposed in the present application is about 1ppm / ℃ under a plurality of process angles.

[0066] To sum up, the multi-segment curvature compensation bandgap reference voltage source with trimming function in the above-mentioned embodiments of the present application can trim the BGR output reference voltage by using the digital trimming method (temperature coefficient trimming and voltage precision trimming), so that the temperature coefficient of the BGR output reference voltage under most process angles can be trimmed to about 1ppm / ℃, and the circuit does not use the trimming resistor matrix to trim the BGR, thereby avoiding the problem of complex circuit structure caused by the large circuit area occupied by the resistors.

[0067] The above description is merely preferred embodiments of the present application and a description of the principles of the technology used. It should be understood by those skilled in the art that the scope of the application involved in the present application is not limited to the technical solutions formed by the specific combinations of the above technical features, and also covers other technical solutions formed by any combination of the above technical features or equivalent features without departing from the above inventive concept. For example, the above features are replaced with each other to form technical solutions with similar functions disclosed in the present application (but not limited to).

Claims

1. A multi-section curvature-compensated bandgap reference voltage source with trimming function, characterized by, The application relates to a voltage reference circuit, comprising a multi-segment curvature compensation circuit, a temperature coefficient trimming circuit, a voltage precision trimming circuit and a V REF A generating circuit; The multi-section curvature compensation circuit comprises a low-temperature compensation circuit and a high-temperature compensation circuit, the low-temperature compensation circuit and the high-temperature compensation circuit are respectively used for generating a low-temperature curvature compensation current and a high-temperature curvature compensation current, and the low-temperature curvature compensation current and the high-temperature curvature compensation current are added to obtain a multi-section curvature compensation current; The temperature coefficient trimming circuit comprises a low temperature coefficient trimming circuit and a high temperature coefficient trimming circuit, the low temperature coefficient trimming circuit has a first current mirror circuit composed of field effect transistors with preset width-length ratio, a first subtraction circuit, a first weighting circuit and a first digital switch circuit, the high temperature coefficient trimming circuit has a second current mirror circuit composed of field effect transistors with preset width-length ratio, a second subtraction circuit, a second weighting circuit and a second digital switch circuit, the low temperature coefficient trimming circuit processes a previously generated bias current I CTAT with negative temperature correlation through the first current mirror circuit and the first subtraction circuit to obtain a low temperature coefficient trimming current, and the high temperature coefficient trimming circuit processes a previously generated bias current I PTAT with positive temperature correlation through the second current mirror circuit and the second subtraction circuit to obtain a high temperature coefficient trimming current, the low temperature coefficient trimming circuit and the high temperature coefficient trimming circuit respectively control the opening of field effect transistors of the first digital switch circuit and the second digital switch circuit based on binary coding to obtain the low temperature coefficient trimming current weighted by the first weighting circuit and the high temperature coefficient trimming current weighted by the second weighting circuit, and the weighted low temperature coefficient trimming current and the weighted high temperature coefficient trimming current are added to obtain a temperature coefficient trimming current. The voltage precision trimming circuit comprises a low-temperature reference current generating circuit, a high-temperature reference current generating circuit, a third weighting circuit and a third digital switch circuit, the low-temperature reference current generating circuit comprises a third current mirror circuit and a third subtraction circuit, the high-temperature reference current generating circuit comprises a fourth current mirror circuit and a fourth subtraction circuit, the low-temperature reference current generating circuit processes the bias current I CTAT through the third current mirror circuit and the third subtraction circuit to obtain a low-temperature reference current, the high-temperature reference current generating circuit processes the bias current I PTAT through the fourth current mirror circuit and the fourth subtraction circuit to obtain a high-temperature reference current, the low-temperature reference current and the high-temperature reference current are added, the opening of a field effect transistor of the third digital switch circuit is controlled based on binary coding to obtain the addition current of the low-temperature reference current and the high-temperature reference current weighted by the third weighting circuit, and a voltage precision trimming current is obtained. The V REF The generating circuit injects the multi-segment curvature compensation current, the temperature coefficient trimming current, and the voltage precision trimming current to obtain an output reference voltage V REF .

2. A multi-curvature compensated bandgap reference voltage source with trimming function according to claim 1, characterized in that, The pre-generated bias current I CTAT and the pre-generated bias current I PTAT based on I CTAT The generating circuit and I PTAT The generating circuit obtains, the I PTAT The generating circuit outputs the bias current I PTAT , the I CTAT The generating circuit outputs the bias current I CTAT , the I PTAT The field effect transistor M1 of the generating circuit has the same width-length ratio as the I CTAT The field effect transistor M4 of the generating circuit has the same width-length ratio as the I 3. A multi-curvature compensated bandgap reference voltage source with trimming function according to claim 2, characterized in that, The low temperature compensation circuit of the multi-segment curvature compensation circuit is connected with the gate of field effect transistor M5, the gate of M 11 and the drain of M CTAT , and the gate of field effect transistor M4 of the generating circuit is connected, respectively based on the drain of M5 and the drain of M 11 , through the current mirror circuit composed of M6-M7 and M 12 -M 13 , the subtraction circuit composed of M7-M9 and M 13 -M 15 to generate two-segment low temperature curvature compensation currents I CP_L1 and I CP_L2 ; The high-temperature compensation circuit of the multi-segment curvature compensation circuit uses a field-effect transistor M. 17 gate, M 20 gate and I PTAT The gates of the field-effect transistor M1 in the generating circuit are connected, respectively based on M 17 The drain and M 23 The drain is through M 18 -M 19 With M 24 -M 25 The current mirror circuit is constructed by M 19 -M 21 With M 25 -M 27 The constructed subtraction circuit generates two high-temperature curvature compensation currents I. CP_H1 and I CP_H2 .

4. A multi-curvature compensated bandgap reference voltage source with trimming function according to claim 3, characterized in that, The multi-segment curvature compensation circuit includes field effect transistors M5-M7, M 11 -M 13 , M 17 -M 19 and M 24 -M 26 have the same width-length ratio and work in the saturation region throughout the temperature range.

5. The multi-curvature compensated bandgap reference voltage source with trimming function according to claim 2, wherein, The low temperature coefficient trimming circuit of the temperature coefficient trimming circuit is connected with the gate of the field effect transistor M 29 The gate of the field effect transistor M4 of the generating circuit is connected with the gate of the field effect transistor M CTAT , and a first current mirror circuit is composed of the field effect transistors M 30 , M 31 and M 29 , and the drain of the field effect transistor M CTAT is connected with the drain of the field effect transistor M 32 to copy the bias current I PTAT The gate of the field effect transistor M1 of the generating circuit is connected with the gate of the field effect transistor M 31 , a first subtraction circuit is composed of the field effect transistors M 32 , M 33 and M CTAT , the bias current I 32 is subtracted from the bias current I PTAT outputted by the drain of the field effect transistor M 34 , and a low temperature coefficient trimming current is obtained, a first weighting circuit is composed of the gates of the field effect transistors M 41 -M C0 , a first digital switch circuit is composed of the gates of the field effect transistors M C7 -M 34 , the drains of the field effect transistors M 41 -M C0 in the first weighting circuit are connected with the sources of the field effect transistors M C7 -M to control the opening of the corresponding field effect transistors based on the binary code to obtain a weighted low temperature coefficient trimming current; The high temperature coefficient trimming circuit of the temperature coefficient trimming circuit is connected with the gate of the field effect transistor M 42 and the I PTAT generation circuit, and is based on M 43 , M 44 and M 42 to constitute a second current mirror circuit connected with the drain of M PTAT to copy the bias current I 45 , the gate of the field effect transistor M4 of the I CTAT generation circuit is connected with I 44 , M 45 and M 46 to constitute a second subtraction circuit to subtract the bias current I PTAT from the bias current I 45 outputted by the drain of M CTAT to obtain a high temperature coefficient trimming current, the gate of the field effect transistor M 47 -M 54 constitutes a second weighting circuit, the gate of the field effect transistor M P0 -M P7 constitutes a second digital switch circuit connected with the binary code input end, the drain of M 47 -M 54 in the second weighting circuit is connected with the source of M P0 -M P7 in the second digital switch circuit to control the opening of the corresponding field effect transistor based on the binary code to obtain a weighted high temperature coefficient trimming current.

6. A multi-curvature compensated bandgap reference voltage source with trimming function according to claim 5, characterized in that, The temperature coefficient adjustment circuit uses a field-effect transistor M. 29 M 30 M 42 M 43 and I PTAT The aspect ratio of M1 in the generation circuit is the same, and the field-effect transistor M... 31 M 32 M 44 and M 45 The aspect ratios of the two components are respectively those of the I. PTAT The width-to-length ratio of the generation circuit M1 is α1-α4 times, and the field-effect transistor M... 34 and M 47 The aspect ratios of the M and M are respectively those of the field-effect transistors. 33 and M 46 A field-effect transistor M with a width-to-length ratio of α5 and α6 times. 29 -M 33 and M 42 -M 46 It operates in the saturation region across the entire temperature range.

7. A multi-curvature compensated bandgap reference voltage source with trimming function according to claim 5, wherein, The temperature coefficient trimming circuit field effect transistor M C0 -M C7 and M P0 -M P7 are controlled by 8-bit binary codes C<0>-C<7> and P<0>-P<7>, respectively, with binary codes 0 and 1 corresponding to the opening and closing of the field effect transistors, respectively.

8. The multi-curvature compensated bandgap reference voltage source with trimming function according to claim 2, wherein, The low-temperature reference current generating circuit of the voltage precision trimming circuit is connected with I 55 by the gate of field effect transistor M CTAT 4 of the generating circuit, and is based on M 56 , M 57 and M 55 to constitute a third current mirror circuit and is connected with the drain of M CTAT to copy the bias current I 58 , and is connected with I PTAT by the gate of field effect transistor M 57 1 of the generating circuit, and is based on M 58 , M 59 and M CTAT to constitute a third subtraction circuit to subtract the bias current I 58 outputted by the drain of M PTAT to obtain a low-temperature reference current, and is based on the drain of M 60 to output the low-temperature reference current to a third weighting circuit; The high-temperature reference current generation circuit of the voltage accuracy adjustment circuit uses a field-effect transistor M. 61 gate and I PTAT The gates of the field-effect transistor M1 in the generating circuit are connected, and based on M 62 and M 63 Constructing the fourth current mirror circuit and M 61 The drain connection is used to replicate the bias current I. PTAT Through field-effect transistor M 64 gate and I CTAT The gates of the field-effect transistor M4 in the generation circuit are connected, based on M 63 M 64 and M 65 The fourth subtraction circuit will convert the bias current I PTAT With M 64 The bias current I at the drain output CTAT The high-temperature reference current is obtained by subtraction, based on M. 66 The high-temperature reference current is output from the drain to the third weighting circuit; The low-temperature reference current and the high-temperature reference current are respectively output to the gate and the drain of a field effect transistor M 67 The gate and the drain of the field effect transistor M 67 -M 71 The gate of the field effect transistor M V0 -M V7 The gate of the field effect transistor M 67 -M 71 The drain of the field effect transistor M V0 -M V7 The source of the field effect transistor M 9. A multi-curvature compensated bandgap reference voltage source with trimming function according to claim 8, characterized in that, The voltage accuracy trimming circuit includes field effect transistors M 68 -M 71 The width-length ratios of the field effect transistors M 67 The width-length ratios of the field effect transistors M 10. The multi-curvature compensated bandgap reference voltage source with trimming function according to claim 9, wherein, The field effect transistor M in the voltage accuracy trimming circuit V0 -M V3 Controlled by 4-bit binary code V<0>-V<3>, binary code 0 and 1 correspond to the opening and closing of the field effect transistor respectively.

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