Data error correction circuit and data transmission method

Abstract

The present disclosure provides a data error correction circuit and a data transmission method. The data transmission circuit includes: a data error correction module, receiving first data and a first check code corresponding to the first data, the data error correction module is used to correct the first data according to the first check code to generate second data, and output the second data; a check code generation module, receiving the first data and the first check code, and generating and outputting a second check code according to the first data and the first check code. The embodiments of the present disclosure can save the components and layout area required for the data error correction function.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to a data error correction circuit and a data transmission method applied to the data error correction circuit. Background Art

[0002] As the channel speed between the memory and the system (controller / processor) becomes higher and higher, it poses a huge challenge to the accuracy of signal transmission. In this context, the relevant technology sets a link error correction circuit (Link ECC, Link Error Correct Circle) in the data receiving terminal (controller / processor) to correct the received data in order to correct the errors that may occur in the channel transmission.

[0003] In order to accurately improve the accuracy of error correction, the relevant technology usually requires that the data receiving terminal generate a second check code including the full check value of the data based on the received data and the first check code corresponding to the data, and then perform error correction on the data based on the second check code. The full check value is generated based on each bit of the data and the first check code. This sets a threshold for the circuit function of the data receiving terminal and also increases the number of components and layout area of ​​the data receiving terminal.

[0004] Therefore, how to reduce the requirements on the data receiving terminal while maintaining the accuracy of error correction has become a technical point that can be improved in integrated circuits with data transmission functions.

[0005] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0006] The purpose of the present disclosure is to provide a data error correction circuit and a data transmission method applied thereto, so as to at least overcome the problem in the related art that the data error correction function requires a large number of circuit elements and occupies a large layout area.

[0007] According to a first aspect of the present disclosure, there is provided a data error correction circuit, which is arranged in a memory and includes: a data error correction module, which receives first data and a first check code corresponding to the first data, and the data error correction module is used to correct the first data according to the first check code to generate second data, and output the second data; a check code generation module, which receives the first data and the first check code, and is used to generate and output a second check code according to the first data and the first check code.

[0008] In an exemplary embodiment of the present disclosure, the data error correction module includes: an error correction code generation unit, which receives the first data and the first check code, and is used to generate a data error correction code and a check error correction code based on the first data and the first check code; a data error correction unit, connected to the error correction code generation unit, is used to receive the first data and the data error correction code, and corrects the first data according to the data error correction code to generate and output second data.

[0009] In an exemplary embodiment of the present disclosure, the check code generation module is connected to the error correction code generation unit and receives the data error correction code and the check error correction code, and the check code generation module corrects the second check code according to the data error correction code or the check error correction code.

[0010] In an exemplary embodiment of the present disclosure, the check code generation module includes: a full check value generation unit, connected to the error correction code generation unit, used to receive the first data and the first check code, and generate a full check value based on the first data, the first check code and the data error correction code, or generate the full check value based on the first data, the first check code and the check error correction code, and the second check code includes the full check value.

[0011] In an exemplary embodiment of the present disclosure, the full check value generation unit includes: a full check value calculation unit, which receives the first data and the first check code, and is used to generate an initial full check value based on the first data and the first check code; a full check value error correction unit, which is connected to the full check value calculation unit and the error correction code generation unit, and is used to correct the initial full check value according to the data error correction code or the check code error correction code and output the full check value.

[0012] In an exemplary embodiment of the present disclosure, the full check value error correction unit is used to invert the initial full check value to generate the full check value after receiving the data error correction code or the check error correction code.

[0013] In an exemplary embodiment of the present disclosure, the initial full check value is obtained by performing an XOR calculation on each bit in the first data and each bit in the first check code.

[0014] In an exemplary embodiment of the present disclosure, the check code generation module includes: a check code error correction unit, connected to the error correction code generation unit, receiving the first check code, and used to correct the first check code according to the check error correction code, and the second check code includes the first check code after error correction.

[0015] In an exemplary embodiment of the present disclosure, the highest bit of the second check code is the full check value, and the first check code after error correction constitutes the remaining bits of the second check code.

[0016] In an exemplary embodiment of the present disclosure, the first check code includes 8 bits of data.

[0017] According to a second aspect of the present disclosure, a memory is provided, comprising: a data error correction circuit as described in any embodiment of the first aspect; a first output terminal for outputting second data; and a second output terminal for outputting a second check code corresponding to the second data.

[0018] According to a third aspect of the present disclosure, an integrated storage device is provided, comprising: the memory as described above; and a controller connected to the memory, configured to receive second data and a second check code, and perform check and error correction on the second data according to the second check code.

[0019] In an exemplary embodiment of the present disclosure, the controller determines whether there are multi-bit errors in the second data according to the second check code.

[0020] According to a fourth aspect of the present disclosure, a data transmission method is provided, which is executed by the memory described in the second aspect, and includes: obtaining first data to be transmitted and a first check code corresponding to the first data; performing error correction on the first data according to the first check code and the first data to generate second data; generating a second check code according to the first data and the first check code; and simultaneously outputting the second data and the second check code to a controller, so that the controller checks and corrects the second data according to the second check code.

[0021] In an exemplary embodiment of the present disclosure, generating a second check code based on the first data and the first check code includes: performing an XOR operation on each bit of the first data and each bit of the first check code to generate an initial full check value; obtaining a check result of the first data and the first check code; and generating the second check code based on the check result, the first check code and the full check value.

[0022] In an exemplary embodiment of the present disclosure, generating the second check code based on the check result, the first check code and the full check value includes: when it is determined according to the check result that an error occurs in the first check code and no error occurs in the first data, correcting the initial full check value to generate a full check value, and correcting the first check code; generating the second check code based on the first check code and the full check value after error correction.

[0023] In an exemplary embodiment of the present disclosure, generating the second check code based on the check result, the first check code and the full check value includes: when it is determined according to the check result that the first check code has no error and an error has occurred in the first data, correcting the initial full check value to generate a full check value; generating the second check code based on the first check code and the full check value.

[0024] In an exemplary embodiment of the present disclosure, generating the second check code according to the check result, the first check code and the full check value includes: when it is determined according to the check result that neither the first data nor the first check code has an error, generating the second check code according to the first check code and the initial full check value.

[0025] In an exemplary embodiment of the present disclosure, the error correction of the initial full check value to generate the full check value includes: inverting the initial full check value to generate the full check value.

[0026] In an exemplary embodiment of the present disclosure, generating a second check code based on the first data and the first check code includes: obtaining the check results of the first data and the first check code; when it is determined according to the check result that neither the first data nor the first check code has an error, performing an XOR operation on each bit of the first data and each bit of the first check code to determine a full check value, and generating the second check code according to the full check value and the first check code; when it is determined according to the check result that only the first data has an error, performing an XOR operation on each bit of the second data and each bit of the first check code to determine a full check value; generating the second check code according to the full check value and the first check code; when it is determined according to the check result that only the first check code has an error, performing an XOR operation on each bit of the first data and each bit of the first check code after error correction to determine a full check value, and generating the second check code according to the full check value and the first check code after error correction.

[0027] The disclosed embodiment completes the generation of the second check code in the data error correction circuit of the memory, and directly outputs the second data after error correction and the second check code corresponding to the second data, so that the data receiving terminal can directly check and correct the second data according to the second check code, thereby reducing the cumbersome procedure of the data receiving terminal generating the check code again according to the received data and the check code in the related technology, saving the functional requirements for the data receiving terminal, thereby reducing the number of components and layout area of ​​the data receiving terminal, and improving the compatibility of the memory.

[0028] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0030] Figure 1 Schematic diagram of the structure of a data error correction circuit in an exemplary embodiment of the present disclosure.

[0031] Figure 2 Schematic diagram of a data error correction circuit in one embodiment of the present disclosure.

[0032] Figure 3 In one embodiment of the present disclosure Figure 2 Schematic diagram of the full check value generating unit 121 is shown.

[0033] Figure 4 is a schematic diagram of a memory provided by an embodiment of the present disclosure.

[0034] Figure 5 It is an application Figure 4 Schematic diagram of the integrated storage device of the memory shown.

[0035] Figure 6 It is a flowchart of the data transmission method provided by an embodiment of the present disclosure.

[0036] Figure 7 It is a sub-flow chart of step S3 in one embodiment of the present disclosure.

[0037] Figure 8 In one embodiment of the present disclosure Figure 7 The sub-flow chart of step S33 is shown.

[0038] Fig. 9 It is a sub-flowchart of step S3 in another embodiment of the present disclosure. DETAILED DESCRIPTION

[0039] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as being limited to the examples set forth herein; on the contrary, these embodiments are provided so that the present disclosure will be more comprehensive and complete, and the concepts of the example embodiments are fully conveyed to those skilled in the art. The described features, structures, or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced while omitting one or more of the specific details, or other methods, components, devices, steps, etc. may be adopted. In other cases, known technical solutions are not shown or described in detail to avoid obscuring various aspects of the present disclosure.

[0040] In addition, the accompanying drawings are only schematic diagrams of the present disclosure, and the same reference numerals in the drawings represent the same or similar parts, so their repeated description will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities, which do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor devices and / or microcontroller devices.

[0041] The exemplary embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0042] Figure 1 Schematic diagram of the structure of a data error correction circuit in an exemplary embodiment of the present disclosure.

[0043] refer to Figure 1 , the data error correction circuit 100 is set in the memory and may include:

[0044] The data error correction module 11 receives the first data Data1 and the first check code Parity1 corresponding to the first data, and is used to correct the first data Data1 according to the first check code Parity1 to generate the second data Data2, and output the second data Data2;

[0045] The check code generation module 12 receives the first data Data1 and the first check code Parity1, and is configured to generate and output the second check code Parity2 according to the first data Data1 and the first check code Parity1.

[0046] When the memory acts as a data sending terminal to send data to a data receiving terminal, it will correct errors in the data to be sent that may be caused by the storage array before outputting the data. That is, an on-chip error correction circuit (On Die ECC, OnDie Error Correct Circle) is set to correct errors in the storage array.

[0047] The disclosed embodiment improves the on-chip error correction circuit of the memory, and can directly generate and output the second check code Parity2 based on the first data Data1 and the first check code Parity1 while correcting the error of the first data Data1, so that the data receiving terminal can directly check and correct the second data Data2 finally output by the memory according to the second check code, thereby reducing the cumbersome procedures of the data receiving terminal in the related art of generating the check code again according to the received data and the check code, saving the functional requirements for the data receiving terminal, thereby reducing the number of components and layout area of ​​the data receiving terminal, and improving the compatibility of the memory.

[0048] Figure 2 FIG. 1 is a schematic diagram of a data error correction circuit in an embodiment of the present disclosure. Figure 2 In the illustrated embodiment, it is assumed that the first data Data1 is 128 bits, represented as Data<127:0>, and correspondingly, the first check code (ECC check code of the first data) Parity1 is 8 bits, represented as Parity<7:0>, the second data Data2 is 128 bits, represented as ABus<127:0>, and the second check code Parity2 includes the full check value of the second data Data2, which is 9 bits, represented as ABusParity<8:0>.

[0049] refer to Figure 2 In one embodiment, the data error correction module 11 includes:

[0050] The error correction code generation unit 111 receives the first data Data<127:0> and the first check code Parity<7:0>, and is configured to generate a data error correction code Code1 or a check error correction code Code2 according to the first data Data<127:0> and the first check code Parity<7:0>.

[0051] The data error correction unit 112 is connected to the error correction code generation unit 111, and is used to receive the first data Data<127:0> and the data error correction code Code1, and perform error correction on the first data Data<127:0> according to the data error correction code Code1 to generate and output the second data ABus<127:0>.

[0052] The check code generation module 12 is connected to the error correction code generation unit 111 and receives the data error correction code Code1 and the check error correction code Code2. The check code generation module 12 corrects the second check code ABusParity<8:0> according to the data error correction code Code1 or the check error correction code Code2.

[0053] Exemplarily, in one embodiment, the verification code generation module 12 includes:

[0054] The full check value generating unit 121 is connected to the error correction code generating unit 111, and is used to receive the first data Data<127:0> and the first check code Parity<7:0>, and generate the full check value Parity according to the first data Data<127:0>, the first check code Parity<7:0> and the data error correction code Code1. <8> , or, generate a full check value Parity according to the first data Data<127:0>, the first check code Parity<7:0> and the check error correction code Code2 <8> The second check code ABusParity<8:0> includes the full check value Parity <8> .

[0055] The check code error correction unit 122 is connected to the error correction code generation unit 111, receives the first check code Parity<7:0>, and is used to correct the first check code Parity<7:0> according to the check code Code2 to output the first check code ABusParity<7:0> after error correction, and the second check code ABusParity<8:0> includes the first check code ABusParity<7:0> after error correction.

[0056] Parity <8> The first check code ABusParity<7:0> after error correction is outputted in combination to form the second check code ABusParity<8:0>. In one embodiment, the highest bit of the second check code ABusParity<8:0> is the full check value Parity <8> The first check code Parity<7:0> after error correction constitutes the remaining bits of the second check code ABusParity<8:0>. By setting the output timing of the full check value generation unit 121 and the check code error correction unit 122, the 9-bit second check code ABusParity<8:0> can be output through the full check value generation unit 121 and the check code error correction unit 122.

[0057] In the disclosed embodiment, the first check code is the ECC check code of the first data output by the memory. The generation of the ECC check code is to perform an XOR operation on different bits in the first data according to a set rule, and set the XOR results of multiple groups of different bits as one bit of the ECC check code. According to the generation rule of the ECC check code, it is possible to detect whether the data has an error according to the ECC check code of the data, and correct the error of the erroneous data bit by using the ECC check code. By using the ECC check code of the data to check the data, errors in odd-numbered bits of the data can be detected.

[0058] The second check code of the data is generated based on the data and the first check code of the data. The lower several bits of the second check code of the data are the first check code of the data, and the highest bit is the full check value of the data. The full check value is generated based on the data and the first check code of the data. In one embodiment, the full check value can be, for example, the XOR result of each bit of the data and each bit of the first check code. According to the above rules, by using the second check code of the data to check the data, it can be detected whether the data has an even number of bit error data.

[0059] By combining the first check code and the second check code of the data, the data can be fully checked and corrected.

[0060] exist Figure 2 In the illustrated embodiment, the error correction code generation unit 111 receives the first data and the first check code. Since the first check code is generated according to the first data, the error correction code generation unit 111 can check the first data and the first check code, and judge whether there is an error in the first data and the first check code according to the check result. The error correction code generation unit 111 indicates the check result by outputting the values ​​of the two error correction codes. One error correction code is a data error correction code Code1 used to indicate that there is an error in the first data, and the other error correction code is a check error correction code Code2 used to indicate that there is an error in the first check code. It can be assumed that when the data error correction code Code1 is a first value, it indicates that there is an error in the first data, and when the data error correction code Code1 is a second value, it indicates that the first data is correct. The first value and the second value are, for example, logic level 1 and logic level 0, respectively, or the first value and the second value are other values, respectively, and the present disclosure does not impose special restrictions on this. Similarly, it can be assumed that when the check error correction code Code2 is a first value, it indicates that there is an error in the first check code, and when the check error correction code Code2 is a second value, it indicates that the first check code is correct.

[0061] The data error correction unit 112 is used to correct the first data. When the data error correction unit 112 receives the data error correction code Code1 representing data errors, the data error correction unit 112 will correct the first data according to the data error correction code Code1 to output second data. When the data error correction unit 112 receives the data error correction code Code1 representing correct data, the data error correction unit 112 will not correct the first data according to the data error correction code Code1 and directly output the first data as the second data.

[0062] Similarly, the check and error correction unit 122 is used to correct the first check code. When the check and error correction unit 122 receives the check and error correction code Code2 representing the error of the first check code, the check and error correction unit 122 will correct the first check code according to the check and error correction code Code2 to output the first check code after error correction. When the check and error correction unit 122 receives the check and error correction code Code2 representing the correctness of the first check code, the check and error correction unit 122 will not correct the first check code according to the check and error correction code Code2, and directly output the first check code as the first check code after error correction.

[0063] The check code generation module 12 needs to generate a second check code involving the first data and the first check code. Whether the first data or the first check code is wrong, it will affect the correctness of the full check value. The check code generation module 12 receives the data error correction code Code1 and the check error correction code Code2.

[0064] The full check value generation unit 121 is used to generate a full check value for the first data. Errors in either the first data or the first check code will affect the correctness of the full check value. The full check value generation unit 121 simultaneously receives the data error correction code Code1 and the check error correction code Code2.

[0065] The check code error correction unit 122 only corrects the first check code, therefore, receives the check code Code2, corrects the first check code according to the instruction of the check code Code2, and outputs the corrected first check code ABusParity<7:0> (also 8 bits).

[0066] In the disclosed embodiment, not only the first data is corrected to generate the second data, but also the full check value is corrected according to whether the first data is correct, and then the second check code is corrected, thereby generating a second check code that guarantees accuracy. In addition, the disclosed embodiment also verifies the first check code, and when an error occurs in the first check code, the first check code and the full check value are corrected, which can further ensure the accuracy of the second check code.

[0067] Therefore, the embodiment of the present disclosure can improve the accuracy of the second check code, and because the existing on-chip error correction circuit of the memory is utilized, the circuit structure and signal connection do not increase a significant burden. Compared with the second check code generation circuit that needs to be set in each data receiving terminal connected to the memory in the related art, the embodiment of the present disclosure can greatly save the total number of circuit elements and layout area of ​​the memory and each data receiving terminal.

[0068] Figure 3 In one embodiment of the present disclosure Figure 2 Schematic diagram of the full check value generating unit 121 is shown.

[0069] refer to Figure 3 In one embodiment, the full check value generating unit 121 may include:

[0070] The full check value calculation unit 1211 receives the first data Data<127:0> and the first check code Parity<7:0>, and is used to generate an initial full check value NParity according to the first data Data<127:0> and the first check code Parity<7:0>. <8> ;

[0071] Full checksum error correction unit 1212, connected to the full checksum Parity <8> The calculation unit and the error correction code generation unit 111 are used to calculate the initial full check value NParity according to the data error correction code Code1 or the check code error correction code Code2. <8> Perform error correction and output the full checksum value Parity <8> .

[0072] Among them, the initial full check value NParity <8> For example, the value may be obtained by performing an XOR calculation on each bit in the first data Data<127:0> and each bit in the first check code Parity<7:0>.

[0073] In one embodiment, the full check value error correction unit 1212 is used to correct the initial full check value NParity after receiving the data error correction code Code1 and the check error correction code Code2. <8> Negate to generate the full checksum Parity <8> .

[0074] Figure 3 The overall working logic of the data error correction circuit corresponding to the embodiment shown is, for example, the following logic:

[0075] The error correction code generation unit 111 determines that if the first data Data<127:0> and the first check code Parity<7:0> are both correct, the error correction code generation unit 111 will output Code1 and Code2 values ​​representing that the data and the check code are correct, then the check code error correction unit 122 will not correct the first check code Parity<7:0> but directly output the first check code ABusParity<7:0> (i.e., the lower 8 bits of the second check code) after error correction, and the full check value error correction unit 1212 will not correct the full check value after receiving the data error correction code Code1 and the check code correction code Code2 values ​​representing that the data and the check code are correct, but will output the initial full check value NParity calculated by the full check value calculation unit 1211. <8> Directly used as full checksum Parity <8> Output, the first check code after error correction ABusParity<7:0> and Parity <8> The data error correction unit 112 directly outputs the first data Data<127:0> as the second data ABus<127:0>, and controls the sending timing of the data error correction module 11 and the check code generation module 12, so as to simultaneously send the second check code ABusParity<8:0> and the second data ABus<127:0> out through the output port.

[0076] If the error correction code generation unit 111 determines that the first data Data<127:0> is wrong, the check code error correction unit 122 receives the check error correction code Code2 representing that the first check code is correct, and will not correct the first check code Parity<7:0> but directly output the first check code Parity<7:0> as the first check code ABusParity<7:0> after error correction (i.e., the lower 8 bits of the second check code). The full check value error correction unit 1212 will calculate the initial full check value NParity calculated by the full check value calculation unit 1211 according to the data error correction code Code1 representing the data error. <8> After negation, it is used as Parity <8> (i.e. the highest bit of the second check code) output, the first check code after error correction ABusParity<7:0> and Parity <8> The second check code ABusParity<8:0> is formed, and the data error correction unit 112 corrects the first data Data<127:0> according to the data error correction code Code1 representing the data error and outputs the second data ABus<127:0>. The sending timing of the data error correction module 11 and the check code generation module 12 is controlled to simultaneously send the second check code ABusParity<8:0> and the second data ABus<127:0> through the output port.

[0077] If the error correction code generation unit 111 determines that the first check code Parity<7:0> is wrong, the check code error correction unit 122 receives the check error correction code Code2 representing that the first check code is correct, corrects the first check code Parity<7:0> and outputs the first check code ABusParity<7:0> (i.e., the lower 8 bits of the second check code) after error correction, and the full check value error correction unit 1212 calculates the initial full check value NParity calculated by the full check value calculation unit 1211 according to the check error correction code Code2 representing that the first check code is correct. <8> After negation, it is used as Parity <8> (i.e. the highest bit of the second check code) output, the first check code after error correction ABusParity<7:0> and Parity <8> The second check code ABusParity<8:0> is formed, and the data error correction unit 112 does not correct the first data Data<127:0> according to the data error correction code Code1 representing the correct data and directly outputs it as the second data ABus<127:0>, and controls the sending timing of the data error correction module 11 and the check code generation module 12 to simultaneously send the second check code ABusParity<8:0> and the second data ABus<127:0> through the output port.

[0078] Figure 4 is a schematic diagram of a memory provided by an embodiment of the present disclosure.

[0079] refer to Figure 4 , a memory 400 may include:

[0080] The data error correction circuit as described in the above embodiment;

[0081] The first output terminal OUT1 is used to output the second data Data2;

[0082] The second output terminal OUT2 is used for outputting a second check code Parity2 corresponding to the second data Data2.

[0083] Figure 4 The memory shown has the function of directly outputting a second check code including a full check code of the second data. There is no need for the data receiving terminal to separately set up a full check code generation module, allowing the data receiving terminal to directly check and correct the second data according to the second check code, which can greatly reduce the technical requirements and power consumption of the data receiving terminal. When connecting multiple data receiving terminals, the area and power consumption of the overall circuit are greatly reduced.

[0084] Figure 5 It is an application Figure 4 Schematic diagram of the integrated storage device of the memory shown.

[0085] refer to Figure 5 , the integrated storage device 500 may include:

[0086] Memory 400;

[0087] The controller 51 is connected to the memory 400 , and is used for receiving the second data Data2 and the second check code Parity2 , and performing check and error correction on the second data Data2 according to the second check code Parity2 .

[0088] In one embodiment, the controller 51 may determine whether there are multi-bit errors in the second data Data2 according to the second check code Parity2.

[0089] Figure 5 The integrated storage device shown does not need to set up a full check value generation circuit in the controller 51. The controller 51 can directly check and correct the second data according to the second check value including the full check value. Therefore, the controller 51 has a smaller circuit area and lower power consumption.

[0090] Figure 6 It is a flowchart of the data transmission method provided by an embodiment of the present disclosure. Figure 6 The method shown can be Figure 5 The memory 400 is shown to execute.

[0091] refer to Figure 6 , the data transmission method 600 may include:

[0092] Step S1, obtaining first data to be transmitted and a first check code corresponding to the first data;

[0093] Step S2, performing error correction on the first data according to the first check code and the first data to generate second data;

[0094] Step S3, generating a second check code according to the first data and the first check code;

[0095] Step S4, outputting the second data and the second check code to the controller simultaneously, so that the controller checks and corrects errors of the second data according to the second check code.

[0096] Combination Figure 1 and Figure 2 , Figure 6 The step S1 shown can be jointly executed by the data error correction module 11 and the check code generation module 12, step S2 is executed by the data error correction module 11, step S3 is executed by the check code generation module 12, and step S4 is jointly executed by the data error correction module 11 and the check code generation module 12.

[0097] The first check code corresponding to the first data is, for example, an ECC check code, and the second check code is formed based on the first data and the ECC check code. By directly generating the second check code based on the first data and the first check code on the memory, the data receiving terminal can directly perform error correction on the second data based on the second check code, thereby saving the number of circuit elements and layout area of ​​the data receiving terminal and improving the compatibility of the memory.

[0098] Figure 7 It is a sub-flow chart of step S3 in one embodiment of the present disclosure.

[0099] refer to Figure 7 In one embodiment, step S3 may include:

[0100] Step S31, performing an XOR operation on each bit of the first data and each bit of the first check code to generate an initial full check value;

[0101] Step S32, obtaining the verification result of the first data and the first verification code;

[0102] Step S33, generating a second check code according to the check result, the first check code and the full check value.

[0103] Figure 7 The illustrated embodiment can be Figure 3 Step S31 may be executed by the full check value calculation unit 1211 , and steps S32 and S33 may be executed by the full check value error correction unit 1212 .

[0104] Figure 8 In one embodiment of the present disclosure Figure 7 The sub-flow chart of step S33 is shown.

[0105] refer to Figure 7 In one embodiment, step S33 may include:

[0106] Step S331, when it is determined according to the verification result that an error occurs in the first check code and no error occurs in the first data, the initial full check value is corrected to generate a full check value, the first check code is corrected, and then a second check code is generated based on the corrected first check code and the full check value.

[0107] Step S332, when it is determined according to the verification result that the first verification code has no error and the first data has an error, the initial full verification value is corrected to generate a full verification value, and then a second verification code is generated according to the first verification code and the full verification value.

[0108] Step S333: when it is determined according to the verification result that neither the first data nor the first verification code has any error, a second verification code is generated according to the first verification code and the initial full verification value.

[0109] Among them, correcting the error of the initial full check value to generate the full check value includes inverting the initial full check value to generate the full check value.

[0110] exist Figure 2 and Figure 3 In the embodiment shown, Figure 7 The method shown can be expressed in the following form:

[0111] If the first data Data<127:0> and the first check code Parity<7:0> are both correct, the first check code Parity<7:0> is used as ABusParity<7:0> (i.e., the lower 8 bits of the second check code), and the initial full check value NParity<7:0> is calculated. <8> As a full checksum Parity <8> , ABusParity<7:0> and Parity <8> The second check code ABusParity<8:0> is formed. The first data Data<127:0> is directly sent as the second data ABus<127:0>, and the second check code ABusParity<8:0> and the second data ABus<127:0> are sent out through the output port at the same time.

[0112] If the first data Data<127:0> is wrong, the first check code Parity<7:0> is used as ABusParity<7:0> (that is, the lower 8 bits of the second check code), and the initial full check value NParity obtained by calculation is <8> After inversion, it is used as the full check code Parity <8> , ABusParity<7:0> and Parity <8> A second check code ABusParity<8:0> is formed, and the second data ABus<127:0> is sent after error correction of the first data Data<127:0>, and then the second check code ABusParity<8:0> and the second data ABus<127:0> are sent out through the output port.

[0113] If the first check code Parity<7:0> is wrong, the full check value error correction unit 1212 corrects the first check code Parity<7:0> as ABusParity<7:0> (i.e., the lower 8 bits of the second check code), and the initial full check value NParity obtained by calculation is <8> After inversion, it is used as the full check code Parity <8> , ABusParity<7:0> and Parity <8> The second check code ABusParity<8:0> is formed, the first data Data<127:0> is directly sent as the second data ABus<127:0>, and then the second check code ABusParity<8:0> and the second data ABus<127:0> are sent out through the output port.

[0114] In addition to first generating a full check value and then directly correcting the full check value based on the data error correction code and the check error correction code, it is also possible to first correct the error and then generate a full check value based on the correct data after the error correction.

[0115] Fig. 9 It is a sub-flowchart of step S3 in another embodiment of the present disclosure.

[0116] refer to Fig. 9 In another embodiment, step S3 may include:

[0117] Step S91, obtaining the verification result of the first data and the first verification code;

[0118] Step S92, when it is determined according to the verification result that neither the first data nor the first verification code has errors, performing an XOR operation on each bit of the first data and each bit of the first verification code to determine a full verification value, and generating a second verification code according to the full verification value and the first verification code;

[0119] Step S93, when it is determined according to the verification result that only the first data has an error, performing an XOR operation on each bit of the second data and each bit of the first verification code to determine a full verification value; and generating a second verification code according to the full verification value and the first verification code;

[0120] Step S94, when it is determined according to the verification result that only the first check code has an error, an XOR operation is performed on each bit of the first data and each bit of the first check code after error correction to determine a full check value, and a second check code is generated according to the full check value and the first check code after error correction.

[0121] Fig. 9 The illustrated embodiment can be applied when the first check code is other types of check codes other than the ECC check code, and has a more accurate processing result.

[0122] exist Fig. 9 In the illustrated embodiment, if only the first data has an error, the second data after error correction is directly used to generate the full check value, which requires that the error correction of the first data must be completed before the second check value is generated. If only the first check code has an error, it is necessary to first correct the error of the first check code and then generate the full check value, which requires that the error correction of the first check code must be completed before the full check value is generated. When the first check code is an ECC check code, Figure 7 Compared with the embodiment shown Fig. 9 The illustrated embodiment can rapidly generate a full check value, and based on the generation principle of the ECC check code, correct the full check value by a simple action of inversion, without waiting for error correction of the first data and error correction of the first check value. The two error corrections can run in parallel with the process of generating the full check value, and the data processing speed is faster.

[0123] To sum up, the data processing method provided by the embodiment of the present disclosure can directly generate and output a second check code based on the first data and the first check code while realizing error correction of the first data, so that the data receiving terminal can directly check and correct the second data finally output by the memory according to the second check code, thereby saving the functional requirements for the data receiving terminal, thereby reducing the number of components and layout area of ​​the data receiving terminal, and improving the compatibility of the memory.

[0124] It should be noted that, although several modules or units of the device for action execution are mentioned in the above detailed description, this division is not mandatory. In fact, according to the embodiments of the present disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. On the contrary, the features and functions of one module or unit described above can be further divided into multiple modules or units to be embodied.

[0125] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and examples are to be considered exemplary only, and the true scope and concept of the present disclosure are indicated by the claims.

Claims

1. A data error correction circuit, characterized in that: Settings in memory, including: a data error correction module, receiving first data and a first check code corresponding to the first data, the data error correction module being used to perform error correction on the first data according to the first check code to generate second data, and output the second data; A verification code generation module receives the first data and the first verification code, and is used to generate and output a second verification code according to the first data and the first verification code; The data error correction module comprises: an error correction code generating unit, receiving the first data and the first check code, and used to generate a data error correction code and a check error correction code according to the first data and the first check code; a data error correction unit, connected to the error correction code generation unit, configured to receive the first data and the data error correction code, and perform error correction on the first data according to the data error correction code to generate and output second data; The check code generation module is connected to the error correction code generation unit and receives the data error correction code and the check error correction code, and the check code generation module corrects the second check code according to the data error correction code or the check error correction code; The verification code generation module comprises: a full check value generating unit, connected to the error correction code generating unit, configured to receive the first data and the first check code, and generate a full check value according to the first data, the first check code and the data error correction code, or generate the full check value according to the first data, the first check code and the check error correction code, wherein the second check code includes the full check value; The full check value generating unit comprises: a full check value calculation unit, receiving the first data and the first check code, and used to generate an initial full check value according to the first data and the first check code; a full check value error correction unit, connected to the full check value calculation unit and the error correction code generation unit, configured to correct the initial full check value according to the data error correction code or the check error correction code and output the full check value; The verification code generation module comprises: A check code error correction unit is connected to the error correction code generation unit, receives the first check code, and is used to correct the first check code according to the check error correction code, wherein the second check code includes the first check code after error correction; the highest bit of the second check code is the full check value, and the first check code after error correction constitutes the remaining bits of the second check code.

2. The data error correction circuit according to claim 1, characterized in that: The full check value error correction unit is used to invert the initial full check value to generate the full check value after receiving the data error correction code or the check error correction code.

3. The data error correction circuit according to any one of claims 1 to 2, characterized in that: The initial full check value is obtained by performing an XOR calculation on each bit in the first data and each bit in the first check code.

4. The data error correction circuit according to claim 1, characterized in that: The first check code includes 8 bits of data.

5. A memory, characterized in that: include: The data error correction circuit according to any one of claims 1 to 4; A first output terminal, used for outputting second data; The second output terminal is used to output a second check code corresponding to the second data.

6. An integrated storage device, comprising: The memory as claimed in claim 5; The controller is connected to the memory and is used to receive the second data and the second check code, and to check and correct errors of the second data according to the second check code.

7. The integrated storage device according to claim 6, characterized in that: The controller determines whether there are multi-bit errors in the second data according to the second check code.

8. A data transmission method, characterized in that: Executed by the memory of claim 5, comprising: Acquire first data to be transmitted and a first check code corresponding to the first data; Performing error correction on the first data according to the first check code and the first data to generate second data; Generate a second check code according to the first data and the first check code; simultaneously outputting the second data and the second check code to the controller, so that the controller performs check and error correction on the second data according to the second check code; The error correction of the initial full check value to generate the full check value comprises: inverting the initial full check value to generate the full check value.

9. The data transmission method according to claim 8, characterized in that: Generating a second check code according to the first data and the first check code comprises: Performing an XOR operation on each bit of the first data and each bit of the first check code to generate an initial full check value; Obtaining a verification result of the first data and the first verification code; Generate the second check code according to the check result, the first check code and the full check value; The step of generating the second check code according to the check result, the first check code and the full check value comprises: When it is determined according to the verification result that an error occurs in the first verification code and no error occurs in the first data, correcting the initial full verification value to generate a full verification value, and correcting the first verification code; Generate the second check code according to the first check code after error correction and the full check value; When it is determined according to the verification result that the first verification code has no error and the first data has an error, correcting the initial full verification value to generate a full verification value; Generate the second check code according to the first check code and the full check value; When it is determined according to the verification result that neither the first data nor the first verification code has any error, the second verification code is generated according to the first verification code and the initial full verification value.

10. The data transmission method according to claim 8, characterized in that: Generating a second check code according to the first data and the first check code comprises: Obtaining a verification result of the first data and the first verification code; When it is determined according to the verification result that neither the first data nor the first verification code has any error, performing an XOR operation on each bit of the first data and each bit of the first verification code to determine a full verification value, and generating the second verification code according to the full verification value and the first verification code; When it is determined according to the verification result that only the first data has an error, performing an XOR operation on each bit of the second data and each bit of the first verification code to determine a full verification value; generating the second verification code according to the full verification value and the first verification code; When it is determined according to the verification result that only the first check code has an error, a full check value is determined by performing an XOR operation on each bit of the first data and each bit of the first check code after error correction, and the second check code is generated according to the full check value and the first check code after error correction.

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