A broadband high-isolation single-pole five-position switch

Abstract

The present invention relates to a broadband, high-isolation, single-pole, five-way switch, wherein first to fifth switches are connected in parallel to form a five-way channel circuit; a radio frequency input signal is input into the five-way channel circuit after passing through a first inductor; wherein each channel circuit includes: a second inductor, a third inductor, a first stacked MOS transistor, a second stacked MOS transistor, a third stacked MOS transistor, and a fourth stacked MOS transistor; the first stacked MOS transistor, the second inductor, the third inductor, and the fourth stacked MOS transistor are sequentially connected in series, the second stacked MOS transistor is connected between the second end of the second inductor and the ground terminal, and the third stacked MOS transistor is connected between the second end of the third inductor and the ground terminal; the channel circuit is turned on and off by controlling the gate control voltage and substrate control voltage of the first stacked MOS transistor, the second stacked MOS transistor, the third stacked MOS transistor, and the fourth stacked MOS transistor. The present invention compensates for the influence of parasitic capacitance on bandwidth through an inductor frequency compensation structure, and has the characteristics of low insertion loss, high bandwidth, and high isolation.

Description

Technical Field

[0001] The invention belongs to the field of radio frequency switch integrated circuits, and in particular relates to a broadband high-isolation single-pole five-position switch. Background Art

[0002] In modern wireless communication terminals, multiple frequency bands often share the same antenna for transmission and reception. Therefore, RF switches are integrated into RF front-end modules to control signal flow. RF switches also isolate the transmit and receive paths, making them a crucial component of RF transceivers. As mobile terminals support an increasing number of communication standards, RF switches must simultaneously meet the performance requirements of each.

[0003] To ensure signal power transmission and isolation between signal paths, RF switches must exhibit ultra-low loss and high isolation. As the final stage of the PA in the transmitter path, RF switches also require high power handling (typically measured by 0.1dB compression point). For example, the GSM protocol requires an output power handling capability of up to 35dBm. Furthermore, to ensure transmitter modulated signal quality and minimize intermodulation interference in the receiving path, RF switches must exhibit high linearity, typically measured by input second-order / third-order intercept points (IIP3 / IIP2) or harmonic levels at a specific input power.

[0004] In traditional RF switches, insertion loss, isolation, and bandwidth constrain each other. Improving insertion loss and isolation requires increasing the size of transistors, but at the same time, more parasitic capacitance is introduced, resulting in a decrease in bandwidth. Summary of the Invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a broadband high-isolation single-pole five-way switch. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0006] The present invention provides a broadband high-isolation single-pole five-way switch, comprising: a first inductor, a first switch, a second switch, a third switch, a fourth switch and a fifth switch;

[0007] The first end of the first inductor serves as an input end of the RF signal to input the RF input signal; the first switch, the second switch, the third switch, the fourth switch, and the fifth switch are connected in parallel to form a five-way channel circuit; the second end of the first inductor is respectively connected to the input end of each channel circuit;

[0008] Each channel circuit includes: a second inductor, a third inductor, a first stacked MOS transistor, a second stacked MOS transistor, a third stacked MOS transistor, and a fourth stacked MOS transistor; the first stacked MOS transistor, the second inductor, the third inductor, and the fourth stacked MOS transistor are sequentially connected in series, the second stacked MOS transistor is connected between the second end of the second inductor and the ground, and the third stacked MOS transistor is connected between the second end of the third inductor and the ground.

[0009] The first end of the first stacked MOS transistor serves as the input end of the channel circuit and is connected to the second end of the first inductor, and the second end of the fourth stacked MOS transistor serves as the output end of the channel circuit to output a radio frequency output signal;

[0010] The channel circuit is turned on and off by controlling the gate control voltage and substrate control voltage of the first stacked MOS transistor, the second stacked MOS transistor, the third stacked MOS transistor, and the fourth stacked MOS transistor.

[0011] In one embodiment of the present invention, each stacked MOS transistor includes a plurality of MOS transistors, a plurality of voltage-dividing resistors, a plurality of floating gate resistors, and a plurality of floating liner resistors;

[0012] The source and drain electrodes of the plurality of MOS tubes are sequentially connected and stacked to form a MOS tube stack structure; the voltage dividing resistor is connected in parallel between the drain and source electrodes of each MOS tube;

[0013] The gate of each MOS tube is connected to the first end of the corresponding floating gate resistor, and the second ends of all floating gate resistors are input with a gate control voltage;

[0014] The substrate of each MOS tube is connected to the first end of the corresponding floating resistor, and the second end of the floating resistor is input with a substrate control voltage.

[0015] In one embodiment of the present invention, the first stacked MOS transistor and the fourth stacked MOS transistor input a first gate control voltage and a first substrate control voltage; the second stacked MOS transistor and the third stacked MOS transistor input a second gate control voltage and a second substrate control voltage.

[0016] In one embodiment of the present invention, by controlling the first gate control voltage, the first substrate control voltage, the second gate control voltage and the second substrate control voltage, one of the five channel circuits is turned on and the other four channel circuits are turned off.

[0017] In one embodiment of the present invention, when the target channel circuit is turned on, the first gate control voltage is 2.5V, the first substrate control voltage is 0V, and the second gate control voltage and the second substrate control voltage are both -2.5V;

[0018] The first gate control voltage and the first substrate control voltage of the other channel circuits except the target channel circuit are both -2.5V, the second gate control voltage is 2.5V, and the second substrate control voltage is 0V.

[0019] Compared with the prior art, the present invention has the following beneficial effects:

[0020] The broadband, high-isolation single-pole, five-way switch of this invention achieves low insertion loss by stacking MOS transistors. An inductive frequency compensation structure compensates for the effect of parasitic capacitance introduced by large transistor size on bandwidth, thereby improving the switch's bandwidth. In each switch channel circuit, the stacked MOS transistors adopt a series-parallel-parallel-series combination, improving the switch's isolation and achieving low insertion loss, high bandwidth, and high isolation.

[0021] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the following preferred embodiments are specifically cited and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 This is a schematic diagram of a broadband, high-isolation, single-pole, five-position switch provided by an embodiment of the present invention;

[0023] Figure 2 This is a circuit schematic diagram of a MOS tube stack structure provided by an embodiment of the present invention;

[0024] Figure 3 2 is a frequency gain curve diagram of the input reflection coefficient S11 and the output-input transmission coefficient S21 of the MOS transistor stack structure provided by an embodiment of the present invention;

[0025] Figure 4 This is a frequency gain curve diagram of the MOS transistor stack structure provided by an embodiment of the present invention;

[0026] Figure 5 This is a graph showing the isolation of each off-channel of a broadband, high-isolation single-pole five-way switch provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0027] In order to further illustrate the technical means and effects adopted by the present invention to achieve the predetermined purpose of the invention, a broadband high-isolation single-pole five-position switch proposed in accordance with the present invention is described in detail below with reference to the accompanying drawings and specific embodiments.

[0028] The aforementioned and other technical contents, features, and effects of the present invention are clearly presented in the following detailed description of the specific embodiments in conjunction with the accompanying drawings. Through the description of the specific embodiments, a deeper and more specific understanding of the technical means and effects adopted by the present invention to achieve the intended purpose can be obtained. However, the accompanying drawings are provided for reference and illustration purposes only and are not intended to limit the technical solutions of the present invention.

[0029] Example 1

[0030] See Figure 1 , Figure 1 This is a schematic diagram of a broadband, high-isolation, single-pole, five-position switch provided by an embodiment of the present invention.

[0031] As shown in the figure, the present invention provides a broadband high-isolation single-pole five-way switch, including: a first inductor L1, a first switch CH1, a second switch CH2, a third switch CH3, a fourth switch CH4 and a fifth switch CH5.

[0032] In this embodiment, the first end of the first inductor L1 is used as the input end of the radio frequency signal to input the radio frequency input signal RF IN .

[0033] In this embodiment, a five-way channel circuit is formed by connecting the first switch CH1, the second switch CH2, the third switch CH3, the fourth switch CH4, and the fifth switch CH5 in parallel; the first inductor L1 serves as a coordination inductor for impedance matching, and its second end is connected to the input end of each channel circuit respectively; wherein the circuit structure of the five channel circuits is consistent, and the RF input signal RF IN After input, only one of the five channel circuits is turned on, and the other channels are turned off. The RF input signal RF IN After passing through the conduction channel, it is output to the output port of the channel ( Figure 1 RF1~RF5).

[0034] In an optional embodiment, each channel circuit includes: a second inductor L2, a third inductor L3, a first stacked MOS transistor MS1, a second stacked MOS transistor MS2, a third stacked MOS transistor MS3, and a fourth stacked MOS transistor MS4; the first stacked MOS transistor MS1, the second inductor L2, the third inductor L3, and the fourth stacked MOS transistor MS4 are connected in series in sequence, the second stacked MOS transistor MS2 is connected between the second end of the second inductor L2 and the ground end, and the third stacked MOS transistor MS3 is connected between the second end of the third inductor L3 and the ground end; the first end of the first stacked MOS transistor MS1 serves as an input end of the channel circuit and is connected to the second end of the first inductor L1, and the second end of the fourth stacked MOS transistor MS4 serves as an output end of the channel circuit to output a radio frequency output signal.

[0035] It is worth noting that the second inductor L2 and the third inductor L3 are connected in series to form an inductor frequency compensation structure, which is used to compensate for the impact of parasitic capacitance introduced by the stacked MOS transistors on the bandwidth, thereby improving the bandwidth of the switch. In addition, the first stacked MOS transistor MS1 and the second stacked MOS transistor MS2 are connected in series, and the third stacked MOS transistor MS3 and the fourth stacked MOS transistor MS4 are connected in parallel to improve the isolation of the switch channel.

[0036] In an optional embodiment, the channel circuit is turned on and off by controlling the gate control voltage and substrate control voltage of the first stacked MOS transistor MS1 , the second stacked MOS transistor MS2 , the third stacked MOS transistor MS3 and the fourth stacked MOS transistor MS4 .

[0037] See Figure 2 , Figure 2 This is a circuit schematic diagram of a MOS tube stacking structure provided by an embodiment of the present invention.

[0038] In an optional embodiment, each stacked MOS transistor includes multiple MOS transistors, multiple voltage-dividing resistors, multiple floating gate resistors, and multiple floating liner resistors.

[0039] The source and drain electrodes of multiple MOS tubes are sequentially connected and stacked to form a MOS tube stack structure; a voltage divider resistor is connected in parallel between the drain and source electrodes of each MOS tube; the gate electrode of each MOS tube is respectively connected to the first end of the corresponding floating gate resistor, and the second ends of all floating gate resistors are input with a gate control voltage; the substrate electrode of each MOS tube is respectively connected to the first end of the corresponding floating liner resistor, and the second ends of the floating liner resistors are input with a substrate control voltage.

[0040] In an optional embodiment, the first stacked MOS transistor MS1 and the fourth stacked MOS transistor MS4 input the first gate control voltage and the first substrate control voltage; the second stacked MOS transistor MS2 and the third stacked MOS transistor MS3 input the second gate control voltage and the second substrate control voltage.

[0041] In an optional embodiment, by controlling the first gate control voltage, the first substrate control voltage, the second gate control voltage and the second substrate control voltage, one of the five channel circuits is turned on and the other four channel circuits are turned off.

[0042] In an optional embodiment, when the target channel circuit is turned on, the first gate control voltage is 2.5V, the first substrate control voltage is 0V, and the second gate control voltage and the second substrate control voltage are both -2.5V; the first gate control voltage and the first substrate control voltage of other channel circuits except the target channel circuit are both -2.5V, the second gate control voltage is 2.5V, and the second substrate control voltage is 0V.

[0043] By way of example, the specific structure of the stacked MOS transistors is described by taking four MOS transistors as an example: each stacked MOS transistor includes: a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, a first voltage-dividing resistor R1_1, a second voltage-dividing resistor R1_2, a third voltage-dividing resistor R1_3, a fourth voltage-dividing resistor R1_4, a first floating resistor R2_1, a second floating resistor R2_2, a third floating resistor R2_3, a fourth floating resistor R2_4, a first floating gate resistor R3_1, a first floating gate resistor R3_2, a first floating gate resistor R3_3, and a first floating gate resistor R3_4.

[0044] In an optional embodiment, the first end of the first voltage-dividing resistor R1_1 is connected to the first end of the stacked MOS transistor, the drain of the first MOS transistor M1 is connected to the first end of the first voltage-dividing resistor R1_1, the source of the first MOS transistor M1 is respectively connected to the second end of the first voltage-dividing resistor R1_1 and the drain of the second MOS transistor M2, the gate of the first MOS transistor M1 is connected to the first end of the first floating gate resistor R3_1; the second end of the first voltage-dividing resistor R1_1 is connected to the first end of the second voltage-dividing resistor R1_2.

[0045] In an optional embodiment, the source of the second MOS transistor M2 is respectively connected to the drain of the third MOS transistor M3 and the second end of the second voltage-dividing resistor R1_2, the gate of the second MOS transistor M2 is connected to the first end of the first floating gate resistor R3_2; the second end of the second voltage-dividing resistor R1_2 is connected to the first end of the third voltage-dividing resistor R1_3.

[0046] In an optional embodiment, the source of the third MOS transistor M3 is respectively connected to the drain of the fourth MOS transistor M4 and the second end of the third voltage-dividing resistor R1_3, the gate of the third MOS transistor M3 is connected to the first end of the first floating gate resistor R3_3; the second end of the third voltage-dividing resistor R1_3 is connected to the first end of the fourth voltage-dividing resistor R1_4; the source of the fourth MOS transistor M4 is connected to the second end of the fourth voltage-dividing resistor R1_4; and the second end of the fourth voltage-dividing resistor R1_4 is connected to the second end of the stacked MOS transistor.

[0047] In an optional implementation, the second ends of the first floating gate resistor R3_1 , the first floating gate resistor R3_2 , the first floating gate resistor R3_3 , and the first floating gate resistor R3_4 are all connected to the gate control voltage terminal of the stacked MOS transistor.

[0048] In an optional embodiment, the first end of the first floating resistor R2_1 is connected to the substrate of the first MOS transistor M1, the first end of the second floating resistor R2_2 is connected to the substrate of the second MOS transistor M2, the first end of the third floating resistor R2_3 is connected to the substrate of the third MOS transistor M3, and the first end of the fourth floating resistor R2_4 is connected to the substrate of the fourth MOS transistor M4; the second ends of the first floating resistor R2_1, the second floating resistor R2_2, the third floating resistor R2_3 and the fourth floating resistor R2_4 are all connected to the substrate control voltage terminal of the stacked MOS transistors.

[0049] It is worth noting that the voltages at the gate and substrate ends of the transistor change together with the signals passing through the source and drain ends of the transistor, ensuring that the DC operating points of the gate-source, gate-drain, and gate-substrate voltages of the transistor do not change, maintaining the performance parameters of the transistor and significantly improving the linearity of the switching MOS tube.

[0050] See Figure 3 , Figure 3 1 is a frequency gain curve diagram of the input reflection coefficient S11 and the output-input transmission coefficient S21 of the MOS transistor stack structure provided by an embodiment of the present invention.

[0051] As shown in the figure, within the 0-20 GHz operating bandwidth, the channel circuit's input reflection coefficient, S11, is less than -10 dB, demonstrating good impedance matching. The output-input transmission coefficient, S21, the transmission gain from the input to the output of the conducting channel circuit, is greater than -2 dB, and the insertion loss is less than 0.5 dB within 10 GHz, indicating low insertion loss. Therefore, the 0-20 GHz operating bandwidth of this RF switch can meet the needs of a variety of RF microwave signal systems, including communication equipment and radars with diverse operating ranges, demonstrating its versatility.

[0052] See Figure 4 , Figure 4 This is a frequency gain curve diagram of the MOS transistor stack structure provided by an embodiment of the present invention.

[0053] To examine the linearity of the switch, the input 1dB compression point (IP1dB) of the circuit was simulated. From the figure, it can be concluded that the IP1dB of the RF switch is 31.5dBm, which can ensure that the RF switch can operate normally in complex electromagnetic environments and environments with strong interference.

[0054] See Figure 5 , Figure 5 This is a graph showing the isolation of each off-channel of a broadband, high-isolation single-pole five-way switch provided by an embodiment of the present invention.

[0055] As shown in the figure, S31, S32, S33, and S34 are the isolation curves for the disabled channels. The figure shows that the isolation between each disabled channel of the RF switch is greater than 55dB, demonstrating excellent isolation. This ensures good isolation between channels in a multi-channel system, improving system stability and anti-interference capabilities.

[0056] The broadband, high-isolation single-pole, five-way switch of this embodiment achieves low insertion loss by stacking MOS transistors. An inductive frequency compensation structure compensates for the effect of parasitic capacitance introduced by large transistor size on bandwidth, thereby improving the switch's bandwidth. In each switch channel circuit, the stacked MOS transistors adopt a series-parallel-parallel-series combination, improving the switch's isolation and achieving low insertion loss, high bandwidth, and high isolation.

[0057] It should be noted that, in this document, relational terms such as first and second are used solely to distinguish one entity or operation from another, and do not necessarily require or imply any actual relationship or order between these entities or operations. Furthermore, the terms "comprise," "include," or any other variations thereof are intended to encompass non-exclusive inclusion, such that an article or device comprising a list of elements includes not only those elements but also other elements not explicitly listed. Without further limitation, an element defined by the phrase "comprising a..." does not preclude the presence of additional identical elements in the article or device comprising the element. Terms such as "connected" or "connected" are not limited to physical or mechanical connections but may include electrical connections, whether direct or indirect. References to orientations or positional relationships, such as "upper," "lower," "left," and "right," are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate description and simplify the description of the present invention. They do not indicate or imply that the device or element referred to must have, be constructed, or operate in a specific orientation, and are therefore not to be construed as limiting the present invention.

[0058] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.

Claims

1. A broadband high isolation single-pole five-position switch, characterized in that: include: a first inductor (L1), a first switch (CH1), a second switch (CH2), a third switch (CH3), a fourth switch (CH4), and a fifth switch (CH5); The first end of the first inductor (L1) is used as an input end of the radio frequency signal to input the radio frequency input signal (RF IN ); a five-way channel circuit formed by connecting the first switch (CH1), the second switch (CH2), the third switch (CH3), the fourth switch (CH4) and the fifth switch (CH5) in parallel; The second end of the first inductor (L1) is respectively connected to the input end of each channel circuit; Each channel circuit includes: a second inductor (L2), a third inductor (L3), a first stacked MOS transistor (MS1), a second stacked MOS transistor (MS2), a third stacked MOS transistor (MS3) and a fourth stacked MOS transistor (MS4); The first stacked MOS transistor (MS1), the second inductor (L2), the third inductor (L3) and the fourth stacked MOS transistor (MS4) are sequentially connected in series; the second stacked MOS transistor (MS2) is connected between the second end of the second inductor (L2) and the ground end; and the third stacked MOS transistor (MS3) is connected between the second end of the third inductor (L3) and the ground end; The first end of the first stacked MOS transistor (MS1) serves as the input end of the channel circuit and is connected to the second end of the first inductor (L1); the second end of the fourth stacked MOS transistor (MS4) serves as the output end of the channel circuit and outputs a radio frequency output signal; The channel circuit is turned on and off by controlling the gate control voltage and substrate control voltage of the first stacked MOS transistor (MS1), the second stacked MOS transistor (MS2), the third stacked MOS transistor (MS3) and the fourth stacked MOS transistor (MS4).

2. The broadband high-isolation single-pole five-position switch according to claim 1, characterized in that: Each stacked MOS tube includes multiple MOS tubes, multiple voltage divider resistors, multiple floating gate resistors and multiple floating liner resistors; The source and drain electrodes of the plurality of MOS tubes are sequentially connected and stacked to form a MOS tube stack structure; The voltage dividing resistor is connected in parallel between the drain and source of each MOS tube; The gate of each MOS tube is connected to the first end of the corresponding floating gate resistor, and the second ends of all floating gate resistors are input with a gate control voltage; The substrate of each MOS tube is connected to the first end of the corresponding floating resistor, and the second end of the floating resistor is input with a substrate control voltage.

3. The broadband high-isolation single-pole five-position switch according to claim 2, characterized in that: The first stacked MOS transistor (MS1) and the fourth stacked MOS transistor (MS4) input a first gate control voltage and a first substrate control voltage; The second stacked MOS transistor (MS2) and the third stacked MOS transistor (MS3) input a second gate control voltage and a second substrate control voltage.

4. The broadband high-isolation single-pole five-position switch according to claim 3, characterized in that: By controlling the first gate control voltage, the first substrate control voltage, the second gate control voltage and the second substrate control voltage, one channel circuit among the five channel circuits is turned on and the other four channel circuits are turned off.

5. The broadband high-isolation single-pole five-position switch according to claim 4, characterized in that: When the target channel circuit is turned on, the first gate control voltage is 2.5V, the first substrate control voltage is 0V, and the second gate control voltage and the second substrate control voltage are both -2.5V; The first gate control voltage and the first substrate control voltage of the other channel circuits except the target channel circuit are both -2.5V, the second gate control voltage is 2.5V, and the second substrate control voltage is 0V.

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