Master control redundancy device and master control redundancy management method

Abstract

The application relates to a master control redundancy device and a master control redundancy management method, which comprises m single boards, n master control boards in the m single boards, m and n are integers, n>=2; the m single boards are connected to an information line, slot information and type information of all the single boards are obtained through the information line; the pth master control board is connected to other single boards through a pth master control in-position interrupt line, in-position information of the pth master control board is sent to other single boards, p belongs to n; the pth master control board is connected to other master control boards through a pth handshaking line, handshaking information is sent to other master control boards; master control boards and standby master control boards are elected through handshaking information between the n master control boards; the pth master control board is connected to other single boards through a pth master-standby interrupt line, master-standby states of the pth master control board are sent to other single boards, the master-standby states correspond to election results of master control boards and standby master control boards. The application increases hardware participation in master-standby competition, and accelerates the time for a board to obtain a role state.

Description

Technical Field

[0001] The present application relates to the field of network transmission technology, and in particular to a master control redundancy device and a master control redundancy management method. Background Art

[0002] In the existing modular switch architecture, the active and standby master controllers are responsible for managing all devices within the entire chassis, presenting a unified management interface to the outside world. The active and standby master controllers serve as dual master control management units to maintain redundancy.

[0003] In existing modular switch architectures, active / standby master control switching is implemented as follows: During the startup and switchover processes, the software in each master and standby control periodically reads their respective board information (the active and standby boards). Based on this information, the software then performs a series of operations, including synchronous board elections (i.e., active / standby competition), without hardware active / standby competition. This requirement for the software to periodically read board information results in long dual-master control startup times, lengthy active / standby master switchovers, and slow interface board registration. This prevents rapid board switching management (active / standby) in modular switches. Summary of the Invention

[0004] In view of the above problems in the prior art, the present application provides a master control redundancy device and a master control redundancy management method to solve the problems of simply using software for master-slave competition, the need for software to periodically read board information when switching between master controls, resulting in long dual master control startup time, long switching process between the primary master control and the backup master control, and slow interface board registration.

[0005] To achieve the above object, the first aspect of the present application provides a master control redundancy device, comprising: m single boards, wherein the m single boards include n main control boards, where m and n are integers, and n>=2; wherein,

[0006] The m boards are connected to an information line, and each board is used to obtain slot information and type information of all boards through the information line, where the type in the type information includes the main control board type;

[0007] The pth main control board is connected to other boards through the pth main control presence interrupt line, which is used to send the pth main control board presence information to other boards, p∈n;

[0008] The pth main control board is also connected to the other main control boards through the pth handshake line, and is used to send handshake information to the other main control boards; the n main control boards elect the main control board and the backup main control board through the handshake information between them;

[0009] The pth master board is also connected to other single boards through a pth master-standby interrupt line, for sending a master-standby state of the pth master board to other single boards, and the master-standby state corresponds to the election result of the master master board and the standby master board.

[0010] From the above, the application sends handshake information to other master boards through the handshake line between master boards, and performs election of the master master board and the standby master board according to the handshake information, so that the hardware participates in the master-standby competition, and the master-standby state of the master board is sent to other single boards through the master-standby interrupt line, so that the participation of the hardware master-standby competition accelerates the time for the board (software) to obtain the role state through the interrupt, and further shortens the dual-master starting time, the master-standby master switching process time and the interface board registration time.

[0011] The second aspect of the application provides a master redundancy management method, applied to the master redundancy device of the first aspect, and including:

[0012] Each single board in the m single boards obtains slot information and type information of all single boards through an information line, and the type in the type information includes a master board type;

[0013] A pth master board in n master boards of the master board type sends in-service information of the pth master board to other single boards through a pth master in-service interrupt line;

[0014] The pth master board in service also sends handshake information to other master boards through a pth handshake line;

[0015] The n master boards perform election of a master master board and a standby master board through the handshake information between the master boards;

[0016] The pth master board also sends a master-standby state of the pth master board to other single boards through a pth master-standby interrupt line, and the master-standby state corresponds to the election result of the master master board and the standby master board;

[0017] Each single board of a non-master master board registers to the elected master master board according to the slot information and the type information.

[0018] The third aspect of the application provides a computing device, including:

[0019] A processor, and

[0020] A memory having program instructions stored thereon, the program instructions causing the processor to execute the method of any of the second aspect when executed by the processor.

[0021] The fourth aspect of the present application provides a computer readable storage medium having program instructions stored thereon, which, when executed by a computer, cause the computer to implement any of the methods of the second aspect described above. BRIEF DESCRIPTION OF DRAWINGS

[0022] Figure 1 is a hardware interface diagram of a master redundancy device provided by an embodiment of the present application;

[0023] Figure 2 is a state machine diagram of a master board in a master-backup competition provided by an embodiment of the present application;

[0024] Figure 3 is a schematic diagram of a master-backup switching process caused by a system running provided by an embodiment of the present application;

[0025] Figure 4 is a schematic diagram of a master redundancy management method provided by an embodiment of the present application;

[0026] Figure 5 is a schematic diagram of a software participating in a master-backup competition provided by an embodiment of the present application;

[0027] Figure 6 is a management initialization flowchart of a frame switch provided by an embodiment of the present application;

[0028] Figure 7 is a structural block diagram of a computing device provided by an embodiment of the present application.

[0029] It should be understood that in the above structural diagrams, the size and shape of each block diagram are only for reference, and should not constitute an exclusive interpretation of the embodiments of the present application. The relative position and inclusion relationship between the blocks presented by the structural diagrams are only used to represent the structural association between the blocks, and not to limit the physical connection mode of the embodiments of the present application. DETAILED DESCRIPTION

[0030] The technical solutions provided by the present application will be further described below in conjunction with the drawings and embodiments. It should be understood that the system structure and business scenarios provided in the embodiments of the present application are mainly used to illustrate possible implementation modes of the technical solutions of the present application, and should not be interpreted as the only limitation of the technical solutions of the present application. Those skilled in the art can know that the technical solutions provided by the present application are also applicable to similar technical problems as the system structure evolves and new business scenarios appear.

[0031] It should be understood that the dual-master fast redundancy management scheme provided by the embodiments of the present application includes a master redundancy device and a master redundancy management method. Since the principles of the technical solutions for solving problems are the same or similar, in the introduction of the following specific embodiments, some repetitions can not be described again, but should be regarded as mutual reference and mutual combination between the specific embodiments.

[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. If there is an inconsistency, the meaning in the specification or the meaning derived from the content described in the specification shall prevail. In addition, the terms used herein are only for the purpose of describing the embodiments of the present application and are not intended to limit the present application. In order to accurately describe the technical content in the present application, and in order to accurately understand the present application, before the specific embodiments are described, the terms used in the present specification are first explained as follows:

[0033] 1) Master board (MPU, Main Processing Unit): responsible for the control plane of the entire system.

[0034] 2) Interface board (LPU, Line Processing Unit): the line processing unit is a module on the physical device for providing data forwarding function, providing optical ports and electrical ports of different rates. The interface boards are connected through the switching network board, and the communication between the interface boards is uniformly forwarded through the switching network board.

[0035] 3) Redundant design, also known as redundant design technology, is to add one or more functional channels, working elements or components to complete the same function at the key position of the system or device to complete the task, so that when the part fails, the system or device can still work normally, to reduce the failure probability of the system or device and improve the system reliability.

[0036] In the existing frame switch architecture, the switching between the active master and the standby master only uses software to periodically read the respective board information (the board information of the active master board and the standby master board), and then the software implements a series of operations such as synchronous election between the boards (i.e., active-standby competition) based on the board information. There is no participation of hardware active-standby competition, which will lead to problems such as long dual-master startup time, long active-master and standby master switching process, slow interface board registration, etc., and cannot achieve the management of fast switching of boards (active-master and standby master) in the frame switch. Based on this, the present application sends handshake information to other main control boards through the handshake line between the main control boards, and elects the active main control board and the standby main control board according to the handshake information, thereby increasing the participation of hardware in active-standby competition, and sending the active-standby status of the main control board to other boards through the active-standby interrupt line. The participation of hardware active-standby competition speeds up the time for the board (software) to obtain the role status through interruption, thereby shortening the dual-master startup time, the active-master and standby master switching process time, and the registration time of the interface board.

[0037] The present application can be applied to any switch where a primary master controller and a backup master controller compete for switching.

[0038] The present application proposes a master control redundancy device, which is described in detail below.

[0039] In some embodiments, the master control redundancy device includes: m single boards, wherein the m single boards include n master control boards, where m and n are integers, and n>=2; wherein,

[0040] The m boards are connected to an information line, and each board is used to obtain slot information and type information of all boards through the information line, where the type in the type information includes the main control board type;

[0041] The pth main control board is connected to other boards through the pth main control presence interrupt line, which is used to send the pth main control board presence information to other boards, p∈n;

[0042] The pth main control board is also connected to the other main control boards through the pth handshake line, and is used to send handshake information to the other main control boards; the n main control boards elect the main control board and the backup main control board through the handshake information between them;

[0043] The pth main control board is also connected to other boards via the pth master-slave interrupt line, and is used to send the master-slave status of the pth main control board to other boards. The master-slave status corresponds to the election result of the active main control board and the backup main control board.

[0044] From the above, this application sends handshake information to other main control boards through the handshake line between the main control boards, elects the main control board and the backup main control board according to the handshake information, increases the hardware participation in the master-slave competition, and sends the master-slave status of the main control board to other boards through the master-slave interrupt line. The participation of the hardware master-slave competition speeds up the time for the board (software) to obtain the role status through interrupts, thereby shortening the dual master startup time, the time of the master and backup master switching process, and the registration time of the interface board.

[0045] In some embodiments, the m single boards further include q interface boards, where q is an integer, q<=mn;

[0046] The q1 interface board is connected to each main control board through the q1 interface board in-position interrupt line, and is used to send the q1 interface board in-position information to each main control board, q1∈q;

[0047] The types of all the single boards obtained by each single board through the information line also include the interface board type.

[0048] In the above embodiments, Figure 1 The master redundant device shown is used as an example for explanation.

[0049] like Figure 1 As shown, the main control redundancy device may include 4 single boards, and the 4 single boards include 2 main control boards (main control boards A\B) and 2 interface boards (interface boards A\B).

[0050] Connect the main control board A\B and the interface board A\B to the information line; obtain the corresponding slot information and type information through the information line;

[0051] Main control board A is connected to main control board B and interface boards A and B through the main control board A in-place interrupt line. Main control board B is connected to main control board A and interface boards A and B through the main control board B in-place interrupt line. The in-place interrupt lines of interface boards A and B are connected to main control boards A and B. In-place information is sent through the in-place interrupt lines.

[0052] Main control board A is connected to main control board B via handshake line A, and main control board B is connected to main control board A via handshake line B. Handshake messages are sent via the handshake lines to elect the active and standby main control boards.

[0053] Main control board A is connected to main control board B and interface boards A and B through master / slave interrupt line A. Main control board B is connected to main control board A and interface boards A and B through master / slave interrupt line B. The master / slave interrupt lines transmit the master / slave status corresponding to the election results of the active and standby main control boards.

[0054] This device is a hardware device and may have the following requirements:

[0055] 1. The hardware needs to provide single board (main control board A\B and interface board A\B) in place information, the main control needs to sense all single board in place information, the interface board needs to sense the main master and standby master in place information; if plugging occurs, an interrupt signal is needed to notify;

[0056] 2. The interface board needs to know the slot of the main master and standby master and the master and standby state; when the main master changes, an interrupt should be notified;

[0057] 3. The software (existing on the main control board A and the main control board B) processing master and standby switching time is too slow, the hardware needs to participate in the master and standby competition, and the hardware can quickly notify the software to obtain information through the interrupt;

[0058] 4. The interface board hardware signal requirements are as shown in Table 1:

[0059] Table 1

[0060]

[0061]

[0062] 5. The main control hardware signal line requirements are as shown in Table 2:

[0063] Table 2

[0064]

[0065]

[0066] The hardware participating in the master and standby competition proposed in the application is completed in the device management initialization stage, which includes the power-on startup stage of the main control. Therefore, when starting up, the software has not yet driven the handshake line, so there is no handshake signal between the two main controls, and both main controls think that they have not started and set their master and standby interrupt lines to standby state (assuming that the two master and standby interrupt lines are both 00).

[0067] In some embodiments, the election of the master control board and the standby control board between the n main control boards is performed through handshake information between them, including:

[0068] During the startup process, the first main control board that starts up successfully first sends handshake information, and the main control board that first sends the handshake information is elected as the master control board, and the other main control boards are standby control boards.

[0069] In this embodiment, it is assumed that master board A starts successfully first, then the FPGA of master board A detects the handshake signal, and the FPGA of master board B also detects the handshake signal of master board A, then master board A writes 1 to its master / standby interrupt line (i.e. the two master / standby interrupt lines are 10), indicating that master board A is the master, and reports the two masters (the interface board also reports at the same time) through the interrupt, then master board A becomes the master, and master board B becomes the standby. Conversely, if master board B starts successfully first, then master board B becomes the master.

[0070] In this embodiment, when one master board detects the handshake signal first, it can directly elect the master board as the master.

[0071] In some embodiments, the election of the master and standby master among the n master boards through the handshake information between the master boards comprises:

[0072] In the starting process, at least two master boards that start successfully first simultaneously send the handshake information, and the master board with the largest or smallest slot information among the master boards that start successfully first is elected as the master, and the other master boards are standby.

[0073] In this embodiment, it is assumed that master board A and master board B start simultaneously, simultaneously perform handshake, and simultaneously set the master / standby interrupt line A and the master / standby interrupt line B to 1 (i.e. the two master / standby interrupt lines are 11), and perform the interrupt reporting software, the software identifies that the two master boards are both masters, then according to the slot information (i.e. the slot number), the master board with the smaller slot is the master, and the master board with the larger slot is the standby. If the slot of master board B is larger, then master board B voluntarily becomes the standby, and simultaneously triggers an interrupt to the software (on master board A and master board B), and the software judges that the master / standby competition is completed.

[0074] In this embodiment, when two master boards simultaneously receive the handshake signal of the other, it is considered that there are two masters, and the master needs to be determined according to the slot information of each master.

[0075] Figure 2 is a state machine diagram of a master board in the master / standby competition provided by the embodiment of the application, as shown in Figure 2As shown in the figure, the main control board can include 7 states, among which state 1 is CARD_NONE state, that is, the board is not detected in place; state 2 is CARD_INSERTED state, that is, the board is detected in place, but the board type and slot information are not correctly identified; state 3 is CARD_INITIALIZING state, that is, the frame type, board type and slot information are correctly identified, and the main control board enters the active-standby competition state, from which the hardware participates in the active-standby competition; state 4 is CARD_REGISTRING state, that is, after the active-standby competition, the main control board becomes the standby main control board. , and then follow the same process as the interface board; State 8 is the CARD_DISCOVERING state, that is, after the active-standby competition, the master becomes the master controller. After this state, all the boards on the chassis enter the stage of registering as the master controller. The state of state 8 means that all the boards on the chassis have not completed registration, or the waiting time for registration has not timed out; State 9 is the CARD_READY state, that is, all the boards on the chassis have completed registration, or the waiting time for registration has timed out; State 12 is the CARD_RUNNING state, that is, after all the boards on the chassis have completed registration, the configuration information is downloaded to the corresponding interface board.

[0076] In some embodiments, the n main control boards elect a master main control board and a backup main control board through handshake information between the n main control boards, including:

[0077] During operation, if the standby main control board fails to obtain the handshake information of the active main control board, the standby main control board will be elected as the active main control board, and the other main control boards will be elected as standby main control boards.

[0078] In these embodiments, during operation, if the backup master controller finds that it has not received the handshake signal from the primary master controller, it will pull up its own primary-standby interrupt line (and also pull down the other party's primary-standby interrupt line). At this time, there are several situations for the other party. The first is that the CPU (primary master controller) crashes, then the logic of the other party (primary master controller) can also detect that there is no handshake, and it will pull down its own primary-standby interrupt line. The second is that the power is off or the single board is unplugged, then the primary-standby interrupt line is required to become low in this case; the third is that the logic is dead, in which case only the backup master controller can pull down the other party's primary-standby interrupt line.

[0079] In this embodiment, when the active master controller fails to send a handshake signal, a new active master controller needs to be elected from all standby master controllers.

[0080] In some embodiments, selecting a master main control board from the standby main control boards includes:

[0081] The standby main control board that first sends the master / slave status switch signal through the master / slave interrupt line will be elected as the master main control board.

[0082] In the embodiments, when multiple standby master control boards are included, the standby master control board that pulls its master standby interrupt line high to 1 is elected as the master master control board. When multiple standby master control boards simultaneously pull their master standby interrupt lines high to 1, then according to the slot positions of the standby master control boards, it is determined which standby master control board is elected as the master master control board.

[0083] In some embodiments, after the interface board A / B obtains the master standby state of the master control board A / B through the master standby interrupt line A / B, the interface board A / B completes registration on the master master control board according to the master standby state.

[0084] In the embodiments, if the interface board finds that two master master controls or two standby master controls occur, it is silent and does not register, and if it is found that the master standby relationship changes during half of the registration, it is reset and re-registered. If it is already in a RUNNING running state, it is not reset, but only the slot position of the master master control is modified.

[0085] The switch also causes the master standby switching during operation, and the specific master standby switching process is as shown in Figure 3 , which includes:

[0086] 1. The standby master control detects event poll (i.e. detects whether there is a specific event);

[0087] 2. When the standby master control detects event poll, it is determined whether the master master control is pulled out, if so, the devsm daemon process is interrupted to report (i.e. interrupt reporting); if not, the standby master control monitors whether the master master control heartbeat is timed out;

[0088] 3. If it is timed out, the standby master control reads the master control backup data, the standby master control sends the unregistration information to the interface board to inform the interface board that the board is upgraded;

[0089] 4. The interface board sends a registration message to the standby master control; that is, after the interface board receives the unregistration message of the standby master control, it monitors the state of the original master master control, confirms the master change, unregisters the original master master control, and reinitiates the registration information to complete the registration of the new master master control;

[0090] 5. The standby master control starts the master control board state machine after being upgraded.

[0091] The application provides a master control redundancy management method, which is described in detail below.

[0092] Figure 4 is a flowchart of a master control redundancy management method provided by the embodiments of the application, as shown in Figure 4 , the master control redundancy management method is applied to the master control redundancy device described above, and includes:

[0093] S21: Each single board in the m single boards acquires slot information and type information of all single boards through an information line, and the type in the type information includes a master control board type;

[0094] S22: A pth master control board in the n master control boards of the master control board type sends in-place information of the pth master control board to other single boards through a pth master control in-place interrupt line;

[0095] S23: The in-place pth master control board also sends handshake information to other master control boards through a pth handshake line;

[0096] S24: The n master control boards elect a master master control board and a standby master control board through the handshake information between the master control boards;

[0097] S25: The pth master control board also sends a master standby state of the pth master control board to other single boards through a pth master standby interrupt line, and the master standby state corresponds to an election result of the master master control board and the standby master control board;

[0098] S26: Each single board of a non-master master control board registers with the elected master master control board according to the slot information and the type information.

[0099] In some embodiments, the master control redundancy management method further comprises:

[0100] The types in the type information of all single boards acquired by each single board through the information line further include an interface board type;

[0101] A q1th interface board in the m single boards of the interface board type sends in-place information of the q1th interface board to each master control board through a q1th interface board in-place interrupt line.

[0102] In some embodiments, the election of the master master control board and the standby master control board through the handshake information between the n master control boards includes one of the following:

[0103] In a startup process, a first master control board that starts successfully first sends handshake information, the master control board that first sends the handshake information is elected as the master master control board, and other master control boards are standby master control boards;

[0104] In a startup process, at least two master control boards that start successfully first simultaneously send handshake information, a master control board with maximum / minimum slot information among the master control boards that start successfully first is elected as the master master control board, and other master control boards are standby master control boards;

[0105] In a running process, a master master control board is elected from standby master control boards when a standby master control board does not acquire handshake information of the master master control board, and other master control boards are standby master control boards.

[0106] In addition to the hardware participation, the software participation is also needed in the master-backup competition. The software participation in the master-backup competition is introduced in detail as follows.

[0107] Figure 5 is a flowchart of the software participation in the master-backup competition provided by the embodiment of the application. As shown in Figure 5 the detailed flowchart of the software master-backup competition in the initialization stage of the device is as follows.

[0108] S31: the processor of a master board receives a master-backup change interrupt signal (READY change interrupt, that is, handshake state change interrupt), and can also receive a system initialization message, a master plug-in interrupt message, etc.

[0109] S32: lock task and interrupt operation are performed; wherein, the task refers to the master-backup competition task.

[0110] S33: whether the board is in place is judged. If not, the board is reduced to a backup master, and the interrupt is opened, the task is unlocked, and the process is completed. If in place, S34 is executed.

[0111] S34: whether the other master board is in place is judged. If not, the board is raised to a master master, and the interrupt is opened, the task is unlocked, and the process is completed. If in place, S35 is executed.

[0112] S35: whether the board is a master master is judged. If yes, the interrupt is opened, the task is unlocked, and the process is completed. If not, S36 is executed.

[0113] S36: whether the other master board is a master master is judged through the master-backup interrupt line of the other master board. If yes, S37 is executed. If not, S38 is executed. The master-backup interrupt line of the other master board is pulled high, indicating that the other master board is a master master. The master-backup interrupt line of the other master board is pulled low, indicating that the other master board is a backup master.

[0114] S37: whether the other master board is a master master is judged through the handshake line of the other master board. If yes, the board is kept in a backup state, the interrupt is opened, the task is unlocked, and the process is completed. If not, the board is raised to a master, the interrupt is opened, the task is unlocked, and the process is completed. The other master board sends a handshake signal through the handshake line, indicating that it is a master master. If the other master board does not send a handshake signal through the handshake line, the other master board has a problem, and the master board is raised.

[0115] S38: the board is raised to a master, waits for 100us, and notifies the other master board, and S39 is executed.

[0116] S39: whether the master-backup interrupt line of the other master board is a master master is judged. If not, the board is kept in a master master state, the interrupt is opened, the task is unlocked, and the process is completed. If yes, S310 is executed.

[0117] S310: Determine whether the slot position of this board is low. If so, keep this board in the master control state, enable interruption, unlock the task, and complete. If not, downgrade this board to standby state, enable interruption, unlock the task, and complete.

[0118] In addition, if there is only one master controller, upgrade it directly.

[0119] The process of master-slave competition may be interrupted. Therefore, it is necessary to ensure that before each master-slave competition is completed, no new master-slave competition processing is allowed in the middle, so it is necessary to lock the master-slave competition task.

[0120] During the initialization process of device management, the active / standby competition process is complete. After the active / standby competition is complete, the system master controller will experience the following situations:

[0121] Dual-active master control: This situation generally does not occur unless there is a problem with the hardware logic or the backplane (the board used to plug in the master control board);

[0122] Dual standby master controllers: This situation may occur when the software on both master controllers is abnormal, or there is a problem with the hardware logic or backplane.

[0123] Furthermore, when the system clock is interrupted, the software periodically feeds the logic (i.e., the software periodically transmits a handshake signal to the master FPGA) during the clock interrupt, notifying the board that the status is READY, and then executing S31. However, if the system crashes or a manual master-slave switch is performed, the software will not periodically feed the logic with READY. If the logic detects that READY is not being fed, it will invalidate its own READY signal. The hardware will then downgrade the master-slave interrupt line to standby and simultaneously notify the other party of the interrupt.

[0124] The preceding describes the software and hardware active / standby contention during device initialization. The following describes the device management initialization process in detail from an overall perspective.

[0125] Figure 6 This is a management initialization flow chart of a modular switch provided in an embodiment of the present application; Figure 6 As shown in the figure, the management initialization process of the modular switch includes:

[0126] S41: Read the CARD_IN signal (in-position information) of the hardware board. For details, refer to the BootROM startup process. Only after the FPGA is successfully initialized can the chassis type and other information be identified. Therefore, the prerequisite for starting device management is that the FPGA is started normally.

[0127] S42: Determine whether the board is in place based on the CARD_IN signal. If not, execute S43; if so, execute S44.

[0128] S43: If a board is not in place, a message indicating that the board is not in place is printed, the device management initialization process is exited, and the system is directly booted. After booting, if the main control unit of the entire chassis is in place and a board is detected, the board state will be set to REBOOT if the registration fails within a timeout.

[0129] S44: Identify and record the board type and slot information;

[0130] S45: Determine whether the board is a main control board. If it is a main control board (either a primary main control board or a backup main control board), execute S46. If it is not a main control board, execute S47.

[0131] S46: If it is a main control board, register the frame information (including frame slot information), and register the board slot information and single board type; that is, if it is identified as a main control board (whether it is the main control board or the backup control board), register the frame information, the slot information on the frame, the board type, the board slot, etc.

[0132] S47: Determine whether it is a switch board. If not, execute S48; if it is a switch board, execute S49-S411.

[0133] S48: If it is not a switch board, print a board type identification error message and reset the board.

[0134] S49: If it is a switch board, register the board slot information and board type, and execute S413;

[0135] S410: Obtain the master control information based on the hardware master / standby interrupt line and record the master control information (i.e., register the master control based on the hardware master / standby interrupt line), and execute S411; (If the master control changes, the logic will report the interrupt to the interface board, and the interface board will modify the master control information).

[0136] S411: Starts registering and interacting with the active master controller. If the board identifies itself as an interface board, it registers its board type and slot number, and registers the active master controller using the hardware master / slave interrupt lines. Subsequently, the board communicates with the active master controller. If the active master controller changes, the logic reports an interrupt to the interface board, which then updates the active master controller information.

[0137] S412: After executing S46, determine whether another main control is in place. If not, execute S413-S414. If so, reduce the current board to standby (depending on the logic design) and then execute S415.

[0138] S413: If the other master controller is not in place, the board is promoted to master, and then S414 is executed;

[0139] S414: After the board registration is complete, the port devices on the chassis are initialized.

[0140] S415: After the board is reduced, it is judged whether the board participates in the master backup competition to upgrade the master (here it involves the software master backup competition and hardware master backup competition mentioned above), if yes, S413 is executed, if not, S411 is executed. That is, if it is the master, according to the information of the hardware master backup interrupt line, it is confirmed whether it is the master or the backup, if it is the master, it responds to the registration information of the interface board and the backup master, and the upgrade information. If it is the backup, it goes to the interface board flow, and registers with the master, etc.

[0141] Figure 7 is a structural schematic diagram of a computing device 900 provided by an embodiment of the present application. The computing device can be used as a master redundant device to execute the optional embodiments of the master redundant management method described above. The computing device can be a terminal, or a chip or chip system inside the terminal. As shown in the figure, the computing device 900 includes a processor 910, a memory 920, and a communication interface 930. Figure 7

[0142] It should be understood that Figure 7 The communication interface 930 in the computing device 900 shown in the figure can be used for communication with other devices, and can specifically include one or more transceiver circuits or interface circuits.

[0143] The processor 910 can be connected with the memory 920. The memory 920 can be used to store program codes and data. Therefore, the memory 920 can be a storage unit inside the processor 910, or an external storage unit independent of the processor 910, or a component including the storage unit inside the processor 910 and the external storage unit independent of the processor 910.

[0144] Optionally, the computing device 900 can further include a bus. The memory 920 and the communication interface 930 can be connected with the processor 910 through the bus. The bus can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For the convenience of representation, Figure 7 In the figure, a line without an arrow is used to represent, but it does not mean that there is only one bus or one type of bus.

[0145] ​It should be understood that in the embodiment of the present application, the processor 910 can adopt a central processing unit (CPU). The processor can also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc. Alternatively, the processor 910 adopts one or more integrated circuits to execute relevant programs to implement the technical solutions provided in the embodiments of the present application.

[0146] The memory 920 may include a read-only memory and a random access memory, and provides instructions and data to the processor 910. A portion of the processor 910 may also include a non-volatile random access memory. For example, the processor 910 may also store information about the device type.

[0147] When the computing device 900 is running, the processor 910 executes the computer-executable instructions in the memory 920 to perform any operation step of the above method and any optional embodiment thereof.

[0148] It should be understood that the computing device 900 according to the embodiment of the present application can correspond to the corresponding subject in executing the method according to each embodiment of the present application, and the above-mentioned and other operations and / or functions of each module in the computing device 900 are respectively for implementing the corresponding processes of each method of the present embodiment. For the sake of brevity, they will not be repeated here.

[0149] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0150] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0151] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0152] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0153] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0154] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0155] An embodiment of the present application also provides a computer-readable storage medium having a computer program stored thereon. When the program is executed by a processor, it is used to execute the above method, which includes at least one of the solutions described in the above embodiments.

[0156] The computer storage medium of the embodiment of the present application can adopt any combination of one or more computer-readable media.Computer-readable media can be computer-readable signal media or computer-readable storage media.Computer-readable storage media can be, for example, but not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or components, or any combination thereof.More specific examples (non-exhaustive list) of computer-readable storage media include: electrical connection with one or more wires, portable computer disks, hard disks, random access memories (RAM), read-only memories (ROM), erasable programmable read-only memories (EPROM or flash memory), optical fibers, portable compact disk read-only memories (CD-ROMs), optical storage devices, magnetic storage devices, or any suitable combination thereof.In this document, computer-readable storage media can be any tangible medium containing or storing a program, which can be used by an instruction execution system, device or device or used in combination with it.

[0157] A computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, which carries computer-readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium that can transmit, propagate, or transport a program for use by or in conjunction with an instruction execution system, apparatus, or device.

[0158] Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

[0159] The computer program code for performing the operations of the present application can be written in one or more programming languages, or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, C++, and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computer (e.g., through the Internet using an Internet service provider).

[0160] In addition, the words "first, second, third, etc." or module A, module B, module C and other similar terms in the specification and claims are only used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that the specific order or sequence can be interchanged where permitted so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0161] In the above description, the numbers representing the steps, such as S110, S120, etc., do not necessarily mean that the steps must be executed in this manner. If permitted, the order of the steps can be interchanged or they can be executed simultaneously.

[0162] The term "comprising" as used in the specification and claims should not be construed as limiting to what is listed thereafter; it does not exclude other elements or steps. Thus, it should be interpreted as specifying the presence of the features, integers, steps, or components mentioned, but not excluding the presence or addition of one or more other features, integers, steps, or components, or groups thereof. Thus, the expression "a device comprising means A and B" should not be limited to a device consisting solely of components A and B.

[0163] References in this specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present application. Therefore, the phrases "in one embodiment" or "in an embodiment" appearing throughout this specification do not necessarily refer to the same embodiment, but may refer to the same embodiment. Furthermore, in one or more embodiments, the particular features, structures, or characteristics can be combined in any suitable manner, as would be apparent to one of ordinary skill in the art from this disclosure.

[0164] Note that the above are only preferred embodiments of the present application and the technical principles employed. Those skilled in the art will understand that the present application is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, and substitutions can be made by those skilled in the art without departing from the scope of protection of the present application. Therefore, although the present application has been described in more detail through the above embodiments, the present application is not limited to the above embodiments and may include many other equivalent embodiments without departing from the scope of protection of the present application, all of which fall within the scope of protection of the present application.

Claims

1. A master control redundancy device, characterized in that: include: m boards, wherein the m boards include n main control boards, m and n are integers, and n>=2; wherein, The m boards are connected to an information line, and each board is used to obtain slot information and type information of all boards through the information line, where the type in the type information includes the main control board type; The pth main control board is connected to other boards through the pth main control presence interrupt line, which is used to send the pth main control board presence information to other boards, p∈n; The pth main control board is also connected to the other main control boards through the pth handshake line, and is used to send handshake information to the other main control boards; the n main control boards elect the main control board and the backup main control board through the handshake information between them; The pth main control board is also connected to other boards via the pth master-slave interrupt line, and is used to send the master-slave status of the pth main control board to other boards. The master-slave status corresponds to the election result of the active main control board and the backup main control board.

2. The device according to claim 1, characterized in that The m single boards also include q interface boards, where q is an integer, q<=mn; in The q1 interface board is connected to each main control board through the q1 interface board in-position interrupt line, and is used to send the q1 interface board in-position information to each main control board, q1∈q; The types of all the single boards obtained by each single board through the information line also include the interface board type.

3. The device according to claim 1, characterized in that The n main control boards elect a master main control board and a backup main control board through handshake information between them, including: During the startup process, a main control board that starts successfully first sends a handshake message first, and the main control board that sends the handshake message first is elected as the main control board, and the other main control boards are standby main control boards.

4. The device according to claim 1, characterized in that The n main control boards elect a master main control board and a backup main control board through handshake information between them, including: During the startup process, at least two main control boards that start up successfully at the same time send handshake messages at the same time. The main control board with the largest or smallest slot information among the main control boards that start up successfully at the same time is elected as the main control board, and the other main control boards are selected as backup main control boards.

5. The device according to claim 1, characterized in that The n main control boards elect a master main control board and a backup main control board through handshake information between them, including: During operation, if the standby main control board fails to obtain the handshake information of the active main control board, the standby main control board will be elected as the active main control board, and the other main control boards will be elected as standby main control boards.

6. The device according to claim 5, characterized in that The step of selecting a master main control board from the standby main control boards includes: The standby main control board that first sends the master / slave status switch signal through the master / slave interrupt line will be elected as the master main control board.

7. A method for managing master redundancy, applied to the master redundancy device according to any one of claims 1 to 6, characterized in that: include: Each of the m boards obtains slot information and type information of all boards through an information line, where the type in the type information includes a main control board type; The pth main control board among the n main control boards of the main control board type sends the pth main control board presence information to other boards through the pth main control board presence interrupt line; The pth main control board in position also sends handshake information to other main control boards through the pth handshake line; The n main control boards elect a master main control board and a backup main control board through handshake information between them; The pth main control board also sends the master / slave status of the pth main control board to other boards through the pth master / slave interrupt line, wherein the master / slave status corresponds to the election result of the active main control board and the standby main control board; Each board of the non-master main control board registers with the elected master main control board according to the slot information and type information.

8. The method according to claim 7, characterized in that Also includes: The type of each single board obtained through the information line includes the type of all single boards, wherein the type also includes the interface board type; The q1th interface board among the m boards of the interface board type sends the presence information of the q1th interface board to each main control board through the q1th interface board presence interrupt line.

9. The method according to claim 7 or 8, characterized in that The n main control boards elect a master main control board and a backup main control board through handshake information between them, including one of the following: During the startup process, the first main control board that starts successfully sends a handshake message first, and the main control board that sends the handshake message first is elected as the main control board, and the other main control boards are standby main control boards; During the startup process, at least two main control boards that start up successfully at the same time send handshake messages at the same time. The main control board with the largest / smallest slot information among the main control boards that start up successfully at the same time is elected as the main control board, and the other main control boards are selected as backup main control boards; During operation, if the standby main control board fails to obtain the handshake information of the active main control board, the standby main control board will be elected as the active main control board, and the other main control boards will be elected as standby main control boards.

10. A computing device, characterized in that include: processor, and A memory having program instructions stored thereon, wherein when the program instructions are executed by the processor, the processor is caused to perform the method according to any one of claims 7 to 9.

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