Method of operating a battery management system, corresponding device and vehicle

Abstract

Embodiments of the present disclosure relate to methods of operating a battery management system, corresponding devices, and vehicles. The methods can be used to control a battery management system. A first voltage drop is sensed between a first terminal of a first battery cell and a second terminal of the first battery cell, and a second voltage drop is sensed between a first terminal of a second battery cell and a second terminal of the second battery cell. A fault condition is detected in the first battery cell or the second battery cell based on the first voltage drop or the second voltage drop. The first voltage drop is commutated for a first commutated voltage drop between the common terminal and the second terminal of the second battery cell.

Description

[0001] This application is a divisional application of the invention patent application filed on June 17, 2020, with Chinese national application number 202010554662.9, entitled "Method, Corresponding Device and Vehicle for Operating a Battery Management System". Technical Field

[0002] This manual relates to battery management systems and related equipment and vehicles. Background Technology

[0003] The ongoing technological advancements in electric vehicles (EVs) and hybrid electric vehicles (HEVs) have made improved battery management system (BMS) performance a desirable feature for promoting safe, reliable, and cost-effective battery operation.

[0004] The task of a battery management system (BMS) involves measuring the voltage of battery cells. This, in turn, involves extracting a relatively small voltage from a relatively high common-mode voltage.

[0005] Additionally, it should be noted that, for example in automotive applications, the vehicle's electric motor and its associated drive circuitry can be sources of noise, either in the form of current injected into the battery cells or in the form of voltage drops across these cells. These can represent electromagnetic interference sources that can adversely affect functional measurements over a wide frequency range.

[0006] A lack of accuracy in these measurements could have an adverse effect on the battery pack's lifespan and performance.

[0007] Accuracy can be provided by placing differential voltage amplifiers with high common-mode rejection ratio (CMRR) at each unit to provide a usable voltage level shift (i.e., the converted signal) for digitization via an analog-to-digital converter (ADC). Such a stage can be equipped with many other features (e.g., protection and diagnostics such as open-circuit load detection, leakage detection, built-in self-test, or BIST). Such features are highly desirable in the automotive sector to facilitate compliance with safety regulations.

[0008] The desired feature of the arrangement considered herein is that, due to the built-in self-test detection of fault conditions, for example, there is the possibility of maintaining detection of undervoltage (UV) and / or overvoltage (OV) conditions occurring in the cells of the battery pack. Summary of the Invention

[0009] This specification relates to battery management systems. One or more embodiments can be applied to the automotive field (e.g., to electric vehicles and / or hybrid electric vehicles).

[0010] One or more embodiments may facilitate the provision of improved solutions along the lines discussed above.

[0011] One or more embodiments may relate to a corresponding device (e.g., a battery management system or BMS).

[0012] One or more embodiments may relate to vehicles equipped with such devices (e.g., motorized vehicles such as EVs or HEVs).

[0013] The claims are an integral part of the technical description of one or more embodiments provided herein.

[0014] One or more embodiments may provide secondary or auxiliary paths independent of the main path to detect the UV / OV conditions of the unit.

[0015] One or more embodiments can therefore provide a certain redundancy to diagnose errors / failures while maintaining the ability to operate properly, even at reduced performance levels.

[0016] One or more embodiments can facilitate the achievement of semiconductor area savings. Attached Figure Description

[0017] One or more embodiments will now be described by way of example only, with reference to the accompanying drawings, in which:

[0018] Figure 1 This is an exemplary block diagram of the possible contexts used in the embodiments.

[0019] Figure 2 This is an exemplary block diagram of a device to which the embodiments can be applied.

[0020] Figure 3 yes Figure 2 An exemplary circuit diagram of a part of the device,

[0021] Figure 4 This is an exemplary diagram of a possible structure of an embodiment.

[0022] Figure 5 and Figure 6 This is an exemplary diagram illustrating the operation of the embodiment, and

[0023] Figure 7 This is an exemplary flowchart of possible operations in the embodiments. Detailed Implementation

[0024] In the following description, one or more specific details are illustrated to provide a thorough understanding of examples of embodiments described. Embodiments may be obtained without one or more specific details, or by utilizing other methods, components, materials, etc. In other instances, known structures, materials, or operations are not illustrated or described in detail, so that certain aspects of the embodiments will not be obscured.

[0025] References to "embodiment" or "one embodiment" within the framework of this specification are intended to indicate that a particular configuration, structure, or feature described with respect to that embodiment is included in at least one embodiment. Therefore, phrases such as "in an embodiment" or "in one embodiment" appearing at one or more points in this specification do not necessarily refer to the same embodiment. Furthermore, in one or more embodiments, particular configurations, structures, or features may be combined in any suitable manner.

[0026] The reference numerals used herein are provided for convenience only and therefore do not limit the extent of protection or the scope of the embodiments.

[0027] As discussed, the desired feature of the arrangement considered herein is, for example, the possibility of maintaining detection of undervoltage (UV) and / or overvoltage (OV) conditions occurring in the cells of the battery pack, due to the detection of fault conditions via a built-in self-test procedure.

[0028] As mentioned earlier, various solutions have been designed to perform fault diagnosis, run built-in self-test (BIST) programs, and activate error flags when errors are detected.

[0029] Examples of such errors / mistakes / faults (these names are used as synonyms in this document) can be described as a lack of integrity in the level shifter embedded in the analog front end and / or a non-compliant analog-to-digital converter or ADC due to bandgap bias or other errors.

[0030] The arrangement for performing such an action may include various arrangements known to those skilled in the art.

[0031] Arrangements for performing such actions may also include the various arrangements discussed in Italian patent applications 102018000005810 (US Family Publication 2019 / 0366849), 102018000005828 (US Family Publication US20190372178), and 102019000009234 (the priority application of this case, filed on the same day). Each of these applications is incorporated herein by reference.

[0032] As a result of such a flag being activated, it is conceivable that a set of window comparators could be enabled and / or a secondary processing chain could be added (e.g., an analog-to-digital converter or an ADC).

[0033] In order to comply with safety regulations (for example, in the automotive industry), such a solution may be difficult to accept at a level that could cause the vehicle to stop.

[0034] Furthermore, adding a programmable UV / OV (undervoltage / overvoltage) comparator set to a cell that can operate even in the event of a fault on the main detection path involves inherent redundancy that can negatively impact circuit complexity and semiconductor area. For example, in the case of n cells, 2 n A comparator is used to detect UV / OV conditions.

[0035] Within this solution framework, adding a secondary processing chain (e.g., an analog-to-digital converter or ADC) appears more promising, as this approach not only detects UV / OV conditions but also facilitates obtaining the actual voltage of the cell. Similarly, a secondary measurement path via a single 10-bit successive approximation register (SAR) ADC with an input multiplexer can facilitate the performance of additional tasks (e.g., measuring external resistors, analog signals on GPIO pins, and various internal voltages).

[0036] This solution may again negatively impact circuit complexity and semiconductor area. This negative impact could be mitigated by using a single (potentially simplified) ADC multiplexed across individual cells, which in turn has adverse effects on performance and time-interleaved measurements of individual cells.

[0037] Figure 1 This is an example of a possible arrangement of the battery pack BP in a vehicle V (e.g., an electric vehicle (EV) or a hybrid electric vehicle (HEV)) equipped with an associated battery management system BMS. A lithium-ion battery pack can be an example of such a battery pack.

[0038] However, references to such potential application areas and / or such battery technologies should not be construed as limiting the embodiments.

[0039] In one or more embodiments illustrated herein, a battery management system (BMS) may include a device 10 (e.g., an integrated circuit IC) that provides various features required to perform battery management, such as (a single) device 10 being configured to monitor 4 to 14 cells C.

[0040] In one or more embodiments, device 10 may be configured to cooperate with a power supply PS (which may be derived from a battery pack BP monitored by device 10), a communication interface CI, and a logic circuit device L.

[0041] In one or more embodiments, Figure 1 The logic block L illustrated in the example can include such a microcontroller.

[0042] Device 10 can also generate a stable internal reference, for example, by means of a voltage regulator and a bootstrap circuit. Furthermore, it can include a bandgap monitored by internal circuitry to improve measurement accuracy.

[0043] The tasks of device 10 may include monitoring the status of cells and battery packs by means of stack voltage measurement and cell voltage measurement. The associated measurement and diagnostic tasks may be performed on demand or periodically (e.g., at programmable cycle intervals).

[0044] This allows the measurement data to be used by an external controller to perform charge balancing and calculate data indicating the state of health (SOH) and state of charge (SOC) of the cell / battery pack.

[0045] In normal operating mode, device 10 can perform measurement conversion, diagnostic, and communication tasks. Optionally, device 10 can be set to a cyclic wake-up state to reduce current consumption (e.g., current consumption drawn from battery pack BP). In the cyclic wake-up state, the main functions of device 10 are periodically activated.

[0046] The device with the trademark name L9963 of STMicroelectronics Group Corporation can be an example of a conventional arrangement of such device 10.

[0047] In one or more embodiments, the device 10 illustrated herein may include a set of converters CV1,...,CV14 and balancing circuit blocks B1,...,B14 associated with corresponding units C in the battery pack BP.

[0048] For example, circuit blocks B1,...,B14 can provide (passive) cell balancing via internal discharge paths. This action is designed to balance the cells to promote a more even charge distribution across all cells. This has been found to improve the performance of the BP battery pack.

[0049] As illustrated herein, device 10 can be configured to perform automatic “verification” of fault events involving a single cell C or the entire battery pack BP.

[0050] For example, in the event of a fault involving cell C or battery pack BP, relevant tests can be performed automatically. This facilitates the provision of reliable information (e.g., via communication interface CI) to an external microcontroller to monitor the operation of the battery management system (BMS).

[0051] For example, as discussed in the cited Italian patent applications 102018000005810, 102018000005828 and 102019000009234, such automatic “verification” of failure events can occur in a variety of ways.

[0052] In fact, the embodiments illustrated herein are primarily aimed at actions that may be performed due to detected faults or errors, rather than at techniques for detecting such faults or errors.

[0053] The device 10 illustrated herein may therefore include at least some features of the BIST circuit disclosed in Italian patent applications 102018000005810, 102018000005828 and 102019000009234, which have been repeatedly cited.

[0054] Figure 1 The representation provided is an overall functional description of device 10.

[0055] More specifically, in the cases illustrated herein, the device 10 illustrated herein (e.g., see [reference]) Figure 2 The battery pack BP may include a charge sensing pin Cn, namely C0, C1, ..., C14. The charge sensing pin Cn is coupled to a cell C in the battery pack BP (e.g., the nth cell Celln arranged between pins Cn and Cn-1).

[0056] As illustrated in this article (for example, see again) Figure 2 The first cell, Cell1, is shown arranged between pins C0 and C1, and so on, until cell14 is arranged between pins C13 and C14.

[0057] For simplicity, the individual cells can be considered identical. Therefore, each of them can have a resistor R arranged to couple pins C0,...,C14 to the corresponding terminals of cell Cell1,...,Cell14. LPF And the capacitor CAP between adjacent pins.

[0058] resistor R LPF The capacitor CAP provides a corresponding low-pass RC filter, which helps to filter out unwanted signals at the battery terminals.

[0059] In one or more embodiments, pins C0,...,C14 of device 10 can be considered as high-impedance nodes, such that resistor R can be considered as high-impedance nodes. LPF There was no significant voltage drop at either end.

[0060] Therefore, it can be assumed that the (differential) voltage V corresponds approximately to the voltage across the nth cell Celln. diff It can be used for "reading" between adjacent pins Cn-1 and Cn.

[0061] In one or more embodiments, an additional pin designated Sn (n = 1,...,14) and pin Bn_n-1 (N = 2,...,14 in the case illustrated herein) can be used for balancing purposes, i.e., to discharge cells detected as “overcharged” in order to equalize the charge distribution across all batteries.

[0062] The amount of (balanced) discharge current can be determined by resistor R. DIS The resistor is configured to couple the “even-numbered” S-pins (i.e., S2,..., S14) to the “upper” end (i.e., the end or node facing the total voltage Vb of the battery pack) and the “odd-numbered” S-pins (i.e., S1,..., S13) to the “lower” end or node of the corresponding cell (opposite to the battery pack voltage VB, i.e., facing ground GND).

[0063] Pin Bn_n-1 is (directly) coupled to resistor R LPF Between the corresponding terminals of cells Cell1,...,Cell14, where no discharge resistor R is provided. DIS .

[0064] Figure 3 By illustrating the corresponding couplings of pins C12, C13, C14, S13, S14, and B14-13 of device 10, the arrangement of the two “topmost” cells (i.e., Cell 14 and Cell 13) in the battery pack BP illustrated above with reference to this document is explained in detail in a simple manner. For simplicity, Figure 3 Not copied from Chinese Figure 2 The relevant capacitor CAP is shown.

[0065] Therefore, the device 10 illustrated herein can be considered to include a plurality of charge sensing pins C0 to C14, which can be considered to be arranged in an ordered (numbered) sequence of pins C0 to C14 (e.g., from ground GND to the “higher” voltage Vb node or ribbon cable of battery pack BP), wherein these charge sensing pins include even-numbered pins (C0, C2, C4, ..., C14) and odd-numbered pins (C1, C3, ..., C13).

[0066] Furthermore, pins C0 to C14 can be considered as comprising multiple charge sensing pin pairs, namely, C0, C1; C1, C2; ...; C12, C13; C13, C14 arranged in the following ordered sequence:

[0067] Those charge sensing pin pairs that are at odd-numbered positions (1, 3, 5, 7, 9, 11, 13) in the ordered sequence of charge sensing pins C1 to C14 (from ground GND to Vb) illustrated in this article, namely:

[0068] C0, C1;

[0069] C2, C3;

[0070] C4, C5;

[0071] C6, C7;

[0072] C8, C9;

[0073] C10, C11;

[0074] C12, C13; and

[0075] Those charge sensing pin pairs that are even-numbered (2, 4, 6, 8, 10, 12, 14) in the ordered sequence of charge sensing pins C1 to C14 (from ground GND to Vb) illustrated in this article, namely:

[0076] C1, C2;

[0077] C3, C4;

[0078] C5, C6;

[0079] C7, C8;

[0080] C9, C10;

[0081] C11, C12;

[0082] C13, C14.

[0083] The charge sensing pins in multiple charge sensing pin pairs (C0, C1; C1, C2; ...; C12, C13; C13, C14) are connected via resistors (R... LPF The cells are coupled to the corresponding cells (Cell1, Cell2, ..., Cell13, Cell14) in the battery pack BP to sense the voltage across the corresponding cells.

[0084] Furthermore, in the ordered sequence of odd-numbered and even-numbered pairs of charge sensing pins, each odd-numbered (C0, C1; ...; C12, C13) (correspondingly, the even-numbered (C1, C2; ...; C13, C14)) charge sensing pin pair shares a common charge sensing pin with the subsequent even-numbered (C1, C2; ...; C13, C14) (correspondingly, the previous odd-numbered (C0, C1; ...; C12, C13)) charge sensing pin pair.

[0085] For example, such as Figure 3 As shown:

[0086] In the ordered sequence of charge sensing pins, the odd-numbered pairs C12 and C13 of the charge sensing pins share the common charge sensing pin C13 with the subsequent even-numbered pairs C13 and C14.

[0087] In the ordered sequence of charge sensing pins, the even-numbered pairs of charge sensing pins C13 and C14 share the common charge sensing pin C13 with the previous odd-numbered pairs C12 and C13.

[0088] Furthermore, the charge distribution pins illustrated herein can be considered to include first charge distribution pins S1,...,S14 and second charge distribution pins B2-1,...,B14-13.

[0089] By referring again Figure 3 It can be further noted that in the device 10 illustrated herein, in the ordered sequence of odd and even numbering of the charge sensing pins, each pair of odd-numbered pins (in) Figure 3 In the case of C12, C13) and the subsequent even-numbered pairs of charge sensing pins (in Figure 3 In the case of C13, C14) including:

[0090] a) The odd-numbered first charge distribution pin (in Figure 3 S13), via discharge resistor R DIS Odd-numbered pairs coupled to the charge sensing pin (in) Figure 3 The charge sensing pins in C12 and C13 (in) Figure 3 The pin in the middle is C12), instead of the common charge sensing pin (in Figure 3 (C13)

[0091] b) The even-numbered first charge distribution pin (in Figure 3 S14), via discharge resistor R DIS Even-numbered pairs coupled to the charge sensing pin (in) Figure 3 The charge sensing pins in C13 and C14 (in) Figure 3 The pin in the middle is C14), instead of the common charge sensing pin (in Figure 3 (C13)

[0092] c) Second charge distribution pin (in) Figure 3 (B14-13 in the middle), via charge sensing resistor R LPF Coupled to common charge sensing pin (in Figure 3 The second charge distribution pin (C13 in the middle) is configured to be selectively coupled to the odd-numbered first charge distribution pin (in the middle) via switches SW13 and SW14. Figure 3 S13) and the even-numbered first charge distribution pin (in Figure 3 The middle part (S14) is used to exchange charges with it in order to perform charge balancing function.

[0093] For the sake of simplicity, if (only) in Figure 3 As indicated in the diagram, when the balancing function is activated on a specific unit, the associated switching circuit is activated to adjust the ratio V. Diff / R DIS A current of intensity I is given to discharge the cell. Two such switches ( Figure 3 SW13 or SW14 in the diagram can be implemented as an electronic switch, such as a MOSFET transistor. Figure 3 The cells shown are associated with Cell13 and Cell14. A similar arrangement (not visible in the figure for simplicity) can be applied to other cells in the battery pack BP.

[0094] As mentioned earlier, R LPF The CAP theorem defines the poles (i.e., cutoff frequency or corner frequency) of the low-pass charge-sensing filter, while the resistor R... DIS The resistance value limits the discharge cell current used for balancing purposes.

[0095] It should be understood that, although referenced in this article Figure 3 As an example, only two cells, Cell13 and Cell14, are visible, but the aforementioned arrangement can be replicated for all odd-numbered and even-numbered charge pin pairs in device 10.

[0096] As mentioned above, for example in the automotive field, the ability to provide (secondary) UV / OV detection and accurate (non-destructive) measurement of unit voltage in the event of a fault / error is a highly desirable feature.

[0097] Therefore, one or more embodiments may utilize charge sensing / distribution pins and associated circuitry (e.g., ADCs) that are already present in the arrangements discussed above and have been provided for charge sensing / balancing and fault / error detection.

[0098] Therefore, in one or more embodiments, by saving semiconductor area and maintaining sufficient performance, the detection of UV / OV conditions and the measurement of battery voltage can be facilitated without reducing accuracy.

[0099] In one or more embodiments, this type of operation can be implemented (e.g., via software code loaded in the logic circuit device L) to “swap” the cell and the associated ADC, such that the cell voltage can be obtained (still) through adjacent signal sensing circuitry (primarily the ADC) with minimal work on the logic circuitry and almost no loss in semiconductor area.

[0100] For example, this could involve utilizing an open-circuit load and unit measurement arrangement compatible with that disclosed in the repeatedly cited Italian patent application 102018000005828. Figure 4 The illustrated switch, multiplexer, and ADC circuit devices are shown.

[0101] Therefore, the secondary UV / OV procedure can be run as needed (e.g., when a fault (failure) or error, such as one occurring in the ADC), via any known technique (e.g., built-in self-test or BIST). Since the corresponding conversion is considered no longer valid (as mentioned above, due to a fault, failure, or error, these names are essentially used synonymously herein), the conversion is no longer considered, and the swapping function is enabled, providing corresponding alternative UV / OV diagnostic (and cell voltage measurement) features.

[0102] For the sake of simplicity, Figure 4 It refers only to two cells out of multiple cells C (i.e., Cell11 (coupled between odd-numbered pin pairs C10 and C11) and Cell12 (coupled between even-numbered pin pairs C11 and C12)).

[0103] It will be understood that these two units can be considered to be located between the "lower" unit set LC (i.e., Cell1 to Cell10) and the "higher" unit set HC (i.e., Cell13 and Cell14).

[0104] like Figure 4 The illustration shows a cascaded arrangement of "odd numbered" cells (Cell11 is an example of these cells) coupled to multiplexers 30O (30-odd) and analog-to-digital converters (ADCs) 40O (40-odd).

[0105] Similarly, the “even-numbered” cell (Cell12 is an example) is shown as coupled to multiplexer 30E (30-even) and analog-to-digital converter (ADC) 40E (40-even).

[0106] In such Figure 4 In one or more embodiments shown, converters 40E and 40O are powered (completely) independently of each other by corresponding reference voltages (bandgap) Vbg1, Vbg2 (in a manner known to those skilled in the art). Among other things, such undesirable variations in the bandgap voltage (suitable for detection in a manner known to those skilled in the art, or using the solutions described in the aforementioned co-pending application, which are repeatedly cited above) can be considered possible errors or mistakes.

[0107] For simplicity, Figure 4Only the multiplexers 30O and 30E and the analog-to-digital converters (ADCs) 40O and 40E of the relevant processing chain are shown in the image. Other circuits (e.g., voltage level shifter modules and digital filters) can be considered as having been incorporated into the image. Figure 4 In other blocks within the ADC. For example, a level shifter can be considered as embedded in the analog front end of the ADC.

[0108] It will be understood that, although shown as separate and distinct elements for simplicity and ease of understanding, the various components 30O, 40O and 30E, 40E can be incorporated into a single combined component.

[0109] In one or more embodiments, multiplexers 30O and 30E may each include three input lines and two output lines. In the case of multiplexer 30E, an additional (fourth) input line (labeled SL = switching line) is added. The fourth input line is configured to be used when performing the "cell switching" operation as described below.

[0110] In one or more embodiments, multiplexers 30O, 30E can be configured to apply (voltage) signals sensed across the respective units to the inputs of the corresponding ADCs 40O, 40E.

[0111] For example, multiplexer 30O can be configured to apply the voltage sensed across Cell11 to its input pins C10, C11 (via resistors R10, R11 (corresponding to resistor R)). LPF (For example), again, for simplicity, the associated capacitor CAP is not visible), while the multiplexer 30E can be configured to apply the voltage sensed across Cell12 to its input pins C11, C12 (via resistors R11, R12 (corresponding to resistor R)). LPF (Example) – Similarly, for simplicity, the associated capacitor CAP is not visible.

[0112] like Figure 4 As shown, in one or more embodiments, multiplexers 30O (odd-numbered cells) and 30E (even-numbered cells) can be coupled such that in each pair of odd-numbered cells (here, Cell11) and even-numbered cells (here, Cell12), the odd-numbered multiplexer 30O is also coupled to the "S" pin (here, pin S12) of the even-numbered cell, while the even-numbered multiplexer 30E is also coupled to the Bn_n-1 pin (here, B12_11) coupled between the two cells (here, Cell11 and Cell12) in the pair.

[0113] like Figure 4As shown, in one or more embodiments, the multiplexer 30E (even-numbered cells) may also make its fourth input suitable (e.g., via swap line SL and resistor R10) for coupling to pin C10, i.e., the voltage sensing pin in the odd-numbered cells (here, Cell 11), rather than the pin (i.e., C11) shared by the odd-numbered cells (here, Cell 11) and the even-numbered cells (here, Cell 12).

[0114] Figure 7 The flowchart is an example of possible operations for the arrangement illustrated in this article.

[0115] exist Figure 7 The block 100 following START in the flowchart is an example of the system's "normal" operation (i.e., in the absence of detected faults), where multiplexers 30E and 30O are controlled by logic circuit L in the following manner:

[0116] The voltage signal at pins C12 and C11 (i.e., V) C12 and V C11 It is applied to the even-numbered ADC 40E.

[0117] The voltage signal (i.e., V) at pins C11 and C10 C11 and V C10 It is applied to the odd-numbered ADC 40O.

[0118] The conversion performed in converters 40E and 40O (e.g., sigma-delta ADC converters) in a manner known per se will produce (in any known manner) a first differential signal V applied to logic circuit L. 12 =V C12 -V C11 (i.e., the difference between the signals at C12 and C11) and the second differential signal V 11 =V C11 -V C10 (That is, the difference between the signals at C11 and C10).

[0119] One or more embodiments may involve recognizing that, under proper system operation (e.g., no open-circuit load or leakage), R12 and R DIS The voltage drop across the two ends is negligible, and the voltages at C12 and S12 can be expected to be equal (i.e., V). C12 -V C11 =V S12 -V C11 ).

[0120] Figure 7 Box 200 in the middle can be inspected (as illustrated at 202) to aim at one of the units (e.g., with Figure 4 Examples of various signal processing operations performed by a signal processing chain that converts the voltage signals at the two ends (exemplified by 30O, 40O and 30E, 40E) to determine whether the chain is operating normally or affected by a fault.

[0121] Such processing / inspection may involve any of the many processes known to those skilled in the art for this purpose (including built-in self-test or BIST processes).

[0122] Such processing / inspection can involve a multi-step procedure, one or more of which involve a first “accurate” BIST action suitable for detecting more or less serious faults at the cell level, followed by a “rough” test that can identify the part or component (e.g., analog-to-digital converter or ADC) that caused the fault if a serious fault is detected.

[0123] For example, Italian patent application 102019000009234 illustrates signal processing (e.g., in logic circuit L) that involves calculating the absolute value (abs) of the difference between VC12-VC11 and VS12-VC11, comparing the absolute value (modulus) with a given threshold, and being able to accurately detect and distinguish more or less serious faults at the cell level.

[0124] Similarly, Italian patent application 102018000005810 (which has been cited repeatedly) discloses a BIST process for differential ADCs, which can identify faulty ADCs due to faults detected at the cell level.

[0125] For the purposes of this explanation, it can be assumed that the specific implementation of the actions illustrated in boxes 200 and 202 is irrelevant:

[0126] The negative result (N) of the action in box 202 (e.g., not exceeding a certain "fault" threshold Vth) will result in continued normal operation;

[0127] The positive result (Y) of the action in block 202 (e.g., exceeding a certain "fault" threshold Vth) will cause a fault state to be declared in action 204 for one of the signal processing chains (ADC 40O or ADC 40E) associated with the cell pair including Cell11 and Cell12.

[0128] As illustrated in this document, a fault condition declared in action 204 (whatever it may be, but is detected in any way) could cause the conversion provided (initially) for one of the cells Cell11 or Cell12, such as via multiplexer 30E and ADC 40E, to be ignored (i.e., not considered, and could be declared "unavailable").

[0129] In one or more embodiments, this will result in a "cell swapping" action 206, wherein multiplexers 30E and 30O are controlled in such a manner as (by logic circuit L):

[0130] The voltage signals at pins C11 and C10 (available at the inputs of multiplexer 30E) (via swap line SL in the case of the voltage at C10) are applied to the even-numbered ADC 40E, where ADC 40E is configured to (instead of the signal V that 40E is expected to provide under normal operating conditions and indicates the voltage drop across cell Cell 12) 12 =V C12 -V C11 The signal V provides the "switch" signal for the voltage drop across the indicator unit Cell11. 12 '=V C11 -V C10 (See the down arrow shown in box 40E);

[0131] The (voltage) signals at pins S12 and C11 (available at the inputs of multiplexer 30O) are applied to the odd-numbered ADC 40O, where ADC 40O is configured to (instead of the signal V that 40O is expected to provide under normal operating conditions and indicates the voltage drop across cell Cell 11) 11 =V C11 -V C10 The signal V provides the "switch" signal for the voltage drop across the indicator cell 12. 11 ’ =V S12 -V C11 (See the down arrow shown in box 40O).

[0132] In this way, for example, assuming the ADC 40E fails, the initially provided signal V... 12 =V C12 -V C11 Unreliable (“unavailable”), as a result of the substitution, can be achieved by ADC 40O by utilizing the previously discussed V S12 =V C12 The fact that this reliably provides the corresponding measurement value V with the desired accuracy. 11 ’ =V S12 -V C11 .

[0133] Conversely, assuming ADC 40O fails, the initially provided signal V... 11 =V C11 -V C10Unreliable (“unavailable”), as a result of the substitution, the ADC 40E can reliably provide the corresponding measurement value V with the desired accuracy. 12 ’ =V C11 -V C10 .

[0134] Box 208 is an example of the possibility of continuing system operation by using cell swapping, such that accurate signal conversion (in a manner known to those skilled in the art) is maintained for cells from which UV / OV information continues to be derived, in accordance with safety specifications.

[0135] This is advantageous in automotive applications, for example, by utilizing the restored normal operation to perform service interventions before vehicle operation (e.g., driving capacity) can be maintained at a tolerable cost of increased computation time. Figure 7 (Box 210 in the middle).

[0136] In one or more embodiments, the switching action described above can occur under the control of a logic circuit L (e.g., a microcontroller).

[0137] For example, as a result of detecting a fault (e.g., via BIST as previously discussed), the actions illustrated in boxes 204 to 210 may involve:

[0138] Remove conversion and diagnostic errors associated with the fault handling chain (e.g., ADC).

[0139] Save the information about the unit and incorporate it into the steps (which can be enabled via SPI), where, as mentioned earlier, the swapping function has been activated.

[0140] Once the swap function is enabled, information other than the cells being analyzed will be deleted, the fault will be read and cleared, and normal operation will resume.

[0141] Figure 5 and Figure 6 (Where cells such as Cell2 and Cell11, Cell12 and Cell13 are not visible due to compactness) is a further example of the cell swapping process described above.

[0142] For example, Figure 5 This is an example of a situation where an error (e.g., a damaged ADC) is detected affecting the sensing action between pins C3 and C4 (even-numbered cells, Cell4, ADC_4).

[0143] Therefore, the (voltage) signal conversion will not apply to C4-C3, but will apply to the "lower" pins (e.g., C3-C2) and the "higher" pins (C5-C4, C6-C5, C7-C6, C8-C7...).

[0144] Since an error was detected (for example) on ADC_4, the conversion on ADC_4 (i.e., C4-C3) is not considered, and the swap function is enabled.

[0145] Figure 6 As an example of the substitution effect discussed in this paper, the voltage drop V across C4-C3 is measured using the corresponding ADC (i.e., ADC_3) in adjacent (odd-numbered) cells (e.g., Cell3). diff This facilitates UV / OV detection (and voltage measurement) on associated units.

[0146] As described, since the self-test (but performed, for example, see the earlier / co-pending application which has been repeatedly cited) revealed the failure condition, the unit swapping process was performed as previously discussed.

[0147] For example, already combined Figure 4 A discussion was held (for simplicity, only Cell11 and Cell12 are illustrated in detail):

[0148] Under normal operating conditions, the ADC 40E measures V corresponding to cell 12. 12 =V C12 -V C11 The ADC 40O measures the V corresponding to cell Cell11. 11 =V C11 -V C10 ;

[0149] Because the self-test revealed a fault in either 40E or 40O, a cell swap was performed to continue measuring UV / OV as needed, so that ADC 40E was configured to measure V' corresponding to cell 11. 12 =V C11 -V C10 The ADC 40O is configured to measure V' corresponding to cell Cell12. 11 =V S12 -V C11 .

[0150] In this way, measurements that are no longer available can be obtained from the faulty ADC (40E and 40O) via adjacent ADCs (40O and 40E, respectively) without loss of accuracy.

[0151] like Figure 5 and Figure 6 As shown, it can be Figure 4 The procedure illustrated for cell pair Cell 11 and Cell 12 is applied to other adjacent cell pairs in the system.

[0152] Figure 5 This is an example of a state where, for instance, during normal cell measurements, a fault is detected in a conversion channel (e.g., ADC_4 between C4 and C3) via the BIST process. As a result, measurements from that conversion channel (e.g., the ADC) are considered unreliable (e.g., declared "unavailable").

[0153] Therefore, as Figure 6 As shown, cell switching is activated, where cells that were declared unavailable for "normal" measurement are measured via adjacent conversion channels (e.g., ADC_3, reactivated between C4 and C3).

[0154] In this way, the arrangement illustrated in this paper can continue to provide measurements for all units while only increasing (doubling) the execution time.

[0155] For example, this could be due to the following fact: in cases such as Figure 5 During the operation shown, the measured values ​​of the cells were saved for Cell1 to Cell14, except for Cell4 (where an ADC_4 fault was detected).

[0156] As Figure 6 The illustrated cell swapping result preserves the measurement value of cell Cell4 (provided via ADC_3), so that information on all cells Cell1 to Cell14 (including Cell4) can eventually be obtained (with the desired accuracy, unaffected by fault conditions).

[0157] In one or more embodiments, Figure 5 and Figure 6 The two conditions illustrated can continue to alternate, thus providing continuous measurements of all cells from Cell1 to Cell14.

[0158] In one or more embodiments, the BIST procedure can be performed on any cell from Cell1 to Cell14 at any time (cyclically or as needed). If the procedure reveals a fault, standard measurements and "switchover" measurements are performed.

[0159] For example, for odd-numbered cells and subsequent even-numbered cells (respectively...) Figure 4 Any pair of Cell11 and Cell12 in the dataset:

[0160] a) During standard measurements:

[0161] The even-numbered ADC 40E (ADC_12) is configured to measure V. 12 =V C12 -V C11That is, the voltage of Cell12, which spans even-numbered cells, and

[0162] The odd-numbered ADC 40O (ADC_11) is configured to measure V. 11 =V C11 -V C10 That is, the voltage of Cell11, which is an odd-numbered cell.

[0163] b) During the “exchange” measurement:

[0164] The even-numbered ADC 40E (ADC_12) is configured to measure V' 12 =V C11 -V C10 That is, the voltage of Cell11 across odd-numbered cells, and

[0165] The odd-numbered ADC 40O (ADC_11) is configured to measure V' 11 =V S12 -V C11 That is, the voltage of Cell12, which spans even-numbered cells.

[0166] One or more embodiments can therefore rely on the (already) provided internal charge transport paths to balance the cells in the battery pack in order to facilitate charge equalization between cells.

[0167] One or more embodiments may be compatible with the built-in self-test (BIST) feature, which verifies the proper functioning of the Vdiff sensing chain (e.g., internal analog comparators and ADCs) through a check process that can be performed automatically, for example, in the event of a failure in one of the two cells or the entire battery pack, and is able to provide corresponding (reliable) information to an external microcontroller.

[0168] The methods illustrated herein can facilitate the operation of control devices (e.g., 10) in a battery management system (e.g., BMS), wherein:

[0169] The control device includes an ordered sequence of charge sensing pins (e.g., C0 to C14), arranged in an ordered sequence of odd-numbered and even-numbered charge sensing pin pairs within multiple charge sensing pin pairs (e.g., C0, C1; C1, C2; ...; C12, C13; C13, C14). The charge sensing pins in each of the multiple charge sensing pin pairs (e.g., C0, C1; C1, C2; ...; C12, C13; C13, C14) are coupled (R... LPFThe system senses the voltage across the corresponding cell (e.g., Cell1, Cell2, ..., Cell13, Cell14) in the battery pack, wherein in an ordered sequence of odd-numbered charge sensing pin pairs and even-numbered charge sensing pin pairs, each odd-numbered charge sensing pin pair (e.g., C0, C1; ...; C12, C13) (correspondingly, even-numbered charge sensing pin pairs (e.g., C1, C2; ...; C13, C14)) shares a common charge sensing pin (e.g., C1, ..., C13) with the subsequent even-numbered charge sensing pin pairs (e.g., C1, C2; ...; C13, C14) (correspondingly, the previous odd-numbered charge sensing pin pairs (e.g., C0, C1; ...; C12, C13)).

[0170] In an ordered sequence of odd-numbered and even-numbered charge sensing pin pairs, each odd-numbered charge sensing pin pair (e.g., C0, C1; ...; C12, C13) and the subsequent even-numbered charge sensing pin pairs (e.g., C1, C2; ...; C13, C14) includes charge distribution pins (e.g., S2, S4, ..., S12, ..., S14), and the charge distribution pins are coupled (e.g., R...). DIS ( ) to the charge sensing pins in the even-numbered charge sensing pin pairs other than the common charge sensing pins (e.g., C1,...,C13).

[0171] As illustrated in this paper, for an ordered sequence of odd-numbered charge sensing pin pairs and even-numbered charge sensing pin pairs, the odd-numbered charge sensing pin pairs (e.g., see...) Figure 4 C10, C11) and subsequent even-numbered charge sensing pin pairs (see, for example, C10, C11) and the even-numbered pairs of charge sensing pins (see, for example, C10, C11). Figure 4 C11, C12), including:

[0172] a) Sensing (e.g., see 100, 30E, 40E, 30O, 40O):

[0173] In subsequent even-numbered pairs, the first voltage drop (e.g., V) between the charge sensing pins other than the common charge sensing pin (e.g., C12) and the common charge sensing pin (e.g., C11) is... 12 The first voltage drop indicates the voltage drop across the charge sensing pin in subsequent even-numbered pairs, and

[0174] The second voltage drop (e.g., V) between the common charge sensing pin (e.g., C11) and the charge sensing pins (e.g., C10) in the previous odd-numbered pair other than the common charge sensing pin. 11The second voltage drop indicates the voltage drop across the charge sensing pins of the previously odd-numbered pairs.

[0175] b) Caused by a fault condition detected in the equipment (e.g., 202):

[0176] The first swap voltage drop between the first voltage drop and the first swap voltage drop between the common charge sensing pin (e.g., C11) and the charge sensing pins (e.g., C10) in the previous odd-numbered pair other than the common charge sensing pin (e.g., C10) is (e.g., V). 12 '), where the first swap voltage drop indicates the voltage drop across the charge sensing pins of the previously odd-numbered pair,

[0177] The second voltage drop is replaced with coupling (e.g., via R). DIS The second switching voltage drop (e.g., V) between the charge distribution pin (e.g., S12) and the common charge sensing pin (e.g., C11) in subsequent even-numbered pairs, excluding the common charge sensing pin (e.g., C12), and the common charge sensing pin (e.g., C11). 11 '), where the second swap voltage drop indicates the voltage drop across the charge sensing pin in the subsequent even-numbered pair (e.g., C11, C12).

[0178] Due to the subsequent even-numbered charge sensing pin pairs (e.g., Figure 4 C11 and C12 in the previous odd-numbered charge sensing pin pairs (e.g., Figure 4 Any one of C10 and C11 in (for example, Figure 4 If one of the ADCs 40O or 40E in the document detects a fault condition, the methods illustrated herein may include:

[0179] The first voltage drop (e.g., V) of the charge sensing pin pair that detects a fault condition is discarded. 12 (Correspondingly, the second voltage drop (e.g., V) 11 See also Figure 5 (C4-C3 were discarded due to an ADC_4 fault) and

[0180] Using the first switching voltage drop (e.g., V') 12 (Correspondingly, the second switching voltage drop (e.g., V') 11 Replace the first voltage drop (and correspondingly the second voltage drop) (see also...) Figure 6 ADC_3 provides fault-free C4-C3).

[0181] The methods illustrated herein may include: detecting fault conditions for multiple charge sensing pin pairs (e.g., C0, C1; C1, C2; ...; C12, C13; C13, C14) within an ordered sequence of odd-numbered and even-numbered charge sensing pin pairs.

[0182] First action: (e.g., at L) Record the first voltage drop (V) of the charge sensing pin pair for the detected fault condition. 12 (Correspondingly, the second voltage drop (V) 11 In addition to the first voltage drop (V) for multiple charge sensing pin pairs 12 ) and second voltage drop (V 11 (For example, see again) Figure 5 The C4-C3 components were discarded due to an ADC_4 fault, and

[0183] Second action: For the charge sensing pin pair where a fault condition is detected, record the first switching voltage drop (and correspondingly, the second switching voltage drop) of the first voltage drop (and correspondingly, the second voltage drop) of the charge sensing pin pair where a fault condition is detected (see again). Figure 6 (C4-C3 provided by the fault-free ADC_3).

[0184] The methods illustrated herein may include alternating the second recording action with the first recording action, such that reliable measurements can be obtained for all pin pairs (i.e., for all cells) despite the increased (doubled) measurement time.

[0185] The method illustrated herein may include, between a first recording action and a second recording action, swapping a first swapped voltage drop (and correspondingly a second swapped voltage drop) for a first voltage drop (and correspondingly a second voltage drop).

[0186] The method illustrated herein may include providing a first signal sensing circuit device (e.g., 30E, 40E) and a second signal sensing circuit device (e.g., 30O, 40O) configured to sense a first voltage drop and a second voltage drop, wherein the first and second signal sensing circuit devices have sensing resolution (e.g., ADC resolution), wherein the sensing resolution is maintained for the first and second switching voltage drops (in a switching configuration, the first and second switching voltage drops are also sensed via the first and second signal sensing circuit devices).

[0187] The illustrated method may include applying undervoltage and / or overvoltage detection to a first switching voltage drop (and correspondingly a second switching voltage drop).

[0188] Control devices (e.g., 10) for a battery management system (e.g., BMS), as illustrated herein, may include:

[0189] An ordered sequence (C0 to C14) of charge sensing pins arranged in multiple charge sensing pin pairs (C0, C1; C1, C2; ...; C12, C13; C13, C14) of odd-numbered and even-numbered charge sensing pin pairs, wherein the charge sensing pins in each charge sensing pin pair (C0, C1; C1, C2; ...; C12, C13; C13, C14) are configured to be coupled (R LPF The system senses the voltage across the corresponding cells (Cell1, Cell2, ..., Cell13, Cell14) in the battery pack (BP). In an ordered sequence of odd-numbered and even-numbered charge sensing pin pairs, each odd-numbered (e.g., C10, C11) (correspondingly, even-numbered (e.g., C11, C12)) charge sensing pin pair shares a common charge sensing pin (e.g., C1, ..., C13) with the subsequent even-numbered charge sensing pin pair (correspondingly, the previous odd-numbered charge sensing pin pair).

[0190] In the ordered sequence of odd-numbered and even-numbered charge sensing pin pairs, each odd-numbered charge sensing pin pair and the subsequent even-numbered charge sensing pin pair include a charge distribution pin (e.g., S2, S4, ..., S14), which is configured to be coupled (e.g., via R...). DIS ) to the charge sensing pins in the even-numbered charge sensing pin pairs, excluding the common charge sensing pin.

[0191] The device may include processor circuitry (e.g., L) and signal sensing circuitry (e.g., 30E, 30O, 40E, 40A).

[0192] The device is configured to operate using the method illustrated herein and includes:

[0193] Signal sensing circuitry can be configured (e.g., via multiplexers 30E, 30O) to sense first and second voltage drops (e.g., V). 12 V 11 ) and the first and second switching voltage drops (e.g., V' 12 ;V' 11 ),

[0194] The processor circuit (e.g., L) is configured to sense a fault condition detected in the device and to switch the first and second voltage drops to the first and second switched voltage drops as a result of the fault condition being detected.

[0195] In the control device illustrated herein, for an ordered sequence of odd-numbered and even-numbered charge sensing pin pairs, the signal sensing circuitry may include the odd-numbered (e.g., C10, C11) charge sensing pin pairs and the subsequent even-numbered (C1, C2, ..., C13, C14) charge sensing pin pairs:

[0196] The first signal sensing circuit device (e.g., 30E, 40E) is configured (e.g., via multiplexer 30E):

[0197] i) Coupled to a common charge sensing pin (e.g., C11) and subsequent even-numbered charge sensing pin pairs (C11, C12) other than the common charge sensing pin (e.g., C12) to sense a first voltage drop (e.g., V) between them. 12 ),as well as

[0198] ii) Coupled to a common charge sensing pin (e.g., C11) and a charge sensing pin (e.g., C10) in a previous odd-numbered charge sensing pin pair (e.g., C10, C11) other than the common charge sensing pin to sense a first switching voltage drop (e.g., V) between them. 12 '),

[0199] The second signal sensing circuit device (e.g., 30O, 40O) is configured (e.g., via multiplexer 30O):

[0200] i) Coupled to a common charge sensing pin (e.g., C11) and a charge sensing pin (e.g., C10) in a previous odd-numbered charge sensing pin pair (e.g., C10, C11) other than the common charge sensing pin to sense a second voltage drop (e.g., V) between them. 11 ),

[0201] ii) Coupled to the charge distribution pin (e.g., S12) and the common charge sensing pin (e.g., C11), the charge distribution pin is coupled (e.g., via R... DIS The charge sensing pins in subsequent even-numbered pairs (e.g., C11, C12) are used to sense a second switching voltage drop (e.g., V') between them, excluding the common charge sensing pin. 11 ).

[0202] The electric vehicles (e.g., V) illustrated herein may include:

[0203] A battery pack (e.g., BP) comprising multiple battery cells (e.g., C).

[0204] A battery management system (e.g., BMS) coupled to the battery pack.

[0205] As illustrated herein, a control device (e.g., 10) is configured to control a battery management system.

[0206] Without prejudice to the fundamental principles, details and embodiments may be significantly altered relative to those described by way of example only, without departing from the scope of protection.

[0207] The scope of protection is determined by the appended claims.

Claims

1. A control device for battery management, the control device comprising: A first circuit includes a first multiplexer and a first ADC, the first circuit being coupled to a first battery cell and a second battery cell, and being configured to sense the voltage drop across the first battery cell via a first channel. as well as The second circuit includes a second multiplexer and a second ADC, the second circuit being coupled to the first battery cell and the second battery cell, and configured to sense the voltage drop across the second battery cell via a second channel. The first circuit is further configured to sense the switching voltage drop across the second battery cell by switching the second channel to the first channel when a fault condition is detected in the second battery cell. The second circuit is further configured to sense the switching voltage drop across the first battery cell by switching the first channel to the second channel when a fault condition in the first battery cell is detected.

2. The control device according to claim 1, wherein: Both the first battery cell and the second battery cell include a first terminal and a second terminal, and the second terminal of the first battery cell and the first terminal of the second battery cell are connected together as a common terminal; and The control device further includes a charge balancing circuit, which includes a first charge distribution pin, a second charge distribution pin, and a third charge distribution pin. The first charge distribution pin is coupled to the first terminal of the first battery cell, the second charge distribution pin is coupled to the common terminal, and the third charge distribution pin is coupled to the second terminal of the second battery cell. The charge balancing circuit is configured to perform a charge balancing function by discharging the first battery cell, the second battery cell, or both.

3. The control device according to claim 2, wherein: The first input of the first multiplexer is coupled to the first terminal of the first battery cell. The second input of the first multiplexer is coupled to the second terminal of the first battery cell. The third input of the first multiplexer is coupled to the second terminal of the second battery cell via the third charge distribution pin, and The first output and the second output of the first multiplexer are coupled to the first ADC, which is configured to sense the difference between the first output and the second output of the first multiplexer.

4. The control device according to claim 3, wherein: The first multiplexer is configured to output its first input and its second input to the first ADC when no fault condition is detected in the second battery cell. The voltage drop across the first battery cell is the voltage difference between the first terminal and the second terminal of the first battery cell sensed by the first ADC when no fault condition is detected in the second battery cell. The first multiplexer is configured to output its second input and third input to the first ADC when a fault condition is detected in the second battery cell. The switching voltage drop across the second battery cell is the voltage difference between the first terminal and the second terminal of the second battery cell sensed by the first ADC when the fault condition in the second battery cell is detected.

5. The control device of claim 4, wherein the fault condition in the second battery cell is detected by the second ADC using a built-in self-test program.

6. The control device according to claim 2, wherein: The first input of the second multiplexer is coupled to the first terminal of the second battery cell; The second input of the second multiplexer is coupled to the second terminal of the second battery cell; The third input of the second multiplexer is coupled to the first terminal of the first battery cell, and The first output and the second output of the second multiplexer are coupled to the second ADC, which is configured to sense the difference between the first output and the second output of the second multiplexer.

7. The control device of claim 6, wherein the second multiplexer further comprises a fourth input, the fourth input being coupled to the common terminal via the second charge distribution pin.

8. The control device according to claim 6, wherein: The second multiplexer is configured to output its first input and second input to the second ADC when no fault condition is detected in the first battery cell. The voltage drop across the second battery cell is the voltage difference between the first terminal and the second terminal of the second battery cell, sensed by the second ADC, when no fault condition is detected in the first battery cell. The second multiplexer is configured to output its second input and third input to the second ADC when the fault condition in the first battery cell is detected. The switching voltage drop across the first battery cell is the voltage difference between the first terminal and the second terminal of the first battery cell, sensed by the second ADC, when the fault condition in the first battery cell is detected.

9. The control device of claim 8, wherein the fault condition in the first battery cell is detected by using a built-in self-test program via the first ADC.

10. The control device according to claim 2, wherein: The first charge distribution pin is coupled to the second charge distribution pin via a first electronic switch, and The second charge distribution pin is coupled to the third charge distribution pin via a second electronic switch, each of the first and second electronic switches being implemented using a metal-oxide-semiconductor field-effect transistor (MOSFET).

11. A control device for battery management, the control device comprising: Multiple circuits are arranged in an ordered sequence of odd-numbered and even-numbered circuits, each of which is coupled to a corresponding battery cell in the ordered sequence of odd-numbered and even-numbered battery cells, wherein: The odd-numbered circuitry includes a first multiplexer and a first ADC, the odd-numbered circuitry being coupled to the odd-numbered battery cells and subsequently the even-numbered battery cells, and is configured to sense the voltage drop across the odd-numbered battery cells via a first channel. The subsequent even-numbered circuitry includes a second multiplexer and a second ADC, which is coupled to both the odd-numbered and even-numbered battery cells and configured to sense the voltage drop across the subsequent even-numbered battery cells via a second channel. The odd-numbered circuit is further configured to: when a fault condition is detected in the subsequent even-numbered battery cell, sense the switching voltage drop across the subsequent even-numbered battery cell by switching the second channel to the first channel, and The subsequent even-numbered circuit is further configured to sense the switching voltage drop across the odd-numbered battery cell when a fault condition is detected in the odd-numbered battery cell by switching the first channel to the second channel.

12. The control device according to claim 11, wherein: Both the odd-numbered battery cells and the subsequent even-numbered battery cells include a first terminal and a second terminal. The second terminal of the odd-numbered battery cells and the first terminal of the subsequent even-numbered battery cells are connected together as a common terminal. The control device further includes an ordered sequence of odd-numbered charge balancing circuits and even-numbered charge balancing circuits, wherein: The odd-numbered charge balancing circuit includes a first charge distribution pin and a second charge distribution pin. The first charge distribution pin is coupled to the first terminal of the odd-numbered battery cell, and the second charge distribution pin is coupled to the common terminal. The odd-numbered charge balancing circuit is configured to perform a charge balancing function by discharging the odd-numbered battery cell. The subsequent even-numbered charge balancing circuits share a second charge distribution pin with the odd-numbered charge balancing circuits, and the subsequent even-numbered charge balancing circuits also include a third charge distribution pin coupled to the second terminal of the subsequent even-numbered battery cell. The subsequent even-numbered charge balancing circuits are configured to perform charge balancing functions by discharging the subsequent even-numbered battery cells.

13. The control device according to claim 12, wherein: The first input of the first multiplexer is coupled to the first terminal of the odd-numbered battery cell. The second input of the first multiplexer is coupled to the second terminal of the odd-numbered battery cell. The third input of the first multiplexer is coupled to the second terminal of the subsequent even-numbered battery cell via the third charge distribution pin, and The first output and the second output of the first multiplexer are coupled to the first ADC, which is configured to sense the difference between the first output and the second output of the first multiplexer.

14. The control device according to claim 13, wherein: The first multiplexer is configured to output its first input and second input to the first ADC when no fault condition is detected in the subsequent even-numbered battery cells. The voltage drop across the odd-numbered battery cell is the voltage difference between the first terminal and the second terminal of the odd-numbered battery cell, sensed by the first ADC, when no fault condition is detected in the subsequent even-numbered battery cell. The first multiplexer is configured to output its second input and third input to the first ADC when a fault condition is detected in a subsequent even-numbered battery cell. The switching voltage drop across the subsequent even-numbered battery cells is the voltage difference between the first terminal and the second terminal of the subsequent even-numbered battery cells, sensed by the first ADC, when the fault condition in the subsequent even-numbered battery cells is detected.

15. The control device of claim 14, wherein the fault condition in the subsequent even-numbered battery cells is detected using a built-in self-test program via the second ADC.

16. The control device according to claim 12, wherein: The first input of the second multiplexer is coupled to the first terminal of the subsequent even-numbered battery cell; The second input of the second multiplexer is coupled to the second terminal of the subsequent even-numbered battery cell; The third input of the second multiplexer is coupled to the first terminal of the odd-numbered battery cell, and The first output and the second output of the second multiplexer are coupled to the second ADC, which is configured to sense the difference between the first output and the second output of the second multiplexer.

17. The control device of claim 16, wherein the second multiplexer further comprises a fourth input, the fourth input being coupled to the common terminal via the second charge distribution pin.

18. The control device according to claim 16, wherein: The second multiplexer is configured to output its first input and second input to the second ADC when no fault condition is detected in the odd-numbered battery cell. The voltage drop across the subsequent even-numbered battery cells is the voltage difference between the first terminal and the second terminal of the subsequent even-numbered battery cell, sensed by the second ADC, when no fault condition is detected in the odd-numbered battery cell. The second multiplexer is configured to output its second input and third input to the second ADC when a fault condition is detected in one of the odd-numbered battery cells. The switching voltage drop across the odd-numbered battery cell is the voltage difference between the first terminal and the second terminal of the odd-numbered battery cell, sensed by the second ADC when the fault condition in the odd-numbered battery cell is detected.

19. The control device of claim 18, wherein the fault condition in the odd-numbered battery cells is detected by using a built-in self-test program via the first ADC.

20. The control device according to claim 12, wherein: The first charge distribution pin is coupled to the second charge distribution pin via a first electronic switch, and The second charge distribution pin is coupled to the third charge distribution pin via a second electronic switch, each of the first and second electronic switches being implemented using a metal-oxide-semiconductor field-effect transistor (MOSFET).

21. An electric vehicle, comprising: A battery pack is an ordered sequence of odd-numbered and even-numbered battery cells. The battery management system is coupled to the battery pack; as well as A control device, configured to control the battery management system, the control device comprising: Multiple circuits are arranged in an ordered sequence of odd-numbered and even-numbered circuits, each of the multiple circuits being coupled to a corresponding battery cell in the ordered sequence of odd-numbered and even-numbered battery cells, wherein: The odd-numbered circuitry includes a first multiplexer and a first ADC, the odd-numbered circuitry being coupled to the odd-numbered battery cells and subsequently the even-numbered battery cells, and is configured to sense the voltage drop across the odd-numbered battery cells via a first channel. The subsequent even-numbered circuitry includes a second multiplexer and a second ADC, which is coupled to both the odd-numbered and even-numbered battery cells and configured to sense the voltage drop across the subsequent even-numbered battery cells via a second channel. The odd-numbered circuit is also configured to sense the switching voltage drop across the subsequent even-numbered battery cell by switching the second channel to the first channel when a fault condition is detected in the subsequent even-numbered battery cell. The subsequent even-numbered circuitry is also configured to sense the switching voltage drop across the odd-numbered battery cell by switching the first channel to the second channel when a fault condition is detected in the odd-numbered battery cell.

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