Method for integrating double-layer polysilicon self-aligned vertical bipolar transistor in germanium-silicon bipolar process and semiconductor device

Abstract

The application provides a method for integrating double-layer polysilicon self-aligned vertical bipolar transistors in a germanium-silicon bipolar process and a semiconductor device, in which, based on the ingenious design of process steps, the double-layer polysilicon self-aligned vertical bipolar transistors are simultaneously integrated in the germanium-silicon bipolar process, and in the case of not significantly increasing the process complexity, the germanium-silicon heterojunction bipolar transistor and the silicon vertical bipolar transistor are simultaneously integrated and prepared in a single manufacturing process, the process efficiency is improved, the process cost is reduced, and the transistor is further divided into NPN type and PNP type, the corresponding prepared semiconductor device can cover various transistor structure combinations, is suitable for various application scenarios with different functional requirements, and can improve the electrical performance of the corresponding semiconductor device or chip as appropriate.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device process technology, and in particular relates to a method and semiconductor device for integrating a double-layer polysilicon self-aligned vertical bipolar transistor in a germanium-silicon bipolar process. Background Technology

[0002] In semiconductor integrated circuit manufacturing processes, bipolar junction transistors (BJTs) typically have two structures: vertical (VBT) and lateral (LBT). The vertical VBT offers significant performance advantages over the lateral LBT, such as a higher characteristic frequency f. T Current gain β, Erlich voltage V A While offering advantages like lower noise characteristics, NF transistors are more complex to manufacture. Conventional bipolar processes typically only include vertically structured NPN transistors (VNPN), with the integrated PNP transistor usually being a lateral structure (LPNP). Simultaneously integrating high-performance vertically structured NPN and PNP complementary bipolar (CB) transistors is not a simple process; adding a vertically structured PNP (VPNP) significantly increases technical complexity and manufacturing costs.

[0003] To further improve the radio frequency performance of bipolar transistors, an important technical approach is to replace the silicon-based region with germanium-silicon (Si). 1-X Ge X The SiGe material is used to form heterojunction bipolar transistors (SiGeHBTs). Because the SiGeHBT process requires additional photolithographic patterning, SiGe heterojunction epitaxy, polysilicon outer base region interconnection, and strict control of the thermal budget, the introduction of the SiGe process further increases the technical difficulty and complexity of the process. In particular, the manufacturing technology for integrating SiGeHBTs with symmetrical complementary silicon vertical VNPN and VPNP transistors has not been reported in the published literature.

[0004] Vertical bipolar transistor (VBT) technology is a key technology for high-speed / high-precision analog and radio frequency (RF) chips. Among them, silicon-germanium heterojunction (SiGeHBT) and silicon vertical bipolar transistor (SiVBT) each have their own advantages and disadvantages: SiGeHBT has excellent RF performance, but due to the lattice matching between silicon and germanium, it has higher crystal defects and higher leakage current; SiVBT can withstand a wider operating voltage range and higher operating current, while having lower leakage current, but the device cutoff frequency is typically limited to below 50 GHz.

[0005] Therefore, there is an urgent need for a SiGe-Si complementary bipolar process that can integrate germanium-silicon heterojunction transistors (SiGeHBT) and silicon vertical bipolar transistors (SiVBT) in a single manufacturing process without significantly increasing process complexity, especially the simultaneous integration of vertical VNPN and PNP transistors. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a process technology solution for integrating a double-layer polysilicon self-aligned vertical bipolar transistor in a germanium-silicon bipolar process. This process structure can simultaneously integrate a germanium-silicon heterojunction transistor and a vertical silicon bipolar transistor in a single manufacturing process without significantly increasing process complexity.

[0007] To achieve the above and other related objectives, the technical solution provided by this invention is as follows.

[0008] A method for integrating a double-layer polysilicon self-aligned vertical bipolar transistor in a germanium-silicon bipolar process includes:

[0009] A silicon substrate is provided in which N collector regions and a plurality of field oxygen isolation regions are formed, wherein the N collector regions include M first collector regions and NM second collector regions, and each collector region is isolated from the others by the plurality of field oxygen isolation regions.

[0010] A first dielectric layer is formed on the silicon substrate, the first dielectric layer contacts and covers each of the collector regions and each of the field oxygen isolation regions, and the first dielectric layer is etched to expose NM of the first collector regions;

[0011] A first doped polysilicon layer is formed, which covers the remaining first dielectric layer and the exposed first collector region. A second dielectric layer is formed on the first doped polysilicon layer. The second dielectric layer and the first doped polysilicon layer are etched to form M first emitter windows corresponding to M first collector regions. The M first emitter windows expose the M first collector regions. NM second emitter windows corresponding to NM second collector regions are formed. The NM second emitter windows expose the first dielectric layer on the NM second collector regions.

[0012] A third dielectric layer is formed, which covers the remaining second dielectric layer and covers M first emitter windows and NM second emitter windows. The third dielectric layer at the bottom of NM second emitter windows is etched to expose the first dielectric layer on the second collector region again.

[0013] Ion implantation is performed along NM second emitter windows, passing through the first dielectric layer, to form a second collector implantation layer in the second collector region;

[0014] Etching is performed along NM second emitter windows to remove the first dielectric layer at the bottom of the second emitter windows, exposing the second collector region and leaving the remaining first doped polysilicon layer at the bottom of the second emitter windows partially suspended.

[0015] Epitaxial growth is performed along NM second emitter windows to form a germanium-silicon heterojunction inner base region on the second collector region at the bottom of the second emitter window;

[0016] A fourth dielectric layer is formed, which covers the remaining third dielectric layer and the inner base region of the germanium-silicon heterojunction. The fourth dielectric layer and the third dielectric layer are etched to expose the first collector region at the bottom of the first emitter window.

[0017] Ion implantation and annealing are performed along M first emitter windows to form a first collector implantation layer, an inner base region and an inner-outer base region connection layer in the first collector region. The inner base region and the inner-outer base region connection layer are located on top of the first collector region, and the inner base region is connected to the residual first doped polysilicon layer through the inner-outer base region connection layer.

[0018] Etching is performed along NM second emitter windows to remove the fourth dielectric layer at the bottom of the second emitter windows, thereby exposing the germanium-silicon heterojunction inner base region in the second collector region;

[0019] Where N is an integer greater than or equal to 2, M is an integer greater than or equal to 1, and M is less than N.

[0020] Optionally, the first collector region includes an N-type doped collector region or a P-type doped collector region, and the second collector region includes an N-type doped collector region or a P-type doped collector region. The step of providing the silicon substrate includes:

[0021] An initial silicon substrate is provided, the initial silicon substrate comprising N device regions;

[0022] N heavily doped buried layers are formed one-to-one on the N device regions of the initial silicon substrate, including N-type heavily doped buried layers and P-type heavily doped buried layers.

[0023] N collector regions are formed one-to-one on the N device regions of the initial silicon substrate. The collector regions include N-type doped collector regions and P-type doped collector regions. The N-type doped collector regions are located on the N-type heavily doped buried layer, and the P-type doped collector regions are located on the P-type heavily doped buried layer.

[0024] Multiple field oxygen isolation regions are formed to isolate N device regions. In a first plane, the field oxygen isolation regions are arranged around the N-type doped collector region and the N-type heavily doped buried layer, or the field oxygen isolation regions are arranged around the P-type doped collector region and the P-type heavily doped buried layer.

[0025] Optionally, the step of forming a first dielectric layer on the silicon substrate, the first dielectric layer contacting and covering each of the collector regions and each of the field oxide isolation regions, and etching the first dielectric layer to expose the M first collector regions includes:

[0026] A first dielectric layer is formed on the silicon substrate using a deposition process, the first dielectric layer contacting and covering each of the collector regions and each of the field oxygen isolation regions;

[0027] A portion of the first dielectric layer is removed using photolithography and etching processes to expose M first collector regions.

[0028] Optionally, the steps of forming a first doped polysilicon layer, the first doped polysilicon layer covering the residual first dielectric layer and the exposed first collector region, forming a second dielectric layer on the first doped polysilicon layer, etching the second dielectric layer and the first doped polysilicon layer, forming M first emitter windows corresponding one-to-one with the M first collector regions, the M first emitter windows exposing the M first collector regions one-to-one, and forming NM second emitter windows corresponding one-to-one with the NM second collector regions, the NM second emitter windows exposing the first dielectric layer on the NM second collector regions one-to-one, include:

[0029] A first polysilicon layer is formed using a deposition process, the first polysilicon layer covering the remaining first dielectric layer and the exposed first collector region;

[0030] The first polysilicon layer is doped using an ion implantation process. P+ type implantation doping is performed on the region of the first polysilicon layer located on the N-type doped collector region, and N+ type implantation doping is performed on the region of the first polysilicon layer located on the P-type doped collector region to form the first doped polysilicon layer.

[0031] The second dielectric layer is formed on the first doped polysilicon layer using a deposition process;

[0032] Using photolithography and etching processes, the second dielectric layer and the first doped polysilicon layer are etched to form M first emitter windows and NM second emitter windows. The M first emitter windows expose M first collector regions one by one, and the NM second emitter windows expose the first dielectric layer on the NM second collector regions one by one.

[0033] Optionally, the step of forming a third dielectric layer, which covers the remaining second dielectric layer and covers M first emitter windows and NM second emitter windows, and etching the third dielectric layer at the bottom of the NM second emitter windows to expose the first dielectric layer on the second collector region again, includes:

[0034] A deposition process is used to form the third dielectric layer, which covers the remaining second dielectric layer and covers M first emitter windows and NM second emitter windows;

[0035] Using photolithography and etching processes, the third dielectric layer at the bottom of NM second emitter windows is etched, exposing the first dielectric layer on the second collector region again.

[0036] Optionally, the step of etching along NM second emitter windows to remove the first dielectric layer at the bottom of the second emitter windows, exposing the second collector region and leaving the remaining first doped polysilicon layer at the bottom of the second emitter windows partially suspended includes:

[0037] Using photolithography and dry etching, dry etching is performed along NM second emitter windows to remove a portion of the first dielectric layer at the bottom of each second emitter window, with the etching remaining in the first dielectric layer;

[0038] A wet etching process is used to perform wet etching along NM second emitter windows to remove the remaining first dielectric layer at the bottom of each second emitter window and a portion of the first dielectric layer below the remaining first doped polysilicon layer, thereby exposing the second collector region and the remaining first doped polysilicon layer, and making the remaining first doped polysilicon layer at the bottom of the second emitter window partially suspended.

[0039] Optionally, the step of performing ion implantation and annealing along the M first emitter windows to form a first collector implantation layer, an inner base region, and an inner-outer base region connection layer in the first collector region, wherein the inner base region and the inner-outer base region connection layer are located on top of the first collector region, and the inner base region is connected to the residual first doped polysilicon layer through the inner-outer base region connection layer, includes:

[0040] The first ion implantation is performed along the M first emitter windows to form the first collector implantation layer in the M first collector regions respectively;

[0041] A second ion implantation is performed along the M first emitter windows, and P-type implantation doping is performed on the N-type doped collector region, and N-type implantation doping is performed on the P-type doped collector region. Inner base regions are formed in the M first collector regions respectively, and the inner base regions are located on top of the first collector regions and above the first collector implantation layer.

[0042] An annealing process is used to activate the impurities after ion implantation, so that the impurities in the remaining first doped polysilicon layer diffuse into the first collector region to form an inner and outer base region connection layer, and the remaining first doped polysilicon layer is connected to the inner base region through the inner and outer base region connection layer.

[0043] Optionally, after the step of etching along the NM second emitter windows to remove the fourth dielectric layer at the bottom of the second emitter windows to expose the germanium-silicon heterojunction inner base region in the second collector region, the method of integrating a double-layer polysilicon self-aligned vertical bipolar transistor in a germanium-silicon bipolar process further includes:

[0044] A fifth dielectric layer is formed, which covers the remaining fourth dielectric layer, the inner base region at the bottom of the first emitter window, and the inner base region of the germanium-silicon heterojunction at the bottom of the second emitter window;

[0045] The fifth dielectric layer is etched to expose the inner base region at the bottom of the first emitter window and the inner base region of the germanium-silicon heterojunction at the bottom of the second emitter window, and to form an emitter-base sidewall barrier structure.

[0046] A second doped polysilicon layer is formed, which covers the remaining fifth dielectric layer, the inner base region at the bottom of the first emitter window, and the inner base region of the germanium-silicon heterojunction at the bottom of the second emitter window.

[0047] The second doped polysilicon layer is etched and rapidly annealed to form a polysilicon emitter region. The impurities doped in the polysilicon emitter region diffuse into the inner base region at the bottom of the first emitter window and the inner base region of the germanium-silicon heterojunction at the bottom of the second emitter window to form an emitter-base junction.

[0048] Optionally, after the steps of etching the second doped polysilicon layer and rapidly annealing to form a polysilicon emitter region, and allowing the impurities doped in the polysilicon emitter region to diffuse into the inner base region at the bottom of the first emitter window and the inner base region of the germanium-silicon heterojunction at the bottom of the second emitter window to form an emitter-base junction, the method for integrating a double-layer polysilicon self-aligned vertical bipolar transistor in a germanium-silicon bipolar process further includes:

[0049] An emitter contact electrode, a base contact electrode, and a collector contact electrode are formed. The emitter contact electrode is in ohmic contact with the polycrystalline silicon emitter region, the base contact electrode is in ohmic contact with the remaining first doped polycrystalline silicon layer, and the collector contact electrode is in ohmic contact with the collector region.

[0050] A semiconductor device is fabricated by the method described in any one of the preceding claims for integrating a double-layer polycrystalline silicon self-aligned vertical bipolar transistor in a germanium-silicon bipolar process. The semiconductor device integrates a germanium-silicon heterojunction bipolar transistor and a silicon vertical bipolar transistor. The germanium-silicon heterojunction bipolar transistor includes a PNP type germanium-silicon heterojunction bipolar transistor or an NPN type germanium-silicon heterojunction bipolar transistor. The silicon vertical bipolar transistor includes a PNP type silicon vertical bipolar transistor or an NPN type silicon vertical bipolar transistor.

[0051] As described above, the method and semiconductor device for integrating a double-layer polysilicon self-aligned vertical bipolar transistor in a germanium-silicon bipolar process provided by the present invention have at least the following beneficial effects:

[0052] A first collector region and a second collector region are simultaneously formed on a silicon substrate. A first dielectric layer is formed and etched on the silicon substrate, exposing the first collector region and covering the second collector region. A first doped polysilicon layer and a second dielectric layer are then formed and etched to form a first emitter window and a second emitter window. The first emitter window exposes the first collector region, and the second emitter window exposes the first dielectric layer on the second collector region. A third dielectric layer is then formed and etched, again exposing the first dielectric layer at the bottom of the second emitter window. Ion implantation, etching, and epitaxial growth are performed along the second emitter window to form a germanium-silicon heterojunction inner base region on the second collector region at the bottom of the second emitter window. A fourth dielectric layer is formed and etched, again exposing the first collector region at the bottom of the first emitter window. Ion implantation and annealing are performed along the first emitter window to form the first collector region. In the bipolar region, a first collector injection layer, an inner base region, and an inner-outer base region connection layer are formed. Finally, etching is performed along the second emitter window to expose the germanium-silicon heterojunction inner base region in the second collector region. Subsequently, a polycrystalline silicon emitter region, as well as emitter contact electrodes, base contact electrodes, and collector contact electrodes are formed simultaneously. In this way, a process that integrates a double-layer polycrystalline silicon self-aligned vertical bipolar transistor in a germanium-silicon bipolar process can simultaneously integrate and fabricate silicon vertical bipolar transistors and germanium-silicon heterojunction bipolar transistors in a single manufacturing process without significantly increasing process complexity. This improves process efficiency and reduces process costs. Furthermore, transistors are further divided into NPN and PNP types, and the corresponding semiconductor devices can cover a variety of transistor structure combinations, suitable for various application scenarios with different functional requirements, and can improve the electrical performance of the corresponding semiconductor devices according to specific conditions. Attached Figure Description

[0053] Figure 1 The diagram illustrates the steps of the method for integrating a double-layer polysilicon self-aligned vertical bipolar transistor in a germanium-silicon bipolar process according to the present invention.

[0054] Figures 2-19 The diagram shown is a process flow diagram of a method for integrating a double-layer polysilicon self-aligned vertical bipolar transistor in a germanium-silicon bipolar process according to an optional embodiment of the present invention.

[0055] Explanation of icon numbers

[0056] 00—Field oxygen isolation region, 01—First collector region, 02—Second collector region, 03—Heavily doped buried layer, 100—Initial silicon substrate, 1—Silicon substrate, 2—First dielectric layer, 3—First doped polysilicon layer, 4—Second dielectric layer, 5—Third dielectric layer, 61—Second collector implantation layer, 62—Inner base region of germanium-silicon heterojunction, 63—First collector implantation layer, 64—Inner base region, 65—Internal and external base region connection layer, 7—Fourth dielectric layer, 8—Fifth dielectric layer, 9—Emitter-base sidewall barrier structure, 10—Second doped polysilicon layer, 11—Polysilicon emitter region, T1—First emitter window, T2—Second emitter window. Detailed Implementation

[0057] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0058] Please see Figures 1 to 19 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show components relevant to the present invention and are not drawn according to the actual number, shape, and size of the components in implementation. In actual implementation, the form, quantity, and proportion of each component can be arbitrarily changed, and the component layout may be more complex. The structures, proportions, sizes, etc., depicted in the accompanying drawings are only for illustrative purposes to aid those skilled in the art and are not intended to limit the implementation conditions of the present invention. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to the size, without affecting the effects and objectives achieved by the present invention, should still fall within the scope of the technical content disclosed in the present invention.

[0059] As described in the background section, the inventors discovered that vertical bipolar transistors are a key technology for high-speed / high-precision analog and radio frequency chips. Vertical silicon-germanium heterojunction bipolar transistors and silicon bipolar transistors each have their own advantages and disadvantages: vertical silicon-germanium heterojunction bipolar transistors have excellent radio frequency performance, but due to the lattice matching between silicon and germanium, they have higher crystal defects and higher leakage current; vertical silicon bipolar transistors can withstand a wider operating voltage and higher operating current, while having lower leakage current, but the device cutoff frequency is usually limited to within 50 GHz.

[0060] Based on this, the present invention proposes a SiGe-Si complementary bipolar process that integrates vertical bipolar transistors: a process for simultaneously integrating two layers of polycrystalline silicon self-aligned vertical bipolar transistors in a germanium-silicon bipolar process. Without significantly increasing process complexity, silicon vertical bipolar transistors and germanium-silicon heterojunction bipolar transistors are simultaneously fabricated in a single manufacturing process, thereby improving process efficiency and reducing process costs. Furthermore, transistors are further divided into NPN and PNP types, and the corresponding semiconductor devices cover a variety of transistor structure combinations, which can be applied to various application scenarios with different functional requirements, and the electrical performance of the corresponding semiconductor devices can be improved according to local conditions.

[0061] like Figure 1 As shown, this invention provides a method for integrating a double-layer polysilicon self-aligned vertical bipolar transistor in a germanium-silicon bipolar process, comprising the following steps:

[0062] S1. A silicon substrate 1 is provided, in which N collector regions and multiple field oxygen isolation regions 00 are formed. The N collector regions further include M first collector regions 01 and NM second collector regions 02, and each collector region is isolated from the others by the multiple field oxygen isolation regions 00.

[0063] S2. A first dielectric layer 2 is formed on a silicon substrate 1. The first dielectric layer 2 contacts and covers each collector region and each field oxygen isolation region 00. The first dielectric layer 2 is etched to expose M first collector regions 01.

[0064] S3. A first doped polysilicon layer 3 is formed, which covers the remaining first dielectric layer 2 and the exposed first collector region 01. A second dielectric layer 4 is formed on the first doped polysilicon layer 3, and the second dielectric layer 4 and the first doped polysilicon layer 3 are etched to form M first emitter windows T1 corresponding to M first collector regions 01. The M first emitter windows T1 expose the M first collector regions 01. NM second emitter windows T2 corresponding to NM second collector regions 02 are formed. The NM second emitter windows T2 expose the first dielectric layer 2 on the NM second collector regions 02.

[0065] S4. Form a third dielectric layer 5. The third dielectric layer 5 covers the remaining second dielectric layer 4 and covers M first emitter windows T1 and NM second emitter windows T2. Etch the third dielectric layer 5 at the bottom of NM second emitter windows T2 to expose the first dielectric layer 2 on the second collector region 02 again.

[0066] S5. Ion implantation is performed along the NM second emitter windows T2, passing through the first dielectric layer 2, to form a second collector implantation layer 61 in the second collector region 02.

[0067] S6. Etch along NM second emitter windows T2 to remove the first dielectric layer 2 at the bottom of the second emitter window T2, expose the second collector region O2 and make the first doped polysilicon layer 3 remaining at the bottom of the second emitter window T2 partially suspended.

[0068] S7. Epitaxial growth is performed along NM second emitter windows T2 to form a germanium-silicon heterojunction inner base region 62 on the second collector region 02 at the bottom of the second emitter window T2.

[0069] S8. Form a fourth dielectric layer 7, which covers the remaining third dielectric layer 5 and the germanium-silicon heterojunction inner base region 62. Etch the fourth dielectric layer 7 and the third dielectric layer 5 to expose the first collector region 01 at the bottom of the first emitter window T1.

[0070] S9. Ion implantation and annealing are performed along the M first emitter windows T1 to form a first collector implantation layer 63, an inner base region 64 and an inner and outer base region connection layer 65 in the first collector region 01. The inner base region 64 and the inner and outer base region connection layer 65 are located at the top of the first collector region 01, and the inner base region 64 is connected to the residual first doped polysilicon layer 3 through the inner and outer base region connection layer 65.

[0071] S10. Etch along NM second emitter windows T2 to remove the fourth dielectric layer 7 at the bottom of the second emitter window T2, so as to expose the germanium-silicon heterojunction inner base region 62 in the second collector region 02.

[0072] Where N is an integer greater than or equal to 2, M is an integer greater than or equal to 1, and M is less than N.

[0073] In detail, in step S1, as Figure 2 As shown, the silicon substrate 1 has N collector regions, including a first collector region 01 and a second collector region 02 (here, M is 1 and N is 2, and the values ​​of M and N are not limited to these, and can be flexibly adjusted according to actual needs). Based on the differentiated requirements of the bipolar transistor types to be formed later, the first collector region 01 can be an N-type doped collector region or a P-type doped collector region, and the second collector region 02 is similar. The collector regions can be formed by epitaxy of doped materials, or they can be prepared by ion implantation doping process (ion implantation + annealing), which is not limited here. At the same time, a heavily doped buried layer 03 and a field oxygen isolation region 00 are also formed in the silicon substrate 1.

[0074] In detail, in an optional embodiment of the invention, such as Figure 2 As shown, step S1, which provides the silicon substrate 01, further includes:

[0075] S101, Provide an initial silicon substrate 100, the initial silicon substrate 100 including N device regions (e.g., Figure 2 (The regions separated by the dashed line);

[0076] S102. N heavily doped buried layers 03 are formed one-to-one on the N device regions of the initial silicon substrate 100. The heavily doped buried layers 03 further include N-type heavily doped buried layers and P-type heavily doped buried layers.

[0077] S103. N collector regions are formed one-to-one on the N device regions of the initial silicon substrate 100. The collector regions include N-type doped collector regions and P-type doped collector regions. Along the Z-axis, the N-type doped collector regions are located on the N-type heavily doped buried layer, and the P-type doped collector regions are located on the P-type heavily doped buried layer.

[0078] S104. Multiple field oxygen isolation regions 00 are formed to isolate N device regions. In the first plane (i.e., the XY plane), the field oxygen isolation regions 00 are arranged around the N-type doped collector region and the N-type heavily doped buried layer, or the field oxygen isolation regions 00 are arranged around the P-type doped collector region and the P-type heavily doped buried layer.

[0079] More specifically, in step S101, the initial silicon substrate 100 is both the support layer and the structural layer of the entire semiconductor device. It can be a single-crystal silicon material or other substrate materials such as silicon-on-insulator (SOI), which are not limited here.

[0080] More specifically, in step S102, an ion implantation process followed by an annealing process or an epitaxial process can be used to form a heavily doped buried layer 03, which is then used to reduce the Rc resistance of the transistor ultimately formed. To further reduce the Rc resistance of the final transistor, N collector penetration layers (not shown in the figure) can be formed one-to-one on the N device regions of the initial silicon substrate 100. For details, please refer to the prior art, which will not be repeated here.

[0081] More specifically, in step S103, an ion implantation process followed by an annealing process or an epitaxial process can be used to form N collector regions corresponding to the N device regions on the initial silicon substrate 100. The N collector regions further include M first collector regions 01 and NM second collector regions 02. The first collector regions 01 are used to form silicon vertical bipolar transistors, and the second collector regions 02 are used to form germanium-silicon heterojunction bipolar transistors. The first collector regions 01 include N-type doped collector regions or P-type doped collector regions, and the second collector regions 02 include N-type doped collector regions or P-type doped collector regions. On each device region, the doping type of the collector region is the same as the doping type of the corresponding heavily doped buried layer 03.

[0082] More specifically, in step S104, photolithography, etching, deposition, photolithography, and etching processes can be used sequentially to form trenches and then fill them, forming multiple field oxygen isolation regions 00 on the initial silicon substrate 100 based on deep trench isolation technology. Alternatively, photolithography and oxidation processes can be used sequentially to form multiple field oxygen isolation regions 00 on the initial silicon substrate 100 based on local field oxygen technology. The field oxygen isolation regions 00 isolate each device region. In the first plane (i.e., the XY plane), the field oxygen isolation regions 00 are arranged around a device region, so that the N-type doped collector region and the N-type heavily doped buried layer in the device region are isolated from other structures, or the P-type doped collector region and the P-type heavily doped buried layer in the device region are isolated from other structures.

[0083] In detail, in an optional embodiment of the invention, such as Figure 3 As shown, step S2, which involves forming a first dielectric layer 2 on a silicon substrate 1, the first dielectric layer 2 contacting and covering each collector region and each field-oxygen isolation region 02, and etching the first dielectric layer 2 to expose M first collector regions 01, further includes:

[0084] S201. A first dielectric layer 2 is formed on a silicon substrate 1 using a deposition process. The first dielectric layer 2 contacts and covers each collector region and each field oxygen isolation region 00.

[0085] S202. Using photolithography and etching processes, a portion of the first dielectric layer 2 is removed to expose M first collector regions 01.

[0086] More specifically, in step S201, a first dielectric layer 2 is formed on the silicon substrate 1 using a chemical vapor deposition (CVD) process or a thermal oxidation process. The first dielectric layer 2 can be made of silicon oxide or silicon nitride. The thickness of the first dielectric layer 2 depends on the thickness of the SiGe epitaxial layer in subsequent process steps (depending on the specific application scenario's requirements for device characteristic frequency and breakdown voltage; for most applications, it is between 20nm and 200nm).

[0087] More specifically, in step S202, photolithography and etching processes are sequentially used to remove the first dielectric layer 2 on the first collector region 01, so as to facilitate the subsequent base region process of the silicon vertical bipolar transistor.

[0088] In detail, in an optional embodiment of the invention, such as Figures 4-6As shown, step S3, which involves forming a first doped polysilicon layer 3, covering the remaining first dielectric layer 2 and the exposed first collector region 01, forming a second dielectric layer 4 on the first doped polysilicon layer 3, and etching the second dielectric layer 4 and the first doped polysilicon layer 3 to form M first emitter windows T1 corresponding to M first collector regions 01, each of which exposes one of the M first collector regions 01, and forming NM second emitter windows T2 corresponding to NM second collector regions 02, each of which exposes one of the first dielectric layers 2 on the NM second collector regions 02, further includes:

[0089] S301, such as Figure 4 As shown, a first polysilicon layer is formed using a deposition process, which covers the remaining first dielectric layer 2 and the exposed first collector region 01.

[0090] S302, such as Figure 4 As shown, the first polysilicon layer is doped using an ion implantation process (not shown in the figure), the region of the first polysilicon layer located on the N-type doped collector region is subjected to P+ type implantation doping, and the region of the first polysilicon layer located on the P-type doped collector region is subjected to N+ type implantation doping to form the first doped polysilicon layer 3.

[0091] S303, such as Figure 5 As shown, a second dielectric layer 4 is formed on the first doped polysilicon layer 3 using a deposition process;

[0092] S304, such as Figure 6 As shown, a photolithography process (not shown in the figure) and an etching process are used to etch the second dielectric layer 4 and the first doped polysilicon layer 3 to form M first emitter windows T1 and NM second emitter windows T2. The M first emitter windows T1 expose M first collector regions 01 one by one, and the NM second emitter windows T2 expose the first dielectric layer 2 on the NM second collector regions 02 one by one.

[0093] More specifically, in steps S301 to S302, such as Figure 4 As shown, the first doped polysilicon layer 3 is formed using a deposition process followed by ion implantation. It is understood that the first doped polysilicon layer 3 can also be formed using a doped polysilicon deposition process; this is not a limitation here.

[0094] More specifically, in step S303, such as Figure 5 As shown, the second dielectric layer 4 formed can be a single layer of silicon nitride or a single layer of silicon oxide, or it can be a multilayer composite layer of silicon nitride and silicon oxide. When the second dielectric layer 4 is a multilayer composite layer of silicon nitride and silicon oxide, the top layer is silicon nitride.

[0095] More specifically, in step S304, such as Figure 6 As shown, a photoresist mask layer is first formed using photolithography. Then, etching is performed using the photoresist mask layer as a mask to form M first emitter windows T1 and NM second emitter windows T2. The etching of the first emitter windows T1 stops on the first collector region 01, exposing the first collector region 01. The etching of the second emitter windows T2 stops on the first dielectric layer 2, exposing the first dielectric layer 2 on the second collector region 02. At the same time, device isolation trenches are formed by etching, cutting off the first doped polysilicon layer 3 and the second dielectric layer 4 in each device region to form independent blocks.

[0096] In detail, in an optional embodiment of the invention, such as Figures 7-8 As shown, step S4, which involves forming a third dielectric layer 5, covering the remaining second dielectric layer 4, and covering M first emitter windows T1 and NM second emitter windows T2, and etching the bottom of the NM second emitter windows T2 to expose the first dielectric layer 2 on the second collector region O2 again, includes:

[0097] S401, such as Figure 7 As shown, a third dielectric layer 5 is formed using a deposition process. The third dielectric layer 5 covers the remaining second dielectric layer 4 and covers M first emitter windows T1 and NM second emitter windows T2.

[0098] S402, such as Figure 8 As shown, the third dielectric layer 5 at the bottom of NM second emitter windows T2 is etched using photolithography and etching processes, thereby exposing the first dielectric layer 2 on the second collector region O2 again.

[0099] More specifically, in steps S401 to S402, the third dielectric layer 5 is first formed and then etched to expose the first dielectric layer 2 on the second collector region 02 again, which serves as a mask for subsequent ion implantation.

[0100] In detail, in an optional embodiment of the present invention, as shown in Figure 8, in step S5, ion implantation is performed along NM second emitter windows T2, passing through the first dielectric layer 2, to form a second collector implantation layer 61 in the second collector region O2. It should be noted that step S5, which forms the second collector implantation layer 61, is a non-essential step and can be flexibly decided whether to take it depending on the circumstances.

[0101] In detail, in an optional embodiment of the present invention, as shown in 9, step S6, which involves etching along NM second emitter windows T2 to remove the first dielectric layer 2 at the bottom of the second emitter windows T2, exposing the second collector region O2, and leaving the first doped polysilicon layer 3 remaining at the bottom of the second emitter windows T2 partially suspended, further includes:

[0102] S601. Using photolithography and dry etching, dry etching is performed along NM second emitter windows T2 to remove part of the first dielectric layer 2 at the bottom of each second emitter window T2, and the etching stops in the first dielectric layer 2.

[0103] S602. Using a wet etching process, wet etching is performed along NM second emitter windows T2 to remove the portion of the first dielectric layer 2 remaining at the bottom of each second emitter window T2 and below the remaining first doped polysilicon layer 3, so as to expose the second collector region O2 and the remaining first doped polysilicon layer 3, and make the portion of the remaining first doped polysilicon layer 3 at the bottom of the second emitter window T2 suspended.

[0104] More specifically, in steps S601 to S602, as follows: Figure 9 As shown, by combining anisotropic dry etching and isotropic wet etching, the first dielectric layer 2 at the bottom of the second emitter window T2 is removed, and a laterally etched "suspended layer" is formed below the first doped polysilicon layer 3 at the bottom of the second emitter window T2. Simultaneously, the sidewalls and bottom of the first emitter window T1 are blocked by the remaining third dielectric layer 5; the sidewalls of the second emitter window T2 are also blocked by the remaining third dielectric layer 5, and the bottom of the second emitter window T2 exposes the second collector region O2.

[0105] In detail, in an optional embodiment of the present invention, as shown in 10, in step S7, an epitaxial growth process is used to perform epitaxial growth along NM second emitter windows T2, and a germanium-silicon heterojunction inner base region 62 of SiGe or SiGe:C material is formed on the second collector region 02 at the bottom of the second emitter window T2. The formed germanium-silicon heterojunction inner base region 62 is connected to the second collector region 02 and the residual first doped polysilicon layer 3, respectively.

[0106] In detail, in an optional embodiment of the invention, such as 11- Figure 12 As shown, in step S8, a deposition process is used to form a fourth dielectric layer 7. The fourth dielectric layer 7 covers the remaining third dielectric layer 5 and the inner base region 62 of the germanium-silicon heterojunction. The fourth dielectric layer 7 and the third dielectric layer 5 are etched to expose the first collector region 01 at the bottom of the first emitter window T1. The fourth dielectric layer 7 is a single layer or a composite layer structure of silicon oxide or silicon nitride, which will not be described in detail here.

[0107] In detail, in an optional embodiment of the invention, such as 12- Figure 14 As shown, step S9, which involves ion implantation and annealing along M first emitter windows T1 to form a first collector implantation layer 63, an inner base region 64, and an inner-outer base region connection layer 65 in the first collector region 01, wherein the inner base region 64 and the inner-outer base region connection layer 65 are located at the top of the first collector region 01, and the inner base region 64 is connected to the residual first doped polysilicon layer 3 through the inner-outer base region connection layer 65, further includes:

[0108] S901, such as Figure 12 As shown, the first ion implantation is performed along the M first emitter windows T1, and the first collector implantation layer 63 is formed in the M first collector regions 01 respectively;

[0109] S902, such as Figure 13 As shown, a second ion implantation is performed along the M first emitter windows T1, P-type implantation doping is performed on the N-type doped collector region, and N-type implantation doping is performed on the P-type doped collector region, forming an inner base region 64 in each of the M first collector regions 01. The inner base region 64 is located at the top of the first collector region 01 and above the first collector implantation layer 63.

[0110] S903, such as Figure 14 As shown, the impurities after ion implantation are activated by annealing, so that the impurities in the residual first doped polysilicon layer 3 diffuse into the first collector region 01 to form the inner and outer base region connection layer 65, and the residual first doped polysilicon layer 3 is connected to the inner base region 64 through the inner and outer base region connection layer 65.

[0111] More specifically, in steps S901 to S902, a first collector implantation layer 63 and an inner base region 64 are formed through two ion implantations. The inner base region 64 is located on top of the first collector region 01 and above the first collector implantation layer 63. Step S901, which forms the first collector implantation layer 63, is optional and can be flexibly determined depending on the situation.

[0112] More specifically, in step S903, after the second ion implantation, impurity activation diffusion is performed based on the annealing process to form an inner and outer base region connection layer 65, and the connection between the residual first doped polysilicon layer 3 and the inner base region 64 is achieved through the inner and outer base region connection layer 65.

[0113] In detail, in an optional embodiment of the present invention, as shown in 15, in step S10, etching is performed along NM second emitter windows T2 to remove the fourth dielectric layer 7 at the bottom of the second emitter window T2, so as to expose the germanium-silicon heterojunction inner base region 62 in the second collector region 02, thereby exposing the silicon inner base region structure in the first emitter window T1 and the germanium-silicon inner base region structure in the second emitter window T2 respectively, which facilitates the synchronous fabrication of the subsequent emitter structure.

[0114] In detail, in an optional embodiment of the invention, such as Figures 16-19 As shown, after step S10, which involves etching along NM second emitter windows T2 to remove the fourth dielectric layer 7 at the bottom of the second emitter windows T2 to expose the germanium-silicon heterojunction inner base region 62 in the second collector region O2, the method for integrating a double-layer polysilicon self-aligned vertical bipolar transistor in a germanium-silicon bipolar process further includes:

[0115] S11, such as Figure 16 As shown, a fifth dielectric layer 8 is formed, which covers the remaining fourth dielectric layer 7, the inner base region 64 at the bottom of the first emitter window T1, and the germanium-silicon heterojunction inner base region 62 at the bottom of the second emitter window T2.

[0116] S12, such as Figure 17 As shown, the fifth dielectric layer 8 is etched to expose the inner base region 64 at the bottom of the first emitter window T1 and the germanium-silicon heterojunction inner base region 62 at the bottom of the second emitter window T2, and to form an emitter-base sidewall barrier structure 9.

[0117] S13, such as Figure 18 As shown, a second doped polysilicon layer 10 is formed, which covers the remaining fifth dielectric layer 8, the inner base region 64 at the bottom of the first emitter window T1, and the germanium-silicon heterojunction inner base region 62 at the bottom of the second emitter window T2.

[0118] S14, such as Figure 19 As shown, the second doped polysilicon layer 10 is etched and rapidly annealed to form a polysilicon emitter region 11, and the impurities doped in the polysilicon emitter region 11 diffuse into the inner base region 64 at the bottom of the first emitter window T1 and the inner base region 62 of the germanium-silicon heterojunction at the bottom of the second emitter window T1 to form an emitter-base junction.

[0119] More specifically, in steps S11 to S12, such as Figures 16-17 As shown, a fifth dielectric layer 8 is first formed on the entire surface using a deposition process. The fifth dielectric layer 8 generally adopts a composite layer structure. Then, the emitter-base sidewall barrier structure 9 with a conventional or "L" shaped morphology is formed by combining the layers using the industry-standard "Spacer" fabrication process.

[0120] More specifically, in step S13, such as Figure 18 As shown, a second polycrystalline silicon layer is first formed on the entire surface using a deposition process. Then, the second polycrystalline silicon layer is heavily doped with ions, such as phosphorus or arsenic for N+ type ion implantation and boron or boron difluoride for P+ type ion implantation, thereby forming the second doped polycrystalline silicon layer 10.

[0121] More specifically, in step S14, as Figure 19 As shown, the second doped polysilicon layer 10 is etched and rapidly annealed (RTA) to form a polysilicon emitter region 11. The impurities doped in the polysilicon emitter region 11 diffuse into the inner base region 64 at the bottom of the first emitter window T1 and the germanium-silicon heterojunction inner base region 62 at the bottom of the second emitter window T2, forming an emitter-base junction. Simultaneously, most of the remaining fifth dielectric layer 8, third dielectric layer 7, third dielectric layer 5, and second dielectric layer 4 are etched away to expose the remaining first polysilicon layer 3, which serves as the outer base region structure, facilitating the subsequent fabrication of the base contact electrode. At this point, the main structures of the silicon vertical bipolar transistor and the germanium-silicon heterojunction bipolar transistor are complete.

[0122] In detail, in an optional embodiment of the present invention, after step S14 of etching the second doped polysilicon layer 10 and rapidly annealing to form a polysilicon emitter region 11, and allowing the impurities doped in the polysilicon emitter region 11 to diffuse into the inner base region 64 at the bottom of the first emitter window T1 and the inner base region 62 of the germanium-silicon heterojunction at the bottom of the second emitter window T1 to form an emitter-base junction, the method for integrating a double-layer polysilicon self-aligned vertical bipolar transistor in a germanium-silicon bipolar process further includes:

[0123] S15. Form an emitter contact electrode, a base contact electrode, and a collector contact electrode. The emitter contact electrode is in 11-ohm contact with the polysilicon emitter region, the base contact electrode is in 3-ohm contact with the remaining first doped polysilicon layer, and the collector contact electrode is in ohm contact with the collector region.

[0124] More specifically, in step S15, metal is deposited and etched to form emitter contact electrodes, base contact electrodes, and collector contact electrodes to electrically lead out the electrodes of each bipolar transistor. Furthermore, depending on the specific application requirements, subsequent processes may involve combinations of silicide, ILD dielectric, vias / through-holes, multilayer metal wiring, surface passivation, etc. These process structures and methods are common practices in the semiconductor industry and are not the focus of this invention; therefore, they will not be detailed here.

[0125] Finally, based on the above method of integrating a double-layer polycrystalline silicon self-aligned vertical bipolar transistor in a germanium-silicon bipolar process, a semiconductor device is prepared. The semiconductor device integrates a germanium-silicon heterojunction bipolar transistor and a silicon vertical bipolar transistor. The germanium-silicon heterojunction bipolar transistor includes a PNP type germanium-silicon heterojunction bipolar transistor or an NPN type germanium-silicon heterojunction bipolar transistor, and the silicon vertical bipolar transistor includes a PNP type silicon vertical bipolar transistor or an NPN type silicon vertical bipolar transistor.

[0126] Among them, such as Figures 2-19 The process shown corresponds to the fabrication of one germanium-silicon heterojunction bipolar transistor and two silicon vertical bipolar transistors. The specific type of each bipolar transistor can be flexibly selected. It should be noted that the semiconductor device simultaneously integrates germanium-silicon heterojunction bipolar transistors and silicon vertical bipolar transistors, and the number and type of the two types of bipolar transistors can be arbitrarily combined and configured, without limitation here.

[0127] In an optional embodiment of the present invention, an NPN germanium-silicon heterojunction bipolar transistor and an NPN silicon vertical bipolar transistor are integrated on the semiconductor device. The NPN germanium-silicon heterojunction bipolar transistor is used to achieve high-performance radio frequency or low-noise performance, while the NPN silicon vertical bipolar transistor is used to extend high-voltage functions, build low-leakage modules, or improve the ESD (electrostatic discharge) capability of the entire circuit.

[0128] In an optional embodiment of the present invention, an NPN type germanium-silicon heterojunction bipolar transistor and a PNP type silicon vertical bipolar transistor are integrated on the semiconductor device. The PNP type silicon vertical bipolar transistor is used to compensate for the shortcomings of the LPNP transistor in conventional SiGe process and to construct a complementary push-pull structure, etc.

[0129] For example, in an optional embodiment of the present invention, an NPN type germanium-silicon heterojunction bipolar transistor, a PNP type silicon vertical bipolar transistor, and an NPN type silicon vertical bipolar transistor are integrated on the semiconductor device. Since it can simultaneously possess the RF performance of an NPN type germanium-silicon heterojunction bipolar transistor and the vertically symmetrical complementary NPN type silicon vertical bipolar transistor and PNP type silicon vertical bipolar transistor, this type of integrated circuit can realize the function of integrating an RF module with a high-speed high-voltage slew rate operational amplifier and a logarithmic detector amplifier with a unique complementary push-pull structure and exponential / logarithmic volt-ampere characteristics on the same chip.

[0130] Currently, the mainstream SiGe bipolar process solutions in the industry fall into two main categories: the first is the conventional SiGe bipolar process, which integrates vertically structured NPN germanium-silicon heterojunction bipolar transistors and lateral PNP silicon bipolar transistors; the second is the complementary SiGe bipolar process, which simultaneously integrates vertically structured NPN germanium-silicon heterojunction bipolar transistors and vertically structured PNP germanium-silicon heterojunction bipolar transistors. Compared with the first type of solution, this invention can integrate vertically structured silicon vertical bipolar transistors to compensate for the performance deficiencies of LPNP transistors in conventional SiGe processes, such as for constructing complementary push-pull structures. This structure has a wide range of applications in high-speed, high-precision, and wideband operational amplifiers and logarithmic amplifier products. Compared with the second type of solution, this invention has significant cost advantages (simpler process, no need for additional N-type SiGe epitaxial furnaces, etc.). In addition, it can utilize the higher withstand voltage and lower leakage current characteristics of silicon vertical bipolar transistors compared to germanium-silicon bipolar transistors to expand high-voltage functions, construct low-leakage modules, or improve the ESD capability of the entire circuit.

[0131] Based on the above analysis, the process scheme for integrating a double-layer polysilicon self-aligned vertical bipolar transistor in a germanium-silicon bipolar process provided by the present invention involves simultaneously forming a first collector region and a second collector region on a silicon substrate. A first dielectric layer is formed and etched on the silicon substrate, exposing the first collector region and covering the second collector region after etching. A first doped polysilicon layer and a second dielectric layer are then formed and etched to form a first emitter window and a second emitter window. The first emitter window exposes the first collector region, and the second emitter window exposes the first dielectric layer on the second collector region. A third dielectric layer is then formed and etched, again exposing the first dielectric layer at the bottom of the second emitter window. Ion implantation, etching, and epitaxial growth are performed along the second emitter window to form a germanium-silicon heterojunction inner base region on the second collector region at the bottom of the second emitter window. A fourth dielectric layer is formed and etched, again exposing the first collector region at the bottom of the first emitter window. Ion implantation and annealing are performed along the first emitter window to form a first collector implantation layer, an inner base region, and an inner-outer base region connection layer in the first collector region. Finally, etching is performed along the second emitter window to expose the germanium-silicon heterojunction inner base region in the second collector region. Subsequently, a polycrystalline silicon emitter region, as well as emitter contact electrodes, base contact electrodes, and collector contact electrodes are formed simultaneously. In this way, a process that integrates a double-layer polycrystalline silicon self-aligned vertical bipolar transistor in a germanium-silicon bipolar process can simultaneously integrate and fabricate silicon vertical bipolar transistors and germanium-silicon heterojunction bipolar transistors in a single manufacturing process without significantly increasing process complexity. This improves process efficiency and reduces process costs. Furthermore, transistors are further divided into NPN and PNP types, and the corresponding semiconductor devices can cover a variety of transistor structure combinations, suitable for various application scenarios with different functional requirements, and can improve the electrical performance of corresponding semiconductor devices according to specific conditions.

[0132] It should be noted that the steps in the above embodiments omit well-known and obvious industry-standard cleaning processes and conditions, which are common knowledge to those skilled in the art and will not be described in detail here.

[0133] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for integrating a double-layer polysilicon self-aligned vertical bipolar transistor in a germanium-silicon bipolar process, characterized in that, include: A silicon substrate is provided in which N collector regions and a plurality of field oxygen isolation regions are formed, wherein the N collector regions include M first collector regions and NM second collector regions, and each collector region is isolated from the others by the plurality of field oxygen isolation regions. A first dielectric layer is formed on the silicon substrate, the first dielectric layer contacts and covers each of the collector regions and each of the field oxygen isolation regions, and the first dielectric layer is etched to expose NM of the first collector regions; A first doped polysilicon layer is formed, which covers the remaining first dielectric layer and the exposed first collector region. A second dielectric layer is formed on the first doped polysilicon layer. The second dielectric layer and the first doped polysilicon layer are etched to form M first emitter windows corresponding to M first collector regions. The M first emitter windows expose the M first collector regions. NM second emitter windows corresponding to NM second collector regions are formed. The NM second emitter windows expose the first dielectric layer on the NM second collector regions. A third dielectric layer is formed, which covers the remaining second dielectric layer and covers M first emitter windows and NM second emitter windows. The third dielectric layer at the bottom of NM second emitter windows is etched to expose the first dielectric layer on the second collector region again. Ion implantation is performed along NM second emitter windows, passing through the first dielectric layer, to form a second collector implantation layer in the second collector region; Etching is performed along NM second emitter windows to remove the first dielectric layer at the bottom of the second emitter windows, exposing the second collector region and leaving the remaining first doped polysilicon layer at the bottom of the second emitter windows partially suspended. Epitaxial growth is performed along NM second emitter windows to form a germanium-silicon heterojunction inner base region on the second collector region at the bottom of the second emitter window; A fourth dielectric layer is formed, which covers the remaining third dielectric layer and the inner base region of the germanium-silicon heterojunction. The fourth dielectric layer and the third dielectric layer are etched to expose the first collector region at the bottom of the first emitter window. Ion implantation and annealing are performed along M first emitter windows to form a first collector implantation layer, an inner base region and an inner-outer base region connection layer in the first collector region. The inner base region and the inner-outer base region connection layer are located on top of the first collector region, and the inner base region is connected to the residual first doped polysilicon layer through the inner-outer base region connection layer. Etching is performed along NM second emitter windows to remove the fourth dielectric layer at the bottom of the second emitter windows, thereby exposing the germanium-silicon heterojunction inner base region in the second collector region; Where N is an integer greater than or equal to 2, M is an integer greater than or equal to 1, and M is less than N.

2. The method for integrating a double-layer polysilicon self-aligned vertical bipolar transistor in a germanium-silicon bipolar process according to claim 1, characterized in that, The first collector region includes an N-type doped collector region or a P-type doped collector region, the second collector region includes an N-type doped collector region or a P-type doped collector region, and the step of providing a silicon substrate includes: An initial silicon substrate is provided, the initial silicon substrate comprising N device regions; N heavily doped buried layers are formed one-to-one on the N device regions of the initial silicon substrate, including N-type heavily doped buried layers and P-type heavily doped buried layers. N collector regions are formed one-to-one on the N device regions of the initial silicon substrate. The collector regions include N-type doped collector regions and P-type doped collector regions. The N-type doped collector regions are located on the N-type heavily doped buried layer, and the P-type doped collector regions are located on the P-type heavily doped buried layer. Multiple field oxygen isolation regions are formed to isolate N device regions. In a first plane, the field oxygen isolation regions are arranged around the N-type doped collector region and the N-type heavily doped buried layer, or the field oxygen isolation regions are arranged around the P-type doped collector region and the P-type heavily doped buried layer.

3. The method for integrating a double-layer polysilicon self-aligned vertical bipolar transistor in a germanium-silicon bipolar process according to claim 2, characterized in that, The step of forming a first dielectric layer on the silicon substrate, the first dielectric layer contacting and covering each of the collector regions and each of the field-oxygen isolation regions, and etching the first dielectric layer to expose M of the first collector regions includes: A first dielectric layer is formed on the silicon substrate using a deposition process, the first dielectric layer contacting and covering each of the collector regions and each of the field oxygen isolation regions; A portion of the first dielectric layer is removed using photolithography and etching processes to expose M first collector regions.

4. The method for integrating a double-layer polysilicon self-aligned vertical bipolar transistor in a germanium-silicon bipolar process according to claim 3, characterized in that, The steps of forming a first doped polysilicon layer, the first doped polysilicon layer covering the residual first dielectric layer and the exposed first collector region, forming a second dielectric layer on the first doped polysilicon layer, etching the second dielectric layer and the first doped polysilicon layer, forming M first emitter windows corresponding one-to-one with M first collector regions, the M first emitter windows exposing M first collector regions one-to-one, and forming NM second emitter windows corresponding one-to-one with NM second collector regions, the NM second emitter windows exposing the first dielectric layer on the NM second collector regions one-to-one, include: A first polysilicon layer is formed using a deposition process, the first polysilicon layer covering the remaining first dielectric layer and the exposed first collector region; The first polysilicon layer is doped using an ion implantation process. P+ type implantation doping is performed on the region of the first polysilicon layer located on the N-type doped collector region, and N+ type implantation doping is performed on the region of the first polysilicon layer located on the P-type doped collector region to form the first doped polysilicon layer. The second dielectric layer is formed on the first doped polysilicon layer using a deposition process; Using photolithography and etching processes, the second dielectric layer and the first doped polysilicon layer are etched to form M first emitter windows and NM second emitter windows. The M first emitter windows expose M first collector regions one by one, and the NM second emitter windows expose the first dielectric layer on the NM second collector regions one by one.

5. The method for integrating a double-layer polysilicon self-aligned vertical bipolar transistor in a germanium-silicon bipolar process according to claim 4, characterized in that, The step of forming a third dielectric layer, which covers the remaining second dielectric layer and covers M first emitter windows and NM second emitter windows, and etching the third dielectric layer at the bottom of the NM second emitter windows to expose the first dielectric layer on the second collector region again, includes: A deposition process is used to form the third dielectric layer, which covers the remaining second dielectric layer and covers M first emitter windows and NM second emitter windows; Using photolithography and etching processes, the third dielectric layer at the bottom of NM second emitter windows is etched, exposing the first dielectric layer on the second collector region again.

6. The method for integrating a double-layer polysilicon self-aligned vertical bipolar transistor in a germanium-silicon bipolar process according to claim 5, characterized in that, The step of etching along NM second emitter windows to remove the first dielectric layer at the bottom of the second emitter windows, exposing the second collector region and leaving the remaining first doped polysilicon layer at the bottom of the second emitter windows partially suspended includes: Using photolithography and dry etching, dry etching is performed along NM second emitter windows to remove a portion of the first dielectric layer at the bottom of each second emitter window, with the etching remaining in the first dielectric layer; A wet etching process is used to perform wet etching along NM second emitter windows to remove the remaining first dielectric layer at the bottom of each second emitter window and a portion of the first dielectric layer below the remaining first doped polysilicon layer, thereby exposing the second collector region and the remaining first doped polysilicon layer, and making the remaining first doped polysilicon layer at the bottom of the second emitter window partially suspended.

7. The method for integrating a double-layer polysilicon self-aligned vertical bipolar transistor in a germanium-silicon bipolar process according to claim 2, characterized in that, The step of ion implantation and annealing along M first emitter windows to form a first collector implantation layer, an inner base region, and an inner-outer base region connection layer in the first collector region, wherein the inner base region and the inner-outer base region connection layer are located on top of the first collector region, and the inner base region is connected to the residual first doped polysilicon layer through the inner-outer base region connection layer, includes: The first ion implantation is performed along the M first emitter windows to form the first collector implantation layer in the M first collector regions respectively; A second ion implantation is performed along the M first emitter windows, and P-type implantation doping is performed on the N-type doped collector region, and N-type implantation doping is performed on the P-type doped collector region. Inner base regions are formed in the M first collector regions respectively, and the inner base regions are located on top of the first collector regions and above the first collector implantation layer. An annealing process is used to activate the impurities after ion implantation, so that the impurities in the remaining first doped polysilicon layer diffuse into the first collector region to form an inner and outer base region connection layer, and the remaining first doped polysilicon layer is connected to the inner base region through the inner and outer base region connection layer.

8. The method for integrating a double-layer polysilicon self-aligned vertical bipolar transistor in a germanium-silicon bipolar process according to claim 1, characterized in that, After the step of etching along NM second emitter windows to remove the fourth dielectric layer at the bottom of the second emitter windows to expose the germanium-silicon heterojunction inner base region in the second collector region, the method of integrating a double-layer polysilicon self-aligned vertical bipolar transistor in a germanium-silicon bipolar process further includes: A fifth dielectric layer is formed, which covers the remaining fourth dielectric layer, the inner base region at the bottom of the first emitter window, and the inner base region of the germanium-silicon heterojunction at the bottom of the second emitter window; The fifth dielectric layer is etched to expose the inner base region at the bottom of the first emitter window and the inner base region of the germanium-silicon heterojunction at the bottom of the second emitter window, and to form an emitter-base sidewall barrier structure. A second doped polysilicon layer is formed, which covers the remaining fifth dielectric layer, the inner base region at the bottom of the first emitter window, and the inner base region of the germanium-silicon heterojunction at the bottom of the second emitter window. The second doped polysilicon layer is etched and rapidly annealed to form a polysilicon emitter region. The impurities doped in the polysilicon emitter region diffuse into the inner base region at the bottom of the first emitter window and the inner base region of the germanium-silicon heterojunction at the bottom of the second emitter window to form an emitter-base junction.

9. The method for integrating a double-layer polysilicon self-aligned vertical bipolar transistor in a germanium-silicon bipolar process according to claim 8, characterized in that, After etching the second doped polysilicon layer and rapidly annealing to form a polysilicon emitter region, and allowing the impurities doped in the polysilicon emitter region to diffuse into the inner base region at the bottom of the first emitter window and the inner base region of the germanium-silicon heterojunction at the bottom of the second emitter window to form an emitter-base junction, the method for integrating a double-layer polysilicon self-aligned vertical bipolar transistor in a germanium-silicon bipolar process further includes: An emitter contact electrode, a base contact electrode, and a collector contact electrode are formed. The emitter contact electrode is in ohmic contact with the polycrystalline silicon emitter region, the base contact electrode is in ohmic contact with the remaining first doped polycrystalline silicon layer, and the collector contact electrode is in ohmic contact with the collector region.

10. A semiconductor device, characterized in that, The semiconductor device is prepared by the method of integrating a double-layer polycrystalline silicon self-aligned vertical bipolar transistor in a germanium-silicon bipolar process according to any one of claims 1-9. The semiconductor device is provided with a germanium-silicon heterojunction bipolar transistor and a silicon vertical bipolar transistor. The germanium-silicon heterojunction bipolar transistor includes a PNP type germanium-silicon heterojunction bipolar transistor or an NPN type germanium-silicon heterojunction bipolar transistor. The silicon vertical bipolar transistor includes a PNP type silicon vertical bipolar transistor or an NPN type silicon vertical bipolar transistor.

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