Silicon controlled rectifier, method for manufacturing silicon controlled rectifier, chip and circuit

Abstract

The application provides a thyristor device, a thyristor device manufacturing method, a chip and a circuit, and belongs to the field of semiconductor devices.The device comprises a substrate, a first well region, a second well region, a first injection region and a third well region formed in the first well region along the length direction of the substrate, a second injection region and a third injection region respectively formed in the second well region and the third well region, a fourth injection region and a fifth injection region respectively formed in the second injection region and the third injection region, a first polysilicon layer and a second polysilicon layer respectively formed on the surface of the substrate on both sides of the first injection region, a first isolation groove and a second isolation groove respectively formed on both sides of the first injection region, and the fourth injection region and the first polysilicon layer are connected to an electrical anode through a metal wire, and the fifth injection region and the second polysilicon layer are connected to an electrical cathode through a metal wire.Through the device provided by the application, higher ESD protection capability can be provided, the current direction is more uniform, and the response speed of the device is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, specifically to a silicon controlled rectifier (SCR) device, a method for manufacturing a SCR device, a chip, and a circuit. Background Technology

[0002] Electrostatic discharge (ESD) is a common natural phenomenon in daily life. For example, you might experience an electric spark when taking off a sweater in winter or feel an electric shock when touching a metal doorknob. Essentially, it's the transfer of static charge between two or more different charged objects. Therefore, an object becoming charged is a prerequisite for ESD. There are various ways an object can become charged, such as through friction or induction. Different types of ESD can have different consequences, ranging from the discomfort of an electric shock to serious incidents like spacecraft malfunctions causing injury or death.

[0003] ESD events are short-lived, but in the integrated circuit field, semiconductor components and chips are extremely fragile. ESD events generate enormous transient currents and voltages, causing significant damage to integrated circuits. Especially with the continuous advancement of semiconductor processes and the increasing scale of integrated circuits, the impact of ESD on integrated circuits is becoming increasingly significant. The high voltage and large current of ESD can cause irreversible integrated circuit failures such as gate oxide breakdown in MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors), thermal damage, and metal interconnect melting failures. It can also lead to latch-up effects, device performance degradation, and other conditions affecting the normal operation of chips. All of this demonstrates that ESD protection design for integrated circuits has become an indispensable research focus in chip design.

[0004] ESD protection design requires a series of ESD protection devices. The most commonly used ESD protection devices include diodes, bipolar junction transistors (BJTs), MOSFETs, and silicon controlled rectifiers (SCRs). Each of these ESD protection devices has its advantages and disadvantages, and the appropriate device should be selected based on the specific needs of the application. Generally, however, ESD protection devices need to meet three conditions: transparency, effectiveness, and robustness. Specifically, the protection device should be in the off state when the integrated circuit is operating normally, and should quickly turn on to discharge the ESD current when an ESD pulse arrives. The protection device itself also needs to have a certain degree of resistance to ESD pulses.

[0005] In the protection of input / output (I / O) pins and power domains of integrated circuit chips, SCRs are one of the most commonly used structures. Compared to diodes and MOSFETs, SCRs have the highest robustness per unit area, meaning they occupy the smallest layout area to achieve the same protection level. SCR devices with embedded MOSFETs are transistor-based devices, widely used in ESD protection due to their controllable breakdown characteristics and high voltage withstand capability. In existing technologies, traditional bidirectional SCRs are typically finger-strip structures, exhibiting poor robustness and slow response speed. Summary of the Invention

[0006] To address the issues of poor robustness and slow response speed of traditional bidirectional SCRs in existing technologies, this invention provides a silicon controlled rectifier (SCR) device, a method for fabricating the SCR device, a chip, and a circuit. Using this SCR device, the invention provides two current inflow / outflow paths, enhancing the robustness of the SCR device. When an ESD pulse arrives, the initial current can be discharged through the embedded double-diffused field-effect transistor path, thereby assisting in triggering the SCR path. Finally, most of the electrostatic current is discharged through the SCR path. Furthermore, the second and third injection regions are formed within the second and third well regions, respectively, and the fourth and fifth injection regions are formed within the second and third injection regions, respectively. Compared to the traditional finger-strip structure, this is more compact, providing higher ESD protection capability within the same device area, with more uniform current flow and faster device response speed.

[0007] To achieve the above objectives, the present invention provides a silicon controlled resonant device, comprising: a substrate having a first conductivity type; a first well region having a second conductivity type different from the first conductivity type; a second well region, a first implantation region, and a third well region formed within the first well region along the length direction of the substrate, wherein the second well region and the third well region have the first conductivity type, and the first implantation region is heavily doped with the second conductivity type; a second implantation region and a third implantation region formed within the second well region and the third well region, respectively, wherein the second implantation region and the third implantation region are heavily doped with the second conductivity type; a fourth implantation region and a fifth implantation region. The fourth and fifth implantation regions are respectively formed in the second and third implantation regions, and are heavily doped with a first conductivity type. A first polysilicon layer and a second polysilicon layer are respectively formed on the substrate surface on both sides of the first implantation region, with the first polysilicon layer surrounding the second implantation region and the second polysilicon layer surrounding the third implantation region. A first isolation trench and a second isolation trench are respectively formed on both sides of the first implantation region. The fourth implantation region and the first polysilicon layer are connected to the electrical anode through a metal interconnect, and the fifth implantation region and the second polysilicon layer are connected to the electrical cathode through a metal interconnect.

[0008] Furthermore, the second well region, the third well region, the second injection region, the third injection region, the fourth injection region, and the fifth injection region are centrally symmetric configurations.

[0009] Furthermore, the second injection region and the third injection region are centrally symmetrical octagonal configurations.

[0010] Furthermore, the fourth injection region and the fifth injection region are centrally symmetrical octagonal configurations.

[0011] Furthermore, the second and third well regions are centrally symmetric octagonal configurations.

[0012] Furthermore, the doping concentration of the second well region and the third well region is less than 10. 15 cm -3 .

[0013] Furthermore, the depth of the first well region is greater than 1 μm.

[0014] A second aspect of the present invention provides a method for fabricating a silicon controlled rectifier (SCR) device, the method comprising: providing a substrate having a first conductivity type; forming a first well region within the substrate by ion implantation, the first well region having a second conductivity type different from the first conductivity type; forming a second well region and a third well region within the first well region along the length of the substrate by ion implantation, the second well region and the third well region having the first conductivity type; forming a first isolation trench and a second isolation trench between the second well region and the third well region along the length of the substrate; forming a first implantation region, a second implantation region, and a third implantation region by ion implantation, the first implantation region being located between the first isolation trench and the second isolation trench, the second implantation region and the third implantation region being formed by ion implantation. The implantation regions are formed in the second well region and the third well region, respectively. The first implantation region, the second implantation region, and the third implantation region are heavily doped with a second conductivity type. A fourth implantation region is formed in the second implantation region by ion implantation, and a fifth implantation region is formed in the third implantation region. The fourth implantation region and the fifth implantation region are heavily doped with a first conductivity type. A first polysilicon layer and a second polysilicon layer are formed on the substrate surface on both sides of the first implantation region by low-pressure chemical deposition. The first polysilicon layer surrounds the second implantation region, and the second polysilicon layer surrounds the third implantation region. The fourth implantation region and the first polysilicon layer are connected to the anode by metal interconnects, and the fifth implantation region and the second polysilicon layer are connected to the cathode by metal interconnects.

[0015] Further, the step of forming the first implantation region, the second implantation region, and the third implantation region by ion implantation includes: forming a photoresist layer on the substrate surface; forming an implantation window on the photoresist layer using a photolithography process; performing heavy doping ion implantation of the second conductivity type on the substrate through the implantation window to form the first implantation region between the first isolation trench and the second isolation trench, forming the second implantation region in the second well region, and forming the third implantation region in the third well region.

[0016] A third aspect of the present invention provides a chip comprising the silicon controlled rectifier device described above.

[0017] A fourth aspect of the present invention provides a circuit comprising the aforementioned thyristor device.

[0018] The present invention has at least the following technical effects through the technical solution provided by the present invention:

[0019] The thyristor device of the present invention includes a substrate having a first conductivity type, and a first well region having a second conductivity type formed within the substrate. A second well region, a first implantation region, and a third well region are formed along the length of the substrate within the first well region. Within the second well region, the second and third well regions have the first conductivity type, and the first implantation region is heavily doped with the second conductivity type. The second and third implantation regions are respectively formed within the second and third well regions, and are heavily doped with the second conductivity type. A fourth and fifth implantation regions are respectively formed within the second and third implantation regions, and are heavily doped with the first conductivity type. A first polysilicon layer and a second polysilicon layer are respectively formed on the substrate surface on both sides of the first implantation region, with the first polysilicon layer surrounding the second implantation region and the second polysilicon layer surrounding the third implantation region. A first isolation trench and a second isolation trench are respectively formed on both sides of the first implantation region. The fourth implantation region and the first polysilicon layer are connected to an electrical anode via a metal interconnect, and the fifth implantation region and the second polysilicon layer are connected to an electrical cathode via a metal interconnect. The thyristor device provided by this invention can protect circuits from damage caused by forward and reverse ESD, providing two current inflow / outflow paths and enhancing the robustness of the thyristor device. When an ESD pulse arrives, the initial current can be discharged through the embedded double-diffused field-effect transistor path, which in turn assists in triggering the thyristor path. Finally, most of the electrostatic current is discharged through the thyristor path. Moreover, the fourth and fifth injection regions are formed within the second and third injection regions, respectively, which is more compact than the traditional finger-strip structure, providing higher ESD protection capability within the same device area, with more uniform current flow and faster device response speed.

[0020] Other features and advantages of the present invention will be described in detail in the following detailed description section. Attached Figure Description

[0021] The accompanying drawings are provided to further illustrate embodiments of the present invention and form part of the specification. They are used together with the following detailed description to explain the embodiments of the present invention, but do not constitute a limitation thereof. In the drawings:

[0022] Figure 1 A top view of a silicon controlled rectifier device provided in an embodiment of the present invention;

[0023] Figure 2 A cross-sectional view of the thyristor device provided in an embodiment of the present invention along the AA' direction;

[0024] Figure 3 A comparison chart of test results of the thyristor device provided in the embodiments of the present invention and the existing finger-shaped thyristor device under forward electrostatic discharge protection;

[0025] Figure 4 This is a flowchart illustrating a method for fabricating a silicon controlled rectifier (SCR) device according to an embodiment of the present invention.

[0026] Explanation of reference numerals in the attached figures

[0027] 1-Substrate; 2-First well region; 3-Second well region; 4-Third well region; 5-First implantation region; 6-Second implantation region; 7-Third implantation region; 8-Fourth implantation region; 9-Fifth implantation region; 10-First polysilicon layer; 11-Second polysilicon layer; 12-First isolation trench; 13-Second isolation trench. Detailed Implementation

[0028] The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit the scope of the present invention.

[0029] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.

[0030] In this invention, unless otherwise stated, directional terms such as "upper," "lower," "top," and "bottom" are generally used to describe the relative positions of components in relation to the directions shown in the accompanying drawings or in relation to the vertical, perpendicular, or gravitational directions.

[0031] The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0032] Please refer to Figures 1-3This invention provides a silicon controlled rectifier (SCR) device, comprising: a substrate 1 having a first conductivity type; a first well region 2 having a second conductivity type different from the first conductivity type; a second well region 3, a first implantation region 5, and a third well region 4 formed along the length of the substrate within the first well region 2, wherein the second well region 3 and the third well region 4 have the first conductivity type, and the first implantation region 5 is heavily doped with the second conductivity type; a second implantation region 6 and a third implantation region 7 formed respectively within the second well region 3 and the third well region 4, wherein the second implantation region 6 and the third implantation region 7 are heavily doped with the second conductivity type; and a fourth implantation region 8 and a fifth implantation region 9 formed respectively within the substrate. Within the second implantation region 6 and the third implantation region 7, the fourth implantation region 8 and the fifth implantation region 9 are heavily doped with a first conductivity type; a first polysilicon layer 10 and a second polysilicon layer 11 are respectively formed on the surface of the substrate 1 on both sides of the first implantation region 5, with the first polysilicon layer 10 surrounding the second implantation region 6 and the second polysilicon layer 11 surrounding the third implantation region 7; a first isolation trench 12 and a second isolation trench 13 are respectively formed on both sides of the first implantation region 5; the fourth implantation region 8 and the first polysilicon layer 10 are connected to the electrical anode via a metal interconnect, and the fifth implantation region 9 and the second polysilicon layer 11 are connected to the electrical cathode via a metal interconnect.

[0033] Specifically, in this embodiment of the invention, the first conductivity type can be either N-type or P-type. This invention does not limit this; the following textual embodiments only use P-type as the first conductivity type and N-type as the second conductivity type for illustration. The thyristor device includes a P-type substrate 1, within which an N-type first well region 2 is formed. Within the first well region 2, a P-type second well region 3, an N-type heavily doped first implantation region 5, and a P-type third well region 4 are sequentially formed along the length of the substrate. An N-type heavily doped second implantation region 6 is formed within the P-type second well region 3, and a P-type heavily doped fourth implantation region 8 is formed within the N-type heavily doped second implantation region 6, forming a structure where the second implantation region 6 surrounds the fourth implantation region 8. An N-type heavily doped third implantation region 7 is formed within the P-type third well region 4, and a P-type heavily doped fifth implantation region 9 is formed within the N-type heavily doped third implantation region 7, forming a structure where the third implantation region 7 surrounds the fifth implantation region 9.

[0034] A first polysilicon layer 10 and a second polysilicon layer 11 are formed on both sides of the N-type first implantation region 5, respectively. In the top view, the first polysilicon layer 10 surrounds the second implantation region 6, and the second polysilicon layer 11 surrounds the third implantation region 7. Figure 1To clearly show the second well region 3 and the third well region 4 within the first well region 2, only a portion of the first polysilicon layer 10 and the second polysilicon layer 11 are shown. A first isolation trench 12 and a second isolation trench 13 are formed on both sides of the first implantation region 5. The first isolation trench 12 isolates the first polysilicon layer 10 from the first implantation region 5, and the second isolation trench 13 isolates the second polysilicon layer 11 from the first implantation region 5.

[0035] The fourth implantation region 8 and the first polysilicon layer 10 are connected to the electrical anode via a metal interconnect, and the fifth implantation region 9 and the second polysilicon layer 11 are connected to the electrical cathode via a metal interconnect.

[0036] In this thyristor device, a bidirectional field-diffused transistor is formed by two drift regions coupled together. The first well region 2, the first injection region 5, the first polysilicon layer 10, the second injection region 6, the second well region 3, and the first isolation trench 12 together constitute a forward N-type bidirectional field-diffused transistor, where the first well region 2 serves as the drift region and the second well region 3 serves as the body region. The first well region 2, the first injection region 5, the second polysilicon layer 11, the third injection region 7, the third well region 4, and the second isolation trench 13 together constitute a reverse N-type bidirectional field-diffused transistor, where the first well region 2 serves as the drift region and the third well region 4 serves as the body region.

[0037] The P-type fourth injection region 8, P-type second well region 3, N-type first well region 2, P-type third well region 4, and N-type third injection region 7 constitute a forward thyristor. The P-type fifth injection region 9, P-type third well region 4, N-type first well region 2, P-type second well region 3, and N-type second injection region 6 constitute a reverse thyristor.

[0038] When a forward electrostatic discharge (ESD) occurs, the forward bidirectional field-diffused transistor (PDT), composed of the first well region 2, the first injection region 5, the first polysilicon layer 10, the second injection region 6, the second well region 3, and the first isolation trench 12, and the reverse bidirectional field-diffused transistor (RDT), composed of the first well region 2, the first injection region 5, the second polysilicon layer 11, the third injection region 7, the third well region 4, and the second isolation trench 13, conducts firstly. Current flows from the second injection region 6 through the channel of the forward DDT into the first well region 2, and then from the first well region 2 through the channel of the reverse DDT into the third injection region 7. As the internal ESD current gradually increases, avalanche breakdown occurs between the first well region 2 and the third well region 4. The forward thyristor path, composed of the P-type fourth injection region 8, the P-type second well region 3, the N-type first well region 2, the P-type third well region 4, and the N-type third injection region 7, opens, discharging most of the current and providing higher ESD protection. Please refer to [reference needed]. Figure 3 , Figure 3 This diagram shows a comparison of test results between the thyristor device provided in this embodiment of the invention and the existing finger-strip thyristor device under forward electrostatic discharge (ESD) protection. Figure 3It can be seen that the forward electrostatic current that the thyristor device provided in this embodiment can withstand is greater than that of the finger bar thyristor device.

[0039] When reverse electrostatic discharge occurs, the reverse bidirectional field-diffused transistor (SDPT), composed of the first well region 2, the first injection region 5, the second polysilicon layer 11, the third injection region 7, the third well region 4, and the second isolation trench 13, and the forward bidirectional field-diffused transistor (PBDT), composed of the first well region 2, the first injection region 5, the first polysilicon layer 10, the second injection region 6, the second well region 3, and the first isolation trench 12, are turned on firstly. Current flows from the third injection region 7 through the channel of the reverse PBDT into the first well region 2, and then from the first well region 2 through the channel of the forward PBDT into the second injection region 6. As the electrostatic discharge current inside the device gradually increases, avalanche breakdown occurs between the first well region 2 and the second well region 3. The reverse thyristor path, composed of the P-type fifth injection region 9, the P-type third well region 4, the N-type first well region 2, the P-type second well region 3, and the N-type second injection region 6, is activated, discharging most of the current and providing higher ESD protection.

[0040] The thyristor device provided by this invention can protect circuits from damage caused by forward and reverse ESD, providing two current inflow / outflow paths and enhancing the robustness of the thyristor device. When an ESD pulse arrives, the initial current can be discharged through the embedded double-diffused field-effect transistor path, thereby assisting in triggering the thyristor path, and finally, most of the electrostatic current is discharged through the thyristor path. Furthermore, the second and third injection regions are formed within the second and third well regions, respectively, and the fourth and fifth injection regions are formed within the second and third injection regions, respectively. Compared to the traditional finger-strip structure, this is more compact, providing higher ESD protection capability within the same device area, with more uniform current flow and faster device response. It also has the advantages of low voltage leakage current and high ESD failure current. It can provide reliable ESD protection under high-speed, high-voltage pulses and is suitable for various high-end electronic equipment applications.

[0041] Furthermore, the second well region 3, the third well region 4, the second injection region 6, the third injection region 7, the fourth injection region 8, and the fifth injection region 9 are centrally symmetric configurations.

[0042] Specifically, in the embodiments of the present invention, the second well region 3, the third well region 4, the second injection region 6, the third injection region 7, the fourth injection region 8, and the fifth injection region 9 are centrally symmetrical. This ensures that the current flows more uniformly in the second well region 3, the second injection region 6, the fourth injection region 8, the third well region 4, the third injection region 7, and the fifth injection region 9, thus ensuring the response speed of the device. Furthermore, the structure of the thyristor device is more compact, providing stronger ESD protection.

[0043] Furthermore, the second injection region 6 and the third injection region 7 are centrally symmetrical octagonal configurations.

[0044] Specifically, in this embodiment of the invention, the second injection region 6 and the third injection region 7 are centrally symmetrical octagonal configurations. This configuration allows for more uniform current flow in the second injection region 6 and the third injection region 7, and is more in line with the layout geometry design rules. This is beneficial for improving device yield during the manufacturing process, reducing the corner peaks of the second injection region 6 and the third injection region 7, and preventing device breakdown.

[0045] Furthermore, the fourth injection region 8 and the fifth injection region 9 are centrally symmetrical octagonal configurations.

[0046] Specifically, in this embodiment of the invention, the fourth injection region 8 and the fifth injection region 9 are centrally symmetrical octagonal configurations. This configuration allows for more uniform current flow in the fourth injection region 8 and the fifth injection region 9, and is more in line with the layout geometry design rules. This is beneficial for improving device yield during the manufacturing process, reducing the corner peaks of the fourth injection region 8 and the fifth injection region 9, and preventing device breakdown.

[0047] Furthermore, the second well region 3 and the third well region 4 are centrally symmetric octagonal configurations.

[0048] Specifically, in this embodiment of the invention, the second well region 3 and the third well region 4 are centrally symmetrical octagonal configurations. This configuration allows for more uniform current flow in the second well region 3 and the third well region 4, and is more in line with the layout geometry design rules. This is beneficial for improving the device yield during the manufacturing process, reducing the corner peaks of the second well region 3 and the third well region 4, and preventing device breakdown.

[0049] Furthermore, the doping concentration of the second well region 3 and the third well region 4 is less than 10. 15 cm -3 .

[0050] Specifically, in this embodiment of the invention, the doping concentration of the second well region 3 and the third well region 4 is less than 10. 15 cm -3 This doping concentration enables the formation of a high-voltage second well region 3 and a high-voltage third well region 4, thereby improving the breakdown voltage of both forward and reverse bidirectional field-diffused transistors.

[0051] Furthermore, the depth of the first well region 2 is greater than 1 μm.

[0052] Specifically, in this embodiment of the invention, the depth of the first well region 2 is greater than 1 μm. The first well region 2 can isolate and protect the thyristor device, preventing interference from other modules to the thyristor device.

[0053] Please refer to Figure 4 The second aspect of the present invention provides a method for fabricating a silicon controlled rectifier (SCR) device, the method comprising: providing a substrate 1 having a first conductivity type; forming a first well region 2 within the substrate 1 by ion implantation, the first well region 2 having a second conductivity type different from the first conductivity type; forming a second well region 3 and a third well region 4 within the first well region 2 along the length direction of the substrate by ion implantation, the second well region 3 and the third well region 4 having the first conductivity type; forming a first isolation trench 12 and a second isolation trench 13 between the second well region 3 and the third well region 4 along the length direction of the substrate; forming a first implantation region 5, a second implantation region 6, and a third implantation region 7 by ion implantation, the first implantation region 5 being located between the first isolation trench 12 and the second isolation trench 13, the second implantation region 6 and the third implantation region 7 being formed by ion implantation. The first implantation region 5, the second implantation region 6, and the third implantation region 7 are respectively formed in the second well region 3 and the third well region 4, and are heavily doped with the second conductivity type. A fourth implantation region 8 is formed in the second implantation region 6 by ion implantation, and a fifth implantation region 9 is formed in the third implantation region 7. The fourth implantation region 8 and the fifth implantation region 9 are heavily doped with the first conductivity type. A first polysilicon layer 10 and a second polysilicon layer 11 are formed on the surface of the substrate 1 on both sides of the first implantation region 5 by low-pressure chemical deposition. The first polysilicon layer 10 surrounds the second implantation region 6, and the second polysilicon layer 11 surrounds the third implantation region 7. The fourth implantation region 8 and the first polysilicon layer 10 are connected to the anode by metal interconnects, and the fifth implantation region 9 and the second polysilicon layer 11 are connected to the cathode by metal interconnects.

[0054] Further, the step of forming the first implantation region 5, the second implantation region 6, and the third implantation region 7 by ion implantation includes: forming a photoresist layer on the surface of the substrate 1; forming an implantation window in the photoresist layer using a photolithography process; performing heavy doping ion implantation of the second conductivity type on the substrate 1 through the implantation window to form the first implantation region 5 between the first isolation trench 12 and the second isolation trench 13, forming the second implantation region 6 in the second well region 3, and forming the third implantation region 7 in the third well region 4.

[0055] A third aspect of the present invention provides a chip comprising the silicon controlled rectifier device described above.

[0056] A fourth aspect of the present invention provides a circuit comprising the aforementioned thyristor device.

[0057] The preferred embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the specific details of the above embodiments. Within the scope of the technical concept of the present invention, various simple modifications can be made to the technical solution of the present invention, and these simple modifications all fall within the protection scope of the present invention.

[0058] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present invention will not describe the various possible combinations separately.

[0059] Furthermore, various different embodiments of the present invention can be combined in any way, as long as they do not violate the spirit of the present invention, they should also be regarded as the content disclosed by the present invention.

Claims

1. A silicon controlled rectifier (SCR) device, characterized in that, The thyristor device includes: The substrate has a first type of conductivity; The first well region has a second conductivity type that is different from the first conductivity type; A second well region, a first implantation region, and a third well region are formed within the first well region along the length of the substrate. The second well region and the third well region have the first conductivity type, and the first implantation region has a second conductivity type and is heavily doped. The second implantation region and the third implantation region are formed in the second well region and the third well region, respectively, and the second implantation region and the third implantation region are heavily doped with the second conductivity type; The fourth and fifth implantation regions are formed in the second and third implantation regions, respectively, and the fourth and fifth implantation regions are heavily doped with a first conductivity type; A first polysilicon layer and a second polysilicon layer are formed on the substrate surfaces on both sides of the first implantation region, and the first polysilicon layer surrounds the second implantation region, and the second polysilicon layer surrounds the third implantation region. The first isolation groove and the second isolation groove are respectively formed on both sides of the first injection area; The fourth injection region and the first polysilicon layer are connected to the electrical anode via a metal interconnect, and the fifth injection region and the second polysilicon layer are connected to the electrical cathode via a metal interconnect.

2. The thyristor device according to claim 1, characterized in that, The second well region, the third well region, the second injection region, the third injection region, the fourth injection region, and the fifth injection region are centrally symmetric.

3. The thyristor device according to claim 2, characterized in that, The second injection region and the third injection region are centrally symmetrical octagonal configurations.

4. The thyristor device according to claim 2, characterized in that, The fourth and fifth injection regions are centrally symmetrical octagonal configurations.

5. The thyristor device according to claim 2, characterized in that, The second and third well regions are centrally symmetric octagonal configurations.

6. The thyristor device according to claim 1, characterized in that, a doping concentration of the second well region and the third well region is less than 10 15 cm -3 .

7. The thyristor device according to claim 1, characterized in that, The depth of the first well region is greater than 1 μm.

8. A method for fabricating a silicon controlled rectifier (SCR) device, characterized in that, The method for manufacturing the thyristor device includes: A substrate is provided, the substrate having a first conductivity type; A first well region is formed in the substrate by ion implantation, the first well region having a second conductivity type different from the first conductivity type; A second well region and a third well region are formed along the length of the substrate within the first well region by ion implantation, and the second well region and the third well region have the first conductivity type; A first isolation trench and a second isolation trench are formed between the second well region and the third well region along the length of the substrate. A first implantation region, a second implantation region, and a third implantation region are formed by ion implantation. The first implantation region is located between the first isolation trench and the second isolation trench. The second implantation region and the third implantation region are respectively formed in the second well region and the third well region. The first implantation region, the second implantation region, and the third implantation region are heavily doped with a second conductivity type. A fourth implantation region is formed in the second implantation region by ion implantation, and a fifth implantation region is formed in the third implantation region, wherein the fourth and fifth implantation regions are heavily doped with a first conductivity type. A first polysilicon layer and a second polysilicon layer are formed on the substrate surfaces on both sides of the first implantation region by low-pressure chemical deposition. The first polysilicon layer surrounds the second implantation region, and the second polysilicon layer surrounds the third implantation region. The fourth injection region and the first polysilicon layer are connected to the electrical anode via metal interconnects, and the fifth injection region and the second polysilicon layer are connected to the electrical cathode via metal interconnects.

9. The method for fabricating a thyristor device according to claim 8, characterized in that, The process of forming the first implantation region, the second implantation region, and the third implantation region by ion implantation includes: A photoresist layer is formed on the surface of the substrate; An injection window is formed in the photoresist layer using photolithography. The substrate is implanted with heavily doped ions of the second conductivity type through the implantation window, forming the first implantation region between the first isolation trench and the second isolation trench, forming the second implantation region in the second well region, and forming the third implantation region in the third well region.

10. A chip, characterized in that, The chip includes the silicon controlled rectifier device according to any one of claims 1-7.

11. A circuit, characterized in that, The circuit includes the thyristor device according to any one of claims 1-7.

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