Printed circuit board (PCB) and inner layer thereof

Abstract

This application relates to wideband routing techniques for PCB layout. In particular, one aspect of the application provides techniques to reduce the amount of crosstalk for single-ended signals in a pin field area of an integrated circuit device on a printed circuit board (PCB). The PCB can include a plurality of layers and a via array including a plurality of rows configured to route signals across layers. An inner layer of the PCB can include a first signal trace and a second signal trace positioned between adjacent first and second rows of the vias, the first signal trace positioned adjacent the first row and the second signal trace positioned adjacent the second row. The first signal trace can include at least one bend segment that curves around a substantial portion of a corresponding via in the first row, such that a gap between the first signal trace and the second signal trace varies along the bend segment.

Description

Technical Field

[0001] The present disclosure generally relates to the design of signal routing on a printed circuit board (PCB). Background Art

[0002] More particularly, the present disclosure relates to routing techniques for broadband signal paths within an escape region of an integrated circuit device on a PCB. Summary of the Invention

[0003] A first aspect of the present disclosure relates to a printed circuit board (PCB), comprising: a plurality of layers; and a via array, the via array comprising a plurality of rows, the plurality of rows being configured to connect signals across layers, the vias in adjacent rows being arranged in a staggered manner; wherein an inner layer comprises a first signal trace and a second signal trace positioned between a first adjacent row and a second adjacent row of vias, the first signal trace being positioned adjacent to the first row, and the second signal trace being positioned adjacent to the second row; the first signal trace comprising at least one bent segment bent around a substantial portion of a corresponding via in the first row, such that a gap between the first signal trace and the second signal trace varies along the bent segment; and the gap between the first signal trace and the second signal trace increases toward a first position between adjacent vias in the first row, and decreases toward a second position between adjacent vias in the second row.

[0004] A second aspect of the present disclosure relates to an inner layer of a printed circuit board (PCB), comprising: a via array, the via array comprising a plurality of rows, the plurality of rows being configured to connect signals across a plurality of layers of the PCB, the vias in adjacent rows being arranged in a staggered manner; and a first signal trace and a second signal trace positioned between adjacent first and second rows of vias, the first signal trace being positioned adjacent to the first row, and the second signal trace being positioned adjacent to the second row; the first signal trace comprising at least one bent segment bent around a substantial portion of a corresponding via in the first row, such that a gap between the first signal trace and the second signal trace varies along the bent segment; and the gap between the first signal trace and the second signal trace increasing toward a first position between adjacent vias in the first row, and decreasing toward a second position between adjacent vias in the second row. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 The diagram illustrates multiple high-speed signal traces running through a pin field via array of a system-on-chip (SOC) device.

[0006] Figure 2 Illustrated are a plurality of high-speed signal traces routed through an array of vias according to one aspect of the present application.

[0007] Figure 3Illustrated is a magnified view of a via anti-pad and a signal trace according to one aspect of the present application.

[0008] Figure 4 Symmetrical routing of signal traces according to one aspect of the present application is illustrated.

[0009] Figure 5 The diagram illustrates the routing of signal traces around signal and ground vias according to one aspect of the present application.

[0010] Figure 6 A signal trace having a widened section according to one aspect of the present application is illustrated.

[0011] Figure 7 A flow chart illustrating a process of designing a through-routing on a PCB according to one aspect of the present application is presented.

[0012] Throughout the drawings, like reference numerals refer to like drawing elements. DETAILED DESCRIPTION

[0013] The following description is presented to enable any person skilled in the art to make and use the examples, and is provided in the context of a specific application and its requirements. Various modifications to the disclosed examples will be apparent to those skilled in the art, and the general principles defined herein may be applied to other examples and applications without departing from the spirit and scope of the present disclosure. Therefore, the scope of the present disclosure is not limited to the examples shown, but is intended to be consistent with the widest scope consistent with the principles and features disclosed herein.

[0014] The present disclosure provides a solution for routing broadband single-ended signal traces that pass through a surface mounted integrated circuit device, such as a ball grid array (BGA) package or a land grid array (LGA) package. According to a first aspect, a pair of single-ended signal traces can be arranged between adjacent rows of a via array of an integrated circuit device. The spacing between the two single-ended signal traces can be adjusted by adding additional length to one of the two signal traces (e.g., the upper signal trace). More specifically, additional length can be added to the signal trace at each position between two adjacent via anti-pads so that the signal trace is routed away from the other signal trace at that position. The increased length increases the gap between the signal traces, thereby reducing crosstalk between the signal traces. According to a second aspect, additional length can be added to two signal traces to increase the overall gap without causing a significant length difference between the two signal traces. According to a third aspect, the signal trace can be routed closer to the ground via because the reference plane does not have a via anti-pad. This can increase the gap between signal traces adjacent to ground vias and break up the repetitive periodic structure of through-routing, further reducing the amount of crosstalk between signal traces. Additionally, the width of signal traces can be widened between adjacent via anti-pads to reduce the impedance of single-ended signal traces.

[0015] The development of system-on-chip (SOC) technology has led to an increase in the number of high-speed input / output (I / O) channels and an increase in the number of memory channels. Generally speaking, the number of signals increases with each new generation of SOC. This can lead to an increase in the SOC package size, thereby increasing the signal path length in the pin field area on the PCB under the SOC package, which can be a BGA package or a LGA package.

[0016] Increased path length can negatively impact the quality of signals propagating along the path, particularly high-speed signals. For example, a typical SOC may have multiple single-ended high-speed / wideband signal channels, such as double data rate 4 or 5 (DDR4 or DDR5) memory channels. Note that DDR5 memory channels can support data transfer rates of several gigabits per second (MT / s), which requires a channel bandwidth well in excess of 3 GHz. When multiple (e.g., two) such high-speed signals are routed parallel to each other over an electrically significant distance (e.g., a distance longer than the rise time of the signal), the effects of long coupling lengths and adjacent pads or vias can adversely impact signal quality, increase crosstalk, and cause frequency-dependent impedance changes.

[0017] Figure 1 The figure shows multiple high-speed signal traces running through the pin field via array of the SOC device. Figure 1, a partial top view of PCB 100 is shown. PCB 100 may be a multi-layer PCB and may include multiple devices mounted on its surface, including SOC device 102 and memory device 104. SOC device 102 and memory device 104 may be interconnected via multiple single-ended high-speed signal traces. SOC device 102 may be a BGA package or LGA package including a pin array. Note that Figure 1 Only a portion of the PCB 100 is shown in FIG. Figure 1 Also shown is an array of vias (e.g., vias 106, 108, and 110) positioned beneath the SOC device 102. The inclusion of vias in the PCB 100 allows signal traces (e.g., traces 112 and 114) on internal PCB signal routing layers to connect to the pins / pads of the SOC device 102. The presence of the array of vias also complicates the routing of signal traces from the pin field of the SOC device 102. More specifically, signal traces must be routed within the spaces between adjacent rows of vias, which are referred to as routing channels. Figure 1 As shown in FIG, signal traces 112 and 114 are routed in the channel between the top row of the via array and the second row of the via array.

[0018] exist Figure 1 In the example shown in FIG, the via array is arranged in a staggered manner, where the vias in adjacent rows are offset in position. For example, vias 106 and 108 are in the same row, and via 110 is in an adjacent row, and via 110 is aligned not with vias 106 or 108, but with the midpoint between vias 106 and 108. Note that the pattern of the via array matches the pattern of the contact pins / pads of the package ( Figure 1 (not shown in Figure 1). The staggered pin / pad array allows for a tighter pin field density. At the same time, closely spaced pins / pads and vias can make routing through the array more challenging. Compared to a non-staggered array, the width of the routing channel (i.e., the space between two adjacent rows) can be much smaller, which means that the distance between a pair of single-ended signal traces (e.g., traces 112 and 114) in each channel can be smaller.

[0019] exist Figure 1 In the example shown in FIG, a pair of signal traces in each routing channel extend substantially parallel to each other, which may result in a considerable amount of crosstalk. As the size of the SOC device 102 increases (e.g., due to an increase in the memory channel count), the length of the signal traces (e.g., traces 112 and 114) that need to pass through the pin field of the SOC device 102 will also increase, resulting in increased crosstalk between these adjacent signal traces. To reduce crosstalk, according to one aspect of the present application, the signal traces in the routing channel can be arranged in a manner different from that of the first signal trace and the second signal trace. Figure 1More specifically, in addition to using the space between adjacent via rows, the routing channel can also use the empty space between adjacent vias in the same row to route the signal trace.

[0020] Figure 2 The figure shows a plurality of high-speed signal traces routed through a via array according to one aspect of the present application. Figure 2 In the example, a particular signal trace layer 200 may include multiple signal traces and an array of via anti-pads. Note that the term "via anti-pad" generally refers to a void on the reference metal layer of a PCB. To maintain signal integrity, signal traces should not be routed over voids on the reference plane. Because this "stop-off" area can be defined by the outer diameter of the corresponding via anti-pad on the reference plane, we can also use the term "via anti-pad" to describe an area on the signal plane where signal traces cannot be routed due to the presence of vias.

[0021] Figure 2 An array of via anti-pads is shown including via anti-pads 202 and 204. Note that the outer circle defines the outer boundary of the via anti-pad, while the inner circle is the actual hole of the via. Figure 2 The via pads are not shown. Figure 2 In FIG, multiple anti-pads (e.g., via anti-pad 214) are shown using dashed circles to represent the outer boundaries of these anti-pads. These dashed via anti-pads correspond to ground vias. We use dashed circles to mark the area around the ground vias that is similar to the via anti-pad area of ​​the signal vias because the ground vias do not actually have a via anti-pad on the ground reference plane. However, in Figure 2 In the example shown in , ground vias (which are vias connected to the ground plane) and signal vias (which carry signals) are treated similarly, which means that signal traces are routed around signal vias and ground vias in a similar manner.

[0022] As mentioned previously, signal traces need to be routed in routing channels between adjacent rows of via anti-pads, and a pair of signal traces (e.g. Figure 1 Long coupling lengths between traces 112 and 114 (shown in FIG. 1 ) can increase crosstalk. To mitigate crosstalk between signal traces, according to one aspect of the present application, additional length can be added to at least one signal trace of a pair of signal traces within each routing channel. Additional length can be added at locations around the perimeter of each via anti-pad and between adjacent via anti-pads in the same row so that the signal trace can wrap around (or "wrap around") a substantial portion of each via anti-pad.

[0023] exist Figure 2In the example shown in FIG, additional length may be added to signal trace 210 at multiple locations (e.g., locations 206 and 208) such that signal trace 210 is routed to wrap around a substantial portion (e.g., up to 50%) of the perimeter of each via anti-pad or to bend along a substantial portion of the perimeter of each via anti-pad. This means that signal traces 210 and 212 no longer extend substantially parallel to each other. This also means that a substantial portion of signal trace 210 (e.g., the portion at location 206) has extended outside of the conventional routing channel between adjacent rows of via anti-pads. On the other hand, signal trace 212 remains largely within the conventional routing channel.

[0024] Adding to the length of signal trace 210 can periodically increase the gap between signal traces 210 and 212. Figure 2 As shown in , the gap between signal traces 210 and 212 can have a minimum value at a position (e.g., position 216) between adjacent via anti-pads in a row adjacent to signal trace 212, and can reach a maximum value at a position (e.g., position 206) between two adjacent via anti-pads in a row adjacent to signal trace 210. More specifically, at locations where the spacing between adjacent signal traces (e.g., traces 210 and 212) increases, the coupling between signals propagating along the signal traces can be reduced, thereby reducing overall crosstalk. Generally speaking, the signal-to-noise ratio (SNR) of the propagating signal can be improved. In some cases, the SNR can be improved by 5% to 10%.

[0025] According to one aspect, a signal trace with a shorter overall distance between a pair of signal traces in the same routing channel can be selected to increase its length (or the shorter signal trace can be bent around the outer boundary of each via anti-pad). In this way, the overall length difference between the signal traces can be kept relatively small. If the length of the selected signal trace needs to match the length of different signal traces on the same PCB, additional length compensation schemes can be used in areas outside the SOC footprint.

[0026] Figure 3 An enlarged view of a via anti-pad and a signal trace is shown in accordance with one aspect of the present application. Figure 3 , the signal via anti-pad 302 and the ground via anti-pad 304 are adjacent via anti-pads in the same row, while the signal via anti-pad 306 is in an adjacent row and is positioned between the via anti-pads 302 and 304. In addition to the outer boundaries of each via anti-pad, Figure 3 Also shown are the hole (eg, innermost circle) and via pad (eg, cross-hatched area) of each via.

[0027] Signal traces 310 and 312 are shown as being routed along a routing channel between two rows of via anti-pads. More specifically, starting from a point on the perimeter of the via anti-pad 302, the signal trace 310 is routed to wrap around a substantial portion of the via anti-pad 302 (which can be up to 50%, e.g., between 25% and 50% or between 40% and 50%) or to curve along a substantial portion of the via anti-pad before being routed away from the via anti-pad 302. According to one aspect, the arc angle (e.g., θ) of the wrapped portion of the perimeter of the via anti-pad can be between π / 2 (or 90°) and π (or 180°). The larger θ is, the larger the gap between the signal traces 310 and 312. According to one aspect, the distance between the edge of signal trace 310 and the outer boundary of the corresponding via anti-pad can be kept to a minimum (e.g., kept to a value that meets manufacturing tolerances) to prevent signal trace 310 from entering the via anti-pad area while keeping signal trace 310 as far away from signal trace 312 as possible.

[0028] Figure 3 Also shown is that, starting from the lowest point, as signal trace 310 is routed along the edge of via anti-pad 302 and then away from via anti-pad 302, the gap between signal traces 310 and 312 increases. The gap value reaches its maximum value at substantially the midpoint between via anti-pads 302 and 304. From the midpoint, signal trace 310 turns back and is routed toward via anti-pad 304, thereby wrapping around or curving along a portion of the perimeter of via anti-pad 304. Note that in order to increase the gap between signal traces 310 and 312, it is desirable to route signal trace 310 as far away from signal trace 312 as possible. However, since signal traces cannot be routed over the area occupied by via anti-pads (e.g., via anti-pads 302 and 304), routing signal trace 310 along (or immediately adjacent to) the perimeter of the via anti-pad can actually provide the greatest amount of gap. It should also be noted that at the midpoint between via anti-pads 302 and 304, the clearance can be increased by routing signal trace 310 further away from signal trace 312. However, the distance between signal trace 310 and another signal trace in an adjacent routing channel also needs to be considered. According to one aspect, the clearance between adjacent signal traces in the same routing channel at the midpoint can be determined to ensure that the clearance between adjacent signal traces of adjacent routing channels is no less than a predetermined threshold.

[0029] exist Figure 2 and Figure 3In the example shown in FIG, a pair of signal traces in a routing channel are routed in an asymmetrical manner. This scheme can maximize the gap between signal traces at certain locations (e.g., at the midpoint between adjacent via anti-pads in the same row). However, this asymmetrical routing scheme can result in large length differences between signal traces, which can sometimes be problematic. In order to reduce trace length differences while reducing signal crosstalk, according to one aspect, the signal traces in each routing channel can be routed substantially symmetrically.

[0030] Figure 4 The diagram illustrates the symmetrical routing of signal traces according to one aspect of the present application. Figure 4 , signal plane 400 includes an array of via anti-pads (e.g., via anti-pads 402, 404, and 406) and a plurality of signal traces (e.g., traces 410 and 412). More specifically, via anti-pads 402 and 404 are positioned in the top row, via anti-pad 406 is positioned in the second row, and signal traces 410 and 412 are routed in a routing channel between the top and second rows. Note that conventional routing channels are primarily limited to the empty space between adjacent rows (e.g., Figure 1 ), the routing channel in the present disclosure also includes the empty space between adjacent via anti-pads in the same row. For example, the empty space between via anti-pads 402 and 404 can now be used to route signal traces.

[0031] and Figures 1 to 3 The signal trace shown in the Figure 4 , the lengths of both signal traces in each routing channel are increased so that each signal trace can include a segment that wraps around a substantial portion of the via anti-pad. For example, signal trace 410 includes a segment that curves around a portion of the perimeter of via anti-pad 402 and a segment that curves around a portion of the perimeter of via anti-pad 404. Additionally, signal trace 412 includes a segment that curves around a portion of the perimeter of via anti-pad 406. This can result in two consecutive portions of the perimeter of the via anti-pad being wrapped (or "wrapped") by the signal trace. For example, an upper portion of the perimeter of via anti-pad 402 can be wrapped by signal trace 414, while a lower portion of its perimeter can be wrapped by signal trace 410.

[0032] exist Figure 4 In the example shown in FIG, the gap between two signal traces in the routing channel changes as each signal trace bends around the via anti-pad of an adjacent row. According to one aspect of the present application, the signal traces are closest to each other where the via anti-pads of adjacent rows (e.g., via anti-pads 402 and 406) are closest to each other. Figure 4In the example shown in , signal traces 410 and 412 are closest to each other at location 422, which can be along a straight line connecting the centers of via anti-pads 402 and 406. According to one aspect, the minimum distance between signal traces 410 and 412 should be greater than two or three times the width of signal traces 410 and 412. The signal traces are farthest apart from each other at the midpoint between adjacent via anti-pads in the same row. For example, signal traces 410 and 412 are farthest apart from each other at location 424, which can be approximately at the midpoint between adjacent via anti-pads 402 and 404. Similar to Figure 3 As shown in , the maximum spacing between signal traces in one routing channel is also constrained by the spacing between signal traces in adjacent routing channels. For example, the spacing between signal traces 410 and 412 at location 424 may be constrained by the spacing between signal traces 410 and 414 at the same location. Increasing the spacing between signal traces 410 and 412 at location 424 results in a decrease in the spacing between signal traces 410 and 414, which may be problematic because it increases crosstalk between signal traces 410 and 414. Note that adjacent signal traces (e.g., traces 410 and 414) in adjacent routing channels are largely separated from each other by via anti-pads, and therefore, the spacing between them at the space between adjacent via anti-pads determines the crosstalk between them. According to one aspect, at the midpoint between adjacent vias (e.g., at location 424), the intra-channel spacing (e.g., the spacing between adjacent signal traces in the same routing channel) and the inter-channel spacing (e.g., the spacing between adjacent signal traces in adjacent routing channels) may be similar. According to an alternative aspect, the intra-channel clearance can be larger (e.g., 20% larger) than the inter-channel clearance at the midpoint between adjacent vias (e.g., at location 424). This is because, generally speaking, intra-channel crosstalk is larger than inter-channel crosstalk, and there is a greater need to ensure sufficient clearance between signal traces in the same routing channel.

[0033] exist Figure 3 In the example shown in FIG, the signal trace 310 wraps about 50% of each via anti-pad, and the arc angle θ can be about π or 180°. This can cause the signal trace 310 to rise above the center of the via anti-pad 302, thereby increasing the gap between the signal traces 310 and 312. However, this arrangement Figure 440 ). More specifically, if the signal trace 410 rises above the center of the via anti-pad 402, the signal trace may get too close to the signal trace 414 that wraps around the upper portion of the via anti-pad 402. In the most extreme case, the signal traces 410 and 414 each wrap around 50% of the via anti-pad 402, which may cause the signal traces 410 and 414 to touch or cross paths with each other. To prevent excessive channel-to-channel crosstalk, according to one embodiment, the portion of the via anti-pad perimeter that is wrapped by the signal trace may be as high as 40%, such as between 0% and 40% or between 20% and 40%.

[0034] exist Figure 4 , the two signal traces can wrap substantially similar amounts around the via anti-pads. For example, signal trace 410 wraps approximately 40% of each via anti-pad in the top row (e.g., via anti-pads 402 and 404), and signal trace 412 similarly wraps approximately 40% of each via anti-pad in the second row (e.g., via anti-pad 406). This arrangement can ensure that the trace gap is increased without increasing the length difference between the signal traces. In other words, the length of each signal trace within the SOC footprint can remain substantially similar. However, this may also cause the phase delay of the coupled signal to vary periodically. To prevent periodic variations in the phase delay, according to one aspect, the two signal traces in each routing channel can have different wrap depths around the via anti-pads. For example, signal trace 410 can wrap approximately 40% of each via anti-pad in the top row, while signal trace 412 only wraps approximately 30% of each via anti-pad in the second row.

[0035] In the previous discussion, all vias, both signal and ground vias, have been treated in a similar manner. On the signal plane, the signal trace is routed around the via anti-pad area around each via. For signal vias, the location and size of the via anti-pad area in the signal plane corresponds to the location and size of the actual via anti-pad on the ground reference plane. On the other hand, ground vias do not have a via anti-pad on the ground reference plane. However, on Figures 2 to 4 In the example shown, the signal trace is routed around the ground vias as if each ground via had a similar via anti-pad area as the signal via. This makes the process of routing the signal traces simpler. However, due to the periodic structure of the signal traces, high-frequency filtering may occur, resulting in frequency-dependent impedance changes or unwanted signal reflections.

[0036] According to one aspect of the present application, the fact that ground vias do not actually have a via anti-pad in the ground reference plane can be exploited and ground vias and signal vias can be treated differently by allowing signal traces to be routed closer to the ground vias. Figure 5The diagram illustrates routing signal traces around signal vias and ground vias according to one aspect of the present application. Figure 5 , signal plane 500 includes an array of via anti-pads (e.g., via anti-pads 502-508) and a plurality of signal traces (e.g., traces 510 and 512). For each via anti-pad, the inner circle represents the hole, and the cross-hatched area represents the via pad. Via anti-pads 502 and 504 are associated with signal vias, where the outer boundaries of the via anti-pads (represented as solid circles) are defined by the corresponding via anti-pads in the reference plane. On the other hand, via anti-pads 506 and 508 are associated with ground vias that do not have via anti-pads in the signal plane. The outer boundaries of via anti-pads 506 and 508 are determined by how tightly the signal traces can be routed around the via pads of the corresponding ground vias. Generally speaking, signal traces can be routed closer to ground vias than to signal vias, which means that the equivalent via anti-pads of the ground vias (e.g., ground via anti-pads 506 and 508) are smaller than the via anti-pads of the signal vias (e.g., signal via anti-pads 502 and 504).

[0037] exist Figure 5 In FIG, signal vias and ground vias are treated differently, where the signal via anti-pad is shown to be larger than the ground via anti-pad. Figure 5 It is also shown that each signal trace is routed around a substantial portion of each signal via anti-pad and around a substantial portion of the ground via anti-pad. More specifically, the signal traces are routed closer to the ground vias than to the signal vias. For example, signal trace 510 wraps around a portion of each of the via anti-pads 502, 504, and 506, and the distance between signal trace 510 and the via pad of either signal via anti-pad 502 or 504 is greater than the distance between signal trace 510 and the via pad of ground via anti-pad 506.

[0038] Because ground vias are somewhat randomly scattered throughout the via array, routing the signal traces differently around the signal and ground vias breaks up the repeating periodic structure of the through-path routing, thereby reducing the high-frequency filtering effect. Furthermore, routing the signal traces closer to the ground vias also increases the gap between the signal traces at such locations. For example, because signal trace 512 is routed closer to the ground via anti-pad 508, the gap between signal traces 510 and 512 can be larger at a location adjacent to the ground via anti-pad 508 than at a location adjacent to the signal via anti-pad.

[0039] Due to the spatial constraints of through-wiring, signal traces are designed to be narrow. For example, the width of a signal trace running through the SOC footprint may be approximately four mils. These narrow traces may have potentially high impedance, which is undesirable. To reduce the impedance of the signal traces, according to one aspect, one or both signal traces may be widened at locations where the gap between the signal traces is relatively large. For example, at a location where the gap between the signal traces reaches a maximum, one or both signal traces may be widened.

[0040] Figure 6 FIGURE 1 illustrates a signal trace with a widened section according to one aspect of the present application. Figure 6 , signal plane 600 may include two rows of via anti-pads, with via anti-pads 602 and 604 positioned in a top row and via anti-pad 606 positioned in a bottom row. Figure 6 Also shown are signal traces 610 and 612 positioned in the routing channel between the top and bottom rows. Figure 6 The through-wiring scheme shown in can be similar to Figure 2 and Figure 3 , where only one signal trace (e.g., signal trace 610) in the routing channel is routed around a substantial portion of each via anti-pad. Figure 3 , the gap between signal traces 610 and 612 can be largest at the midpoint between via anti-pads 602 and 604. This relatively large gap allows signal trace 610 to include a widened section 614 at this location. According to one aspect, widened section 614 can be tapered.

[0041] exist Figure 6 In the example shown in , only one signal trace includes a widening section. In practice, both signal traces can include widening sections. For example, although not shown as widening, signal trace 612 can also have widening sections at positions (e.g., positions 616 and 618) between adjacent via anti-pads. According to one aspect, widening sections can also be randomly placed in the through-wiring path to further break up the periodicity of the through-wiring, thereby reducing high-frequency filtering effects.

[0042] Figure 6 Also illustrated are exemplary row and column spacings for the via array.The density of the via array and the size of the individual vias may determine the amount of wrapping required to achieve a desired gap (eg, a desired gap at the midpoint between adjacent vias in a row).

[0043] Figure 7A flow chart illustrating a process for designing a through-hole routing on a PCB according to one aspect of the present application is presented. During operation, the location of the vias may first be determined (operation 702), and which vias are signal vias and which are ground vias may be identified (operation 704). The via anti-pad or "stop-in" area for each signal via or ground via is then determined (operation 706). Depending on the design, the stop-in areas for the signal vias and the ground vias may be the same or different. For example, the stop-in area for the ground via may be smaller than the stop-in area for the signal via.

[0044] For each signal trace that passes through the via array, a wrap ratio (i.e., the proportion of the via anti-pad perimeter that is wrapped by the signal trace) can be determined (operation 708). According to one aspect, two signal traces within a routing channel can have the same wrap ratio. According to an alternative aspect, two signal traces in the same routing channel can have different wrap ratios, with one signal trace wrapping a larger portion of each via anti-pad. In addition, the wrap ratio can be determined based on the spacing of the via array (e.g., row spacing and column spacing) and the size of the via anti-pad. Larger spacing and / or smaller vias can mean that a smaller wrap ratio can be used to achieve the desired gap between traces. Note that it is desirable to have the minimum gap between signal traces be greater than two or three times the width of the signal trace.

[0045] Once the wrap rate is determined, the designer can route segments of the signal trace (called via anti-pad wrap segments) around the via anti-pads according to the determined wrap rate (operation 710), and then use connecting segments to connect each pair of adjacent via anti-pad wrap segments to complete the routing of the signal trace that escapes the SOC footprint (operation 712). The connecting segments are typically positioned in the blank space between adjacent via anti-pads, and their curvature can also be determined based on the spacing of the via array. According to one aspect, the connecting segments can be partially widened to reduce the impedance of the signal trace. According to a further aspect, the widened portion of the connecting segment can be tapered. The routing of the signal trace outside the via array can then be completed according to the PCB design (operation 714).

[0046] In general, the present disclosure provides a technology for reducing crosstalk within through-wiring of integrated circuit devices on PCBs. More specifically, in cases where signal traces need to pass through a high-density via array of a large SOC device, the long coupling length and close spacing between a pair of signal traces in a wiring channel can result in a greater amount of crosstalk. In order to reduce the amount of crosstalk, according to a first aspect of the present application, a signal trace in a wiring channel can include multiple via anti-pad wrap segments, wherein each via anti-pad wrap segment wraps a substantial portion of the corresponding via anti-pad. Depending on the desired gap and the spacing of the via array, the wrap portion of the perimeter of the via anti-pad (i.e., the wrap rate) can vary (e.g., varying between 0% and 50%, varying between 25% and 50%, or varying between 40% and 50%). According to a second aspect, both signal traces in a wiring channel can have a via anti-pad wrap portion. The wrap rates of the two signal traces can be the same or different. According to a third aspect, the via anti-pads or "stop-in" areas of the signal vias and ground vias can be defined in different ways. The "block-in" area of ​​the ground via can be smaller to allow the routing of signal traces closer to the ground via, thereby further increasing the gap between signal traces in each routing channel. According to a fourth aspect, at least one signal trace can include one or more widening sections. The widening sections can be located in the area between adjacent via anti-pads in the same row.

[0047] In the disclosed examples (e.g., Figures 2 to 6 In the example shown in FIG, , the signal trace is a stripline positioned on an inner layer of a PCB, and through-routing is used to route the signal trace through an array of vias. In practice, the same routing techniques can be used to route a microstrip through an array of contact pads on a top surface routing layer of a PCB (e.g., by routing a segment of the signal trace around a portion of the perimeter of the block-out region). Furthermore, in the disclosed example, the via array is a staggered array. In practice, the same routing techniques can be used to route a signal trace through any form of via or contact pad array.

[0048] One aspect of the present application provides a printed circuit board (PCB). The PCB may include multiple layers and an array of vias, the array of vias including multiple rows, the multiple rows configured to connect signals across layers. An inner layer of the PCB may include a first signal trace and a second signal trace positioned between a first and a second adjacent row of vias, the first signal trace being positioned adjacent to the first row, and the second signal trace being positioned adjacent to the second row. The first signal trace may include at least one curved segment that curves around a substantial portion of a corresponding via in the first row, such that a gap between the first signal trace and the second signal trace varies along the curved segment.

[0049] In variations on this aspect, the curved segment curves along a portion of a perimeter of a via anti-pad area associated with the corresponding via.

[0050] In a further variation, the curved segment curves along 0% to 50% of the perimeter of the via anti-pad area.

[0051] In a further variation, the corresponding via is a signal via, and the via anti-pad area of ​​the signal via corresponds to a via anti-pad on a reference plane associated with the first signal trace.

[0052] In a further variation, the corresponding via is a ground via, and the via anti-pad area of ​​the ground via is smaller than the via anti-pad area of ​​the signal via.

[0053] In variations on this aspect, the second signal trace may include at least one curved segment that bends around a substantial portion of a corresponding via in the second row.

[0054] In a further variation, the curved segment of the second signal trace curves along 0% to 40% of the perimeter of the via anti-pad area in the second row.

[0055] In a variation on this aspect, at least one signal trace includes a widened portion at a location where the gap between the first signal trace and the second signal trace is increased.

[0056] In a further variant, the widened portion is positioned between adjacent vias in the same row.

[0057] In variations on this aspect, the PCB may further include a system-on-chip (SOC) device including an array of contact pads coupled to the array of vias.

[0058] One aspect of the present application provides an inner layer of a printed circuit board (PCB). The inner layer may include: an array of vias, the array of vias comprising a plurality of rows, the plurality of rows configured to connect signals across multiple layers of the PCB; and a first signal trace and a second signal trace positioned between first and second adjacent rows of the vias, the first signal trace being positioned adjacent to the first row, and the second signal trace being positioned adjacent to the second row. The first signal trace includes at least one curved segment that curves around a substantial portion of a corresponding via in the first row, such that a gap between the first and second signal traces varies along the curved segment.

[0059] In variations on this aspect, the gap between the first and second signal traces between adjacent vias in the first row is greater than the gap between the first and second signal traces between adjacent vias in the second row.

[0060] The methods and processes described in the detailed description can be embodied as code and / or data, which can be stored in a computer-readable storage medium as described above. When a computer system reads and executes the code and / or data stored on the computer-readable storage medium, the computer system executes the methods and processes embodied as data structures and code and stored in the computer-readable storage medium.

[0061] Furthermore, the above methods and processes may be included in hardware modules or devices. Hardware modules or devices may include, but are not limited to, application-specific integrated circuit (ASIC) chips, field-programmable gate arrays (FPGAs), dedicated or shared processors that execute specific software modules or codes at specific times, and other programmable logic devices now known or later developed. When the hardware modules or devices are activated, they execute the methods and processes included therein.

[0062] The foregoing description has been presented for purposes of illustration and description only. The description is not intended to be exhaustive or to limit the scope of the present disclosure to the disclosed forms. Accordingly, many modifications and variations will be apparent to those of ordinary skill in the art.

Claims

1. A printed circuit board (PCB), comprising: Multiple layers; as well as a via array comprising a plurality of rows configured to connect signals across layers, wherein vias in adjacent rows are arranged in a staggered manner; wherein the inner layer includes a first signal trace and a second signal trace positioned between adjacent first and second rows of vias, the first signal trace being positioned adjacent to the first row, and the second signal trace being positioned adjacent to the second row; the first signal trace including at least one curved segment that bends around a substantial portion of a corresponding via in the first row such that a gap between the first signal trace and the second signal trace varies along the curved segment; and The gap between the first signal trace and the second signal trace increases toward a first position between adjacent vias in the first row and decreases toward a second position between adjacent vias in the second row.

2. The PCB according to claim 1, wherein The curved segment curves along a portion of a perimeter of a via anti-pad area associated with a corresponding via.

3. The PCB according to claim 2, wherein: The curved segment curves along 25% to 50% of the perimeter of the via anti-pad area.

4. The PCB according to claim 2, wherein The corresponding via is a signal via, and wherein the via anti-pad area of ​​the signal via corresponds to a via anti-pad on a reference plane associated with the first signal trace.

5. The PCB according to claim 4, wherein The corresponding via is a ground via, and wherein the via anti-pad area of ​​the ground via is smaller than the via anti-pad area of ​​the signal via.

6. The PCB according to claim 2, wherein The curved segment curves along 40% to 50% of the perimeter of the via anti-pad area.

7. The PCB according to claim 2, wherein: The second signal trace includes at least one curved segment that bends around a substantial portion of a corresponding via in the second row.

8. The PCB according to claim 7, wherein The meandering segment of the second signal trace curves along 25% to 40% of the perimeter of the via anti-pad area in the second row.

9. The PCB according to claim 1, wherein At least one signal trace includes a widened portion at a location where the gap between the first signal trace and the second signal trace is increased.

10. The PCB according to claim 9, wherein The widened portion is positioned between adjacent vias in the same row.

11. The PCB of claim 1 , further comprising: A system-on-chip (SOC) device includes an array of contact pads coupled to the array of vias.

12. An inner layer of a printed circuit board (PCB), comprising: a via array comprising a plurality of rows configured to connect signals across multiple layers of the PCB, wherein vias in adjacent rows are arranged in a staggered manner; as well as a first signal trace and a second signal trace positioned between adjacent first and second rows of vias, the first signal trace positioned adjacent to the first row and the second signal trace positioned adjacent to the second row; the first signal trace including at least one curved segment that bends around a substantial portion of a corresponding via in the first row such that a gap between the first signal trace and the second signal trace varies along the curved segment; as well as The gap between the first signal trace and the second signal trace increases toward a first position between adjacent vias in the first row and decreases toward a second position between adjacent vias in the second row.

13. The inner layer according to claim 12, wherein The curved segment curves along a portion of a perimeter of a via anti-pad area associated with the corresponding via.

14. The inner layer according to claim 13, wherein The curved segment curves along 25% to 50% of the perimeter of the via anti-pad area.

15. The inner layer of claim 13, wherein The corresponding via is a signal via, and wherein the via anti-pad area of ​​the signal via corresponds to a via anti-pad on a reference plane associated with the first signal trace.

16. The inner layer of claim 15, wherein The corresponding via is a ground via, and wherein the via anti-pad area of ​​the ground via is smaller than the via anti-pad area of ​​the signal via.

17. The inner layer of claim 13, wherein: The curved segment curves along 40% to 50% of the perimeter of the via anti-pad area.

18. The inner layer of claim 13, wherein The second signal trace includes at least one curved segment that bends around a substantial portion of a corresponding via in the second row.

19. The inner layer of claim 18, wherein The meandering segment of the second signal trace curves along 25% to 40% of the perimeter of the via anti-pad area in the second row.

20. The inner layer of claim 12, wherein At least one signal trace includes a widened portion at a location where the gap between the first signal trace and the second signal trace is increased.

21. The inner layer of claim 20, wherein The widened portion is positioned between adjacent vias in the same row.

Images