Display panel and display device

Abstract

Embodiments of the present application provide a display panel and a display device, comprising a normal display area and a functional display area for setting an optical functional element; the normal display area comprises a plurality of first pixel circuits and a plurality of first fixed potential lines, the first fixed potential lines are electrically connected with the first pixel circuits; the functional display area comprises a plurality of second pixel circuits and a plurality of second fixed potential lines, the second fixed potential lines are electrically connected with the second pixel circuits; wherein, m1 groups of first pixel circuit groups are arranged between any two adjacent first fixed potential lines, and m2 groups of second pixel circuit groups are arranged between any two adjacent second fixed potential lines; m1 and m2 are positive integers greater than or equal to 1 and m2>m1. In the embodiments of the present application, the number of the second fixed potential lines in the functional display area is reduced, the light transmittance of the functional display area can be improved, and meanwhile the brightness uniformity of the functional display area and the normal display area can be ensured, so that the light transmittance of the functional display area and the display uniformity of the display panel are taken into account.

Description

A display panel and display device Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] With increasing consumer demand, full-screen displays are gradually becoming the mainstream display technology. Existing full-screen displays typically incorporate a light-transmitting display area within the main display area. This area houses optical components. Because the light-transmitting display area is not located in the non-display area, the bezels are narrowed, thus achieving a full-screen display. Simultaneously, to improve the visual experience, the light-transmitting display area usually also needs to be functional. To increase the light transmittance of this area, the light-blocking area needs to be minimized. However, current designs, while reducing the light-blocking area, often result in uneven display. Therefore, ensuring that the light-transmitting display area possesses both good display performance and high light transmittance has become a pressing issue.

[0003] [Application Content]

[0004] In view of this, embodiments of this application provide a display panel and a display device to solve the above problems.

[0005] In a first aspect, embodiments of this application provide a display panel, which includes a conventional display area and a functional display area. The functional display area is used to house optical functional elements. The conventional display area includes multiple first pixel circuits and multiple first fixed potential lines. The first fixed potential lines extend along a first direction and are arranged along a second direction, and are electrically connected to the first pixel circuits. The functional display area includes multiple second pixel circuits and multiple second fixed potential lines. The second fixed potential lines extend along a third direction and are arranged along a fourth direction, and are electrically connected to the second pixel circuits. Among them, m1 groups of first pixel circuits are arranged between two adjacent first fixed potential lines. Each first pixel circuit group includes multiple first pixel circuits arranged along the first direction. m2 groups of second pixel circuits are arranged between two adjacent second fixed potential lines. Each second pixel circuit group includes multiple second pixel circuits arranged along a third direction. m1 and m2 are both positive integers greater than or equal to 1, and m2 > m1.

[0006] Secondly, embodiments of this application provide a display device, including a display panel and optical functional elements as provided in the first aspect, wherein the optical functional elements are disposed at a position corresponding to the functional display area of ​​the display device.

[0007] In this embodiment, by reducing the number of second fixed potential lines in the functional display area, the light transmittance of the functional display area can be improved, while ensuring the brightness uniformity between the functional display area and the conventional display area. Thus, both the light transmittance of the functional display area and the display uniformity of the display panel are taken into account. Figure Description

[0008] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0009] Figure 1 is a schematic diagram of a display panel provided in an embodiment of this application;

[0010] Figure 2 is a schematic diagram of another display panel provided in an embodiment of this application;

[0011] Figure 3 is a magnified view of the CC region in Figures 1 and 2;

[0012] Figure 4 is a partial enlarged view of a display panel provided in an embodiment of this application;

[0013] Figure 5 is a partial enlarged view of another display panel provided in an embodiment of this application;

[0014] Figure 6 is a partial enlarged view of another display panel provided in an embodiment of this application;

[0015] Figure 7 is a partial enlarged view of another display panel provided in an embodiment of this application;

[0016] Figure 8 is a schematic diagram of the current of the display panel shown in Figure 7;

[0017] Figure 9 is an equivalent circuit diagram of the first pixel circuit and the second pixel circuit in a display panel provided in an embodiment of this application;

[0018] Figure 10 is a schematic diagram of the actual structure and layout of the pixel circuit shown in Figure 9;

[0019] Figure 11 is a partial cross-sectional view of Figure 10;

[0020] Figure 12 is a cross-sectional view along the MN direction in Figure 10;

[0021] Figure 13 is a schematic cross-sectional view along the M'N' direction in Figure 10;

[0022] Figure 14 is a partial enlarged view of another display panel provided in an embodiment of this application;

[0023] Figure 15 is a schematic diagram of a display device provided in an embodiment of this application. Detailed Implementation Methods

[0024] To better understand the technical solution of this application, the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0025] It should be understood that the described embodiments are merely some, not all, of the embodiments in this application. All other embodiments obtained by those skilled in the art based on the embodiments in this application without inventive effort are within the scope of protection of this application.

[0026] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application. The singular forms “a,” “the,” and “the” used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0027] It should be understood that the term "and / or" used in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article generally indicates that the preceding and following related objects have an "or" relationship.

[0028] In the description of this specification, it should be understood that the terms "substantially", "approximately", "about", "about", "generally", "largely" used in the claims and embodiments of this application refer to values ​​that can be generally agreed upon within a reasonable range of process operations or tolerances, rather than a precise value.

[0029] It should be understood that although the terms first, second, third, etc., may be used to refer to fixed potential lines in the embodiments of this application, these fixed potential lines should not be limited to these terms. These terms are only used to distinguish fixed potential lines from each other. For example, without departing from the scope of the embodiments of this application, a first fixed potential line may also be referred to as a second fixed potential line, and similarly, a second fixed potential line may also be referred to as a first fixed potential line.

[0030] Through meticulous and in-depth research, the applicant in this case has provided a solution to the problems existing in the prior art.

[0031] Through research and analysis of existing display panels and devices with full-screen display effects, the inventors discovered at least three reasons for the significant difference in display brightness between the light-transmitting display area and the conventional display area:

[0032] One possible solution is to reduce the area of ​​the anode, which acts as the reflective electrode, in the light-transmitting display area. However, to ensure high brightness in this area, a high driving current is required for the LEDs. This leads to significant performance degradation of the light-emitting materials in the LEDs, resulting in a substantial decrease in brightness in the light-transmitting display area. Consequently, after a period of use, existing display panels and devices exhibit a noticeable difference in brightness between the light-transmitting and conventional display areas.

[0033] The second scenario involves a solution that reduces the width of at least some of the signal lines in the light-transmitting display area. Reducing the width of the signal lines increases their resistance, resulting in a significant voltage drop during signal transmission. This leads to uneven pixel brightness in the light-transmitting display area, with a noticeable difference in brightness compared to the conventional display area.

[0034] The third scenario involves reducing the area of ​​the storage capacitor in the pixel circuit of the light-transmitting display area. However, this reduces the stability of the storage capacitor's potential. This causes leakage current in some transistors within the pixel circuit, resulting in unstable pixel brightness in the light-transmitting display area and a significant difference in brightness compared to the conventional display area.

[0035] The above reasons lead to uneven display while increasing the light transmittance of the light-transmitting display area. To achieve display uniformity between the light-transmitting display area and the regular display area, designers have begun to focus on reducing the overall pixel density of the display panel. The embodiments provided in this application innovatively change the number of pixel circuit groups between adjacent specific fixed potential lines, increasing the light transmittance of the light-transmitting display area (hereinafter referred to as the functional display area) while ensuring minimal impact on display uniformity.

[0036] This application provides a display panel and a display device.

[0037] Figure 1 is a schematic diagram of a display panel provided in an embodiment of this application, Figure 2 is a schematic diagram of another display panel provided in an embodiment of this application, and Figure 3 is a partial enlarged view of the CC area in Figures 1 and 2. The CC area includes a portion of the conventional display area 01 and a portion of the functional display area 02.

[0038] As shown in Figures 1 and 2, the display panel provided in this embodiment includes a conventional display area 01 and a functional display area 02. The area where the functional display area 02 is located is used to set optical functional elements. The conventional display area 01 can perform light-emitting display, while the functional display area 02, in addition to performing the light-emitting display function together with the conventional display area 01, can also perform optical signal transmission functions, such as at least one of the functions of taking pictures, biometric recognition, and illumination.

[0039] It should be noted that the function display area 02 can be rectangular as shown in Figures 1 and 2, or it can be elliptical, circular or other shapes. This application does not limit this.

[0040] Referring to Figure 3, the conventional display area 01 includes multiple first pixel circuits 11, multiple first light-emitting diodes (LEDs) 12, and multiple first fixed potential lines 13. Each first pixel circuit 11 is electrically connected to at least one first LED 12. The first LED 12 can be an organic light-emitting diode (OLED) or a miniature LED. The first pixel circuit 11 provides the light-emitting driving current required for the first LED 12 to emit light. The first fixed potential lines 13 extend along a first direction X and are arranged along a second direction Y, and are electrically connected to the first pixel circuits 11 to provide a fixed potential signal to the first pixel circuits 11.

[0041] Please continue referring to Figure 3. The functional display area 02 includes multiple second pixel circuits 21, multiple second light-emitting diodes 22, and multiple second fixed potential lines 23. Each second pixel circuit 21 is electrically connected to at least one second light-emitting diode 22. The second light-emitting diode 22 can be an organic light-emitting diode or a miniature light-emitting diode. The second pixel circuit 21 provides the light-emitting driving current required for the second light-emitting diode 22 to emit light. The second fixed potential lines 23 extend along the third direction X' and are arranged along the fourth direction Y', and are electrically connected to the second pixel circuits 21 to provide fixed potential signals to the second pixel circuits 21.

[0042] As shown in Figure 3, m1 groups of first pixel circuit groups 11A are arranged between two adjacent first fixed potential lines 13 arranged along the second direction Y. The first pixel circuit group 11A includes a plurality of first pixel circuits 11 arranged along the first direction X. Furthermore, m2 groups of second pixel circuit groups 21A are arranged between two adjacent second fixed potential lines 13' arranged along the third direction X'. The second pixel circuit group 21A includes a plurality of second pixel circuits 21 arranged along the third direction X'.

[0043] In this embodiment, m1 and m2 are both positive integers greater than or equal to 1, and m2 > m1. That is, the number of first pixel circuit groups 11A corresponding to one first fixed potential line 13 is less than the number of second pixel circuit groups 21A corresponding to one second fixed potential line 23. For example, as shown in FIG3, there are 3 first pixel circuit groups 11A between two adjacent first fixed potential lines 13, and there are 6 second pixel circuit groups 21A between two adjacent second fixed potential lines 23.

[0044] In this embodiment of the application, by reducing the number of second fixed potential lines 23 in the functional display area 02, the light transmittance of the functional display area 02 can be improved, thereby improving the reliability of optical signal transmission in the functional display area 02.

[0045] Furthermore, reducing the number of second fixed potential lines 23 has a very small impact on the display effect of the functional display area 02. On the one hand, the second fixed potential lines 23 transmit fixed potential signals, and the attenuation of the fixed potential signals on the second fixed potential lines 23 remains basically consistent at different times, so it is easy to compensate for the fixed potential signals on the second fixed potential lines 23; on the other hand, the second fixed potential lines 23 can maintain the transmission of fixed potential signals for a certain period of time without frequent charging and discharging, thus avoiding the charging delay problem caused by potential ramp-up during charging; and thirdly, reducing the density of the second fixed potential lines 23, compared to reducing the width of the second fixed potential lines 23, does not change the resistance and parasitic capacitance of the second fixed potential lines 23, so the impact on the display effect is small.

[0046] It should be noted that the first direction X and the third direction X' can be parallel, and the second direction Y and the fourth direction Y' can also be parallel.

[0047] In one embodiment of this application, referring to Figures 1 and 2, the conventional display area 01 at least partially surrounds the functional display area 02. For example, as shown in Figure 1, the functional display area 02 can be completely surrounded by the conventional display area 01; as shown in Figure 2, the functional display area 02 can also be partially surrounded by the conventional display area 01. Furthermore, the light transmittance of at least a portion of the functional display area 02 is greater than that of the conventional display area 01, to ensure that more light signals can pass through the functional display area 02.

[0048] In one embodiment of this application, as shown in FIG3, the density of the first pixel circuit 11 in the conventional display area 01 is equal to the density of the second pixel circuit 21 in the functional display area 02. Therefore, the arrangement pattern of the first pixel circuit 11 in the conventional display area 01 is the same as the arrangement pattern of the second pixel circuit 21 in the functional display area 02. This same arrangement pattern includes the same composition of repeating units and the same spacing between pixel circuits.

[0049] In this embodiment, the light transmittance of the functional display area 02 can be increased by reducing the area of ​​the second pixel circuit 21 or by reducing the light-shielding traces in the functional display area 02, while ensuring the display resolution of the functional display area 02.

[0050] Figure 4 is a partial enlarged view of a display panel provided in an embodiment of this application.

[0051] In another embodiment of this application, as shown in FIG4, the density of the first pixel circuit 11 in the conventional display area 01 is greater than the density of the second pixel circuit 21 in the functional display area 02, and the second pixel circuit 21 in the functional display area 02 is uniformly distributed. Alternatively, both the first pixel circuit 11 in the conventional display area 01 and the second pixel circuit 21 in the functional display area 02 are uniformly distributed, and the density of the second pixel circuit 21 in the functional display area 02 is less than the density of the first pixel circuit 11.

[0052] It should be noted that, in the above embodiments, the uniform distribution of the first pixel circuit 11 and the uniform distribution of the second pixel circuit 21 means that the first pixel circuit 11 and the second pixel circuit are basically uniformly distributed. For example, the distance between two first pixel circuits 11 that are adjacent to the first fixed potential line 13 and arranged along the second direction Y is greater than the distance between two first pixel circuits 11 that are not adjacent to the first fixed potential line 13 and arranged along the second direction Y, and the distance between two second pixel circuits 21 that are adjacent to the second fixed potential line 23 and arranged along the second direction Y is greater than the distance between two second pixel circuits 21 that are not adjacent to the second fixed potential line 23 and arranged along the second direction Y, then, without considering the space occupied by the first fixed potential line 13 and the second fixed potential line 23, the first pixel circuit 11 is basically uniformly distributed and the second pixel circuit 21 is also basically uniformly distributed.

[0053] In this embodiment, by setting the density of the second pixel circuit 21 in the functional display area 02 to be relatively small, the light transmittance of the functional display area 02 can be significantly increased.

[0054] Figure 5 is a partial enlarged view of another display panel provided in an embodiment of this application.

[0055] In another embodiment of this application, as shown in FIG5, the density of the first pixel circuit 11 in the conventional display area 01 is greater than the density of the second pixel circuit 21 in the functional display area 02; and at least two second pixel circuits 21 in the functional display area 02 constitute a pixel circuit cluster 021, wherein the distance between adjacent second pixel circuits 21 in the pixel circuit cluster 021 is less than the distance between adjacent pixel circuit clusters 021. At least two second pixel circuits 21 in the same pixel circuit cluster 021 are electrically connected to the same second fixed potential line 23.

[0056] In this embodiment, the second pixel circuit 21 in the functional display area 02 is not uniformly distributed as a single unit, but can be uniformly distributed as a pixel circuit cluster 021. Therefore, the density of the second pixel circuit 21 is less than the density of the first pixel circuit 11 in this embodiment. It can be understood that the area value corresponding to the functional display area 02 is the first area, and the number of second pixel circuits 21 set in the first area is less than the number of first pixel circuits 11 set in the first area.

[0057] For example, as shown in Figure 5, in the functional display area 02, the distance between two adjacent pixel circuit clusters 021 arranged along the first direction X is greater than the width of the pixel circuit cluster 021 along the first direction X. Therefore, as shown in Figure 5, in two adjacent pixel circuit clusters 021 arranged along the first direction X, the distance between the lower second pixel circuit 21 in the upper pixel circuit cluster 021 and the upper second pixel circuit 21 in the lower pixel circuit cluster 021 is greater than the width of one pixel circuit cluster 021. In the functional display area 02, the distance between two adjacent pixel circuit clusters 021 arranged along the second direction Y is greater than the width of the pixel circuit cluster 021 along the second direction Y. Therefore, as shown in Figure 5, in two adjacent pixel circuit clusters 021 arranged along the second direction Y, the distance between the right second pixel circuit 21 in the left pixel circuit cluster 021 and the left second pixel circuit 21 in the right pixel circuit cluster 021 is greater than the width of one pixel circuit cluster 021.

[0058] Within the conventional display area 01, among the plurality of first pixel circuits 11 arranged along the first direction X, the spacing between adjacent first pixel circuits 11 is substantially equal, and among the plurality of first pixel circuits 11 arranged along the second direction Y, the spacing between adjacent first pixel circuits 11 is also substantially equal. Here, "substantially equal" means that, without considering the space occupied by the first fixed potential line 13 and the second fixed potential line 23, the spacing between the first pixel circuits 11 is substantially equal, and this spacing is significantly smaller than the width of the pixel circuit cluster 021.

[0059] Furthermore, referring to Figure 5, to avoid uneven display within the functional display area 01, the pixel circuit clusters 021 in the functional display area 01 are arranged in a staggered manner. Specifically, multiple pixel circuit clusters 021 arranged along the second direction Y are spaced apart, with a blank space between adjacent pixel circuit clusters 021. Similarly, multiple pixel circuit clusters 021 arranged along the first direction X are also spaced apart, with a blank space between adjacent pixel circuit clusters 021. In the first direction X, the pixel circuit clusters 021 are arranged adjacent to the blank space. Because the pixel circuit cluster 021 is misaligned, the second pixel circuits 21 in the pixel circuit cluster 021 are also misaligned. For example, if the pixel circuit cluster 021 includes three second pixel circuits 21 that provide light-emitting driving current to red sub-pixels, green sub-pixels and blue sub-pixels respectively, then the multiple second pixel circuits 21 that provide light-emitting driving current to multiple red sub-pixels, the multiple second pixel circuits 21 that provide light-emitting driving current to multiple green sub-pixels, and the multiple second pixel circuits 21 that provide light-emitting driving current to multiple blue sub-pixels are also misaligned.

[0060] In the conventional display area 01, the first pixel circuits 11 are arranged in a matrix, that is, the first pixel circuits 11 are arranged sequentially along the first direction X and the second direction Y. Thus, the multiple first pixel circuits 11 that provide light-emitting driving current to multiple red sub-pixels are arranged in a matrix, the multiple first pixel circuits 11 that provide light-emitting driving current to multiple green sub-pixels are arranged in a matrix, and the multiple first pixel circuits 11 that provide light-emitting driving current to multiple blue sub-pixels are also arranged in a matrix.

[0061] In this embodiment, the increased distance between two adjacent second fixed potential lines 23 reduces the impact of diffraction on the optical signal acquisition in the area where the functional display area 02 is located. According to the principle of proximity, the distance between each second fixed potential line 23 and the second pixel circuit 21 it supports is not increased, but the transmittance of the functional display area 01 is increased.

[0062] Furthermore, since at least two second pixel circuits 21 within the pixel circuit cluster 021 are electrically connected to at least two second light-emitting diodes 12 of different colors, the functional display area 02 can ensure a good white balance effect within the functional display area 01 while reducing the light transmittance of the high density of the second pixel circuits 21.

[0063] Furthermore, in this embodiment, if the multiple pixel circuit clusters 021 arranged along the first direction X are considered as a single pixel circuit cluster group, as shown in Figure 5, although the pixel circuit cluster group between two adjacent second fixed potential signal lines 23 increases to two pixel circuit cluster groups, because the pixel circuit clusters 021 are arranged in a staggered manner, the number of pixel circuit clusters 021 loaded on each individual second fixed potential line 23 does not actually increase. In this embodiment, since the number of second pixel circuits 21 loaded on the second fixed potential line 34 does not increase, the load current of the second fixed potential line 23 also does not increase, ensuring that the second pixel circuit 21 can obtain a stable fixed potential signal.

[0064] Figure 6 is a partial enlarged view of another display panel provided in an embodiment of this application.

[0065] In another embodiment of this application, as shown in FIG6, the functional display area 02 includes a light-transmitting display area 02A and a transition display area 02B, with the transition display area 02B located between the conventional display area 01 and the light-transmitting display area 01A. Both the light-transmitting display area 02A and the transition display area 02B are equipped with second light-emitting diodes 22. However, the second pixel circuit 21 in the functional display area 02 is located in the transition display area 02B; that is, the second pixel circuit 21 electrically connected to the second light-emitting diode 22 in the light-transmitting display area 02A is located in the transition display area 02B. As shown in FIG6, a portion of the second pixel circuit 21 located in the transition display area 02B is electrically connected to the second light-emitting diode 22 located in the transition display area 02B and provides it with a light-emitting driving current, while another portion of the second pixel circuit 21 is electrically connected to the second light-emitting diode 22 located in the light-transmitting display area 02A and provides it with a light-emitting driving current.

[0066] It should be noted that Figure 6 illustrates the overlap between the second light-emitting diode 22 located in the transition display area 02B and the second pixel circuit 21 electrically connected to it. However, the overlap between the second light-emitting diode 22 and the second pixel circuit 21 in the transition display area 02B is not necessary; they only need to be electrically connected. For example, the second light-emitting diode 22 can be evenly distributed in the transition display area 02B, and its density can be the same as that of the first light-emitting diode 12 in the conventional display area 01.

[0067] In this embodiment, the density of the second pixel circuit 21 located in the transition display area 02B is greater than the density of the first pixel circuit 11 located in the conventional display area 01, and the distance between adjacent first fixed potential lines 13 is equal to the distance between adjacent second fixed potential lines 23.

[0068] For example, as shown in Figure 6, exemplarily, the density of the second pixel circuit 21 located in the transition display area 02B is approximately twice the density of the second light-emitting diode 22 located in the transition display area 02B. Furthermore, the second pixel circuits 21 in the transition display area 02B are uniformly distributed in a matrix, and the first pixel circuits 11 in the conventional display area 01 are also uniformly distributed in a matrix. Therefore, in the second direction Y, the density of the second pixel circuits 21 in the transition display area 02B is twice the density of the first pixel circuits 11 in the conventional display area 01. At this time, the distance between two adjacent second fixed potential lines 23 can be equal to the distance between two adjacent first fixed potential lines 13, and the number of columns of the second pixel circuits 21 between two adjacent second fixed potential lines 23 is twice the number of columns of the first pixel circuits 11 between two adjacent first fixed potential lines 13.

[0069] In one implementation of this embodiment, please continue to refer to FIG6. Along the thickness direction of the display panel, the second fixed potential line 23 does not overlap with the light-transmitting display area 02A. That is, the second fixed potential line 23 is not provided in the light-transmitting display area 02A.

[0070] In this embodiment, the second pixel circuit 21 and related signal lines are not provided in the light-transmitting display area 02A, resulting in better light transmittance. Furthermore, in this embodiment, the density of the second fixed potential signal line 23 in the transition display area 02B is consistent with the density of the first fixed potential line 13 in the conventional display area 01. Therefore, from a macroscopic perspective, the resistance distribution on the fixed potential lines providing fixed potential signals to the pixel circuit is uniform, without increasing local resistance. This can, to a certain extent, avoid voltage drop differences on the fixed potential lines at different locations, thus further improving the display uniformity of the display panel.

[0071] It should be noted that, in the above embodiments, the uniform distribution of the first pixel circuit 11 and the uniform distribution of the second pixel circuit 21 means that the first pixel circuit 11 and the second pixel circuit are basically uniformly distributed. For example, the distance between two first pixel circuits 11 that are adjacent to the first fixed potential line 13 and arranged along the second direction Y is greater than the distance between two first pixel circuits 11 that are not adjacent to the first fixed potential line 13 and arranged along the second direction Y, and the distance between two second pixel circuits 21 that are adjacent to the second fixed potential line 23 and arranged along the second direction Y is greater than the distance between two second pixel circuits 21 that are not adjacent to the second fixed potential line 23 and arranged along the second direction Y, then, without considering the space occupied by the first fixed potential line 13 and the second fixed potential line 23, the first pixel circuit 11 is basically uniformly distributed and the second pixel circuit 21 is also basically uniformly distributed.

[0072] In one embodiment of this application, as shown in Figures 3-6, the first direction X is parallel to the third direction X', the second direction Y is parallel to the fourth direction Y', and the first direction X is perpendicular to the second direction Y. That is, the first fixed potential line 13 is parallel to the second fixed potential line 23, and the arrangement direction of the first fixed potential line 13 is the same as the arrangement direction of the second fixed potential line 23.

[0073] In one implementation of this embodiment, as shown in Figures 3-6, the second fixed potential line 23 is aligned with a first fixed potential line 13 along the second direction Y, and the second fixed potential line 23 is connected to the first fixed potential line 13. It can be understood that in this implementation, the second fixed potential line 23 and the first fixed potential line 11 to which it is aligned and connected are the same potential line, located in different parts of the functional display area 02 and the conventional display area 01, respectively.

[0074] Figure 7 is a partial enlarged view of another display panel provided in an embodiment of this application, and Figure 8 is a current diagram of the display panel shown in Figure 7.

[0075] In another implementation of this embodiment, as shown in FIG7, the second fixed potential line 23 is offset from any one of the first fixed potential lines 13 in the second direction Y. This can be understood as follows: in this implementation, the second fixed potential line 23 and the first fixed potential line 11 are fixed potential lines located in the functional display area 02 and the conventional display area 01, respectively, and are not continuous along the second direction Y.

[0076] Referring to Figures 7 and 8, when the second fixed potential line 23 and the first fixed potential line 13 are not continuous along the second direction Y, i.e., when they are misaligned, the current I1 transmitted by the first fixed potential line 13, when flowing along the second direction Y and towards the second fixed potential line 23, will result in a current I2 flowing in a direction intersecting the second direction Y. Therefore, the current reaching the second fixed potential line 23 becomes current I3, where I3 < I1. Alternatively, when the current I3 transmitted by the second fixed potential line 23, when flowing along the second direction Y and towards the first fixed potential line 13, becomes current I1, where I1 < I3. This is equivalent to dispersing the voltage drop originally between the first fixed potential line 23 and the second fixed potential line 13 to the connection portion of the misaligned second fixed potential line 23 and the first fixed potential line 13. This voltage drop dispersion can improve display uniformity.

[0077] In one specific implementation, the first fixed potential line 13 and the second fixed potential line 23 are adjacent to the blue sub-pixel. Since the blue sub-pixel uses a low-efficiency fluorescent light-emitting material, the voltage difference between the fixed potential signal and the data voltage signal in the corresponding first pixel circuit 11 and second pixel circuit 21 must be maximized to ensure the brightness of the blue sub-pixel. Placing the fixed potential signal lines near the blue sub-pixel can minimize the display unevenness of the blue sub-pixel.

[0078] Furthermore, the first fixed potential line 13 and the second fixed potential line 23 are positioned between the blue sub-pixel and the green sub-pixel. Since the green sub-pixel contributes the most to the display brightness, its display unevenness is most easily noticed. Therefore, setting the first fixed potential line 13 and the second fixed potential line 23 adjacent to the green sub-pixel has a significant effect on improving the display uniformity of white screens or other high-brightness screens.

[0079] Figure 9 is an equivalent circuit diagram of the first pixel circuit and the second pixel circuit in a display panel provided in an embodiment of this application.

[0080] In this application, as shown in FIG9, the first pixel circuit 11 includes a first driving transistor Td, which is used to generate a light-emitting driving current for driving the first light-emitting diode 12 to emit light. The second pixel circuit 21 includes a second driving transistor Td', which is used to generate a light-emitting driving current for driving the second light-emitting diode 22 to emit light.

[0081] In one embodiment of this application, referring to FIG9, the first pixel circuit 11 further includes at least one first reset transistor, the control terminal of the first driving transistor Td is electrically connected to the output terminal of the first reset transistor, and / or the anode of the first light-emitting diode 12 is electrically connected to the output terminal of the first reset transistor. The second pixel circuit 21 further includes at least one second reset transistor T0', the control terminal of the second driving transistor Td' is electrically connected to the output terminal of the second reset transistor T0', and / or the anode of the second light-emitting diode 22 is electrically connected to the output terminal of the second reset transistor.

[0082] In one implementation of this application, the first pixel circuit 11 includes two first reset transistors T0 and T5. The output terminal of the first reset transistor T0 is electrically connected to the control terminal of the first driving transistor Td, and the input terminal V0 of the first reset transistor T0 receives a reset signal and transmits the reset signal to the control terminal of the driving transistor Td to reset the control terminal of the driving transistor Td. The output terminal of the first reset transistor T5 is electrically connected to the anode of the first light-emitting diode 12, and the input terminal V5 of the first reset transistor T5 receives a reset signal and transmits the reset signal to the anode of the first light-emitting diode 12 to reset the anode of the first light-emitting diode 12.

[0083] In another implementation of this application, the second pixel circuit 21 includes two second reset transistors T0' and T5'. The output terminal of the second reset transistor T0' is electrically connected to the control terminal of the second driving transistor Td', and the input terminal V0' of the second reset transistor T0' receives a reset signal and transmits the reset signal to the control terminal of the driving transistor Td' to reset the control terminal of the second driving transistor Td'. The output terminal of the second reset transistor T5' is electrically connected to the anode of the second light-emitting diode 22, and the input terminal V5' of the second reset transistor T0' receives a reset signal and transmits the reset signal to the anode of the second light-emitting diode 22 to reset the anode of the second light-emitting diode 22.

[0084] In one embodiment of this application, referring to FIG9, the first pixel circuit 11 further includes a first power supply voltage transistor T1, the output terminal of which is electrically connected to a first driving transistor Td. Specifically, the output terminal of the first power supply voltage transistor T1 can be electrically connected to the input terminal V1 of the first driving transistor Td. The input terminal V1 of the first power supply voltage transistor T1 receives the power supply voltage and transmits the power supply voltage to the first driving transistor T1. The second pixel circuit 21 includes a second power supply voltage transistor T1', the output terminal of which is electrically connected to a second driving transistor Td'. Specifically, the output terminal of the second power supply voltage transistor T1' can be electrically connected to the input terminal of the second driving transistor Td'. The input terminal V1' of the second power supply voltage transistor T1' receives the power supply voltage signal and transmits the power supply voltage signal to the second driving transistor Td'.

[0085] It should be noted that the first pixel circuit 11 and the second pixel circuit 21 in this application can have the same circuit structure, as shown in Figure 9. The first pixel circuit 11 may include a first driving transistor Td, a first reset transistor T0 / T5, a first power supply voltage transistor T1, a first data voltage writing transistor T2, a first threshold grabbing transistor T3, a first light emission control transistor T4, and a first storage capacitor C; the second pixel circuit 21 may include a second driving transistor Td', a second reset transistor T0' / T5', a second power supply voltage transistor T1', a second data voltage writing transistor T2', a second threshold grabbing transistor T3', a second light emission control transistor T4', and a second storage capacitor C'. Furthermore, the input terminal V2' of the second data voltage writing transistor T2 and the input terminal V1' of the first data voltage writing transistor T1 can be connected to the same type of signal line.

[0086] Furthermore, the first pixel circuit 11 and the second pixel circuit 21 in this application can have different circuit structures. The operation of the first pixel circuit 11 will be described below using the first pixel circuit 11 shown in FIG9 as an example.

[0087] In the example shown in Figure 9, the first driving transistor Td, the first reset transistor T0 / T5, the first power supply voltage transistor T1, the first data voltage writing transistor T2, the first threshold grasping transistor T3, and the first light-emitting control transistor T4 in the first pixel circuit 11 are all P-type transistors. In other optional embodiments, the first driving transistor Td, the first reset transistor T0 / T5, the first power supply voltage transistor T1, the first data voltage writing transistor T2, the first threshold grasping transistor T3, and the first light-emitting control transistor T4 can also all be N-type transistors, or some can be P-type transistors and some can be N-type transistors.

[0088] In this configuration, the output of one first reset transistor T0 is electrically connected to the control terminal S0 of the first driving transistor Td; the output of another first reset transistor T5 is electrically connected to the anode of the first light-emitting diode 12. The output of the first power supply voltage transistor T1 is electrically connected to the input of the light-emitting driving transistor Td, and the input V1 of the first power supply voltage transistor T1 is electrically connected to one plate of the first storage capacitor C. The control terminal of the first driving transistor Td is electrically connected to the other plate of the first storage capacitor C. The input V2 of the first data voltage writing transistor T2 receives the data voltage, and its output is electrically connected to the input of the first driving transistor Td. The input of the first threshold grabbing transistor T3 is electrically connected to the output of the first driving transistor Td, and its output is electrically connected to the control terminal of the first driving transistor Td. The input of the first light-emitting control transistor T4 is electrically connected to the output of the first driving transistor Td, and its output is electrically connected to the first light-emitting diode 12.

[0089] The operation of the first pixel circuit 11 shown in Figure 9 may include a reset stage, a data voltage writing stage, and a light emission stage.

[0090] During the reset phase, the first reset transistor T0 is turned on under the control of its control terminal S0, and its input terminal V0 receives a reset signal, which is then written to the control terminal of the first driving transistor Td. In other embodiments, if the first reset transistor T5 is turned on under the control of its control terminal S5 and its input terminal V5 receives a reset signal, the anode of the first light-emitting diode 12 is also written with a reset signal.

[0091] During the data voltage writing phase, the first power supply voltage transistor T1 is turned off under the control of its control terminal S1, and the first light-emitting control transistor T4 is turned off under the control of its control terminal S4. The first data voltage writing transistor T2 is turned on under the control of its control terminal S2, and the first threshold capture transistor T3 is turned on under the control of its control terminal S3. The input terminal V2 of the first data voltage writing transistor T2 receives the data voltage Vdata. Since the potential of the data voltage Vdata is higher than the potential of the reset signal stored in the first storage capacitor C, the first driving transistor Td is turned on, and the data voltage Vdata is written to the control terminal of the first driving transistor Td. The first driving transistor Td is turned off when the voltage at the control terminal of the first driving transistor Td is Vdata - |Vth|. The first storage capacitor C can then store the potential Vdata - |Vth| that was electrically connected to the control terminal of the first driving transistor Td at the end of the data voltage writing phase. In another embodiment of this application, during the reset phase, the control terminal S5 of the first reset transistor T5 receives a cutoff signal; during the data voltage writing phase, the control terminal S5 of the first reset transistor T5 receives a conduction signal to control the first reset transistor T5 to turn on and the input terminal V5 of the first reset transistor T5 receives a reset signal, so that the anode reset of the first light-emitting diode 12 is completed simultaneously during the data voltage writing phase.

[0092] During the light-emitting phase, the first data voltage writing transistor T2 is turned off under the control of its control terminal S2, and the first threshold grabbing transistor T3 is turned off under the control of its control terminal S3. The first power supply voltage transistor T1 is turned on under the control of its control terminal S1, and the first light-emitting control transistor T4 is turned on under the control of its control terminal S4. The input terminal V1 of the first power supply voltage transistor T1 receives the power supply voltage VDD, which is then transmitted to the input terminal of the light-emitting driving transistor Td. Since the potential of the power supply voltage VDD is greater than the potential of the data voltage Vdata, the first driving transistor Td generates a light-emitting driving current, which is transmitted to the first light-emitting diode 12 through the first light-emitting control transistor T4. At this time, the light-emitting driving current generated by the first driving transistor Td is: Ids = K*(VDD-Vdata)^2.

[0093] It should be noted that Figure 9 only shows an equivalent circuit diagram of a first pixel circuit 11 and a second pixel circuit. The specific structures of the first pixel circuit 11 and the second pixel circuit 21 in this application can also be other forms.

[0094] In one embodiment of this application, the input terminal V0 of the first reset transistor T0 is electrically connected to the first fixed potential line 13, that is, the fixed potential signal received by the first fixed potential line 13 can be a reset signal, and the first fixed potential line 13 can provide a reset signal to the input terminal V0 of the first reset transistor T0; the input terminal V0' of the second reset transistor T0' is electrically connected to the second fixed potential line 23, that is, the fixed potential signal received by the second fixed potential line 23 can be a reset signal, and the second fixed potential line 23 can provide a reset signal to the input terminal V0' of the second reset transistor T0'.

[0095] In this embodiment, when the number of second pixel circuit groups 21A between adjacent second fixed potential lines 23 in the functional display area 02 increases compared to the number of first pixel circuit groups 11A between adjacent first fixed potential lines 13 in the conventional display area 02, it is equivalent to a decrease in the number of parallel second fixed potential lines 23, and the resistance of the corresponding parallel second fixed potential lines 23 increases. However, the inventors have discovered that since the second fixed potential lines 23 transmit fixed potential signals as reset signals, the increase in resistance of the parallel second fixed potential lines 23 does not significantly affect the light-emitting driving current generated by the second pixel circuit 21. This will be explained in detail below.

[0096] On the one hand, since the voltage drop level of the fixed potential signal, which serves as the reset signal, is very low, the increase in resistance of the parallel second fixed potential line 23 has almost no effect on the reset process of the first reset transistor T0 in the second pixel circuit 21.

[0097] Here, the analysis is performed using the infinitesimal element method. According to the formula for calculating voltage drop, ΔV = I * R, the voltage drop on the second fixed potential line 23 depends on the current flowing through the second fixed potential line 23 and the resistance of the second fixed potential line 23. Here, ΔV is the voltage drop on the second fixed potential line 23, I is the current on the second fixed potential line 23, and R is the resistance on the second fixed potential line 23.

[0098] When the control terminals of the first driving transistor Td and the second driving transistor Td' are reset, the first storage capacitor electrically connected to the control terminal of the first driving transistor Td and the second storage capacitor C' electrically connected to the control terminal of the second driving transistor Td' are actually charged, respectively. Taking the embodiments shown in Figures 3-4, 6-7, and 14 as examples, a first fixed potential line 13 in the conventional display area 01 is equivalent to charging the first storage capacitor C in the three groups of first pixel circuits 11A, and a second fixed potential line 23 in the functional display area 02 is equivalent to charging the second storage capacitor C' in the six groups of second pixel circuits 21A. Since the capacitance values ​​of the first and second storage capacitors C and C' are very small and the resistance value of the second fixed potential line 23 is very low, although the voltage drop of the second fixed potential line 23 in the functional display area 02 increases compared to the conventional display area 01, the difference in voltage drop between the first fixed potential line 13 and the second fixed potential line 23 is almost negligible.

[0099] For example, taking an organic light-emitting display panel as an example, the capacitance values ​​of the first storage capacitor C and the second storage capacitor C' are both on the order of pF, and the reset phase time is on the order of μs. The voltage difference between the control terminals of the first driving transistor Td and the second driving transistor Td' from the data voltage of the previous frame to the reset signal voltage of the current frame is within 10V. Therefore, it can be calculated that the charging current of the control terminals of the first driving transistor Td and the second driving transistor Td' during the reset phase is on the order of μA. The material of the first fixed potential line 13 and the second fixed potential line 23 transmitting the reset signal is usually Ti / Al / Ti, and its sheet resistance is 10 Ω. -2 The voltage drop difference is on the order of Ω / □, therefore, the voltage drop difference between the first fixed potential line 13 and the second fixed potential line 23 is both within 10 Ω / □. -2 The value is on the order of μV and is almost negligible. Even if the first fixed potential line 13 and the second fixed potential line 23, which transmit the reset signal, are made of Mo, their sheet resistance would only be 10⁻⁶ Ω. -1 The voltage drop difference is on the order of Ω / □, therefore, the voltage drop difference between the first fixed potential line 13 and the second fixed potential line 23 is on the order of 10Ω / □. -1 The voltage drop is on the order of μV and can still be ignored. Furthermore, in organic light-emitting display panels, the fixed potential signal used as the reset signal is typically around -2V. The voltage drop difference between the first fixed potential line 13 and the second fixed potential line 23 during the reset phase is so small as to be negligible compared to the voltage value of the reset signal.

[0100] When it is also necessary to reset the anodes of the first LED 12 and the second LED 22, in order to reduce the current flowing through the second fixed potential line 23, in this embodiment, the process of resetting the control terminals of the first driving transistor Td and the second driving transistor Td' can be performed in a time-sharing manner with the process of resetting the anodes of the first LED 12 and the second LED 22. For example, the process of resetting the control terminals of the first driving transistor Td and the second driving transistor Td' is performed during the reset phase, and the process of resetting the anodes of the first LED 12 and the second LED 22 is performed during the data voltage writing phase. Therefore, even if the voltage drop difference between the first fixed potential line 13 and the second fixed potential line 23 is large when resetting the anodes of the first LED 12 and the second LED 22, it will not affect the potentials of the terminals of the first driving transistor Td and the second driving transistor Td' used to generate the light-emitting driving current.

[0101] On the other hand, the fixed potential signal, which serves as a reset signal, does not directly affect the generation of the light-emitting driving current. Therefore, its influence on the light-emitting driving current is negligible. In other words, the change in the fixed potential signal transmitted by the second fixed potential line 23 has a negligible effect on the light-emitting driving current generated by the second light-emitting diode 22.

[0102] First, in non-solid color images, the potential differences at the control terminals of the various second driving transistors Td' in the previous frame are significant, while the voltage drop across the second fixed potential line 23 is negligible compared to these potential differences. In solid color images, although the target data voltages of sub-pixels of the same color are identical, and the reset signal potential at the control terminal of the second driving transistor Td' affects the generation of the light-emitting driving current, the charging of the second storage capacitor C' during the reset phase is a process that is initially fast and then slows down. The longer the charging time, the closer the potential at the control terminal of the second driving transistor Td' is to the reset signal. The impact of the charging time of the second storage capacitor C' during the reset phase on the potential at the control terminal of the second driving transistor Td' is far greater than the impact of the voltage drop across the second fixed potential line 23 on the potential at the control terminal of the second driving transistor Td'.

[0103] Secondly, although the different reset signals of the control terminals of the first driving transistor Td and the second driving transistor Td' during the data voltage writing stage will cause the actual data voltage charged to the control terminals of the first driving transistor Td and the second driving transistor Td' to be different, the difference in threshold voltage of each first driving transistor Td in the first pixel circuit 11 and the difference in threshold voltage of each second driving transistor Td' in the second pixel circuit 21 will have a much greater impact on the difference in light-emitting driving current caused by the voltage drop on the second fixed potential line 23.

[0104] On the other hand, the reset signals transmitted by the first fixed potential line 13 and the second fixed potential line 23 as reset signals are fixed potential signals, not pulse signals. Therefore, the first fixed potential line 13 and the second fixed potential line 23 do not need to be frequently charged and discharged, which reduces the impact of the number of the first fixed potential line 13 and the second fixed potential line 23 on their respective loads. Furthermore, reducing the number of second fixed potential lines 23 also reduces the parasitic capacitance of the second fixed potential lines 23 in the functional display area 02. Therefore, even the load of a single second fixed potential line 23 does not increase the total load of all second fixed potential lines 23, and thus the impact on the light-emitting driving current is negligible.

[0105] Therefore, in summary, when the first fixed potential line 13 and the second fixed potential line 23 of this application transmit fixed potential signals, they can reduce the area of ​​the non-transparent portion of the functional display area 02. While increasing the light transmittance of the functional display area 02, they have virtually no impact on the display brightness, ensuring the display uniformity of the functional display area 02 and the uniformity of display brightness between the functional display area 02 and the conventional display area 01. In other words, the display panel with the functional display area 02 provided by this application balances display effect and light transmittance, solving a major problem restricting under-display optical sensor technology.

[0106] It is important to emphasize that the advantages of the technical solution provided in this application embodiment are particularly prominent in display panels where the pixel density of the functional display area 02 and the conventional display area 01 is essentially the same. When the pixel density of the functional display area 02 and the conventional display area 01 in the display panel is essentially the same, the number of data signal lines and scan signals cannot be reduced for normal display function. However, narrowing the data voltage signal lines and scan lines would affect the parasitic capacitance on the scan lines and data voltage signal lines, resulting in a poorer line charging effect. This would cause the data voltage signal to deviate from the target value, and the charging time of the scan lines for the first pixel circuit 11 and the second pixel circuit 21 would be severely insufficient. As can be seen from the above analysis, reducing the number of second fixed potential lines 23 that transmit reset signals has a negligible impact on display uniformity. Therefore, while achieving the ultimate goal of not reducing the resolution of the functional display area 02, the design of reducing the number of second fixed potential lines 23 that transmit reset signals can play a crucial role.

[0107] In one embodiment of this application, the function display area 02 is located away from the access terminal of the fixed potential signal. That is, the distance between the function display area 02 and the access terminal of the fixed potential signal is greater than the distance between the function display area 02 and the side of the conventional display area 01 away from the access terminal of the fixed potential signal.

[0108] Since the fixed potential signal, which serves as the reset signal, enters the conventional display area 01 and functional display area 02 of the display panel from the fixed potential signal input terminal, along the extension direction of the first fixed potential line 13 and the second fixed potential line 23, the current per unit length of the first fixed potential line 13 or the second fixed potential line closer to the fixed potential signal input terminal is greater than the current per unit length of the first fixed potential line 13 or the second fixed potential line 23 farther from the fixed potential signal input terminal. That is, along the extension direction of the first fixed potential line 13 and the second fixed potential line 23, the voltage drop at a position farther from the fixed potential signal input terminal in the first fixed potential line 13 and the second fixed potential line 23 is less than the voltage drop at a position closer to the fixed potential signal input terminal. Therefore, by setting the functional display area 02 farther from the fixed potential signal input terminal, the voltage drop difference between the second fixed potential line in the functional display area 02 and the first fixed potential line 13 in the adjacent conventional display area 01 can be reduced.

[0109] Similarly, if the input terminals of the fixed potential signals are located on opposite sides of the display panel, the function display area 02 can be set in the middle of the opposite sides of the display panel.

[0110] In one implementation of this embodiment, (m2 / m1)*H≤200, where H is the total number of rows of the second pixel circuits 21 arranged along the first direction X in the functional display area 02. According to the description of the above embodiment, the voltage drop difference of the second fixed potential line 23 is typically within 10... -2 On the order of μV, when the design of the second fixed potential line 23 in the functional display area 02 and the design of the first fixed potential line 13 in the conventional display area 01 satisfy the above relationship, the difference in the reset signal received in the functional display area 01 between the two rows of second pixel circuits 21 is also on the order of μV, which is still difficult to detect with the naked eye. For the same reason, the voltage drop of the first fixed potential signal 13 in the area of ​​the conventional display area 01 adjacent to the functional display area 02 and the voltage drop of the second fixed potential signal 23 in the functional display area 02 are also very small. Therefore, it is difficult for consumers to perceive a difference in brightness between the functional display area 02 and the conventional display area 01 with the naked eye.

[0111] In one implementation of this embodiment, the functional display area 02 is located on the side of the conventional display area 01 away from the access terminal of the fixed potential signal. In this case, the edge of the functional display area 02 away from the access terminal of the fixed potential signal is also away from the conventional display area 01. That is, not all the edges in the functional display area 02 are adjacent to the conventional display area 01, which reduces the length of the dangerous area where the conventional display area 01 and the functional display area 02 may experience sudden brightness changes.

[0112] In one implementation of this embodiment, as shown in Figures 3-7, the conventional display area 01 further includes multiple third fixed potential lines 14. These third fixed potential lines 14 extend along the fifth direction Y1 and are arranged along the sixth direction X1. Each third fixed potential line 14 is electrically connected to at least two first fixed potential lines 13. The functional display area 02 further includes multiple fourth fixed potential lines 24. These fourth fixed potential lines 24 extend along the seventh direction Y2 and are arranged along the eighth direction X2. Each fourth fixed potential line 24 is electrically connected to at least two second fixed potential lines 23.

[0113] Specifically, the fifth direction Y1 and the seventh direction Y2 can be parallel to the second direction Y and the fourth direction Y', and the sixth direction X1 and the eighth direction X2 can be parallel to the first direction X and the second direction X'. That is, the third fixed potential line 14 and the fourth fixed potential line 24 are also used to transmit reset signals, and the first fixed potential line 13 and the third fixed potential line 14 are cross-connected to form a mesh structure, and the second fixed potential line 23 and the fourth fixed potential line 24 are cross-connected to form a mesh structure.

[0114] Referring to Figure 8, when the first fixed potential line 13 and the third fixed potential line 14 are electrically connected to form a mesh structure, and the second fixed potential line 23 and the fourth fixed potential line 24 are electrically connected to form a mesh structure, the current transmitted on the second fixed potential line 23 and the first fixed potential line 13 will be distributed to the third fixed potential line 14 and the fourth fixed potential line 24. This reduces the current on the first fixed potential line 13 and the second fixed potential line 23, thus reducing the voltage drop on the first fixed potential line 13 and the second fixed potential line 23. This voltage drop dispersion can improve display uniformity.

[0115] In one technical solution corresponding to this embodiment, the first fixed potential line 13 and the second fixed potential line 23 are both metal conductive structures, and the third fixed potential line 14 and the fourth fixed potential line 24 are both semiconductor conductive structures.

[0116] Figure 10 is a schematic diagram of the actual structure and layout of the pixel circuit shown in Figure 9. Figure 11 is a partial cross-sectional view of Figure 10. Figure 12 is a cross-sectional view along the MN direction in Figure 10. Figure 13 is a cross-sectional view along the M'N' direction in Figure 10. It should be noted that, in order to avoid the diagrams being unclear due to excessive film layer stacking, the structures of the first storage capacitor C and the second storage capacitor C' are not shown in Figure 10.

[0117] Referring to Figures 10 and 11, the transistors in both the first pixel circuit 11 and the second pixel circuit 12 include a semiconductor layer PL, a gate GL, a source SL, and a drain. The semiconductor layer PL is disposed on the substrate. A gate insulating layer is disposed between the gate GL and the semiconductor layer PL. An interlayer insulating layer is disposed between the source SL and the gate GL. A planarization layer is disposed between the anode and the source SL. A pixel defining layer is disposed on the anode, and an organic light-emitting layer is disposed in the opening of the pixel defining layer. The first light-emitting diode 12 and the second light-emitting diode 22 are electrically connected to the first pixel circuit 11 and the second pixel circuit 21, respectively. When the first light-emitting diode 12 and the second light-emitting diode 22 are organic light-emitting diodes, they both include an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. In addition, the first light-emitting diode 12 and the second light-emitting diode 22 also include a TFE encapsulation layer on the side near the light-emitting surface. It should be noted that some organic light-emitting display panels also have a capacitor metal layer. The capacitor metal layer is disposed between the film layer where the gate GL is located and the film layer where the source SL is located. A first interlayer insulating layer is disposed between the capacitor metal layer and the film layer where the gate GL is located, and a second interlayer insulating layer is disposed between the capacitor metal layer and the film layer where the source SL is located.

[0118] Referring to Figures 10 and 12, the first reset transistor T0 in the first pixel circuit 11 includes a first semiconductor structure SL1, a first gate, a first source, and a first drain. The first gate serves as a control terminal and is electrically connected to the scan line GL1, and the two are located on the same layer. The first source serves as an input terminal and is electrically connected to the first fixed potential line 13. The first drain serves as an output terminal and is electrically connected to the connection line CL1. The connection line CL1 is electrically connected to the control terminal of the first driving transistor Td.

[0119] Please continue to refer to Figure 10. Each transistor in the first pixel circuit 11 includes a first semiconductor structure (semiconductor layer PL), and the first semiconductor structures (semiconductor layers PL) of each transistor are connected together. For example, the first semiconductor structures of the first driving transistor Td, the first reset transistor T0, the first power supply voltage transistor T1, the first data voltage writing transistor T2, the first threshold grabbing transistor T3, and the first light emission control transistor T4 in the first pixel circuit 11 are connected together.

[0120] Furthermore, referring to Figure 10, the first semiconductor structures in adjacent first pixel circuits 11 are also connected together. These first semiconductor structures can be connected via a third fixed potential line 14. Specifically, the first semiconductor structures in the first pixel circuits 11 arranged along the second direction Y are arranged on the same layer and continuously with the adjacent third fixed potential line 14, and the first semiconductor structures in the first pixel circuits 11 on both sides of the third fixed potential line 14 are also arranged on the same layer and continuously with the third fixed potential line 14.

[0121] Furthermore, referring to Figures 10 and 12, the third fixed potential line 14 and the first fixed potential line 13 are connected together through a via, so the first fixed potential line 13 can receive a reset signal and transmit it to the first pixel circuit 11 through the third fixed potential line.

[0122] Referring to Figures 10 and 13, the second reset transistor T0' in the second pixel circuit 21 includes a second semiconductor structure SL2, a second gate, a second source, and a second drain. The second gate serves as a control terminal and is electrically connected to the scan line GL2; the second source serves as an input terminal and is electrically connected to the second fixed potential line 23; and the second drain serves as an output terminal and is electrically connected to the connection line CL2. The connection line CL2 is electrically connected to the control terminal of the second driving transistor Td'.

[0123] Please continue to refer to Figure 10. Each transistor in the second pixel circuit 21 includes a second semiconductor structure (semiconductor layer PL), and the second semiconductor structures (semiconductor layers PL) of each transistor are connected together. For example, the second semiconductor structures of the second driving transistor Td', the second reset transistor T0', the second power supply voltage transistor T1', the second data voltage writing transistor T2', the second threshold grabbing transistor T3', and the second light emission control transistor T4' in the second pixel circuit 21 are connected together.

[0124] Furthermore, referring to Figure 10, the second semiconductor structures in adjacent second pixel circuits 21 are also connected together. These second semiconductor structures can be connected via a fourth fixed potential line 24. Specifically, the second semiconductor structures in the second pixel circuits 21 arranged along the fourth direction Y' are arranged on the same layer and continuously with the adjacent fourth fixed potential line 24, and the second semiconductor structures in the second pixel circuits 21 on both sides of the fourth fixed potential line 24 are also arranged on the same layer and continuously with the fourth fixed potential line 24.

[0125] Furthermore, referring to Figures 10 and 13, the fourth fixed potential line 24 and the second fixed potential line 23 are connected together through a via, so the second fixed potential line 23 can receive a reset signal and transmit it to the second pixel circuit 21 through the fourth fixed potential line.

[0126] Furthermore, referring to Figure 10, the third fixed potential line 14 and the fourth fixed potential line 24 are continuous semiconductor structures, but they are located in the conventional display area 01 and the functional display area, respectively. Therefore, the first semiconductor structure in the first pixel circuit 11 and the second semiconductor structure in the second pixel circuit 21 can also be connected together.

[0127] It should be noted that the gates of transistors with the same function or transistors that are simultaneously turned on and off in the plurality of first pixel circuits 11 arranged along the second direction Y can be connected to the same scan line. For example, the first gate of the first reset transistor T0 in the plurality of first pixel circuits 11 arranged along the second direction Y can be connected to the same scan line GL1; the control terminal S2 of the first data voltage writing transistor T2 and the control terminal S3 of the first threshold grabbing transistor T3 in the plurality of first pixel circuits 11 arranged along the second direction Y can be connected to the same scan line GL2; the control terminal S1 of the first power supply voltage transistor T1 and the control terminal S4 of the first light emission control transistor T4 in the plurality of first pixel circuits 11 arranged along the second direction Y can be connected to the same scan line GL3; the control terminal S5 of the first reset transistor T5 in the plurality of first pixel circuits 11 arranged along the second direction Y can be connected to the same scan line GL4, and the scan line GL4 can be multiplexed with the scan line GL1 of the next row.

[0128] The gates of transistors with the same function or transistors that are simultaneously turned on and off in a plurality of second pixel circuits 21 arranged along the fourth direction Y' can be connected to the same scan line. For example, the second gate of the second reset transistor T0' in a plurality of second pixel circuits 21 arranged along the fourth direction Y' can be connected to the same scan line GL1'; the control terminal of the second data voltage writing transistor T2' and the control terminal of the second threshold grabbing transistor T3' in a plurality of second pixel circuits 21 arranged along the second direction Y can be connected to the same scan line GL2'; the control terminal of the second power supply voltage transistor T1' and the control terminal of the second light emission control transistor T4' in a plurality of second pixel circuits 21 arranged along the second direction Y can be connected to the same scan line GL3; the control terminal S5 of the second reset transistor T5' in a plurality of second pixel circuits 21 arranged along the second direction Y can be connected to the same scan line GL4', and the scan line GL4' can be multiplexed with the scan line GL1' of the next row.

[0129] Furthermore, when the second direction Y is parallel to the fourth direction Y', the gates of transistors with the same function or transistors that are simultaneously turned on and off in the plurality of first pixel circuits 11 and the plurality of second pixel circuits 21 arranged along the second direction Y can be connected to the same scan line. For example, the scan line GL1 connected to the first gate of the first reset transistor T0 in the plurality of first pixel circuits 11 arranged along the second direction Y and the scan line GL1' connected to the second gate of the second reset transistor T0' in the plurality of second pixel circuits 21 are the same scan line. Similarly, the scan lines GL2 and GL2' located in the same row are the same scan line, the scan lines GL3 and GL3' located in the same row are the same scan line, and the scan lines GL4 and GL4' located in the same row are the same scan line.

[0130] Furthermore, the input terminal V2 of the first data voltage writing transistor T2 in the plurality of first pixel circuits 11 arranged along the first direction X can be connected to the same data voltage signal line DL1, and the input terminal V2' of the second data voltage writing transistor T2' in the plurality of second pixel circuits 21 arranged along the third direction X' can be connected to the same data voltage signal line DL2. The input terminal V1 of the first power supply voltage transistor T1 in the plurality of first pixel circuits 11 arranged along the first direction X can be connected to the same power supply voltage signal line VL1, and the input terminal V1' of the first power supply voltage transistor T1' in the plurality of second pixel circuits 21 arranged along the third direction X' can be connected to the same power supply voltage signal line VL2.

[0131] Figure 14 is a partial enlarged view of another display panel provided in an embodiment of this application.

[0132] In one technical solution corresponding to this embodiment, as shown in Figures 3, 4, 6, 7, and 14, the number of first pixel circuits 11 in the area enclosed by two adjacent first fixed potential lines 13 and two adjacent third fixed potential lines 14 is n1; the number of second pixel circuits 21 in the area enclosed by two adjacent second fixed potential lines 23 and two adjacent fourth fixed potential lines 24 is n2; n1 and n2 are both positive integers greater than or equal to 2, and n2 > n1. For example, as shown in Figures 3, 4, 6, and 7, n1 = 3, n2 = 6; as shown in Figure 14, n1 = 3, n2 = 12.

[0133] In one implementation of this technical solution, as shown in Figure 14, a third pixel circuit group s1 is provided between two adjacent third fixed potential lines 14, the third pixel circuit group including a plurality of first pixel circuits arranged along the fifth direction; a fourth pixel circuit group s2 is provided between two adjacent fourth fixed potential lines, the fourth pixel circuit group including a plurality of second pixel circuits arranged along the seventh direction; s1 and s2 are both positive integers greater than or equal to 1 and s2 > s1.

[0134] In another implementation of this technical solution, as shown in Figures 3, 4, 6 and 7, a third pixel circuit group s1 is provided between two adjacent third fixed potential lines. The third pixel circuit group includes a plurality of first pixel circuits arranged along the fifth direction. A fourth pixel circuit group s2 is provided between two adjacent fourth fixed potential lines. The fourth pixel circuit group includes a plurality of second pixel circuits arranged along the seventh direction. s1 and s2 are both positive integers greater than or equal to 1 and s2 = s1.

[0135] In this technical solution, s1 = 1.

[0136] In one embodiment of this application, the first fixed potential line 13 is electrically connected to the input terminal V1 of the first power supply voltage transistor T1, or to the cathode of the first light-emitting diode 12; the second fixed potential line 23 is electrically connected to the input terminal V1' of the second power supply voltage transistor T1', or to the cathode of the second light-emitting diode 22. That is, the first fixed potential line 13 provides a power supply voltage to the first power supply voltage transistor T1 or to the first light-emitting diode 12, and the second fixed potential line 23 provides a power supply voltage to the second power supply voltage transistor T1' or to the second light-emitting diode 22.

[0137] On the one hand, since the second fixed potential line 23 transmits the power supply voltage, the attenuation of the power supply voltage on the second fixed potential line 23 remains basically consistent at different times, making it easy to compensate for the power supply voltage on the second fixed potential line 23. On the other hand, the second fixed potential line 23 can maintain the transmission of a fixed potential signal for a certain period of time without frequent charging and discharging, thus avoiding the charging delay problem caused by potential ramp-up during charging. Furthermore, reducing the density of the second fixed potential line 23, compared to reducing the width of the second fixed potential line 23, does not change the resistance and parasitic capacitance of the second fixed potential line 23, thus having a small impact on the display effect.

[0138] In one implementation of this embodiment, the function display area 02 is located at the access terminal away from the power supply voltage. That is, the distance between the function display area 02 and the power supply voltage access terminal is greater than the distance between the function display area 02 and the side of the conventional display area 01 away from the power supply voltage access terminal.

[0139] The power supply voltage enters the conventional display area 01 and the functional display area 02 of the display panel from the power supply voltage input terminal. Along the extension direction of the first fixed potential line 13 and the second fixed potential line 23, the current per unit length of the first fixed potential line 13 or the second fixed potential line closer to the power supply voltage input terminal is greater than the current per unit length of the first fixed potential line 13 or the second fixed potential line 23 farther from the power supply voltage input terminal. That is, along the extension direction of the first fixed potential line 13 and the second fixed potential line 23, the voltage drop at the position farther from the power supply voltage input terminal is less than the voltage drop at the position closer to the power supply voltage input terminal. Therefore, setting the functional display area 02 farther from the power supply voltage input terminal can reduce the voltage drop difference between the second fixed potential line in the functional display area 02 and the first fixed potential line 13 in the adjacent conventional display area 01.

[0140] Similarly, if the power supply voltage input terminals are located on opposite sides of the display panel, the function display area 02 can be set in the middle of those opposite sides of the display panel.

[0141] In one technical solution of this embodiment, the functional display area 02 is located on the side of the conventional display area 01 away from the power supply voltage input terminal. In this case, the edge of the functional display area 02 away from the power supply voltage input terminal is also away from the conventional display area 01. That is, not all the edges in the functional display area 02 are adjacent to the conventional display area 01, which reduces the length of the dangerous area where the conventional display area 01 and the functional display area 02 may experience sudden brightness changes.

[0142] Figure 15 is a schematic diagram of a display device provided in an embodiment of this application.

[0143] As shown in Figure 15, the display device includes the display panel 001 provided in any of the above embodiments. The display device provided in this application embodiment can be a mobile phone; in addition, the display device provided in this application embodiment can also be a computer, television, or other display device.

[0144] As shown in Figure 15, the display device provided in this embodiment further includes an optical functional element 002, which is disposed at a position corresponding to the functional display area 02 of the display panel 001. Specifically, along the thickness direction of the display panel 001, the optical functional element 002 is disposed below the functional display area 002 of the display panel 001. Thus, the optical functional element 002 can emit light towards the light-emitting surface of the display panel 001 through the functional display area 02, or receive light from the light-emitting surface of the display panel 001 through the functional display area 02.

[0145] Among them, the optical functional element 002 is at least one of an optical fingerprint sensor, an iris recognition sensor, a camera, and a flashlight.

[0146] In this embodiment of the application, by reducing the number of second fixed potential lines 23 in the functional display area 02, the light transmittance of the functional display area 02 can be improved, thereby improving the reliability of optical signal transmission in the functional display area 02.

[0147] In the display device provided in this application embodiment, reducing the number of second fixed potential lines 23 has a very small impact on the display effect of the functional display area 02. On the one hand, the second fixed potential lines 23 transmit fixed potential signals, and the attenuation of the fixed potential signals on the second fixed potential lines 23 remains basically consistent at different times, so it is easy to compensate for the fixed potential signals on the second fixed potential lines 23; on the other hand, the second fixed potential lines 23 can always transmit fixed potential signals for a certain period of time without frequent charging and discharging, thus avoiding the charging delay problem caused by potential ramp-up during charging; furthermore, reducing the density of the second fixed potential lines 23, compared to reducing the width of the second fixed potential lines 23, does not change the resistance and parasitic capacitance of the second fixed potential lines 23, so the impact on the display effect is small.

[0148] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A display panel, characterized in that, include: A conventional display area includes: multiple first pixel circuits; multiple first fixed potential lines extending along a first direction and arranged along a second direction, the first fixed potential lines being electrically connected to the first pixel circuits; a functional display area, the area where the functional display area is located is used to set optical functional elements; it includes: multiple second pixel circuits; multiple second fixed potential lines extending along a third direction and arranged along a fourth direction, the second fixed potential lines being electrically connected to the second pixel circuits; wherein, m1 groups of first pixel circuits are arranged between two adjacent first fixed potential lines, the first pixel circuit group including multiple first pixel circuits arranged along the first direction. A pixel circuit; m2 groups of second pixel circuits are arranged between two adjacent second fixed potential lines, each group comprising multiple second pixel circuits arranged along a third direction; m1 and m2 are both positive integers greater than or equal to 1 and m2 > m1; the first direction is parallel to the third direction, the second direction is parallel to the fourth direction, and the first direction is perpendicular to the second direction; the second fixed potential line is aligned with one of the first fixed potential lines along the second direction, and the second fixed potential line is connected to the first fixed potential line; or, the second fixed potential line is misaligned with any of the first fixed potential lines in the second direction.

2. The display panel according to claim 1, characterized in that, The conventional display area at least partially surrounds the functional display area, and at least a portion of the functional display area has a higher light transmittance than the conventional display area.

3. The display panel according to claim 1, characterized in that, The conventional display area further includes multiple first light-emitting diodes (LEDs), and the first pixel circuit is electrically connected to at least one of the first LEDs; the first pixel circuit includes a first driving transistor and at least one first reset transistor; the functional display area further includes multiple second LEDs, and the second pixel circuit is electrically connected to at least one of the second LEDs; the second pixel circuit includes a second driving transistor and at least one second reset transistor; wherein, the control terminal of the first driving transistor is electrically connected to the output terminal of the first reset transistor, and / or the anode of the first LED is electrically connected to the output terminal of the first reset transistor, and the input terminal of the first reset transistor is electrically connected to the first fixed potential line; the control terminal of the second driving transistor is electrically connected to the output terminal of the second reset transistor, and / or the anode of the second LED is electrically connected to the output terminal of the second reset transistor, and the input terminal of the second reset transistor is electrically connected to the second fixed potential line.

4. The display panel according to claim 3, characterized in that, The conventional display area also includes multiple third fixed potential lines, which extend along the fifth direction and are arranged along the sixth direction, and are electrically connected to at least two first fixed potential lines; the functional display area also includes multiple fourth fixed potential lines, which extend along the seventh direction and are arranged along the eighth direction, and are electrically connected to at least two second fixed potential lines.

5. The display panel according to claim 4, characterized in that, Both the first and second fixed potential lines are metallic conductive structures, while both the third and fourth fixed potential lines are semiconductor conductive structures.

6. The display panel according to claim 4, characterized in that, Within the area enclosed by two adjacent first fixed potential lines and two adjacent third fixed potential lines, the number of first pixel circuits is n1; within the area enclosed by two adjacent second fixed potential lines and two adjacent fourth fixed potential lines, the number of second pixel circuits is n2; n1 and n2 are both positive integers greater than or equal to 2 and n2 > n1.

7. The display panel according to claim 6, characterized in that, A third pixel circuit group s1 is provided between two adjacent third fixed potential lines, the third pixel circuit group including a plurality of first pixel circuits arranged along the fifth direction; a fourth pixel circuit group s2 is provided between two adjacent fourth fixed potential lines, the fourth pixel circuit group including a plurality of second pixel circuits arranged along the seventh direction; s1 and s2 are both positive integers greater than or equal to 1 and s2 > s1.

8. The display panel according to claim 6, characterized in that, A third pixel circuit group s1 is provided between two adjacent third fixed potential lines. The third pixel circuit group includes a plurality of first pixel circuits arranged along the fifth direction. A fourth pixel circuit group s2 is provided between two adjacent fourth fixed potential lines. The fourth pixel circuit group includes a plurality of second pixel circuits arranged along the seventh direction. s1 and s2 are both positive integers greater than or equal to 1 and s2 = s1.

9. The display panel according to claim 7 or 8, characterized in that, s1＝1。 10. The display panel according to claim 1, characterized in that, The conventional display area further includes multiple first light-emitting diodes (LEDs), and the first pixel circuit is electrically connected to at least one of the first LEDs. The first pixel circuit includes a first driving transistor and a first power supply voltage transistor, and the output terminal of the first power supply voltage transistor is electrically connected to the first driving transistor. The functional display area further includes multiple second LEDs, and the second pixel circuit is electrically connected to at least one of the second LEDs. The second pixel circuit includes a second driving transistor and a second power supply voltage transistor, and the output terminal of the second power supply voltage transistor is electrically connected to the second driving transistor. The first fixed potential line is electrically connected to the input terminal of the first power supply voltage transistor or to the cathode of the first LED; the second fixed potential line is electrically connected to the input terminal of the second power supply voltage transistor or to the cathode of the second LED.

11. The display panel according to claim 3 or 10, characterized in that, The density of the first pixel circuit in the conventional display area is greater than the density of the second pixel circuit in the functional display area; the second pixel circuit is evenly distributed in the functional display area.

12. The display panel according to claim 3 or 10, characterized in that, The density of the first pixel circuit in the conventional display area is greater than the density of the second pixel circuit in the functional display area; in the functional display area, at least two second pixel circuits constitute a pixel circuit cluster, and the distance between adjacent second pixel circuits in the pixel circuit cluster is less than the distance between adjacent pixel circuit clusters; wherein, the at least two second pixel circuits in the same pixel circuit cluster are electrically connected to the same second fixed potential line.

13. The display panel according to claim 3 or 10, characterized in that, The functional display area includes a light-transmitting display area and a transition display area, with the transition display area located between the functional display area and the light-transmitting display area. The second pixel circuit is disposed in the transition display area, and both the light-transmitting display area and the transition display area are provided with the second light-emitting diode. The density of the second pixel circuit located in the transition display area is greater than the density of the first pixel circuit located in the conventional display area, and the distance between adjacent first fixed potential lines is equal to the distance between adjacent second fixed potential lines.

14. The display panel according to claim 13, characterized in that, Along the thickness direction of the display panel, the second fixed potential line does not overlap with the light-transmitting display area.

15. A display device, characterized in that, It includes a display panel and optical functional elements as described in any one of claims 1-14, wherein the optical functional elements are disposed in the display device at a position corresponding to the functional display area.

16. The display device according to claim 15, characterized in that, The optical functional element is at least one of an optical fingerprint sensor, an iris recognition sensor, a camera, and a flashlight.

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