Semiconductor product with edge integrity detection structure

Abstract

Embodiments of the present application relate to semiconductor products with edge integrity detection structures. A semiconductor product includes a semiconductor chip, an edge integrity detection structure extending along at least a portion of an edge of the semiconductor chip, and evaluation circuitry formed in and / or on the semiconductor chip, electrically connected with the edge integrity detection structure and configured to evaluate an electrical characteristic of the edge integrity detection structure to provide an evaluation signal indicative of a detected edge integrity status of the edge.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor products. Background Technology

[0002] Delamination or fracture at the die edge can lead to reliability issues and yield losses. It can occur during wafer dicing and is exacerbated by the introduction of ICs with low-k dielectrics in 65nm and above technology nodes. The use of low-k dielectrics reduces interconnect coupling capacitance and also reduces mechanical strength and adhesion. Delamination and fracture become even more severe when laser grooving is used in the dicing process, where increased thermal damage to the die edges can be achieved at the expense of reduced edge peeling. For example, cutting a wafer at high temperatures using a laser can cause metal oxidation and the formation of an enlarged metal oxide layer. Metal oxidation can increase the volume of the metal layer, for example, at the edge of the die. This enlarged metal oxide layer loses strength and can peel or fracture. Cracks can further penetrate the chip and cause device failure. Summary of the Invention

[0003] On one hand, a semiconductor product is described. The semiconductor product includes: a semiconductor chip; an edge integrity detection structure; and a circuit system formed in and / or on the semiconductor chip. The edge integrity detection structure extends along at least a portion of the edge of the semiconductor chip. The circuit system formed in and / or on the semiconductor chip is electrically connected to the edge integrity detection structure and configured to evaluate the electrical characteristics of the edge integrity detection structure to provide a signal indicating the integrity state of the edge.

[0004] On the other hand, a semiconductor product is described. The semiconductor product includes: a semiconductor chip; an integrated circuit formed in and / or on the semiconductor chip; and an edge structure. The edge structure extends at least a portion of the edge of the semiconductor chip and includes a plurality of parallel planar conductive layer structures. The plurality of parallel planar conductive layer structures are substantially aligned with each other in a plan view and are interconnected with each other by conductive vertical connecting elements.

[0005] In another aspect, a semiconductor product is described. The semiconductor product includes: a semiconductor chip; an integrated circuit formed in and / or on the semiconductor chip; and an edge integrity detection structure. The edge integrity detection structure extends at least partially along the edge of the semiconductor chip and includes a plurality of electrically connected planar conductive layer structures, wherein each of at least three of the conductive layer structures at least partially overlaps with each of the other three conductive layer structures in a planar view. Attached Figure Description

[0006] The various objectives, aspects, features, and advantages of this disclosure will become more apparent and better understood through a detailed description taken in conjunction with the accompanying drawings. In the drawings, similar reference numerals generally indicate identical, functionally similar, and / or structurally similar elements.

[0007] Figure 1 This illustrates a plan view of a semiconductor product according to some embodiments;

[0008] Figure 2 A schematic cross-sectional view illustrating a portion of a semiconductor product according to some embodiments;

[0009] Figure 3 This illustrates a cross-sectional view of a semiconductor product edge integrity detection structure according to some embodiments.

[0010] Figure 4 This illustrates a cross-sectional view of a semiconductor product edge integrity detection structure according to some embodiments.

[0011] Figure 5 This illustrates a plan view and a cross-sectional view of an edge integrity detection structure embedded in a sealing ring of a semiconductor product according to some embodiments.

[0012] Figure 6 This diagram illustrates an electrical schematic of an evaluation circuit system for a semiconductor product according to some embodiments.

[0013] Figure 7 This diagram illustrates an electrical schematic of an evaluation circuit system for a semiconductor product according to some embodiments.

[0014] Figure 8 A schematic plan view illustrating a portion of a semiconductor product according to some embodiments;

[0015] Figure 9 A schematic plan view illustrating a portion of a semiconductor product according to some embodiments;

[0016] Figure 10 This diagram illustrates an evaluation circuit system for a semiconductor product according to some embodiments.

[0017] Figure 11 This diagram illustrates an electrical schematic of an evaluation circuit system for a semiconductor product according to some embodiments.

[0018] Details of various embodiments of the method and system are set forth in the accompanying drawings and the following description. Detailed Implementation

[0019] The following is a detailed description of various concepts and embodiments related to techniques, methods, devices, and systems for edge integrity detection. The various concepts introduced above and discussed in detail below can be implemented in any of a number of ways, as the described concepts are not limited to any particular implementation. Examples of specific embodiments and applications are provided primarily for illustrative purposes.

[0020] An integrated circuit with an edge-protection structure is provided. The edge-protection structure can be positioned around the edge of the integrated circuit. The edge-protection structure may comprise multiple V-shaped structures interconnected using multiple ultra-thick paths. The integrated circuit may include pads coupled to the edge-protection structure. These pads can be used to measure the resistance of the edge-protection structure.

[0021] In some embodiments, a semiconductor product is provided, comprising: a semiconductor chip or substrate; an integrated circuit (IC) formed in and / or on the semiconductor chip; an edge integrity detection structure extending at least a portion along an edge of the semiconductor chip; and an evaluation circuit system formed in and / or on the semiconductor chip. The circuit system is electrically connected to the edge integrity detection structure and configured to evaluate the electrical characteristics of the edge integrity detection structure to provide an evaluation signal indicating the detected edge integrity state. In some embodiments, the use of the edge integrity detection structure reduces the time required for monitoring device delamination and other defects, for example, through visual inspection and / or time-consuming and inefficient manual probing.

[0022] In some embodiments, a semiconductor product includes: a semiconductor chip; an integrated circuit formed in and / or on the semiconductor chip; and an edge integrity detection structure extending at least a portion of the edge of the semiconductor chip. The edge integrity detection structure includes electrically connected planar conductive layer structures. Each of at least three (e.g., each of at least five) conductive layer structures at least partially overlaps (e.g., substantially completely overlaps) each of the other three (e.g., at least five) conductive layer structures in a planar view.

[0023] In yet another embodiment, a semiconductor product includes: a semiconductor chip; an integrated circuit formed in and / or on the semiconductor chip; and an edge integrity detection structure extending at least a portion of the edge of the semiconductor chip. The edge integrity detection structure includes parallel planar conductive layer structures that are substantially aligned with each other in a plan view and connected to each other by conductive vertical connecting elements.

[0024] In the context of this application, "semiconductor product" may, for example, include a physical body, component, or member, or even device, made of two or more different elements, partially or entirely manufactured using semiconductor technology. For example, a semiconductor product may include one or more semiconductor chips, specifically, bare dies or molded dies. Furthermore, a system-on-a-chip (SoC), module, chipset, or other electronic device comprising one or more semiconductor chips may be identified as a semiconductor product. Semiconductor products may be manufactured, for example, using group IV semiconductor technology (e.g., silicon technology) or group III-V semiconductor technology (e.g., gallium arsenide technology).

[0025] In the context of this application, the term "semiconductor chip" may refer to a substrate that includes, for example, a semiconductor material (e.g., silicon) and contains an integrated electrical circuit system. For example, a semiconductor chip may be a bare die or an encapsulated die. A semiconductor chip can be manufactured by dicing a wafer (initially comprising multiple interconnected semiconductor chips) into individual semiconductor chips. Dicing a semiconductor chip from a wafer compound can be done, for example, by sawing, dicing, or laser cutting.

[0026] In the context of this application, the term "integrated circuit" or IC may refer to, for example, a plurality of interconnected integrated circuit elements manufactured at least partially by semiconductor processing technology. For example, such integrated circuit elements may include at least one of transistors, diodes, resistors, conductive traces, contacts, circuits, capacitors, inductors, etc. The integrated circuit elements forming an integrated circuit may be monolithically integrated onto a semiconductor chip. Therefore, an integrated circuit can be a monolithic integrated circuit.

[0027] In the context of this application, the term "edge integrity detection structure" can refer to, for example, a conductive physical structure positioned and / or configured to detect information indicating whether the edges along or around a semiconductor chip are intact (e.g., damaged). Specifically, edge integrity can be affected by separating a semiconductor chip from a wafer through cutting or sawing along the edges of each semiconductor chip. For example, the edges of a semiconductor chip can break or delaminate during a single-cutting process. An edge integrity detection structure can be positioned along an edge or a portion thereof to be affected by edge separation processes that cause edge damage. The edge integrity detection structure can be used as a damage probe for detecting edge integrity degradation events.

[0028] In the context of this application, the term "planar conductive layer structure" may refer to, for example, a flat, patterned, or structured metal layer. Each of the layer structures may extend in a horizontal plane. Different layer structures may be positioned in different planes that are parallel to each other. Layer structures may form portions of a common layer stack.

[0029] In the context of this application, the term "conductive layer structures that at least partially overlap each other in a planar view" can refer, for example, to the arrangement of conductive layer structures in relation to a vertical viewing direction to the main surface of a semiconductor chip. The main surface of the semiconductor chip is the top surface when the chip is attached to a packaging substrate, or in some embodiments, the largest surface in a region of the chip. In this viewing direction, the mentioned conductive layer structures may collectively have at least a number of portions that overlap each other in a planar view. In some embodiments, the conductive layer structures may completely overlap to have a common profile in the mentioned vertical viewing direction.

[0030] In the context of this application, the term "each of at least three conductive layer structures at least partially overlaps with each of the other of at least three conductive layer structures in a plan view" can mean, for example, that all at least three conductive layer structures intersect when traversed along a direction corresponding to the vertical direction of the plan view (perpendicular to the plane in which the layer structure extends).

[0031] In the context of this application, the term "conductive layer structures substantially aligned with each other in a plan view" can refer to, for example, the arrangement of conductive layer structures in relation to a vertical viewing direction. In this viewing direction toward the main surface of the semiconductor chip, the mentioned conductive layer structures can substantially completely overlap each other. An anomaly of complete overlap (and specifically, the only anomaly) can be a very small gap between different segments of the respective conductive layer structures. Such a very small gap can be the result of patterning or structuring the respective conductive layer structures. Apart from such a very small gap, all conductive layer structures can have a common profile in which all conductive layer structures can extend substantially continuously. Descriptively speaking, parallel conductive layer structures substantially aligned with each other in a plan view can form a common wall with substantially complete metallic coverage in each conductive layer structure. The conductive layer structure of the edge integrity detection structure can be a parallel metal strip shaped into an open rectangle (see, for example...). Figure 1 ).

[0032] In the context of this application, the term "conductive vertical interconnect element" can refer to, for example, a metallic structure extending perpendicular to a parallel plane conductive layer structure such that each vertical interconnect element is vertically interconnected or bridged in at least two of layer structures extending in different parallel planes. For example, a conductive vertical interconnect element can be a metallic pathway, a metallic support, etc.

[0033] In the context of this application, the term "evaluation circuit system" can refer to, for example, a circuit system configured to evaluate electrical signals of an edge integrity detection structure to determine information about edge integrity. For example, this evaluation circuit system may include hardware elements. For instance, the evaluation circuit system may be hardwired. However, it is also possible that the evaluation circuit system includes software elements (e.g., firmware). The evaluation circuit system may be on-chip, for example, monolithically integrated into a semiconductor chip of a semiconductor product.

[0034] In the context of this application, the term "evaluation signal indicating the detected edge integrity state" can refer to, for example, an electrical signal carrying information about the integrity or incompleteness of an edge of a characterized semiconductor chip. For instance, an edge integrity state can indicate whether the integrity of an edge is confirmed or whether the edge exhibits incompleteness. Therefore, the edge integrity state can be indicated digitally (e.g., by logic values ​​"1" or "0"). It is also possible to distinguish more than two different edge integrity states, such as fully complete, incomplete, limited but still acceptable integrity, and limited but no longer acceptable integrity. Alternatively, the edge integrity state can be indicated by asymptotic values ​​(e.g., analog values). The evaluation signal can be an on-chip signal.

[0035] Generally, some embodiments of the first aspect provide semiconductor products with an edge integrity detection structure having multiple overlapping interconnected planar conductive layer structures. In some embodiments, such interconnected conductive layer structures may be aligned with each other such that they have a common, identical outline in a top view. The conductive layer structures may form an aligned conductive network or frame along the outer edge of the semiconductor chip. The integrity of the edge integrity detection structure may be intentionally compromised when, specifically, the edge of the semiconductor chip is damaged during separation from the semiconductor wafer. For example, electrical connections of components of the edge integrity detection structure may be compromised when phenomena such as breakage or delamination occur at the edge of the semiconductor chip or at the surrounding sealing ring. Subsequently, evaluation of the electrical characteristics of the edge integrity detection structure can allow the derivation of information about the edge integrity status of the chip edge. Advantageously, constructing an edge integrity detection structure from three or more interconnected planar conductive layer structures that partially or substantially completely overlap all others in a planar view can create a quasi-continuous conductive wall constituting an extended two-dimensional resistor chain. This structure can be highly sensitive to any kind of damage around the edge of the semiconductor chip. Specifically, an edge integrity detection structure constructed from multiple interconnected planar conductive layer structures that are almost perfectly aligned with each other in a planar view allows for the formation of a quasi-continuous mesh-type edge damage probe that is intentionally designed to be damaged when the edges surrounding a semiconductor chip are damaged. The quasi-continuous conductive network of interconnected layers is highly sensitive to virtually any type of edge damage, enabling reliable prevention of erroneous outputs that incorrectly confirm edge integrity.

[0036] Furthermore, some embodiments of the second aspect provide a semiconductor chip having an edge integrity detection structure (e.g., of the type mentioned above or another type) extending along the outer edge of an integrated circuit on the semiconductor chip and having an on-chip evaluation circuitry system. In some embodiments, the evaluation circuitry system may be formed as part of the same semiconductor chip that also includes the edge integrity detection structure. Therefore, an evaluation signal indicating a detected edge integrity state—characterizing the integrity or incompleteness of the semiconductor chip edge—can be created by and on the semiconductor chip itself. In some embodiments, the electrical path is kept short, thereby ensuring high quality of the evaluation signal. Furthermore, providing an on-chip evaluation circuitry system electrically connected to the edge integrity detection structure allows for the generation of an on-chip evaluation signal indicating the detected edge integrity state. This evaluation signal can be read out during chip testing. In some embodiments, a large pad may be provided to further process the evaluation signal away from the chip. In some embodiments, processing the evaluation signal away from the chip allows for a more compact semiconductor chip.

[0037] Some embodiments provide an easily fabricated and robust chip edge damage monitor and a simple testing method. Some embodiments of the systems and methods discussed herein allow for the low-efficiency and high-reliability identification of chip edge damage (e.g., sealing ring damage) before the chip is transferred to an application.

[0038] In some embodiments, at least 80%, and preferably at least 90%, of the main surface of each of the conductive layer structures is aligned with at least 80% (e.g., at least 90%) of the main surface of each of the other conductive layer structures. Thus, the majority of the metal regions of the overlapping conductive layer structures can be aligned. Therefore, a substantially homogeneous metal network consisting of vertically spaced parallel patterned metal layers and interconnecting vertical connection elements in between can be created. In some embodiments, this has the advantage that substantially any edge damage event can be reliably detected by the edge integrity detection structure.

[0039] In some embodiments, the semiconductor product includes conductive vertical interconnect elements, such as metal vias, that connect conductive layer structures to each other. The conductive vertical interconnect elements may be grouped into several groups, wherein the conductive vertical interconnect elements in a respective group may be aligned with each other in a plan view. Thus, the conductive layer structures are aligned, and in some embodiments, the vertical interconnect elements are aligned. For example, an aligned stacked via sequence may be formed.

[0040] In some embodiments, the edge integrity detection structure is configured such that at least a portion of the conductive layer structures are disconnected from each other in the event of damage at the edge of the semiconductor chip. Alternatively, the edge integrity detection structure may be configured such that at least a portion of the conductive layer structures are disconnected from the conductive vertical interconnects in the event of delamination at the edge of the semiconductor chip. For example, damage at the edge of the semiconductor chip may occur after dicing. Damage may include phenomena such as breakage and peeling. Damage at the chip edge can lead to an expected interruption of the interconnections between the conductive layer structures of the edge integrity detection structure. Another artifact that may occur at the chip edge during processing may be delamination, i.e., unintentional separation of different layers. This phenomenon can also be detected by changes in the electrical properties of the edge integrity detection structure, as delamination can disconnect the corresponding layer structure from the assigned vertical interconnects.

[0041] In some embodiments, the conductive layer structure forms a tortuous structure with the conductive vertical connection element. Some embodiments, for example, in... Figure 3 and Figure 4 As shown in the image. The tortuous structure allows for the extension of resistor paths or chains while consuming very little space. Therefore, the tortuous structure combines high detection sensitivity with a compact design.

[0042] In some embodiments, the conductive layer structure and the conductive vertical connecting element further form another zigzag structure. Advantageously, the zigzag structure and the other zigzag structure can be electrically connected to each other (see, for example...). Figure 3 Therefore, the conductive path formed by the edge integrity detection structure can be further extended to further improve detection accuracy while maintaining a compact design.

[0043] In some embodiments, the tortuous structure intersects with another tortuous structure (see also, for example...). Figure 3 This can further reduce the space consumption of the edge integrity detection structure. Furthermore, the staggered, tortuous structure reduces the dead volume in which edge damage events might not be detected.

[0044] In some embodiments, the semiconductor product includes another bend structure arranged side-by-side with and alongside the bend structure. This embodiment is exemplified in... Figure 4 As shown in the diagram, several convoluted structures can be arranged close together along the edge of a semiconductor chip. This expands the area within the semiconductor chip where edge damage would result in a detectable signal.

[0045] In some embodiments, the edge integrity detection structure surrounds at least 90% of the perimeter of the integrated circuit. In some embodiments, the edge integrity detection structure may be substantially annular with open ends defining two terminals. This two-terminal configuration may be advantageous for resistance-based detection of edge integrity information. In some embodiments, the nearly closed annular geometry of the edge integrity detection structure allows for spatial expansion of detection sensitivity substantially around the entire contour of the semiconductor chip.

[0046] In some embodiments, the semiconductor product includes a sealing ring that partially or completely surrounds the integrated circuit. For example, the sealing ring may be a continuous loop. This sealing ring may be, for example, an annular closed metal structure extending around the entire circumference of the semiconductor chip to protect the chip from peeling and breakage. The sealing ring may form part of the semiconductor chip or may be formed separately around the semiconductor chip. While the sealing ring protects the semiconductor chip from damage along its edges, edge integrity detection structures can detect edge damage events.

[0047] In some embodiments, the edge integrity detection structure is at least partially integrated into the sealing ring. The edge integrity detection structure may be positioned inside the sealing ring. This allows for a compact chip design. Furthermore, specifically, this positioning of the edge integrity detection structure can provide meaningful detection results at locations where edge damage is likely to occur.

[0048] In some embodiments, at least a portion of the edge integrity detection structure is disposed inside the sealing ring. In this configuration, the edge integrity detection structure may be positioned between the sealing ring and the integrated circuit. In yet another embodiment, at least a portion of the edge integrity detection structure is disposed outside the sealing ring. In some embodiments, the sealing ring may be positioned between the edge integrity detection structure and the integrated circuit.

[0049] In some embodiments, the edge integrity detection structure is configured as a two-terminal resistor chain. The first and second open ends of the edge integrity detection structure are electrically coupled to each other via the resistance created by the conductive layer structure and vertical connection elements of the edge integrity detection structure when intact. However, when the conductive edge integrity detection structure is incomplete due to damage to the semiconductor chip edge, the conductive connection along the conductive layer structure and vertical connection elements is interrupted, causing the first and second open ends to be electrically decoupled from each other. When configured as a two-terminal resistor chain, this resistance difference between the intact and damaged states of the edge integrity detection structure can be electrically detected. In some embodiments, the two-terminal resistor chain is connected between a lower supply voltage terminal (e.g., a ground terminal) and a sensing terminal.

[0050] In some embodiments, the evaluation circuitry is electrically connected to or can be connected to the edge integrity detection structure and is configured to evaluate the resistance of the edge integrity detection structure to provide an evaluation signal indicating the detected edge integrity status. The evaluation measures the ohmic resistance of the edge integrity detection structure, and the result of this measurement can be used to derive information about the integrity status of the semiconductor chip or the sealing ring surrounding the semiconductor chip. For example, a measured low ohmic resistance may indicate that the edge integrity detection structure and therefore the edge of the semiconductor chip is intact. In contrast, a measured high ohmic resistance may indicate that the edge integrity detection structure is interrupted and therefore the edge of the semiconductor chip is damaged.

[0051] In some embodiments, the evaluation circuitry is monolithically integrated into a semiconductor chip. Therefore, the evaluation circuitry can be created from integrated circuit elements formed in and / or on the semiconductor chip. Specifically, the evaluation circuitry can form a portion of the integrated circuit on the semiconductor chip. This can result in small space consumption and thereby facilitate the miniaturization of the semiconductor chip.

[0052] In some embodiments, the evaluation circuitry is electrically connected to an edge integrity detection structure via a connection structure buried within a semiconductor chip and extending below the edge integrity detection structure. In some embodiments, the semiconductor product may include a sealing ring surrounding an integrated circuit in which at least a portion of the edge integrity detection structure is integrated. In some embodiments, the semiconductor product may include a buried connection structure extending within the semiconductor chip below the sealing ring and below the edge integrity detection structure, electrically connecting the edge integrity detection structure and the evaluation circuitry. The edge integrity detection structure may be electrically connected to the evaluation circuitry via conductive wires that extend deeper into the semiconductor substrate of the semiconductor chip than the sealing ring, which is at least partially located between the edge integrity detection structure and the evaluation circuitry. Electrical signals are transmitted from the edge integrity detection structure to the evaluation circuitry via the connection wires, which in some embodiments are deeply buried within the semiconductor substrate. This measurement provides a short signal path. Simultaneously, any unwanted interactions between the transmitted electrical signals and the sealing ring can be reliably prevented. In some embodiments, the connection structure may be implemented as a deep-well connection.

[0053] In some embodiments, the evaluation circuitry is configured to evaluate the resistance of the edge integrity detection structure as a basis for evaluating the signal. In some embodiments, the evaluation circuitry may be configured to evaluate the resistance by detecting the current flowing through the edge integrity detection structure. In some embodiments, zero current may indicate a detected defective edge integrity state, and non-zero current may indicate a detected intact edge integrity state.

[0054] In some embodiments, the evaluation circuitry forms a portion of the integrated circuit and / or is electrically connected to the integrated circuit. Subsequently, the external evaluation circuitry may be optional.

[0055] In some embodiments, the evaluation circuitry is disposed at an edge of the integrated circuit that is at least partially adjacent to the sealing ring, thereby keeping the electrical path between the edge integrity detection structure and the evaluation circuitry short. In some embodiments, the integrated circuit allows for the provision of semiconductor product functionality in a central region of a semiconductor chip that may not otherwise have an evaluation circuitry.

[0056] In some embodiments, the evaluation circuitry is configured to provide a logic evaluation signal indicating the detected edge integrity state. The logic evaluation signal may have at least two (preferably exactly two) different states for indicating the detected edge integrity state. For example, a logic value "0" may indicate that the semiconductor chip edge is intact, while a logic value "1" may indicate that the semiconductor chip edge is damaged. For instance, the logic evaluation signal may be a digital signal. Digital outputs are less prone to distortion and can therefore be highly reliable.

[0057] In some embodiments, the evaluation circuitry includes an analog block for detecting information indicating the resistance of the edge integrity detection structure. In some embodiments, the evaluation circuitry may be configured to provide a digital evaluation signal indicating the detected edge integrity state. The evaluation circuitry may have analog inputs and digital outputs. This improves the reliability of the output signal in indicating the integrity state of the chip edge.

[0058] In some embodiments, the digital evaluation signal is a single bit. Advantageously, a single bit can allow the edge integrity state to be indicated as "intact" (corresponding to a first logic value of the bit signal, such as "0") or "damaged" (corresponding to a second logic value of the bit signal, such as "1"). This single bit signal indicating the chip edge integrity state can be perfectly integrated into chip testing (e.g., self-test). Therefore, the evaluation circuitry system can be configured to provide the evaluation signal within the framework of a semiconductor product testing procedure.

[0059] Advantageously, providing a pad at the semiconductor product to probe evaluation signals via external probes may be unnecessary. This can have a positive impact on the compactness of the semiconductor chip. In some embodiments, the semiconductor product includes an electrical output interface (e.g., a pad) configured to provide evaluation signals to external automated test equipment.

[0060] In some embodiments, the evaluation circuitry includes: a reference resistor structure having a higher resistance value than the edge integrity detection structure in its intact state; and a comparator circuitry configured to compare a signal indicating the resistance value of the edge integrity detection structure with a signal indicating the resistance value of the reference resistor structure, such that an evaluation signal is provided as the output of the comparator circuitry. In some embodiments, the comparator architecture allows for efficient and robust provision of a reliable evaluation signal. In some embodiments, the evaluation circuitry includes a bias circuitry to electrically bias the edge integrity detection structure and the reference resistor structure. In some embodiments, the bias circuitry can apply a voltage to the edge integrity detection structure and the reference resistor structure.

[0061] Low-k dielectric materials are susceptible to breakage and spalling during wafer dicing at the die edges. Such artifacts at the edges can potentially damage the resulting semiconductor chip. Affected chips may pass final testing, but despite this, failures may occur later in use due to broken metal connections or the like.

[0062] Significant effort has been invested in detecting and screening damaged components before they are actually used to achieve specific functions. However, conventional solutions may require mandatory chip pads and / or significantly additional chip area for the detection structure and associated protective structures.

[0063] To overcome the aforementioned and / or other conventional drawbacks, some embodiments may place the edge integrity detection structure within a sealing ring structure, thus eliminating the need for active chip area for edge integrity detection. An evaluation circuitry system, which may be embodied as a core logic block, can convert the detected signal, indicating the resistance value of the edge integrity detection structure, into a logic level that can be incorporated into the chip's built-in tests or other self-test procedures. Some embodiments may provide an edge integrity detection structure configured as a sealing ring monitor, wherein an evaluation signal indicating the edge integrity status of the chip can be provided by an on-chip evaluation circuitry system based on the detected signal.

[0064] In some embodiments, an edge integrity detection structure (e.g., a continuous metal path chain) is placed within a sealing ring structure to detect any breaks and delamination. Breaks can result in broken metal lines, while delamination can result in broken path connections. Therefore, different types of damage at the chip edge can be detected based on the resulting breakage of the metal path chain. In some embodiments, an undamaged or intact metal path chain can indicate the absence of die edge damage attributable to wafer dicing. A broken metal path chain can result in a higher resistance compared to an intact metal path chain. The latter can be predicted or calculated from the geometry (specifically, the length) of the resistor chain. An analog circuit block evaluating the circuit system can convert the detected resistance change into a first logic level (e.g., a logic value "1") in the case of a broken resistor chain and into another second logic level (e.g., a logic value "0") in the case of an intact resistor chain.

[0065] According to some embodiments, the edge integrity detection structure can be electrically connected to the evaluation circuit system via conductive chain detection wires embedded in the semiconductor substrate of a semiconductor chip. These conductive chain detection wires may extend, for example, below a sealing ring. This conductive chain detection wire can advantageously be embodied as NWELL and / or DeepNWell. This architecture allows the edge integrity detection structure to be electrically coupled to the evaluation circuit system without damaging the sealing ring metal when the resistor chain is inserted into the sealing ring. This buried connection maintains the integrity of the sealing ring metal layer.

[0066] According to some embodiments, the metal path detection chain layout can be configured with parallel, aligned, and substantially continuous metal layers to ensure both high die edge breakage detection rates and high delamination detection rates. In some embodiments, this design (examples are shown in...) Figure 3 and Figure 4 (As shown in the image) It can be guaranteed that the vast majority of fault events at the chip edge can actually be identified by the edge integrity detection structure.

[0067] An exemplary application of the exemplary embodiments is, for example, a silicon chip product that specifically uses a low-k dielectric or the like in a back-end process.

[0068] In some embodiments, it is possible to widen the sealing ring by monitoring the width of the metal pathway chain and the associated spacing through edge damage. This may allow for compliance with potential sealing ring design rules.

[0069] In some embodiments, the edge damage monitoring chain may be arranged close to the sealing ring inside the chip area.

[0070] Many different embodiments of an evaluation circuit system can be used to convert detected chain resistance into a logic output signal. One corresponding embodiment of the evaluation circuit system may include: a bias circuit for biasing the chain resistor of the edge integrity detection structure; and a dummy resistor (e.g., implemented as a polysilicon region in a semiconductor chip) having a higher resistance than the metal-path chain resistance, specifically exceeding normal process variations. A comparator circuit can then be used to compare the voltages across the two resistors. If the edge damage detection chain is broken, its resistance can be much higher than that of the dummy resistor, allowing the comparator output to be switched to indicate an edge-damaged chip.

[0071] Advantageously, exemplary embodiments may provide a buried connection structure to electrically connect the edge integrity detection structure to the on-chip evaluation circuitry. For example, this buried connection structure may be embodied as a buried trap connection to a detection metal path chain. Advantageously, this maintains the integrity of the sealing ring.

[0072] According to some embodiments, on-chip analog circuitry can be provided to convert chain resistance detection into core logic signals, making it usable in scan testing of the semiconductor chip (e.g., built-in self-test (BIST)) or any other self-test. Advantageously, dedicated input / output pads and associated protection circuitry systems can be provided.

[0073] In some embodiments, the edge damage detection chain may be part of a sealing ring. This has the advantage of having a metal via chain that requires no additional chip area. The corresponding detection chain for this edge integrity detection structure can be manufactured with minimal workload.

[0074] In some embodiments, it may be advantageous to configure the metal and pathway connections and their locations of the edge integrity detection structure to achieve high coverage of potential fracture damage. This can be achieved, for example, by... Figure 3 or Figure 4This can be achieved through configuration. For example, this can be achieved by configuring an edge integrity detection structure with nearly 100% die edge sidewall coverage. The corresponding layout of the detection chain can also allow for detection layering, which can lead to broken pathways and thus a significant increase in the resistance of the edge integrity detection structure detectable by the evaluation circuitry. In some embodiments, the evaluation circuitry includes an analog block for detecting chain resistance. In some embodiments, the evaluation circuitry is configured to output a one-bit digital signal to the main chip. In some embodiments, this fault-robust one-bit digital signal can indicate whether the semiconductor chip edge is intact. The core logic implementation can be tested on an ATE (Automatic Test Equipment) or on another tester.

[0075] Figure 1 A schematic plan view illustrating a semiconductor product 100 according to an exemplary embodiment. Figure 2 A cross-sectional view illustrating the layout implementation of this semiconductor product 100. Figure 3 Explanation as follows Figure 1 and Figure 2 The image shows a cross-sectional view of the edge integrity detection structure 106 of the semiconductor product 100. Figure 4 Explanation for example Figure 1 and Figure 2 A cross-sectional view of another edge integrity detection structure 106 of one of the semiconductor products 100. Figure 5 The illustration describes the embedding of the exemplary embodiment in an implementable manner. Figure 2 The plan view and cross-sectional view are shown of the edge integrity detection structure 106 in the sealing ring 118 of the semiconductor product 100. The sealing ring 118 may be a metal passage ring surrounding the integrated circuit 104 of the semiconductor product 100.

[0076] The following text is for reference only. Figures 1 to 5 Describe various aspects of the exemplary embodiments.

[0077] refer to Figure 1Semiconductor product 100 may include semiconductor chip 102. Semiconductor chip 102 may include a semiconductor substrate, such as a silicon substrate. Furthermore, integrated circuit 104 (illustrated only) may be formed in and / or on semiconductor chip 102. Specifically, integrated circuit 104 may be monolithically integrated into semiconductor chip 102. Integrated circuit 104 may include at least one of several integrated circuit elements, such as transistors, diodes, resistors, conductive traces, contacts, circuits, capacitors, or inductors. Advantageously, integrated circuit 104 may be formed in a central portion of semiconductor chip 102 (e.g., away from the edge). Integrated circuit 104 can provide or facilitate functional applications of semiconductor product 100. For example, semiconductor product 100 may be configured to provide Wi-Fi applications, Bluetooth applications, video applications, audio applications, mobile phone applications, and / or automotive applications. Many other and / or different functional applications are possible.

[0078] Reference numeral 140 indicates the boundary of semiconductor chip 102. Reference numeral 142 shows the placement and routing boundary (prBoundary). A sealing ring 118 of semiconductor product 100 surrounds semiconductor chip 102 and its integrated circuit 104. The sealing ring 118 may be a metal structure protecting semiconductor chip 102 from peeling and cracking. The sealing ring 118 may form part of semiconductor chip 102 or may be arranged to surround semiconductor chip 102.

[0079] An edge integrity detection structure 106 is provided to extend along a major portion of the edge of the semiconductor chip 102. In some embodiments, the edge integrity detection structure 106 may extend along almost the entire perimeter of the semiconductor chip 102 (for more than 80 percent (e.g., more than 90 percent or 95 percent) of the perimeter). In some embodiments, the edge integrity detection structure 106 extends along the entire perimeter except for a short path between the first terminal 144 and the second terminal 146. The edge integrity detection structure 106 allows the detection of the integrity of the edge of the semiconductor chip 102 or the area around the semiconductor chip 102 using the electrical detection of the signal between the first terminal 144 and the second terminal 146, as will be described in more detail below. In some embodiments (e.g., for certain modern semiconductor chips), the actual gap between the two terminals 144 and 146 is approximately one-tenth of a micrometer or less. Figure 1 The gaps seen above are not proportional.

[0080] In some embodiments, the edge integrity detection structure 106 is integrated into the sealing ring 118. (See reference) Figure 2A first portion 147 of the sealing ring 118 is located at an external position of the edge integrity detection structure 106, while a second portion 148 of the sealing ring 118 is located at an internal position of the edge integrity detection structure 106. By integrating the edge integrity detection structure 106 into the sealing ring 118, a compact configuration of the semiconductor product 100 is achieved. The first portion 147 of the sealing ring 118 is the outer sealing ring. The gap used to create the edge integrity detection structure 106 is between the first portion 147 and the structure 106 and between the second portion 148. The second portion 148 is the inner sealing ring. The sealing ring buffer region is a buffer or transition region 164 disposed on the inner side of the second portion 148.

[0081] like Figure 2 Showcased in China and in Figure 3 and Figure 4 As shown in more detail below, in some embodiments, the edge integrity detection structure 106 includes a plurality of electrically connected planar conductive layer structures 108. In some embodiments, conductive vertical connection elements 110 electrically connect adjacent conductive layer structures 108. In some embodiments, the vertical connection elements 110 are conductive (e.g., metallic (e.g., copper, copper alloy, aluminum, aluminum alloy, or other metals)) pathways. Figure 3 and Figure 4 As seen, more than 10 horizontally extended conductive layer structures 108 are provided, all of which almost completely overlap each other in the plan view. The plan view corresponds to... Figure 2 , Figure 3 and Figure 4 The observation direction is 150. For example... Figure 3 and Figure 4 As shown, the conductive layer structures 108, which can be metal layers, are aligned with each other in the viewing direction 150. The viewing direction 150 corresponds to... Figure 1 The direction of observation on the paper. (Reference) Figure 3 and Figure 4 More than 90% of the main surface of each of the conductive layer structures 108 is aligned with more than 90% of the main surface of each of the other conductive layer structures 108. The only slight deviation from the perfect alignment of the stacked conductive layer structures 108 occurs at a specific vertical level in the region of the gap 152 between different segments of the respective conductive layer structures 108. In some embodiments, the conductive layer structures 108 are substantially aligned with each other over the entire extension, as... Figure 3 and 4 As shown in the diagram. Each of the conductive layer structures 108 can be shaped into an open rectangle (see [reference]). Figure 1The planar metal strip, wherein the layer structures 108 can be stacked to align with each other. The strong overlap or alignment of the conductive layer structures 108 at different vertical levels of the edge integrity detection structure 106 has the advantage that, by almost completely covering the two-dimensional region defining the edge integrity detection structure 106 by the planar parallel conductive layer structures 108 and the vertical connecting elements 110, the provided resistor chain is sensitive to potential damage along almost the entire edge of the semiconductor chip 102. If damage occurs at the corresponding location on the edge, the continuous resistor chain formed by the layer structures 108 and the vertical connecting elements 110 is interrupted, and a strong increase in the resistance of the edge integrity detection structure 106 can be detected by the evaluation circuit 120 described below. In some embodiments, according to Figure 3 and Figure 4 The dense metal mesh wall arrangement of the layer structure 108 and the vertical connecting element 110 ensures that there are no blind spots inside the edge integrity detection structure 106. Damage to the edge of the semiconductor chip in the blind spot will not cause a detectable change in resistance, thereby ensuring high reliability and accuracy of edge integrity detection.

[0082] refer to Figure 3 and Figure 4 The vertical connecting elements 110 can be grouped into several groups, wherein the conductive vertical connecting elements 110 of the corresponding groups are aligned with each other in a plan view corresponding to the viewing direction 150. For example, Figure 3 Vertical connecting elements 110 of a first group 153 aligned along the viewing direction 150 corresponding to the plan view are shown. Similarly, vertical connecting elements 110 of a second group 154 ​​aligned with each other along the viewing direction 150 corresponding to the plan view are also shown. (Referring to...) Figure 3 and Figure 4 The vertical connecting element 110 can be arranged as a conductive vertical bridge to connect corresponding segments of two vertically adjacent layer structures 108. Therefore, in some embodiments, a tortuous resistor chain is formed between the interconnecting layer structure 108 and the vertical connecting element 110. For this purpose, each of the vertical connecting elements 110 can be positioned at a corresponding lateral end of an assigned segment of the corresponding layer structure 108.

[0083] refer to Figure 3 and Figure 4 The conductive layer structure 108 and the conductive vertical connecting element 110 form a zigzag structure 112 and another zigzag structure 114. As shown, the zigzag structure 112 and the other zigzag structure 114 are electrically connected to each other at the bottom side. In addition, the zigzag structure 112 and the other zigzag structure 114 are interleaved (as schematically indicated by reference numeral 190) to further reduce the size of the non-metallic region inside the edge integrity detection resistor chain.

[0084] like Figure 4As shown in the diagram, it is also possible that the edge integrity detection structure 106 includes additional zigzag structures 116, 117 arranged side by side with the zigzag structure 112 and another zigzag structure 114 and interconnected and intersected in a corresponding manner. Figure 3 and Figure 4 The structure shown can be spatially expanded to enclose almost the entire semiconductor chip or product 100, such as Figure 1 It is displayed in the middle.

[0085] Figure 3 and Figure 4 Each illustrated unit is a component of the edge integrity detection structure 106 configured as an edge detection monitoring ring. The illustrated configuration has the advantage of near 100% coverage for each metal layer or edge integrity detection structure 106. The vertical connecting element 110, illustrated as a vertical rod, can serve as a conductive path between the horizontal metal layer structures 108. According to... Figure 3 and Figure 4 Each layer structure 108 is almost entirely covered along the length of the described area using a metal sensor or probe material. Due to this complete coverage with metal, there is a high probability of detecting any kind of damage, regardless of where it occurs.

[0086] Because they are interconnected, the layer structure 108 and the vertical connecting element 110 can be connected between the first terminal 144 and the second terminal 146. Figure 1 A continuous resistor chain is formed between the conductive layer structures 108 and the conductive vertical connection element 110. Subsequently, the edge integrity detection structure 106 can be configured such that the conductive layer structure 108 and the conductive vertical connection element 110 can be disconnected from each other in the event of damage and / or delamination at the edge of the semiconductor chip 102. In the event of damage, the resistor chain can be interrupted at the damaged layer structure 108. In the event of delamination, the interconnection of two adjacent layer structures 108 via the intermediate vertical connection element 110 can be interrupted. Such events can cause an increase in resistance between terminals 144, 146, which can be measured by the evaluation circuit 120. The evaluation circuit 120 can also be designated as a sensor circuit.

[0087] As discussed above, the edge integrity detection structure 106 can be configured to connect to a two-terminal resistor chain in the evaluation circuit 120. The layer structure 108 and the vertical connection element 110 form a resistor chain between the first terminal 144 and the second terminal 146. The two-terminal resistor chain can be connected between the first terminal 144, which constitutes the lower supply voltage terminal VSS_SR_EDM (e.g., ground), and the second terminal 146, which serves as the sensing terminal SR_EDM_i. Furthermore, the sensing terminal SR_EDM_i can be coupled to the supply voltage VDD_SR_EDM via a pull-up resistor 156 in the pull-up circuit system.

[0088] The labels VSS_SR_EDM, VDD_SR_EDM, SR_EDM_i, and SR_EDM_o are defined as follows: "VSS" indicates a lower supply potential (e.g., ground), "VDD" indicates a higher supply potential (used to provide electrical operating energy), "SR" indicates a reference to the sealing ring 118, "EDM" relates to the edge damage monitoring ring (corresponding to the edge integrity detection structure 106), "i" indicates an input, and "o" indicates an output.

[0089] Still referencing Figure 1 The evaluation circuit 120 can be electrically connected to the edge integrity detection structure 106 via a first terminal 144 and a second terminal 146. In some embodiments, the evaluation circuit 120 includes a logic block 158 configured to evaluate the resistance of the edge integrity detection structure 106 to provide an evaluation signal at the output terminal SR_EDM_o indicating the detected edge integrity status of the edge of the semiconductor chip 102.

[0090] Advantageously, the evaluation circuit 120 can be monolithically integrated into the semiconductor chip 102. In some embodiments, the evaluation circuit 120 may be formed in and / or on the semiconductor chip 102. This keeps the size of the semiconductor product 100 small. Furthermore, a short connection path between the edge integrity detection structure 106 and the evaluation circuit 120 can be ensured, which can have a positive impact on the quality and integrity of the evaluation signal. In addition, the evaluation circuit 120 forms part of or is electrically connected to the integrated circuit 104. Therefore, the evaluation signal can be transmitted to the integrated circuit 104 so that it can be provided for further processing during chip testing, etc. Monolithically integrating the evaluation circuit 120 into the semiconductor chip 102 also facilitates miniaturization or smaller designs.

[0091] according to Figure 1 The evaluation circuit 120 is disposed on the left-hand side of the semiconductor chip 102 at the edge of the integrated circuit 104 adjacent to the sealing ring 118. However, alternatively, it is possible for the evaluation circuit 120 to be located on the right-hand side, on the top and / or bottom side of the semiconductor chip 102. Therefore, it is possible to freely design according to... Figure 1 The circuit system.

[0092] As already mentioned, evaluation circuit 120 may be electrically connected to edge integrity detection structure 106. Furthermore, evaluation circuit 120 may be configured to evaluate the electrical characteristics of edge integrity detection structure 106 to provide an evaluation signal indicating the detected edge integrity state of the edge of semiconductor chip 102. More specifically, evaluation circuit 120 may be configured to evaluate the resistance of edge integrity detection structure 106 as the basis for the evaluation signal. For example, resistance evaluation can be accomplished by detecting the current flowing through edge integrity detection structure 106. For instance, zero current may indicate a detected defective edge integrity state because an interruption in the resistor chain formed by layer structure 108 and vertical connecting element 110 can increase the resistance to extremely high values. Furthermore, a non-zero current flowing along edge integrity detection structure 106 may indicate a detected complete edge integrity state because current can only flow along complete resistor chains.

[0093] Advantageously, Figure 1 The evaluation circuit 120 can be configured to provide a logic evaluation signal indicating the detected edge integrity state and supplied at the terminal SR_EDM_o. The logic or digital evaluation signal is preferably a one-bit signal that indicates whether the edges of the edge integrity detection structure 106 and therefore the semiconductor chip 102 are intact via a logic value of "0" or "1". To create this logic digital evaluation signal, the evaluation circuit 120 may include an analog block for detecting information indicating the resistance of the edge integrity detection structure 106. Furthermore, the evaluation circuit 120 can be configured to provide a digital evaluation signal indicating the detected edge integrity state at the terminal SR_EDM_o. The terminal SR_EDM_o can be used as an electrical output interface configured to provide the evaluation signal to external automated test equipment (not shown). For example, the evaluation circuit 120 can provide the evaluation signal within the framework of a semiconductor product test procedure.

[0094] The evaluation circuit 120 can be any hardware circuitry or software process used to detect structural integrity. In some embodiments, the evaluation circuit 120 is a processor, microcontroller (e.g., executing firmware), ASIC, field-programmable gate array (FPGA), or logic device, or any other type and form of dedicated semiconductor logic or processing circuitry system capable of processing or supporting the operations described herein.

[0095] refer to Figure 2 and Figure 5The evaluation circuit 120 is electrically connected to the edge integrity detection structure 106 via a conductive connection structure 128, which is buried within the semiconductor chip 102 and extends below the edge integrity detection structure 106 and below the internal portion 148 of the sealing ring 118. According to the described embodiment, the sealing ring 118 of the semiconductor product 100 surrounds the integrated circuit 104, where the edge integrity detection structure 106 is integrated. The buried connection structure 128 extends within the semiconductor chip 102 below the sealing ring 118 and the edge integrity detection structure 106, and electrically connects the edge integrity detection structure 106 to the evaluation circuit 120. A deep n-well connection can be used as the buried connection structure 128 to connect SR_EDM_i to the sensor block. By performing this measurement, a sensed signal can be supplied as input to the on-chip evaluation circuit 120 via the buried connection structure 128. The sensed signal can be transmitted at the semiconductor layer below the metal layer. Advantageously, the function of the sealing ring 118 is not negatively affected by the function of the edge integrity detection structure 106, and the integrity of the sealing ring 118 can be maintained. In contrast, a lower potential VSS can be connected to the edge integrity detection structure 106 via the sealing ring 118, which may be a grounded metal ring. Furthermore, a buffer or transition region 164 can be disposed between the sealing ring 118 and the integrated circuit 104 (e.g., chip boundary 166). Figure 5 The buried connecting line or structure 128 is also illustrated in both the top view 168 and the cross-sectional view 170.

[0096] Refer again Figure 1 The described sealing ring monitor includes a continuous metal path chain as an edge damage detection ring or edge integrity detection structure 106. The latter can be embedded in the sealing ring 118. One end of the resistor chain of the edge integrity detection structure 106 (e.g., the second terminal 146) can be connected to the sensing input of the evaluation circuit 120. The other end (e.g., the first terminal 144) can be connected to the chip core and thus to a lower potential VSS. When the sealing ring monitoring chain is damaged, i.e., when the sealing ring 118 is damaged, the output SR_EDM_o can be high or can be a logic value "1". Otherwise, the output SR_EDM_o can be low or can be a logic value "0".

[0097] In some embodiments, the three pins can be connected to the main chip. In some embodiments, these pins are a core-level logic output corresponding to SR_EDM_o and two core supply pins corresponding to VDD_SR_EDM and VSS_SR_EDM.

[0098] In some embodiments, a test method for testing the integrity of the chip edge at or adjacent to the sealing ring 118 can be implemented. For this purpose, it is possible to create an analog block or circuit to detect chain resistance and output a one-bit digital signal to the main chip. The analog block may have inputs to the chip's I / O and inputs to the core supply VDD. The output can be used in the main chip's power-on test logic to report results: a logic value "1" indicates a fault in the sealing ring monitor, and a logic value "0" indicates a pass. The analog block may include comparators, bias circuitry, and level shifters.

[0099] Figure 6 This describes the evaluation circuit 120 of the semiconductor product 100 according to an exemplary embodiment. Figure 6 It also demonstrates various terminals mentioned above and provides examples for implementing the evaluation circuit 120 at the level of transistor level 172 and logic gate 174.

[0100] Figure 7 This describes the evaluation circuit 120 of the semiconductor product 100 according to an exemplary embodiment.

[0101] To be more specific, Figure 7 An example of the connection between the sealing ring 118 and the evaluation circuit 120 is shown. The sensing terminal labeled SENSE is also shown. During operation, in some embodiments, the terminal Redm_top remains floating. In some embodiments, VDD_SR_EDM and VSS_SR_EDM are connected to the core potentials VDD and VSS, respectively. In some embodiments, SR_EDM_o is connected to an internal chip register or multiplexer for testing, such as ATE and bench testing.

[0102] Figure 8 Another plan view illustrating a portion of a semiconductor product 100 according to an exemplary embodiment.

[0103] The sensor block or circuitry of evaluation circuit 120 is connected to sealing ring 118 via an overlapping arch. For example, the sensor block may have four pins: SR_EDM_i (input), SR_EDM_o (output, core-level digital signal), VDD (input / output, core VDD), and VSS (input / output, core VSS). The three last mentioned pins can be connected to the chip core. SR_EDM_i remains disconnected within chip 102. Inside the sensor block, SR_EDM_i has a weak pull-up. SR_EDM_i can be connected to one end of the sealing ring resistor via the arch. The other end of the ring metal-path resistor can be connected to VSS via the arch.

[0104] Figure 9 A plan view or top view illustrating a portion of a semiconductor product 100 according to an exemplary embodiment.

[0105] Embedded within the sealing ring 118, a continuous metal path stacked ring can be used as an edge integrity detection structure 106 to detect the integrity of the sealing ring 118. The sensor can be placed on a tab on the right or left side of the main chip.

[0106] Figure 10 This describes the evaluation circuit 120 of a semiconductor product 100 according to some embodiments. Figure 10 This demonstrates a core logic implementation scheme with an analog resistor-to-logic signal converter. Figure 10 Various terminals mentioned above are also shown, and in some embodiments, evaluation circuitry 120 is provided at the level of transistor level 172 and logic gate 174.

[0107] Figure 11 This describes the evaluation circuit 120 of a semiconductor product 100 according to some embodiments.

[0108] The illustrated evaluation circuit 120 includes a reference resistor structure 122 having a higher resistance value than the edge integrity detection structure 106 in its intact state. The evaluation circuit 120 includes a comparator circuit 124. The comparator circuit 124 is configured to compare a signal indicating the resistance value of the edge integrity detection structure 106 with a signal indicating the resistance value of the reference resistor structure 122. Therefore, an evaluation signal provided by the comparator circuit 124 can be provided as the output of the comparator circuit 124. In some embodiments, the evaluation circuit 120 includes a bias circuit system 126 to electrically bias the edge integrity detection structure 106 and the reference resistor structure 122.

[0109] Many modifications to the described embodiments are possible. For example, according to the drawings, the VSS_SR_EDM connection may extend through the sealing ring structure. Specifically, it is also possible to use... Figure 5 The second connection described herein is used to connect the VSS end of the tortuous structure. This can be achieved through... Figure 5 The connection described herein is used to connect the two ends of the tortuous structure without damaging the internal sealing ring. In some embodiments, the well / deep well is a p-type well.

[0110] It should be noted that certain paragraphs of this disclosure may use terms such as “first” and “second” in connection with apparatus, mode of operation, transmission chain, etc., for the purpose of identifying or distinguishing one another or for other purposes. These terms are not intended to associate entities (e.g., first apparatus and second apparatus) merely in time or in sequence, but in some cases, these entities may contain this relationship. These terms also do not limit the number of possible entities (e.g., apparatuses) that can operate within a system or environment.

[0111] While the foregoing written description of the methods and systems enables those skilled in the art to make and use what is currently considered the best mode of implementation, those skilled in the art should understand and recognize that variations, combinations, and equivalents of specific embodiments, methods, and examples exist herein. Therefore, these methods and systems should not be limited to the embodiments, methods, and examples described above, but rather to all embodiments and methods within the scope and spirit of this disclosure.

[0112] Some illustrative embodiments have been described, and it is obvious that the foregoing is illustrative and non-limiting, and is presented as examples. Specifically, although many of the examples presented herein relate to specific combinations of method actions or system elements, those actions and elements can be combined in other ways to accomplish the same objective. Actions, elements, and features discussed in connection with only one embodiment are not intended to exclude them from similar roles in other embodiments.

[0113] The phrases and terms used herein are for descriptive purposes and should not be considered limiting. The use of “comprising,” “including,” “having,” “containing,” “involving,” “characterized by,” and variations thereof herein means to cover items listed herein, their equivalents, additional items, and alternative embodiments that include only those listed herein. In one embodiment, the systems and methods described herein consist of one, more than one, or all of the described elements, actions, or components.

[0114] Any reference to an embodiment, element, or action of a system or method herein cited in the singular may also include embodiments that include a plurality of such elements, and any reference to any embodiment, element, or action herein cited in the plural may also include embodiments that include only a single element. References in either the singular or plural form are not intended to limit the currently disclosed systems or methods, their components, actions, or elements to a singular or plural configuration. A reference to any action or element based on any information, action, or element may include that said action or element is at least in part based on an embodiment of that information, action, or element.

[0115] Any embodiment disclosed herein may be combined with any other embodiment, and references to “implementation,” “some embodiments,” “alternative embodiments,” “various embodiments,” “an embodiment,” or the like are not necessarily mutually exclusive and are intended to indicate that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment. Such terms as used herein do not necessarily all refer to the same embodiment. Any embodiment may be combined with any other embodiment inclusively or exclusively in any manner consistent with the aspects and embodiments disclosed herein.

[0116] A reference to "or" can be understood as inclusive, such that any term described using "or" can refer to any one, more than one, or all of the described items.

[0117] Where a reference numeral follows a technical feature in the drawings, detailed description, or any claim, the reference numeral is included solely for the purpose of enhancing the comprehensibility of the drawings, detailed description, and claims. Therefore, the reference numeral and its presence do not have any limiting effect on the scope of any claim element.

[0118] The systems and methods described herein may be embodied in other specific forms without departing from their characteristics. The foregoing embodiments are illustrative and not limiting of the systems and methods described herein. The scope of the systems and methods described herein is therefore indicated by the appended claims, rather than by the foregoing description, and variations derived from the equivalent meaning and scope of the claims are included therein.

Claims

1. A semiconductor product comprising: a semiconductor chip; an edge integrity detection structure extending along at least a portion of an edge of the semiconductor chip, the edge integrity detection structure comprising a stack of electrically conductive layers, wherein the stack has a first lateral side and a second lateral side opposite the first lateral side, wherein a first layer of the electrically conductive layers extends from a first end of the first layer associated with the first lateral side to a second end of the first layer associated with the second lateral side and is coupled to a second layer of the stack by a first vertical connection element at the first end of the first layer of the stack, wherein the second layer extends from a first end of the second layer associated with the first lateral side to a second end of the second layer associated with the second lateral side, wherein a third layer of the electrically conductive layers extends from a first end of the third layer associated with the first lateral side to a second end of the third layer associated with the second lateral side and is coupled to the second layer of the stack by a second vertical connection element at the second end of the third layer of the stack, wherein a fourth layer of the electrically conductive layers extends from a first end of the fourth layer associated with the first lateral side to a second end of the fourth layer associated with the second lateral side and is coupled to the third layer of the stack by a third vertical connection element at the first end of the fourth layer of the stack, wherein the second layer is not coupled to the third layer at the first end of the third layer, wherein the first end of the first layer is opposite the second end of the first layer, the first end of the second layer is opposite the second end of the second layer, the first end of the third layer is opposite the second end of the third layer, and the first end of the fourth layer is opposite the second end of the fourth layer; and circuitry formed in and / or on the semiconductor chip, electrically connected with the edge integrity detection structure and configured to evaluate an electrical property of the edge integrity detection structure to provide a signal indicative of an integrity status of the edge.

2. The semiconductor product of claim 1, wherein the circuitry forms part of and / or is electrically connected with an integrated circuit formed in and / or on the semiconductor chip.

3. The semiconductor product of claim 2, wherein the circuitry is arranged at an edge of the integrated circuit adjacent to at least a portion of a sealing ring.

4. The semiconductor product of claim 1, wherein the circuitry is configured to provide the signal indicative of the integrity status as an on-chip signal.

5. The semiconductor product of claim 1, wherein the circuitry comprises an analog block configured to detect information indicative of a resistance of the edge integrity detection structure, and is configured to provide the signal indicative of the integrity status as a digital evaluation signal.

6. The semiconductor product of claim 5, wherein the digital evaluation signal is a one-bit signal.

7. The semiconductor product of claim 1, wherein the circuitry is configured to provide an evaluation signal in a semiconductor product test procedure.

8. The semiconductor product of claim 1, further comprising: a sealing ring surrounding at least part of an integrated circuit formed in and / or on the semiconductor chip and in which the edge integrity detection structure is integrated; and a buried connection structure extending in the semiconductor chip below the sealing ring and below the edge integrity detection structure and electrically connecting the edge integrity detection structure and the circuitry.

9. A semiconductor product, comprising; a semiconductor chip; an integrated circuit formed in and / or on the semiconductor chip; and an edge structure extending along at least part of an edge of the semiconductor chip and comprising a plurality of parallel planar conductive layers, the edge structure comprising a first section of a first plurality of conductive layers extending from a first side to a second side opposite the first side and a second section of a second plurality of conductive layers extending from a third side to a fourth side opposite the third side, wherein the second side and the third side are between the first side and the fourth side, wherein the first section and the second section are gapwise arranged relative to each other such that a first conductive layer and a second conductive layer of the first plurality of conductive layers in the first section overlap a third conductive layer and a fourth conductive layer of the second plurality of conductive layers in the second section along a perpendicular through the first plurality of conductive layers and the second plurality of conductive layers at a location associated with the second side and the third side, a second end of the third conductive layer in the second section at the third side and a second end of the fourth conductive layer in the second section are between a first end of the first conductive layer in the first section at the second side and a first end of the second conductive layer in the first section.

10. The semiconductor product of claim 9, further comprising a sealing ring surrounding at least part of the integrated circuit, wherein at least part of the edge structure is integrated in the sealing ring.

11. The semiconductor product of claim 9, wherein the edge structure is configured as a two-terminal resistor chain.

12. The semiconductor product of claim 9, further comprising circuitry electrically connected or connectable with the edge structure and configured to evaluate a resistance of the edge structure to provide an evaluation signal indicative of a detected edge integrity status of the edge.

13. The semiconductor product of claim 9, wherein the first of the first plurality of conductive layers in the first section and another conductive layer in the first section are coupled by a first vertical element at the first end of the first of the first plurality of conductive layers and a first end of the other conductive layer in the first section, and the third of the second plurality of conductive layers in the second section and the fourth of the second plurality of conductive layers in the second section are coupled by a second vertical element at the second end of the third conductive layer and the second end of the fourth conductive layer in the second section.

14. The semiconductor product of claim 12, wherein the circuitry is electrically connected with the edge structure by a connection structure that is buried within the semiconductor chip and extends under the edge structure.

15. A semiconductor product, comprising: a semiconductor chip; an integrated circuit formed in and / or on the semiconductor chip; and an edge integrity detection structure that extends along at least a portion of an edge of the semiconductor chip and comprises a plurality of electrically connected planar conductive layer structures, wherein the conductive layer structures have a first side and a second side opposite the first side and comprise a stack of a first layer, a second layer, and a third layer, wherein each of the first layer, the second layer, and the third layer at least partially overlap each other in a plan view, wherein a current path is provided from a first side of the first layer to a second side of the first layer, through a first vertical connection element at the second side of the first layer to a second side of the second layer, from the second side of the second layer to a first side of the second layer, through a second vertical connection element at the first side of the second layer to a first side of the third layer, and from the first side of the third layer to a second side of the third layer, wherein the integrated circuit is configured to provide a current that is conveyed along the current path, wherein a perpendicular line through the first vertical connection element at the second side of the first layer extends through all of the first layer, the second layer, and the third layer.

16. The semiconductor product of claim 15, wherein at least 80% of a major surface of each of a first set of the conductive layer structures is aligned with at least 80% of a major surface of each of a second set of the conductive layer structures.

17. The semiconductor product of claim 15, wherein the current path is provided from the second side of the third layer through a third vertical connection element at the second side of the third layer to a second side of a fourth layer, from the second side of the fourth layer to a first side of the fourth layer, and through a fourth vertical connection element at the first side of the fourth layer to a fifth layer, wherein the second and fourth vertical connection elements are vertically aligned and the first and third vertical connection elements are not vertically aligned.

18. The semiconductor product of claim 17, wherein the conductive layer structures form a meander structure.

19. The semiconductor product of claim 18, wherein the conductive layer structures additionally form another meander structure. ​ 20. The semiconductor product of claim 19, wherein the meander structure is interleaved with the other meander structure.

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