Semiconductor devices and their fabrication methods

Abstract

The present application discloses a semiconductor device and a method of fabricating the same. The semiconductor device includes a substrate, a capacitor structure, and a support structure. The capacitor structure is disposed on the substrate and includes a plurality of columnar bottom electrodes, a capacitor dielectric layer, and a top electrode layer. The top portion of each columnar bottom electrode has a recess, and the capacitor dielectric layer fills the recess. The support structure is disposed between adjacent columnar bottom electrodes and includes a first support layer and a second support layer disposed in sequence from bottom to top. In this way, the adhesion between the columnar bottom electrodes and the dielectric material is strengthened by the capacitor dielectric layer, so that the semiconductor device has a more stable and reliable structure and achieves a relatively optimized device performance.

Description

Technical Field

[0001] This invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor memory device and a method for manufacturing the same. Background Technology

[0002] With the trend towards miniaturization in various electronic products, the design of semiconductor devices must also meet the requirements of high integration and high density. For dynamic random access memory (DRAM) with a recessed gate structure, it can achieve a longer carrier channel length within the same semiconductor substrate, reducing leakage current caused by capacitor structures. Therefore, under the current mainstream development trend, it has gradually replaced DRAM with only planar gate structures. Generally, DRAM with a recessed gate structure consists of a large number of memory cells clustered into an array area to store information. Each memory cell can be composed of transistor components and capacitor components connected in series to receive voltage information from the word line (WL) and bit line (BL). Due to product demands, the density of memory cells in the array area must continue to increase, resulting in increasing difficulty and complexity in related manufacturing processes and designs. Therefore, existing technologies or structures need further improvement to effectively enhance the performance and reliability of related memory devices. Summary of the Invention

[0003] One objective of this invention is to provide a method for fabricating a semiconductor device, which involves forming a groove on a columnar bottom electrode and filling the groove with a subsequently formed capacitor dielectric layer. This enhances the adhesion between the metal (the columnar bottom electrode) and the dielectric material (the capacitor dielectric layer), reduces the chance of the capacitor dielectric layer peeling off from the capacitor structure, and allows the resulting semiconductor device to have a more stable and reliable structure, achieving relatively optimized device performance.

[0004] One objective of this invention is to provide a semiconductor device in which a groove is formed on a columnar bottom electrode and a capacitor dielectric layer fills the groove. This strengthens the adhesion between the metal (the columnar bottom electrode) and the dielectric material (the capacitor dielectric layer), reduces the chance of the capacitor dielectric layer peeling off from the capacitor structure, and enables the semiconductor device to have a more stable and reliable structure, thereby achieving relatively optimized device performance.

[0005] To achieve the above objectives, one embodiment of the present invention provides a semiconductor device including a substrate, a capacitor structure, and a support structure. The capacitor structure is disposed on the substrate and includes a plurality of columnar bottom electrodes, a capacitor dielectric layer, and a top electrode layer. Each columnar bottom electrode has a groove at its top, and the capacitor dielectric layer fills the groove. The support structure is disposed between adjacent columnar bottom electrodes and includes a first support layer and a second support layer sequentially disposed from bottom to top.

[0006] To achieve the above objectives, one embodiment of the present invention provides a method for fabricating a semiconductor device, comprising the following steps: First, a substrate is provided, and a capacitor structure is formed on the substrate. The capacitor structure includes a plurality of pillar-shaped bottom electrodes, a capacitor dielectric layer, and a top electrode layer, wherein each pillar-shaped bottom electrode has a groove at its top, and the capacitor dielectric layer fills the groove. Then, a support structure is formed between adjacent pillar-shaped bottom electrodes. The support structure includes a first support layer and a second support layer sequentially disposed from bottom to top. Attached Figure Description

[0007] The accompanying drawings provide a more detailed understanding of embodiments of the invention and are incorporated herein by reference as a whole. These drawings and descriptions are used to illustrate the principles of some embodiments. It should be noted that all drawings are schematic diagrams, and for illustrative and drafting purposes, relative sizes and proportions have been adjusted. The same symbols represent corresponding or similar features in different embodiments.

[0008] Figures 1 to 10 A schematic diagram illustrating the steps of a method for fabricating a semiconductor device according to an embodiment of the present invention is provided, wherein:

[0009] Figure 1 This is a schematic cross-sectional view of the semiconductor device of the present invention after the memory node pads have been formed;

[0010] Figure 2 This is a schematic cross-sectional view of the semiconductor device of the present invention after the support layer structure has been formed;

[0011] Figure 3 This is a schematic cross-sectional view of the semiconductor device of the present invention after the dielectric material layer has been formed;

[0012] Figure 4 This is a schematic cross-sectional view of the semiconductor device of the present invention after the dielectric layer has been formed;

[0013] Figure 5 This is a schematic cross-sectional view of the semiconductor device of the present invention after the bottom electrode layer has been formed;

[0014] Figure 6 This is a schematic cross-sectional view of the semiconductor device of the present invention after the mask layer has been formed;

[0015] Figure 7 This is a schematic cross-sectional view of the semiconductor device of the present invention after the third support material layer has been removed;

[0016] Figure 8 This is a cross-sectional schematic diagram of the semiconductor device of the present invention after the first support material layer has been removed;

[0017] Figure 9 This is a schematic cross-sectional view of the semiconductor device of the present invention after the formation of the capacitor dielectric layer; and

[0018] Figure 10 This is a schematic cross-sectional view of the semiconductor device of the present invention after the top electrode layer has been formed.

[0019] The reference numerals in the attached figures are explained as follows:

[0020] 100 substrate

[0021] 101 Shallow Ditch Isolation

[0022] 103 Active Zone

[0023] 110 Dielectric Layer

[0024] 111 Oxide Layer

[0025] 113 Nitride layer

[0026] 115 Oxide Layer

[0027] 120-bit line

[0028] 120a bit line contact

[0029] 121 Semiconductor layer

[0030] 123 Barrier Layer

[0031] 125 conductive layer

[0032] 127 cap layer

[0033] 130 plug

[0034] 140 Spacer Wall Structure

[0035] 141 First gap wall

[0036] 143 Second spacer wall

[0037] 145 Third spacer wall

[0038] 150 dielectric layer

[0039] 151 storage node pads

[0040] 160 insulation layer

[0041] 170 Support layer structure

[0042] 171 First Support Material Layer

[0043] 172, 172a Opening

[0044] 173 Second Support Material Layer

[0045] 175 Third Support Material Layer

[0046] 177 Fourth Support Material Layer

[0047] 179 Fifth Support Material Layer

[0048] 180 Dielectric Material Layer

[0049] 181 High dielectric constant dielectric layer

[0050] 190 Bottom Electrode Layer

[0051] 191 Columnar bottom electrode

[0052] 193 Capacitor Dielectric Layer

[0053] 193a First Dielectric Layer

[0054] 193b Second Dielectric Layer

[0055] 195 Top Electrode Layer

[0056] 200 mask patterns

[0057] 270 Supporting Structure

[0058] 273 First Support Layer

[0059] 277 Second Support Layer

[0060] 290 Capacitor Structure

[0061] 300 Semiconductor Devices

[0062] R1 Groove Detailed Implementation

[0063] To enable those skilled in the art to further understand the present invention, preferred embodiments are described below in conjunction with the accompanying drawings to explain in detail the composition and desired effects of the invention. It should be understood that the features described below can be substituted, rearranged, or mixed to achieve other embodiments without departing from the spirit of the invention.

[0064] Please refer to Figures 1 to 10The illustration shows the steps of a method for fabricating a semiconductor device 300 according to an embodiment of the present invention. First, as... Figure 1 As shown, a substrate 100 is provided, such as a silicon substrate, a silicon-containing substrate (e.g., SiC, SiGe, etc.), or a silicon-on-insulator (SOI) substrate. At least one insulating region, such as a shallow trench isolation (STI) 101, is formed within the substrate 100. Multiple active areas (AA) 103 are defined on the substrate 100, so that, from a top view (not shown), the shallow trench isolation 101 surrounds all the active areas 103. In one embodiment, the shallow trench isolation 101 is formed, for example, by first etching multiple trenches (not shown) in the substrate 100, and then filling the trenches with at least one insulating material (e.g., silicon oxide or silicon oxynitride, etc.) to form a shallow trench isolation 101 with a surface flush with the top surface of the substrate 100, but this is not a limitation.

[0065] Next, a dielectric layer 110 is formed on the substrate 100. The dielectric layer 110 preferably has a composite layer structure, such as an oxide-nitride-oxide (ONO) structure consisting of oxide layer 111, nitride layer 113, and oxide layer 115 stacked sequentially from bottom to top, but is not limited thereto. It should be noted that before forming the dielectric layer 110, a plurality of buried gates (not shown) are also formed within the substrate 100, such that the dielectric layer 110 covers the top surface of the buried gates. The buried gates extend parallel to each other along a direction (e.g., the x-direction, not shown) to serve as buried word lines (BWLs, not shown) of the semiconductor device 300. On the other hand, a plurality of bit lines 120 and a plurality of plugs 130 are further formed above the substrate 100, wherein each bit line 120 extends parallel to each other in another direction perpendicular to the stated direction (e.g., the y-direction, not shown). Although the specific extension directions of the active region 103, the embedded gate, and the bit line 120 are not shown in the accompanying drawings of this embodiment, those skilled in the art should easily understand that, viewed from a top view (not shown), the extension direction of the active region 103 is different from the extension directions of the word line and the bit line 120, and the bit line 120 should be perpendicular to the embedded gate and intersect with the active region 103 and the embedded gate.

[0066] In detail, each bit line 120 is arranged alternately with the plug 130 in a specific direction, and includes, but is not limited to, a semiconductor layer (e.g., containing polysilicon) 121, a barrier layer 123 (e.g., containing titanium and / or titanium nitride), a conductive layer 125 (e.g., containing low-resistivity metals such as tungsten, aluminum, or copper), and a capping layer 127 (e.g., containing silicon oxide, silicon nitride, or silicon oxynitride). It should be noted that, in principle, all bit lines 120 are formed on the dielectric layer 110 in a spaced manner and intersect with multiple active regions 103. The bit lines 120 falling on each active region 103 extend further into each active region 103 through corresponding bit line contacts (BLCs) 120a formed below them. Figure 1 As shown. That is to say, in this embodiment, each bit line plug 120a is integrally formed with the semiconductor layer 121 of the bit line 120 and directly contacts the corresponding active region 103, but is not limited thereto.

[0067] The plugs 130 are also formed on the substrate 100 in a spaced manner and directly contact the underlying substrate 100 (including the active region 103 and the shallow trench isolation 101). Thus, each plug 130 can serve as a storage node contact (SNC) of the semiconductor device 300 to receive or transmit voltage signals from each memory cell. In one embodiment, the plugs 130 are made of low-resistivity metals such as aluminum (Al), titanium (Ti), copper (Cu), or tungsten (W), and each plug 130 is insulated from each other by a spacer structure 140. In one embodiment, the spacer structure 140 may selectively have a single-layer structure or a layered structure. Figure 1 The composite layer structure shown may include, for example, a first spacer wall 141 (e.g., containing silicon nitride), a second spacer wall 143 (e.g., containing silicon oxide), and a third spacer wall 145 (e.g., containing silicon nitride) stacked sequentially on the sidewalls of each line 120, but is not limited thereto.

[0068] Please refer to again Figure 1As shown, a dielectric layer 150 and a plurality of storage node pads (SN pads) 151 are formed above. The dielectric layer 150 integrally covers the plug 130 and the bit line 120, while each storage node pad 151 is formed separately within the dielectric layer 150 and has a top surface flush with the top surface of the dielectric layer 150. Each storage node pad 151 contacts the plug 130 below and is electrically connected to it. In one embodiment, the storage node pad 151 also comprises a low-resistivity metal material such as aluminum, titanium, copper, or tungsten, for example, a metal material different from that of the plug 130, while the dielectric layer 150 comprises a dielectric material such as silicon nitride, but is not limited thereto. In another embodiment, the storage node pad may also be integrally formed with the plug 130 and may comprise the same material.

[0069] like Figure 2 As shown, an insulating layer 160 and a support layer structure 170 are sequentially formed on the dielectric layer 150. The insulating layer 160 includes, for example, an insulating material such as silicon oxide or silicon oxynitride, while the support layer structure 170 includes at least one oxide layer and at least one nitride layer stacked alternately. In this embodiment, the support layer structure 170 may include, for example, a first support material layer 171 (e.g., including silicon oxide), a second support material layer 173 (e.g., including silicon nitride or silicon carbonitride), a third support material layer 175 (e.g., including silicon oxide), a fourth support material layer 177 (e.g., including silicon nitride or silicon carbonitride), and a fifth support material layer 179 (e.g., including silicon oxide) stacked sequentially from bottom to top, but is not limited thereto. Then, multiple openings 172 are formed in the support layer structure 170, sequentially penetrating the fifth support material layer 179, the fourth support material layer 177, the third support material layer 175, the second support material layer 173, the first support material layer 171 and the insulating layer 160, and aligned with the pads 151 of each storage node below, so that the top surface of each pad 151 of the storage node can be exposed from each opening 172.

[0070] Preferably, the oxide layer (e.g., including a first support material layer 171 and a third support material layer 175) may have a relatively large thickness, for example, approximately 5 to 10 times or more the thickness of the nitride layer (e.g., including a second support material layer 173 or a fourth support material layer 177), and the thickness of the nitride layer (e.g., the fourth support material layer 177) disposed away from the substrate 100 is preferably greater than the thickness of the nitride layer (e.g., the second support material layer 173) disposed adjacent to the substrate 100. Figure 2As shown, but not limited thereto. In this embodiment, the overall thickness of the support layer structure 170 is approximately 1600 to 2000 angstroms, but not limited thereto. Those skilled in the art will understand that the specific number of oxide layers (such as the first support material layer 171, or the third support material layer 175, or the fifth support material layer 179) and nitride layers (such as the second support material layer 173 or the fourth support material layer 177) stacked together is not limited to the aforementioned number, but can be adjusted according to actual needs, for example, 4 layers, 5 layers, or other numbers.

[0071] Next, as Figure 3 As shown, a deposition process is performed to form a dielectric material layer 180 on the support layer structure 170. Specifically, the dielectric material layer 180 is conformally and uniformly covered on the top surface of the support layer structure 170, the surface of the opening 172, and the storage node pads 151, and includes, for example, a high dielectric constant dielectric material such as hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), tantalum oxide (Ta2O3), titanium oxide (TiO2), yttrium oxide (Y2O3), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO4), and hafnium zirconium oxide. Strontium bismuth tantalum oxide (HfZrO), strontium bismuth tantalum oxide (SrBi2Ta2O9, SBT), lead zirconate titanate (PbZrxTi) 1-x O3, PZT) or Barium Strontium Titanate (BaxSr) 1-x TiO3, BST, etc., but not limited to these.

[0072] like Figure 4As shown, an etching process is performed on the dielectric material layer 180 to remove the dielectric material layer 180 covering the top surface of the support layer structure 170 and the memory node pads 151, forming a high-dielectric-coefficient dielectric layer 181 only located on the sidewalls of each opening 172, exposing the top surface of the memory node pads 151. Then, an etching process, such as a dry etching process, is performed over the high-dielectric-coefficient dielectric layer 181 to etch a portion of the memory node pads 151 downwards from the exposed top surface, forming openings 172a that further extend into a portion of the memory node pads 151.

[0073] like Figure 5 As shown, a deposition process is performed to form a bottom electrode layer 190 that fills each opening 172a and further covers the top surface of the support layer structure 170. In one embodiment, the bottom electrode layer 190 comprises a low-resistivity metal material such as aluminum, titanium, copper, or tungsten, preferably including titanium, but not limited thereto. Then, another etching process is performed to remove the bottom electrode layer 190 covering the top surface of the support layer structure 170, forming as shown in the figure. Figure 6 The diagram shows multiple columnar bottom electrodes 191. Each columnar bottom electrode 191 can thus have a symmetrical, vertical columnar structure. The bottom of the columnar bottom electrode 191 is not flush with the bottom surface of the high-dielectric-coefficient dielectric layer 181, but extends further into a portion of the memory node pad 151 and directly contacts the memory node pad 151, thereby increasing the contact area between the columnar bottom electrode 191 and the memory node pad 151. The top surface of the columnar bottom electrode 191 is flush with the top surface of the fifth support material layer 179 and the high-dielectric-coefficient dielectric layer 181.

[0074] Then, for example Figure 6 As shown, a plurality of mask patterns 200 are formed on the substrate 100, covering a portion of the fifth support material layer 179 and a portion of the columnar bottom electrodes 191. Specifically, each mask pattern 200 covers the support layer structure 170 in such a way that it simultaneously covers a portion of the top surface of two adjacent columnar bottom electrodes 191 and the entire top surface of the fifth support material layer 179 between them. Approximately two-thirds to one-half of the top surface of two adjacent columnar bottom electrodes 191 is covered by the mask pattern 200, exposing at least approximately one-third to one-half of the top surface, but not limited thereto.

[0075] like Figure 7As shown, at least one etching process is performed through the mask pattern 200 to partially remove the support layer structure 170. Specifically, in this embodiment, a first etching process, such as a dry etching process, is performed to remove a portion of the fifth support material layer 179 and the fourth support material layer 177 and the third support material layer 175 below it from the top surface not covered by the mask pattern 200. Then, a second etching process, such as an isotropic wet etching process, is performed, introducing an etchant such as tetramethylammonium hydroxide (TMAH) to laterally remove the remaining portion of the fifth support material layer 179 and the third support material layer 175. Thus, the fifth support material layer 179 and the third support material layer 175 of the support layer structure 170 can be completely removed.

[0076] Furthermore, it should be specifically noted that during the at least one etching process, the columnar bottom electrodes 191 not covered by the mask pattern 200 are further etched by adjusting the etching selection of the etching process, but the high dielectric constant dielectric layer 181 not covered by the mask pattern 200 is not etched. Thus, a groove R1 is etched on the top of each columnar bottom electrode 191, sandwiched between the high dielectric constant dielectric layer 181 and the unetched columnar bottom electrodes 191. The lowest surface of each groove R1 is higher than the top surface of the fourth support material layer 177 and lower than the top surface of the high dielectric constant dielectric layer 181. In this embodiment, due to the aforementioned coverage method of the mask pattern 200, the groove R1 is only formed on the top of one side of each columnar bottom electrode 191, making the top of each columnar bottom electrode 191 asymmetrical. The side of each columnar bottom electrode with the groove does not contact the support structure, and two adjacent columnar bottom electrodes 191 can be mirror-symmetrical to each other. Figure 7 As shown, this is to facilitate the expansion of the deposition space between the capacitor dielectric layer and the top electrode layer that are subsequently formed.

[0077] like Figure 8 As shown, a third etching process, such as a dry etching process, and a fourth etching process, such as an isotropic wet etching process, are sequentially performed through the mask pattern 200. The third etching process involves removing a portion of the second support material layer 173 and the first support material layer 171 from the top surface of the second support material layer 173 not covered by the mask pattern 200. Then, the fourth etching process is used to laterally remove the remaining portion of the first support material layer 171 by introducing an etchant such as tetramethylammonium hydroxide.

[0078] It should be specifically noted that, in this embodiment, the third and fourth etching processes preferably adjust the etching selection of the aforementioned etching processes, without further etching the tops of each columnar bottom electrode 191, so that the lowest surface of each groove R1 remains above the fourth support material layer 177 and below the top surface of the high dielectric constant dielectric layer 181, to avoid excessively large grooves R1, but this is not a limitation. In another embodiment, the same etching selection as described above can also be maintained, and the tops of each columnar bottom electrode 191 can be further etched through the third and fourth etching processes to increase the depth of the grooves, so that the lowest surface of the grooves can be lowered to a position below the top surface of the fourth support material layer 177. In addition, since the high dielectric constant dielectric layer 181 covers the sidewalls of the columnar bottom electrode 191, the columnar bottom electrode 191 can be further protected during the aforementioned etching processes, avoiding the influence of the aforementioned etching processes.

[0079] Then, as Figure 9 As shown, the mask pattern 200 is completely removed, so that the remaining fourth support material layer 177 and the remaining second support material layer 173 form a second support layer 277 and a first support layer 273 respectively arranged sequentially from top to bottom, and are disposed on at least one sidewall of each columnar bottom electrode 191 to form a support structure 270 of the semiconductor device 300. Then, as shown... Figure 9 As shown, at least one deposition process is performed on the support structure 270 to form a capacitor dielectric layer 193. Specifically, the capacitor dielectric layer 193 includes a first dielectric layer 193a and a second dielectric layer 193b stacked sequentially, both integrally covering all exposed surfaces of the support structure 270, the columnar bottom electrode 191, and the high-dielectric-coefficient dielectric layer 181. The first dielectric layer 193a further fills each groove R1. Thus, multiple surfaces of the first support layer 273 and the second support layer 277 are respectively covered by the high-dielectric-coefficient dielectric layer 181 and the first dielectric layer 193a, and the first capacitor dielectric layer 193a covering the sidewall of the columnar bottom electrode 191 directly contacts the high-dielectric-coefficient dielectric layer 181.

[0080] In this embodiment, the first dielectric layer 193a and the second dielectric layer 193b each comprise different high dielectric constant dielectric materials, such as hafnium oxide, hafnium silicate oxide, hafnium silicate nitride, aluminum oxide, lanthanum oxide, lanthanum aluminate, tantalum oxide, titanium oxide, yttrium oxide, zirconium oxide, zirconium silicate oxide, hafnium zirconate, strontium bismuth tantalum oxide, lead zirconate titanate, or barium strontium titanate, but are not limited thereto. Preferably, the first dielectric layer 193a has a high dielectric constant dielectric material with good adhesion to the metal material, and the material selection of the first dielectric layer 193a and the second dielectric layer 193b differs from the material selection of the high dielectric constant dielectric layer 181, but is not limited thereto.

[0081] like Figure 10 As shown, another deposition process is performed on the capacitor dielectric layer 193 to form a top electrode layer 195, filling the remaining space between the columnar bottom electrodes 191. Thus, the columnar bottom electrodes 191, the capacitor dielectric layer 193, and the top electrode layer 195 together form a capacitor structure 290. A portion of the top electrode layer 195 may further fill the space between the second support layer 277 and the first support layer 273, and also further fill the space between the first support layer 273 and the insulating layer 160, to increase the contact area and improve the capacitance value. In one embodiment, the top electrode layer 195 may be made of a low-resistivity metal material such as aluminum, titanium, copper, or tungsten, preferably titanium, but not limited thereto.

[0082] Thus, the fabrication process of capacitor structure 290 is completed. Capacitor structure 290 includes multiple vertically extending capacitors to serve as storage nodes (SNs) of semiconductor device 300. These storage nodes are electrically connected to transistor components (not shown) of semiconductor device 300 via storage node pads 151 and storage node plugs (i.e., plugs 130), ensuring good contact between capacitor structure 290 and the storage node plugs disposed on substrate 100. With this configuration, semiconductor device 300 of this embodiment can form a dynamic random access memory (DRAM) device, consisting of at least one transistor component and at least one capacitor constituting the smallest unit (memory cell) in a DRAM array, to receive voltage information from bit line 120 and the buried word line.

[0083] According to the fabrication method of the present invention, a high-dielectric-coefficient dielectric layer 181 and a columnar bottom electrode layer 191 are first formed within the opening 172. The high-dielectric-coefficient dielectric layer 181 protects the sidewalls of the columnar bottom electrode layer 191 from damage during the etching process and improves the adhesion between the columnar bottom electrode layer 191 and the subsequently formed capacitor dielectric layer 193. Furthermore, the high-dielectric-coefficient dielectric material of the high-dielectric-coefficient dielectric layer 181 can further increase the capacitance value. Moreover, the capacitor dielectric layer 193 further fills the groove R1 at the top of the columnar bottom electrode layer 191, further reducing the chance of the capacitor dielectric layer 193 peeling off from the capacitor structure 290. Thus, in the fabrication method of this embodiment, the deposition process of the capacitor dielectric layer 193 and the top electrode layer 195 can be carried out more smoothly, achieving the effect of simplified fabrication process. At the same time, the semiconductor device obtained by the fabrication method of this embodiment has a more stable and reliable structure and achieves relatively optimized device performance.

[0084] On the other hand, during the first etching process, the columnar bottom electrode layer 191 not covered by the mask pattern 200 can be selectively etched, so that the tops of two adjacent columnar bottom electrodes 191 form opposite or back-to-back grooves R1. With this arrangement, the two adjacent columnar bottom electrodes 191 are mirror-symmetrical, further expanding the deposition space of the subsequently formed capacitor dielectric layer 193. In other words, the fabrication method of this embodiment strengthens the adhesion between the columnar bottom electrodes 191 and the capacitor dielectric layer 193 by setting the high dielectric constant dielectric layer 181 and the grooves R1, reducing the chance of the capacitor dielectric layer 193 peeling off from the capacitor structure 290, thus enabling the fabricated semiconductor device 300 to have a more stable and reliable structure and achieve relatively optimized device performance.

[0085] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A semiconductor device, characterized by Comprising: a substrate; a capacitor structure disposed on the substrate, the capacitor structure comprising a plurality of columnar bottom electrodes, a capacitor dielectric layer, and a top electrode layer, wherein a top portion of each of the columnar bottom electrodes has a recess, the capacitor dielectric layer fills the recess; a high dielectric constant dielectric layer disposed on two opposite sidewalls of each of the columnar bottom electrodes, the recess is sandwiched between the high dielectric constant dielectric layer and each of the columnar bottom electrodes, and the capacitor dielectric layer covers the high dielectric constant dielectric layer; and a support structure disposed between adjacent ones of the columnar bottom electrodes, the support structure comprising a first support layer and a second support layer disposed sequentially from bottom to top.

2. The semiconductor device according to claim 1, wherein The capacitor dielectric layer comprises a first dielectric layer and a second dielectric layer stacked sequentially, wherein the first dielectric layer fills each of the recesses.

3. The semiconductor device of claim 2, wherein, The first dielectric layer and the second dielectric layer respectively comprise different high dielectric constant dielectric materials.

4. The semiconductor device of claim 2, wherein A plurality of surfaces of the first support layer and the second support layer are respectively covered by the first dielectric layer and the high dielectric constant dielectric layer.

5. The semiconductor device of claim 1, wherein Further comprising: a plurality of storage node pads disposed on the substrate and respectively contacting each of the columnar bottom electrodes, wherein a portion of each of the columnar bottom electrodes extends into each of the storage node pads.

6. The semiconductor device of claim 1, wherein A lowest surface of each of the recesses is higher than a top surface of the second support layer.

7. The semiconductor device of claim 1, wherein Each of the columnar bottom electrodes has a side of the recess not contacting the support structure.

8. The semiconductor device of claim 7, wherein, Two adjacent ones of the columnar bottom electrodes are mirror-symmetric to each other.

9. A method of fabricating a semiconductor device, characterized by Comprising: providing a substrate; forming a capacitor structure on the substrate, the capacitor structure comprising a plurality of columnar bottom electrodes, a capacitor dielectric layer, and a top electrode layer, wherein a high dielectric constant dielectric layer is disposed on two opposite sidewalls of each of the columnar bottom electrodes, a top portion of each of the columnar bottom electrodes has a recess, the recess is sandwiched between the high dielectric constant dielectric layer and each of the columnar bottom electrodes, and the capacitor dielectric layer fills the recess and covers the high dielectric constant dielectric layer; and forming a support structure between adjacent ones of the columnar bottom electrodes, the support structure comprising a first support layer and a second support layer disposed sequentially from bottom to top. Further comprising:

10. The method of manufacturing a semiconductor device according to Claim 9, wherein forming a first support material layer, a second support material layer, a third support material layer, a fourth support material layer, and a fifth support material layer sequentially stacked on the substrate; forming a plurality of openings through the fifth support material layer, the fourth support material layer, the third support material layer, the second support material layer, and the first support material layer; forming a plurality of columnar bottom electrodes respectively filling each of the openings; forming a plurality of mask patterns on the fifth support material; removing portions of the fifth support material layer, portions of the fourth support material layer, and portions of the third support material layer through the mask patterns; removing portions of the second support material layer and portions of the first support material layer through the mask patterns; and completely removing the mask patterns to form the support structure. Further comprising: ​ 11. The method of fabricating a semiconductor device according to Claim 10, wherein ​ Etching a top portion of the columnar bottom electrode to form the recess before removing the second support material layer of the portion and the first support material layer of the portion.

12. The method of fabricating a semiconductor device according to Claim 10, wherein Further comprising: performing a first wet etching fabrication process to remove a remaining portion of the fifth support material layer and a remaining portion of the third support material layer; and performing a second wet etching fabrication process to remove a remaining portion of the first support material layer.

13. The method of fabricating a semiconductor device according to Claim 12, wherein The first wet etching fabrication process and the second wet etching fabrication process are both performed before completely removing the mask pattern.

14. The method of fabricating a semiconductor device according to Claim 10, wherein Further comprising: forming a high dielectric constant dielectric layer on two opposite sidewalls of each of the openings before forming the columnar bottom electrode.

15. The method of fabricating a semiconductor device according to Claim 14, wherein Further comprising: forming a dielectric material layer covering the openings and a surface of the fifth support material layer; performing a first etch-back fabrication process to partially remove the dielectric material layer to form the high dielectric constant dielectric layer; forming a bottom electrode layer filling the openings and covering the surface of the fifth support material layer; and performing a second etch-back fabrication process to partially remove the bottom electrode layer to form the columnar bottom electrode.

16. The method of fabricating a semiconductor device according to Claim 14, wherein Further comprising: forming a plurality of storage node pads on the substrate, surfaces of the storage node pads being respectively exposed from the openings; partially etching the storage node pads from the openings after forming the high dielectric constant dielectric layer; and forming the columnar bottom electrode filling the openings, wherein a portion of each of the columnar bottom electrodes extends into each of the storage node pads.

17. The method of fabricating a semiconductor device according to Claim 10, wherein Further comprising: forming the capacitor dielectric layer and the top electrode layer after forming the support structure.

18. The method of fabricating a semiconductor device according to Claim 17, wherein Forming the capacitor dielectric layer further comprises: forming a first dielectric layer on the support structure and the columnar bottom electrode, the first dielectric layer filling each of the recesses; and forming a second dielectric layer on the first dielectric layer.

19. The method of fabricating a semiconductor device according to Claim 18, wherein A plurality of surfaces of the first support layer and the second support layer are respectively covered by the first dielectric layer and the high dielectric constant dielectric layer.

20. The method of fabricating a semiconductor device according to Claim 9, wherein A lowest surface of each of the recesses is higher than a top surface of the second support layer.

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