A method for calculating transistor aging stress based on an analytical model

Abstract

This invention discloses a method for calculating transistor aging stress based on an analytical model. It is an analytical formula automatic generation method applicable to transistors with aging mechanisms of bias temperature instability (BTI) and hot carrier degradation (HCD). The analytical model of this invention calculates the stress of the internal transistor based on statistical dynamic information such as duty factor (DF) and toggle rate (TR) obtained from gate-level simulation. The analytical formula used is automatically generated through transistor-level logic simulation and supports stress analysis for different aging mechanisms.

Description

Technical Field

[0001] This invention relates to the field of digital circuits, and in particular to a method for calculating transistor aging stress based on an analytical model. Background Technology

[0002] As microelectronic processes continue to shrink proportionally, various non-ideal effects, such as random process variation and transistor aging, become increasingly severe, leading to greater performance fluctuations in circuits. To ensure circuit lifespan, designers typically use static timing analysis to estimate the circuit's delay under worst-case conditions (i.e., all transistors are at the worst process corner and have experienced maximum degradation), and use this as a constraint to design the circuit's operating voltage and frequency, resulting in overdesign. This overdesign increases with each further reduction in process technology, resulting in significant performance improvements in devices between each generation, but ultimately, the overall circuit performance does not improve proportionally.

[0003] To improve circuit performance at advanced nodes, reliability-aware timing analysis methods are essential. Among the many non-ideal factors affecting circuit performance, aging is the most difficult to analyze because it depends on the actual operating conditions and loads of the circuit. The challenges of aging-aware analysis are twofold: first, calculating degradation levels; and second, developing an aging-aware timing model based on degradation levels to calculate the timing information of standard cells. The challenge in calculating degradation levels lies in the fact that device-level models require the stress waveform of each transistor. However, recording all device stress waveforms in large-scale digital circuits requires substantial storage and time, which is impractical. Summary of the Invention

[0004] In view of the above-mentioned deficiencies of the prior art, the technical problem to be solved by the present invention is to avoid time-consuming full-net-list SPICE simulation and waveform recording, and to calculate the degradation of each transistor in each standard cell based on the duty cycle and toggle rate statistics of each internal node obtained from gate-level simulation. The present invention provides a transistor aging stress calculation method based on an analytical model, which is an analytical formula automatic generation method applicable to transistors with aging mechanisms of bias temperature instability (BTI) and hot carrier degradation (HCD). The analytical model of the present invention calculates the stress of the internal transistors based on statistical dynamic information such as duty cycle (DF) and toggle rate (TR) obtained from gate-level simulation. The analytical formula used is automatically generated through transistor-level logic simulation and supports stress analysis for different aging mechanisms.

[0005] To achieve the above objectives, this invention provides a method for calculating transistor aging stress based on an analytical model, comprising the following steps:

[0006] Obtain the SPICE netlist of the standard cell, parse out the inputs and input ports as well as each internal node, and prepare the simulation configuration;

[0007] Perform static logic analysis, traverse all possible input combinations, and obtain the analytical expression for static aging stress;

[0008] Perform transient flip analysis, iterate through all combinations of other inputs for each input during the flip, and obtain the analytical expression for dynamic aging stress.

[0009] Based on the analytical expressions for static aging stress and dynamic aging stress, and the duty cycle and toggle rate of each standard cell input obtained from gate-level simulation, the degradation amount of different transistors inside the standard cell under different degradation mechanisms is calculated.

[0010] Further, obtain the SPICE netlist of the standard cell, parse out the inputs and input ports as well as each internal node, and prepare the simulation configuration, specifically including the following steps:

[0011] Analyze the netlist to identify the input and output pins;

[0012] Parse the names of the internal nodes and create the corresponding data structures;

[0013] The name of each transistor is parsed, the node to which the source, drain, and gate are connected is determined, and the data structure is created.

[0014] Based on the type of aging stress to be analyzed specified by the user, aging stress conditions are created. For example, NBTI means the source and drain are at high levels and the gate is at low levels; HCD means a short-circuit current flows through it.

[0015] Furthermore, static logic analysis is performed on all inputs to obtain the analytical expression of static aging stress. Specifically, this involves traversing all inputs to obtain the truth table of each node, and generating the analytical expression of static aging stress based on this table.

[0016] Furthermore, the analytical formula for static aging stress includes negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI); these are the main degradation of PMOS and NMOS, respectively. NBTI occurs when the gate voltage of PMOS is low and the source / drain voltage is high; PBTI occurs when the gate voltage of NMOS is high and the source / drain voltage is low.

[0017] Furthermore, the analytical expression of NBTI is based on static logic simulation, obtaining a truth table for each possible input. The number of simulations for a unit with input n is 2^n. n Next, at this time, as long as the input is low and the source / drain is high, it is determined to be an NBTI stress state.

[0018] Furthermore, the analytical expression of NBTI specifically includes:

[0019] First, based on the NBTI stress conditions in the truth table, write the logical expression that the current transistor will cause NBTI aging.

[0020] Based on the logical expression, the corresponding probability calculation formula is derived. That is, the positive / negative value of each input in the logical expression is converted into the probability of that input being positive / negative in the probability calculation formula.

[0021] Furthermore, the analytical formula for dynamic aging stress calculates the total number of flip-flops based on the flip-flop rate information and clock cycle provided by the gate-level simulation. Then, it calculates the number of times each transistor experiences saturation current based on the logic formula for charging and discharging each transistor obtained from the truth table. Based on timing analysis, it obtains the output conversion time of the current standard cell. The number of times saturation current occurs is multiplied by the time of each occurrence (approximately half of the output conversion time) to obtain the HCD stress time of the design in the total lifetime.

[0022] Furthermore, the process of obtaining the logical expression based on the simulation results is a typical two-level logic synthesis algorithm. Each row of input combinations in the table corresponds to an expression. By adding all the stress-causing expressions together and then simplifying, the final logical expression can be obtained.

[0023] Furthermore, the analytical method for calculating the stress duty cycle SP is to transform the logical expression into the probability of the combination contained in the logical expression. When each input is independent, the joint probability is calculated using the input duty cycle DF.

[0024] Furthermore, considering the floating state, the complete BTI stress bias condition is: low gate voltage, high source / drain voltage, or floating state.

[0025] Technical effect

[0026] The present invention provides a transistor aging stress calculation method based on an analytical model. The analytical model is used to calculate the aging stress of each transistor, avoiding long-term SPICE simulation and extremely time-consuming and storage-intensive waveform recording. It can calculate the degradation amount of each transistor in large-scale digital circuits under different degradation mechanisms.

[0027] The following will further explain the concept, specific structure, and technical effects of the present invention in conjunction with the accompanying drawings, so as to fully understand the purpose, features, and effects of the present invention. Attached Figure Description

[0028] Figure 1 This is a schematic diagram of an NBTI stress calculation analytical expression generation method, which is a preferred embodiment of the present invention, for calculating transistor aging stress based on an analytical model.

[0029] Figure 2 This is a schematic diagram of a PBTI stress calculation analytical expression generation method, which is a preferred embodiment of the present invention, for calculating transistor aging stress based on an analytical model.

[0030] Figure 3 This is a schematic diagram of an analytical formula generation method for NBTI stress calculation considering floating state stress, which is a preferred embodiment of the present invention for calculating transistor aging stress based on an analytical model.

[0031] Figure 4 This is a schematic diagram of an HCD stress calculation analytical formula generation method for a preferred embodiment of the present invention, which is a transistor aging stress calculation method based on an analytical model. Detailed Implementation

[0032] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.

[0033] In the following description, specific details, such as particular internal procedures and techniques, are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of the invention. However, those skilled in the art will appreciate that the invention may be practiced in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of the invention with unnecessary detail.

[0034] This invention provides a method for calculating transistor aging stress based on an analytical model, comprising the following steps:

[0035] Step 100: Obtain the SPICE netlist of the standard cell, parse out the inputs and input ports as well as each internal node, and prepare the simulation configuration;

[0036] Step 200: Perform static logic analysis, traverse all input combinations, and obtain the analytical expression of static aging stress;

[0037] Step 300: Perform transient flip analysis, iterate through all combinations of other inputs during the flip of each input, and obtain the analytical expression of dynamic aging stress;

[0038] Step 400: Based on the analytical expressions for static aging stress and dynamic aging stress, and the duty cycle and toggle rate of each standard cell input obtained from gate-level simulation, calculate the degradation amount of different transistors inside the standard cell under different degradation mechanisms.

[0039] Step 100 involves obtaining the SPICE netlist of the standard cell, parsing out the inputs, input ports, and each internal node, and preparing the simulation configuration. This includes the following steps:

[0040] Analyze the netlist to identify the input and output pins;

[0041] Parse the names of the internal nodes and create the corresponding data structures;

[0042] The name of each transistor is parsed, the node to which the source, drain, and gate are connected is determined, and the data structure is created.

[0043] Based on the type of aging stress to be analyzed specified by the user, aging stress conditions are created. For example, NBTI means the source and drain are at high levels and the gate is at low levels; HCD means a short-circuit current flows through it.

[0044] Step 200: Perform static logic analysis, traverse all possible input combinations, and obtain the analytical expression of static aging stress. Specifically, this includes traversing all inputs, obtaining the truth table of each node, and generating the analytical expression of static aging stress based on this.

[0045] Among them, the analytical formula for static aging stress includes negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI); these are the main degradation of PMOS and NMOS, respectively. NBTI occurs when the gate voltage of PMOS is low and the source-drain voltage is high; PBTI occurs when the gate voltage of NMOS is high and the source-drain voltage is low.

[0046] The analytical expression of NBTI is based on static logic simulation, which yields a truth table for every possible input. The number of simulations for a unit with input n is 2^n. n Next, at this time, as long as the input is low and the source / drain is high, it is determined to be an NBTI stress state.

[0047] The specific analytical expressions of NBTI include:

[0048] First, based on the NBTI stress conditions in the truth table, write the logical expression that the current transistor will cause NBTI aging.

[0049] Based on the logical expression, the corresponding probability calculation formula is derived. That is, the positive / negative value of each input in the logical expression is converted into the probability of that input being positive / negative in the probability calculation formula.

[0050] The analytical formula for dynamic aging stress calculates the total number of flip-flops based on the flip-flop rate information and clock cycle provided by gate-level simulation. Then, it calculates the number of times each transistor experiences saturation current based on the truth table's charging and discharging logic. Timing analysis yields the output transition time of the current standard cell. The number of saturation current occurrences multiplied by the time of each occurrence (approximately half the output transition time) gives the HCD stress time over the total lifespan of the design. The process of deriving the logic expression from the simulation results is a typical two-level logic synthesis algorithm. Each row of input combinations in the table corresponds to an expression. Adding all stress-causing expressions and simplifying yields the final logic expression. The analytical method for calculating the stress duty cycle (SP) involves transforming the logic expression into the probability of the combinations it contains. When each input is independent, the joint probability is calculated using the input duty cycle (DF).

[0051] The embodiments of the present invention also include, after considering the floating state, the complete BTI stress bias condition is: the gate is at a low voltage, and the source and drain are at a high voltage or in a floating state.

[0052] The transistor aging stress calculation method based on an analytical model proposed in this invention is applicable to the aging mechanisms of bias temperature instability (BTI) and hot carrier degradation (HCD), which are the main mechanisms of transistor degradation under current processes. BTI aging stress is a static stress, resulting from the longitudinal electric field caused by voltage bias; HCD aging stress is a dynamic stress, resulting from the saturation current in the channel when the transistor is in the on-state.

[0053] Different aging mechanisms have different bias conditions. BTI is divided into NBTI and PBTI, which are the main degradation of PMOS and NMOS, respectively. NBTI occurs when the gate voltage of PMOS is low and the source-drain voltage is high; PBTI occurs when the gate voltage of NMOS is high and the source-drain voltage is low. HCD occurs when the output load is charged and discharged due to input switching. The transistors through which the charging and discharging path passes will carry saturation current, causing hot carrier injection.

[0054] First, this embodiment introduces a method for analytically generating BTI stress. In digital circuits, the waveform can be approximated as a square wave, and voltage and temperature can be considered global parameters. Therefore, BTI degradation mainly depends on the stress probability (SP) of each transistor, i.e., the proportion of time spent in a stress state to the total time. For example... Figure 1 The diagram illustrates an analytical method for calculating the NBTI stress duty cycle in a NOR3 standard cell. Based on static logic simulation, a truth table can be obtained for each possible input. Static logic simulation is essentially a DC simulation in the SPICE simulation mode. It obtains the voltage value of each internal node based on the netlist and input port values ​​of the standard cell, and then fills the corresponding positions in the truth table with this value. A cell with n input ports can have 2 possible input combinations. n The number of simulations was 2. n Second-rate, Figure 1 The diagram shows 8 iterations. If the input (gate) of a transistor is low and the source / drain is high, it is considered an NBTI stress state. For example, the logical expression for the stress states of transistors MP1, MP2, and MP3 can be written as:

[0055]

[0056] The process of deriving the logical expression from the simulation results is a typical two-level logic synthesis algorithm. Each row of input combinations in the table corresponds to an expression, such as the first row. The second line is By adding all the stress-causing expressions and then simplifying, we can obtain the final logical expression. For example, the logical expression for MP1, which is obtained by adding the rows in the table that contain stress, can be written as:

[0057]

[0058] After simplification, the most concise logical expression can be obtained as follows: The simplification method draws on algorithms commonly used in two-level logic synthesis, including the Quine-McCluskey algorithm and heuristic algorithms. The method proposed in this patent requires only a correct logical expression at this step, not the most concise and correct logical expression; therefore, a simple heuristic algorithm suffices.

[0059] The method for generating the corresponding probability calculation expression, i.e., the analytical expression for calculating the stress duty cycle SP, based on the logical expression is to transform the logical expression into the probability of the combinations contained in the logical expression. For example, the logical expression for stress MP1 is... The corresponding probability expression is the probability P(A1=0) that the input A1 is 0. Following this correspondence rule, the following probability expression is generated:

[0060] SP(MP1)=P(A1=0)

[0061] SP(MP2) = P(A1 = 0, A2 = 0)

[0062] SP(MP3)=P(A1=0,A2=0,A3=0)

[0063] Assuming each input is independent, the joint probability can be calculated using the input's duty cycle (DF):

[0064] P(A1=0,A2=0,A3=0)

[0065] =(1-DF(A1))×(1-DF(A2))×(1-DF(A3))

[0066] Therefore, the expression for calculating the stress duty cycle of each internal transistor based on the duty cycle of the input port is:

[0067] SP(MP1)=1-DF(A1)

[0068] SP(MP2)=(1-DF(DF1))×(1-DF(A2))

[0069] SP(MP3)=(1-DF(A1))×(1-DF(A2))×(1-DF(A3))

[0070] like Figure 2The diagram illustrates the method for generating analytical stress calculation formulas using PBTI. The steps are identical to those of the NBTI analytical stress calculation formula generation method in the previous embodiment, except for the different stress determination criteria. All steps following the generation of the corresponding truth table according to the PBTI stress criteria are exactly the same as those for generating the NBTI analytical stress formula.

[0071] like Figure 3 The diagram illustrates an analytical method for generating BTI stress considering the floating effect. The floating effect occurs in the stacked structure, and its stress condition is a low input level and a floating source / drain state F (undetermined state X). Considering the floating effect, the BTI stress requires an additional term: the case where the gate is at a low voltage and the source / drain is in a floating state. That is, considering the floating state, the complete BTI stress bias condition is: a low gate voltage and either a high source / drain voltage or a floating state.

[0072] To identify BTI stress that takes into account the buoyancy effect, the truth table needs to be expanded to include the states of all nodes. The rows in the table that match the stress need to be identified. For example, MP2 has three rows with stress, and its logical expression can be written as:

[0073]

[0074] After simplification, we can obtain:

[0075]

[0076] This logical expression can be transformed into the corresponding probability calculation formula as follows:

[0077] SP(MP2)=P(A1=0,A2=0)+P(A1=1,A2=0,A3=1)

[0078] This formula means that when the input is low and the source is either floating or high, the calculated probability is the probability of BTI stress occurring after taking the floating effect into account.

[0079] Based on the assumption of input independence, the joint probability can be rewritten as the product of the independent probabilities:

[0080] SP(MP2)=(1-DF(A1))×(1-DF(A2))+DF(A1)×(1-DF(A2))

[0081] ×DF(A3)

[0082] The aging stress duty cycle of the internal crystal can be calculated using the input duty cycle.

[0083] Since MP1 and MP3 are not in a floating state because their sources are not connected to power or output, the stress duty cycle calculation is the same as the method that does not consider the floating effect.

[0084] Figure 4 An analytical method for generating HCD stress is demonstrated. HCD occurs when a transistor experiences saturation current. After circuit implementation, the input and output transition times of internal cells are essentially determined, and the saturation current stress time for each charge / discharge cycle can be approximated as half the transition time. Therefore, calculating HCD stress requires determining the statistical number of charge / discharge cycles each transistor will participate in over its lifetime. Gate-level simulation provides toggle rate information, which can be used to calculate the number of charge / discharge cycles. This step requires performing transient toggle logic matrix calculations at each stable state, resulting in a total of n² simulations. n Each simulation condition corresponds to a row in the truth table. If a transistor participates in the charging and discharging path under this simulation condition and there is a saturation current, this row is marked as a stress state.

[0085] like Figure 4 As shown, the first three columns of the table represent steady-state values, and the fourth column represents the flip-flop input for the flip-flop simulation. From Figure 4 As can be seen from the table, MN1 participates in charging and discharging when the input is 000 and A1 flips. Therefore, the HCD logic expression for MN1 can be written as:

[0086]

[0087] Therefore, the stress duty cycle SP can be calculated based on the overturning rate TR of A1:

[0088] SP(MN1)=P(A1=0,A2=0,A3=0)×TR(A1)

[0089] Based on the input independence assumption, it can be transformed into the following formula, calculated based on the input duty cycle and toggle rate:

[0090] SP(MN1)=(1-DF(A1))×91-DF(A2))×(1-DF(A3))×TR(A1) The total HCD stress time can be calculated as:

[0091] t stress (MN1)=t age ×SP(MN1)×transition t ime / 2

[0092] Then, the degradation amount can be calculated based on the device model.

[0093] Similarly, the HCD stress duty cycle of the other transistors can be written out:

[0094] SP(MN2)=(1-DF(A1))×(1-DF(A2))×(1-DF(A3))×TR(A2)

[0095] SP(MN3)=(1-DF(A1))×(1-DF(A2))×(1-DF(A3))×TR(A3)

[0096] SP(MP1) = SP(MP2) = SP(MP3)

[0097] =(DF(A1))×(1-DF(A2))×(1-DF(A3))×TR(A1)

[0098] +(1-DF(A1))×(DF(A2))×(1-DF(A3))×TR(A2)

[0099] +(1-DF(A1))×(1-DF(A2))×(DF(A3))×TR(A3) and calculate the total degradation time based on the corresponding output conversion time.

[0100] The preferred embodiments of the present invention have been described in detail above. It should be understood that those skilled in the art can make numerous modifications and variations based on the concept of the present invention without creative effort. Therefore, all technical solutions that can be obtained by those skilled in the art based on the concept of the present invention through logical analysis, reasoning, or limited experimentation on the basis of existing technology should be within the scope of protection defined by the claims.

Claims

1. A method for calculating transistor aging stress based on an analytical model, characterized in that, Includes the following steps: Obtain the SPICE netlist of the standard cell, parse out the inputs and input ports as well as each internal node, and prepare the simulation configuration; Static logic analysis is performed, traversing all input combinations to obtain the analytical expression for static aging stress. The analytical expression for static aging stress includes negative bias temperature instability (NBTI) and positive bias temperature instability (PBTI), which are the main degradation of PMOS and NMOS, respectively. NBTI occurs when the gate voltage of PMOS is low and the source / drain voltage is high; PBTI occurs when the gate voltage of NMOS is high and the source / drain voltage is low. Transient flip-over analysis is performed, iterating through all combinations of other inputs during each flip-over to obtain the analytical expression of dynamic aging stress. The analytical expression of dynamic aging stress is calculated based on the flip-over rate information provided by gate-level simulation and the clock cycle to calculate the total number of flip-overs. Then, the logic expression for charging and discharging of each transistor is obtained from the truth table to calculate the number of times each transistor experiences saturation current. The output conversion time of the current standard cell is obtained based on timing analysis. The number of times saturation current occurs is multiplied by the time of each occurrence to obtain the HCD stress time. Based on the analytical expressions for static and dynamic aging stress, and the duty cycle and toggle rate of each standard cell input obtained from gate-level simulation, the degradation amount of different transistors within the standard cell under different degradation mechanisms is calculated; the specific method for generating the analytical expression of the NBTI stress of each transistor within the standard cell includes: First, based on the NBTI stress situation in the truth table, write the logical expression that the current transistor will cause NBTI aging; The logical expression is transformed into the probability of the combination contained in the logical expression. When each input is independent, the joint probability is calculated using the duty cycle DF of the input.

2. The transistor aging stress calculation method based on an analytical model as described in claim 1, characterized in that, Obtain the SPICE netlist of the standard cell, parse out the inputs, input ports, and each internal node, and prepare the simulation configuration. This includes the following steps: Analyze the SPICE netlist to identify the input / output pins; Parse the names of the internal nodes and create the corresponding data structures; The name of each transistor is parsed, the node to which the source, drain, and gate are connected is determined, and the data structure is created. Based on the user-specified type of aging stress to be analyzed, aging stress conditions are created, including NBTI and HCD. NBTI is when the source and drain are high and the gate is low; HCD is when a short-circuit current flows.

3. The transistor aging stress calculation method based on an analytical model as described in claim 1, characterized in that, The analytical expression of NBTI is derived from static logic simulation, yielding a truth table for each possible input. The number of simulation iterations for a unit with input n is 2^n. n Next, at this time, as long as the input is low and the source / drain is high, it is determined to be an NBTI stress state.

4. The transistor aging stress calculation method based on an analytical model as described in claim 3, characterized in that, The process of obtaining the logical expression based on the simulation results is a typical two-level logic synthesis algorithm. Each row of input combinations in the table corresponds to an expression. By adding all the stress-causing expressions together and then simplifying, the final logical expression can be obtained.

5. The transistor aging stress calculation method based on an analytical model as described in claim 1, characterized in that, It also includes the complete BTI stress bias condition after considering the floating state: the gate is at a low voltage, and the source and drain are at a high voltage or in a floating state.

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