Differential circuit

Abstract

This invention discloses a differential circuit, comprising: an input pair, a first load, an adjustment circuit, a current generation circuit, and a mobility follower circuit. The adjustment circuit includes: a constant transconductance bias circuit, a current generation circuit, and a mobility follower circuit. The constant transconductance bias circuit generates a bias current; the current generation circuit generates a compensation current, including a reference circuit for generating one or more compensation currents or a compensation current generation circuit for generating one or more compensation currents based on the bias current; the mobility follower circuit generates an adjustment current based on the bias current and the compensation current, or generates an adjustment current based on the bias current and the compensation current. According to the differential circuit of this invention, by using the adjustment current as the bias current of the input pair and the calibration input current at the output of the differential circuit, zero-temperature-drift offset voltage can be achieved in the differential circuit, and low offset voltage can be achieved across the entire temperature range.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits, and more particularly to a differential circuit. Background Technology

[0002] In differential circuits, random offset voltages exist at the input terminals due to device (load) mismatches. Existing solutions use trimming to reduce this input offset voltage; however, trimming only reduces offset voltage at room temperature and cannot achieve low-temperature offset voltage reduction across the entire temperature range.

[0003] The information disclosed in this background section is intended only to enhance the understanding of the overall background of the invention and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0004] The purpose of this invention is to provide a differential circuit that can achieve low temperature drift offset voltage across the entire temperature range.

[0005] To achieve the above objectives, embodiments of the present invention provide a differential circuit, including: a set of input transistors, a pair of first loads, and an adjustment circuit.

[0006] A pair of input transistors has a pair of input terminals, a pair of first terminals, and a pair of second terminals. The pair of input terminals of the input transistors is used to receive differential signals, and the pair of first terminals of the input transistors is used to output signals.

[0007] A pair of first loads are connected to a pair of first terminals of the input transistors;

[0008] A regulating circuit is used to generate a regulating current supplied to the first and / or second terminals of the input pair transistors;

[0009] The regulating circuit includes: one or more constant transconductance bias circuits, a current generation circuit, and a mobility follower circuit.

[0010] One or more constant transconductance bias circuits are used to generate bias current;

[0011] The current generating circuit includes a reference circuit for generating one or more compensation currents or a compensation current generating circuit for generating one or more compensation currents based on a bias current.

[0012] Mobility follower circuits are used to generate a regulating current based on bias current and compensation current, or based on bias current and compensation current.

[0013] In one or more embodiments of the present invention, the constant transconductance bias circuit includes a first current mirror, a third MOSFET, a fourth MOSFET, and a third resistor. The first terminal of the third resistor is connected to the drain of the third MOSFET and the gate of the fourth MOSFET. The second terminal of the third resistor is connected to the gate of the third MOSFET and the first current mirror. The drain of the fourth MOSFET is connected to the first current mirror. The sources of the third MOSFET and the fourth MOSFET are connected to the power supply voltage.

[0014] In one or more embodiments of the present invention, the differential circuit further includes a second current mirror connected to a constant transconductance bias circuit and a mobility follower circuit, the second current mirror being used to deliver a bias current to the mobility follower circuit.

[0015] In one or more embodiments of the present invention, the constant transconductance bias circuit includes a first current mirror, a third current mirror, and a third resistor, wherein the first current mirror and the third current mirror are connected together, a first terminal of the third resistor is connected to the first current mirror, and a second terminal of the third resistor is connected to a reference voltage.

[0016] In one or more embodiments of the present invention, the constant transconductance bias circuit includes a first current mirror, a third current mirror, and a third resistor. The first current mirror and the third current mirror are connected together. The first end of the third resistor is connected to the third current mirror, and the second end of the third resistor is connected to the power supply voltage.

[0017] In one or more embodiments of the present invention, the compensation current generating circuit includes a tenth MOS transistor, an eleventh MOS transistor, a fourth resistor, and a fourth current mirror. The drain of the tenth MOS transistor is connected to the gate of the eleventh MOS transistor to receive bias current. The gate of the tenth MOS transistor is connected to the source of the eleventh MOS transistor and the first terminal of the fourth resistor. The second terminal of the fourth resistor is connected to the source of the tenth MOS transistor and a reference voltage. The fourth current mirror is connected to the drain of the eleventh MOS transistor. The fourth current mirror is used to generate one or more compensation currents.

[0018] In one or more embodiments of the present invention, the differential circuit further includes a calculation circuit connected to the current generation circuit and the mobility follower circuit, the calculation circuit being used to perform calculations on the compensation current and transmit the calculation results to the mobility follower circuit.

[0019] In one or more embodiments of the present invention, the computing circuit includes a first computing circuit and a second computing circuit;

[0020] The first computing circuit includes a fifth current mirror and a sixth current mirror connected together, the fifth current mirror and the sixth current mirror being used to receive compensation current and generate an operational current proportional to the sum of the compensation currents.

[0021] The second computing circuit includes a seventh current mirror, an eighth current mirror, a ninth current mirror, and a tenth current mirror. The seventh and eighth current mirrors are connected to the ninth current mirror, and the tenth current mirror is connected to the ninth current mirror. The seventh and eighth current mirrors are used to receive and transmit compensation currents respectively, and the ninth and tenth current mirrors are used to generate an operational current that is proportional to the difference between the compensation currents.

[0022] In one or more embodiments of the present invention, the mobility follower circuit includes an eleventh current mirror, a twelfth current mirror, and a second load. The eleventh current mirror is connected to the twelfth current mirror to receive the operational current between the compensation currents and output an adjustment current. The twelfth current mirror also receives the bias current and is simultaneously connected to the second load to output the operational current between the compensation currents.

[0023] In one or more embodiments of the present invention, the mobility follower circuit includes a thirteenth current mirror, a fourteenth current mirror, a fifteenth current mirror, a sixteenth current mirror, a seventeenth current mirror, and a third load. The thirteenth current mirror is used to receive a bias current. The fourteenth current mirror is connected to the thirteenth current mirror. The fifteenth current mirror is connected to the fourteenth current mirror. The first terminal of the third load is connected to the fifteenth current mirror. The second terminal of the third load is connected to a reference voltage. The sixteenth current mirror is connected to the fifteenth current mirror and is used to receive a compensation current. The seventeenth current mirror is connected to the fourteenth, fifteenth, and sixteenth current mirrors and outputs a regulating current.

[0024] In one or more embodiments of the present invention, the differential circuit further includes an eighteenth current mirror for proportionally replicating the regulating current to deliver to the first and / or second terminals of the input pair transistors.

[0025] Compared with the prior art, the differential circuit according to the embodiments of the present invention generates a bias current through a constant transconductance bias circuit, generates a compensation current through a current generation circuit, and generates an adjustment current based on the bias current and the compensation current through a mobility follower circuit. The adjustment current is used as the bias current of the input pair transistors and the calibration input current of the differential circuit output terminal. This can achieve zero temperature drift offset voltage in the differential circuit and low offset voltage over the entire temperature range. Attached Figure Description

[0026] Figure 1 This is a circuit diagram of the differential circuit according to the present invention.

[0027] Figure 2 This is a circuit diagram of the constant transconductance bias circuit and the second current mirror according to Embodiment 1 of the present invention.

[0028] Figure 3 This is a circuit diagram of the current generating circuit according to Embodiment 1 of the present invention.

[0029] Figure 4 This is a circuit diagram of the first computing circuit according to Embodiment 1 of the present invention.

[0030] Figure 5 This is a circuit diagram of the second computing circuit according to Embodiment 1 of the present invention.

[0031] Figure 6 This is a circuit schematic diagram of a mobility follower circuit according to Embodiment 1 of the present invention.

[0032] Figure 7 This is a circuit diagram of the eighteenth current mirror according to Embodiment 1 of the present invention.

[0033] Figure 8 This is a circuit diagram of the constant transconductance bias circuit, the second current mirror, and the compensation current generation circuit according to Embodiment 2 of the present invention.

[0034] Figure 9 This is a circuit diagram of the constant transconductance bias circuit and the second current mirror according to Embodiment 3 of the present invention.

[0035] Figure 10 This is a circuit diagram of the constant transconductance bias circuit and the second current mirror according to Embodiment 4 of the present invention.

[0036] Figure 11 This is a circuit schematic diagram of the mobility follower circuit according to Embodiment 5 of the present invention. Detailed Implementation

[0037] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings, but it should be understood that the scope of protection of the present invention is not limited to the specific embodiments.

[0038] Unless otherwise expressly stated, throughout the specification and claims, the term "comprising" or its variations such as "including" or "comprises" shall be understood to include the stated elements or components without excluding other elements or other components.

[0039] The terms "coupled," "connected," or "linked" in this specification include both direct and indirect connections. An indirect connection is a connection made through an intermediate medium, such as an electrical conduction medium, which may have parasitic inductance or capacitance. Indirect connections may also include connections made through other active or passive devices to achieve the same or similar functional purpose, such as connections through switches, follower circuits, or other circuits or components. Furthermore, in this invention, terms such as "first" and "second" are primarily used to distinguish one technical feature from another, and do not necessarily require or imply any actual relationship, quantity, or order between these technical features.

[0040] Example 1

[0041] like Figure 1 As shown, in a differential circuit with a resistive load, the formula for the input offset voltage is:

[0042]

[0043] in, I D This represents the current on either the first MOSFET M1 or the second MOSFET M2, g m Indicates the transconductance of the first MOSFET M1 or the second MOSFET M2, ΔV TH Let C be the difference in threshold voltage between the first MOSFET M1 and the second MOSFET M2, μ be the semiconductor mobility of the first MOSFET M1 and the second MOSFET M2, and C be the threshold voltage difference between the first MOSFET M1 and the second MOSFET M2. ox The gate oxide capacitance per unit area of ​​either the first MOSFET M1 or the second MOSFET M2. The width-to-length ratio of the first MOSFET M1 or the second MOSFET M2.

[0044] In a calibrated differential circuit, ΔI D It consists of two parts. One part is the current mismatch caused by device (resistor) mismatch, denoted as I. DM The other part is the current introduced by calibration to compensate for the offset voltage, denoted as I. T ,but

[0045] ΔI D =ΔI DM +ΔI T

[0046] Substituting into the formula for input offset voltage:

[0047]

[0048] The relationship between input offset voltage and temperature is as follows:

[0049]

[0050] Where, ΔV TH It is almost unrelated to temperature.

[0051] It can be expanded as follows:

[0052]

[0053] therefore, It depends on the parameters of the device itself and is almost independent of temperature.

[0054] Without introducing calibration, Through the formula:

[0055] I D R2=(I D +ΔI DM (R2+ΔR0)

[0056] achievable

[0057]

[0058] ΔR0 represents the resistance change caused by circuit mismatch across the second resistor R2. This is caused by a mismatch in the resistor itself and is almost unrelated to temperature.

[0059] Therefore, retaining the principal term in the formula, the relationship between input offset voltage and temperature can be simplified to:

[0060]

[0061] As can be seen from the formula, the temperature coefficient of the offset voltage is mainly determined by two parts: one is the ratio of the current to the transconductance of the circuit itself. Secondly, the ratio of current to transconductance added to the circuit is calibrated. Furthermore, the mismatch in the circuit itself is random, so Δβ and ΔR0 can be positive or negative, and ΔI T The direction is determined by the calibration position, and the direction is fixed. When the temperature coefficient is not processed, calibration will increase the temperature coefficient of the offset voltage.

[0062] Therefore, to reduce the temperature coefficient of the offset voltage of the entire circuit, it is necessary to design I... D and ΔI T Following the transconductance g of the first MOSFET M1 and / or the second MOSFET M2 m The changes made and It is unrelated to temperature.

[0063] like Figure 1As shown, the present invention discloses a differential circuit, including: a set of input transistors, a pair of first loads 10a and 10b, and an adjustment circuit 20.

[0064] In this setup, an input pair of transistors has a pair of input terminals, a pair of first terminals, and a pair of second terminals. The pair of input terminals of the input pair is used to receive differential signals, and the pair of first terminals of the input pair is used to output signals. Specifically, the input pair includes a first MOSFET M1 and a second MOSFET M2. The gates of the first MOSFET M1 and the second MOSFET M2 form a pair of input terminals, the drains of the first MOSFET M1 and the second MOSFET M2 form a pair of output terminals, and the sources of the first MOSFET M1 and the second MOSFET M2 form a pair of second terminals. In other embodiments, the first MOSFET M1 and the second MOSFET M2 can be P-channel MOSFETs.

[0065] A pair of first loads 10a and 10b are connected to a pair of first terminals of the input transistor pair. Specifically, the pair of first loads 10a and 10b includes a first resistor R1 and a second resistor R2. The first terminal of the first resistor R1 and the first terminal of the second resistor R2 are connected to the power supply voltage VDD. The second terminal of the first resistor R1 is connected to the drain of the first MOSFET M1, and the second terminal of the second resistor R2 is connected to the drain of the second MOSFET M2. In other embodiments, the first resistor R1 and the second resistor R2 can also be replaced by diodes or MOSFETs connected in a diode configuration.

[0066] like Figure 1 As shown, the regulating circuit 20 is used to generate a regulating current supplied to the first and second terminals of the input pair transistors. Specifically, the regulating circuit 20 is connected to the drain and source of the first MOSFET M1 and the second MOSFET M2 to supply the regulating current. In other embodiments, the regulating circuit 20 may only supply the regulating current to the first or second terminal of the input pair transistors for regulation.

[0067] In one embodiment, the adjustment circuit 20 includes: a constant transconductance bias circuit, a current generation circuit, and a mobility follower circuit.

[0068] like Figure 2 As shown, the constant transconductance bias circuit is used to generate the bias current Ib. The constant transconductance bias circuit includes a first current mirror 21, a third MOSFET M3, a fourth MOSFET M4, and a third resistor R3. The width-to-length ratio of the third MOSFET M3 and the fourth MOSFET M4 is k:1, where k is greater than 0, and k can be set as needed.

[0069] The first end of the third resistor R3 is connected to the drain of the third MOSFET M3 and the gate of the fourth MOSFET M4. The second end of the third resistor R3 is connected to the gate of the third MOSFET M3 and the first current mirror 21. The drain of the fourth MOSFET M4 is connected to the first current mirror 21. The source of the third MOSFET M3 and the source of the fourth MOSFET M4 are connected to the power supply voltage VDD.

[0070] In one embodiment, the first current mirror 21 includes a fifth MOSFET M5 and a sixth MOSFET M6. The drain of the fifth MOSFET M5 is connected to the second terminal of the third resistor R3. The gate and drain of the sixth MOSFET M6 are connected to the drain of the fourth MOSFET M4. The gate of the fifth MOSFET M5 is connected to the gate of the sixth MOSFET M6. In other embodiments, the third MOSFET M3 and the fourth MOSFET M4 can also be N-channel MOSFETs, and the fifth MOSFET M5 and the sixth MOSFET M6 can also be P-channel MOSFETs.

[0071] like Figure 2 As shown, the differential circuit also includes a second current mirror 30 connected to the constant transconductance bias circuit and the mobility follower circuit. The second current mirror 30 is used to deliver the bias current Ib to the mobility follower circuit.

[0072] The second current mirror 30 includes a seventh MOSFET M7, an eighth MOSFET M8, and a ninth MOSFET M9. The gate of the seventh MOSFET M7 is connected to the drain of the fourth MOSFET M4, the source of the seventh MOSFET M7 is connected to a reference voltage, the drain of the seventh MOSFET M7 is connected to the drain of the eighth MOSFET M8, the gate of the eighth MOSFET M8 is connected to both its drain and the gate of the ninth MOSFET M9, the sources of the eighth MOSFET M8 and the ninth MOSFET M9 are connected to the power supply voltage VDD, and the drain of the ninth MOSFET M9 is connected to a migration follower circuit to output a bias current Ib. In other embodiments, the eighth MOSFET M8 and the ninth MOSFET M9 can be N-channel MOSFETs, and the seventh MOSFET M7 can be a P-channel MOSFET. In one embodiment, the reference voltage is ground.

[0073] like Figure 3 As shown, the current generating circuit includes a reference circuit BG for generating one or more compensation currents. In one embodiment, the reference circuit BG generates two compensation currents Ix and Iy. Two reference circuits BG may be provided to generate two compensation currents Ix and Iy respectively.

[0074] The differential circuit also includes a calculation circuit connected to the current generation circuit and the mobility follower circuit. The calculation circuit performs calculations on the compensation currents Ix and Iy and sends the calculation results to the mobility follower circuit. In one embodiment, the calculation circuit includes a first calculation circuit and a second calculation circuit.

[0075] like Figure 4 As shown, the first computing circuit includes a fifth current mirror 41 and a sixth current mirror 42 connected together. The fifth current mirror 41 and the sixth current mirror 42 are used to receive compensation currents Ix and Iy and generate an operational current that is proportional to the sum of the compensation currents Ix and Iy.

[0076] The fifth current mirror 41 includes a tenth MOSFET M10, an eleventh MOSFET M11, and a twelfth MOSFET M12. The tenth MOSFET M10, eleventh MOSFET M11, and twelfth MOSFET M12 are connected via a common gate. The gate and drain of the tenth MOSFET M10 are connected to receive two compensation currents Ix and Iy. The sources of the tenth MOSFET M10, eleventh MOSFET M11, and twelfth MOSFET M12 are all connected to a reference voltage. The width-to-length ratio of the tenth MOSFET M10, eleventh MOSFET M11, and twelfth MOSFET M12 is 1:1:2. The operational current generated on the twelfth MOSFET M12 is twice the sum of the two compensation currents Ix and Iy. In other embodiments, the width-to-length ratio of the tenth MOSFET M10, eleventh MOSFET M11, and twelfth MOSFET M12 can be set to other values ​​according to the required current magnitude. The tenth MOSFET M10, eleventh MOSFET M11, and twelfth MOSFET M12 can be P-channel MOSFETs.

[0077] The sixth current mirror 42 includes a thirteenth MOSFET M13 and a fourteenth MOSFET M14. The sources of both thirteenth and fourteenth MOSFETs M13 and M14 are connected to the power supply voltage VDD. The gates of thirteenth and fourteenth MOSFETs M13 and M14 are connected, as are their drains. The drain of thirteenth MOSFET M13 is connected to the drain of eleventh MOSFET M11. The width-to-length ratio of thirteenth and fourteenth MOSFETs M14 is 1:1. The operational current generated on the fourteenth MOSFET M14 is the sum of the two compensation currents Ix and Iy. In other embodiments, the width-to-length ratio of thirteenth and fourteenth MOSFETs M13 and M14 can be set to other values ​​according to the required current magnitude. N-channel MOSFETs can be used for both thirteenth and fourteenth MOSFETs.

[0078] like Figure 5As shown, the second calculation circuit includes a seventh current mirror 43, an eighth current mirror 44, a ninth current mirror 45, and a tenth current mirror 46. The seventh current mirror 43 and the eighth current mirror 44 are connected to the ninth current mirror 45, and the tenth current mirror 46 is connected to the ninth current mirror 45. The seventh current mirror 43 and the eighth current mirror 44 are used to receive and transmit compensation currents Ix and Iy, respectively, and the ninth current mirror 45 and the tenth current mirror 46 are used to generate an operational current that is proportional to the difference between the compensation currents Ix and Iy.

[0079] like Figure 5 As shown, the seventh current mirror 43 includes a fifteenth MOSFET M15 and a sixteenth MOSFET M16. The sources of both the fifteenth and sixteenth MOSFETs M15 and M16 are connected to the power supply voltage VDD. The gate and drain of the fifteenth MOSFET M15 are connected to receive a compensation current Ix. The width-to-length ratio of the fifteenth and sixteenth MOSFETs M15 is 1:1. The drain of the sixteenth MOSFET M16 is used to output the compensation current Ix. In other embodiments, the width-to-length ratio of the fifteenth and sixteenth MOSFETs M15 and M16 can be set to other values ​​according to the required current magnitude. The fifteenth and sixteenth MOSFETs M15 and M16 can be N-channel MOSFETs.

[0080] like Figure 5 As shown, the eighth current mirror 44 includes a seventeenth MOSFET M17 and an eighteenth MOSFET M18. The gate of the seventeenth MOSFET M17 is connected to its drain to receive a compensation current Iy, and the gate of the seventeenth MOSFET M17 is connected to the gate of the eighteenth MOSFET M18. The sources of both the seventeenth MOSFET M17 and the eighteenth MOSFET M18 are connected to a reference voltage. The drain of the eighteenth MOSFET M18 is connected to the drain of the sixteenth MOSFET M16. The width-to-length ratio of the seventeenth MOSFET M17 and the eighteenth MOSFET M18 is 1:1, and the drain of the eighteenth MOSFET M18 is used to output the compensation current Iy. In other embodiments, the width-to-length ratio of the seventeenth MOSFET M17 and the eighteenth MOSFET M18 can be set to other values ​​according to the required current magnitude, and the seventeenth MOSFET M17 and the eighteenth MOSFET M18 can be P-channel MOSFETs.

[0081] like Figure 5As shown, the ninth current mirror 45 includes a nineteenth MOSFET M19, a twentieth MOSFET M20, and a twenty-first MOSFET M21. The nineteenth MOSFET M19, twentieth MOSFET M20, and twenty-first MOSFET M21 are connected via a common gate. The gate and drain of the nineteenth MOSFET M19 are connected, and the drain of the nineteenth MOSFET M19 is connected to the drain of the eighteenth MOSFET M18. The sources of the nineteenth MOSFET M19, twentieth MOSFET M20, and twenty-first MOSFET M21 are connected to a reference voltage. The width-to-length ratio of the nineteenth MOSFET M19, twentieth MOSFET M20, and twenty-first MOSFET M21 is 1:1:2. The operating current generated on the twenty-first MOSFET M21 is twice the difference between the two compensation currents Ix and Iy. In other embodiments, the width-to-length ratio of the nineteenth MOSFET M19, twentieth MOSFET M20, and twenty-first MOSFET M21 can be changed according to the required current magnitude. The nineteenth MOSFET M19, the twentieth MOSFET M20, and the twenty-first MOSFET M21 can be P-channel MOSFETs.

[0082] like Figure 5 As shown, the tenth current mirror 46 includes a twenty-second MOSFET M22 and a twenty-third MOSFET M23. The sources of both MOSFETs M22 and M23 are connected to the power supply voltage VDD. MOSFETs M22 and M23 are connected via a common gate. The gate and drain of MOSFET M22 are connected. The drain of MOSFET M22 is connected to the drain of MOSFET M20. The width-to-length ratio of MOSFETs M22 and M23 is 1:1. The operational current output from the drain of MOSFET M23 is the difference between the two compensation currents Ix and Iy. In other embodiments, the width-to-length ratio of MOSFETs M22 and M23 can be changed according to the required current magnitude. MOSFETs M22 and M23 can be N-channel MOSFETs.

[0083] like Figure 6 As shown, the mobility follower circuit is used to generate an adjustment current Iout based on the bias current Ib and the compensation currents Ix and Iy. In one embodiment, the compensation currents Ix and Iy need to be calculated by a calculation circuit first, and the calculated current is then sent to the mobility follower circuit.

[0084] Specifically, the mobility follower circuit includes an eleventh current mirror 51, a twelfth current mirror 52, and second loads 53a, 53b, and 53c. The eleventh current mirror 51 is connected to the twelfth current mirror 52 to receive the operational current generated between the compensation currents Ix and Iy and output the regulating current Iout. The twelfth current mirror 52 also receives the bias current Ib and is connected to the second loads 53a, 53b, and 53c to output the operational current generated between the compensation currents Ix and Iy.

[0085] like Figure 6 As shown, the eleventh current mirror 51 includes a twenty-fourth MOSFET M24 and a twenty-fifth MOSFET M25. The twenty-fourth MOSFET M24 and the twenty-fifth MOSFET M25 are connected in a common-gate configuration. The sources of both the twenty-fourth MOSFET M24 and the twenty-fifth MOSFET M25 are connected to the power supply voltage VDD, and the gate and drain of the twenty-fourth MOSFET M24 are connected. In other embodiments, the twenty-fourth MOSFET M24 and the twenty-fifth MOSFET M25 may be N-channel MOSFETs.

[0086] like Figure 6 As shown, the twelfth current mirror 52 includes a twenty-sixth MOSFET M26, a twenty-seventh MOSFET M27, and a twenty-eighth MOSFET M28. The twenty-sixth MOSFET M26, the twenty-seventh MOSFET M27, and the twenty-eighth MOSFET M28 are connected via a common gate. The drain of the twenty-sixth MOSFET M26 is connected to the drain of the twenty-fourth MOSFET M24 and to the drain of the fourteenth MOSFET M14 of the first computing circuit to receive the operational current generated by the sum of the two compensation currents Ix and Iy. The drain of the twenty-eighth MOSFET M28 is connected to the drain of the twenty-fifth MOSFET M25 and to the drain of the twenty-third MOSFET M23 of the second computing circuit to receive the operational current generated by the subtraction of the two compensation currents Ix and Iy. The gate of the twenty-seventh MOSFET M27 is connected to the drain of the twenty-seventh MOSFET M27, and the drain of the twenty-seventh MOSFET M27 is connected to the drain of the ninth MOSFET M9 of the second current mirror 30 to receive the bias current Ib. In other embodiments, the twenty-sixth MOSFET M26, the twenty-seventh MOSFET M27, and the twenty-eighth MOSFET M28 may be P-channel MOSFETs.

[0087] In one embodiment, three second loads 53a, 53b, and 53c are provided, corresponding to the twenty-ninth MOSFET M29, the thirtieth MOSFET M30, and the thirty-first MOSFET M31, respectively. The gate and drain of the twenty-ninth MOSFET M29 are connected, the gate and drain of the thirtieth MOSFET M30 are connected, and the gate and drain of the thirty-first MOSFET M31 are connected. The drain of the thirtieth MOSFET M30 is connected to the source of the twenty-seventh MOSFET M27. The sources of the twenty-ninth MOSFET M29, the thirtieth MOSFET M30, and the thirty-first MOSFET M31 are all connected to a reference voltage.

[0088] The drain of the 29th MOSFET M29 is connected to the source of the 26th MOSFET M26 and to the drain of the 12th MOSFET M12 of the first computing circuit. The first computing circuit draws an operational current from the node where the drain of the 29th MOSFET M29 is connected to the source of the 26th MOSFET M26. The operational current is twice the sum of the two compensation currents Ix and Iy.

[0089] The drain of the 31st MOSFET M31 is connected to the source of the 28th MOSFET M28 and is also connected to the drain of the 21st MOSFET M21 in the second calculation circuit. The second calculation circuit draws an operational current from the node where the source of the 28th MOSFET M28 and the drain of the 31st MOSFET M31 are connected. The operational current is twice the difference between the two compensation currents Ix and Iy.

[0090] In other embodiments, the twenty-ninth MOSFET M29, the thirtieth MOSFET M30, and the thirty-first MOSFET M31 may be P-channel MOSFETs.

[0091] like Figure 7 As shown, the differential circuit also includes an eighteenth current mirror 60, which is used to proportionally replicate the regulating current Iout to supply the first and second terminals of the input pair transistors. The eighteenth current mirror 60 includes a thirty-second MOSFET M32, a thirty-third MOSFET M33, a thirty-fourth MOSFET M34, and a thirty-fifth MOSFET M35. The thirty-second MOSFET M32, thirty-third MOSFET M33, thirty-fourth MOSFET M34, and thirty-fifth MOSFET M35 are connected in a common-gate configuration, and their sources are connected to a reference voltage. The gate of the thirty-third MOSFET M33 is connected to its drain and also to the drain of the twenty-fifth MOSFET in the mobility follower circuit to receive the regulating current Iout.

[0092] In one embodiment, the drain of the thirty-second MOSFET M32 is connected to the drain of the first MOSFET M1, the drain of the thirty-fourth MOSFET M34 is connected to the drain of the second MOSFET M2, and the drain of the thirty-fifth MOSFET M35 is connected to the source of both the first MOSFET M1 and the second MOSFET M2. The width-to-length ratio of the thirty-second MOSFET M32, the thirty-third MOSFET M33, the thirty-fourth MOSFET M34, and the thirty-fifth MOSFET M35 is m:1:n:w, where m, n, and w are all greater than 0. The values ​​of m, n, and w can be set according to the required magnitude of the adjustment current Iout.

[0093] In other embodiments, the thirty-second MOSFET M32, the thirty-third MOSFET M33, the thirty-fourth MOSFET M34, and the thirty-fifth MOSFET M35 can be P-channel MOSFETs.

[0094] In one embodiment, current following can be achieved through a constant transconductance bias circuit and a mobility follower circuit, as described in the above formula for the input offset voltage. Further expansion yields:

[0095]

[0096] From the above formula, it can be seen that in order to make If it is a constant, then It should be a constant value; the mobility μ is determined by the process and cannot be changed, thus affecting the current I. D I is a function of mobility μ D =n*μ, where n is a constant such that the current I D The current I is proportional to the mobility μ. D For transconductance g m Following.

[0097] In a constant transconductance bias circuit, the bias current Ib varies with temperature, thereby maintaining the transconductance g of the fourth MOSFET M4. m4 The constancy of.

[0098]

[0099] Where R3 is the resistance of the third resistor R3, k is the width-to-length ratio of the fourth MOSFET M4 and the third MOSFET M3, μ4 is the semiconductor mobility of the fourth MOSFET M4, and C ox4 This refers to the gate oxide capacitance per unit area of ​​the fourth MOSFET M4. Let N be the width-to-length ratio of the fourth MOSFET M4. Therefore, the product of the bias current Ib and the mobility μ4 is a constant, denoted as N = Ib * μ4.

[0100] In a mobility follower circuit, the relationship between the output regulation current Iout and the bias current Ib and compensation currents Ix and Iy is as follows:

[0101]

[0102] Will Substituting into the above formula, we get:

[0103]

[0104] Using the adjustment current Iout as I D Substitution From this, we can obtain:

[0105]

[0106] It can be known Only the compensation currents Ix and Iy are temperature-dependent, and their temperature coefficients can be well achieved by the reference circuit BG. By using this adjustment current Iout as the bias current of the differential circuit and the calibration input current, a zero-temperature-drift input offset voltage can be achieved.

[0107] Example 2

[0108] like Figure 8 As shown, in one embodiment, the reference circuit in Embodiment 1 is replaced by a compensation current generation circuit 70. The compensation current generation circuit 70 is used to generate one or more compensation currents Ix and Iy based on the bias current Ib. The bias current Ib can be generated by the constant transconductance bias circuit and the second current mirror 30 in Embodiment 1, or a set of constant transconductance bias circuits and the second current mirror 30 can be added to Embodiment 1. In the second current mirror 30, a MOSFET M9' can be added. The gate of the MOSFET M9' is connected to the gate of the ninth MOSFET M9, and the source of the ninth MOSFET M9 is connected to the power supply voltage VDD. By setting the MOSFET M9', a bias current Ib' can be independently drawn from the drain of the ninth MOSFET M9.

[0109] Specifically, the compensation current generating circuit 70 includes a 36th MOSFET M36, a 37th MOSFET M37, a fourth resistor R4, and a fourth current mirror 71. The drain of the 36th MOSFET M36 is connected to the gate of the 37th MOSFET M37 to receive the bias current Ib. The gate of the 36th MOSFET M36 is connected to the source of the 37th MOSFET M37 and the first terminal of the fourth resistor R4. The second terminal of the fourth resistor R4 is connected to the source of the 36th MOSFET M36 and a reference voltage. The fourth current mirror 71 is connected to the drain of the 37th MOSFET M37 and is used to generate one or more compensation currents. In one embodiment, the fourth current mirror 71 generates two compensation currents Ix and Iy, with the reference voltage being ground.

[0110] The fourth current mirror 71 includes the thirty-eighth MOSFET M38, the thirty-ninth MOSFET M39, and the fortieth MOSFET M40. The thirty-eighth MOSFET M38, the thirty-ninth MOSFET M39, and the fortieth MOSFET M40 are connected via a common gate. The sources of all three MOSFETs are connected to the power supply voltage VDD. The drain of the thirty-eighth MOSFET M38 is connected to its gate and the drain of the thirty-seventh MOSFET M37. The drains of the thirty-ninth MOSFET M39 and the fortieth MOSFET M40 output compensation currents Ix and Iy, respectively. The magnitudes of the compensation currents Ix and Iy can be set by changing the width-to-length ratio of the thirty-eighth MOSFET M38, the thirty-ninth MOSFET M39, and the fortieth MOSFET M40.

[0111] Example 3

[0112] like Figure 9 As shown, the structure of the constant transconductance bias circuit in one embodiment is different from that in Embodiments 1 and 2.

[0113] Specifically, the constant transconductance bias circuit includes a first current mirror 21, a third current mirror 22, and a third resistor R3. The first current mirror 21 and the third current mirror 22 are connected, forming two current branches. The first end of the third resistor R3 is connected to the first current mirror 21, and the second end of the third resistor R3 is connected to the reference voltage, which is the ground voltage.

[0114] The first current mirror 21 includes a fifth MOSFET M5 and a sixth MOSFET M6, and the third current mirror 22 includes a third MOSFET M3 and a fourth MOSFET M4. The third MOSFET M3 and the fourth MOSFET M4 are connected via a common gate, and their sources are both connected to the power supply voltage VDD. The fifth MOSFET M5 and the sixth MOSFET M6 are also connected via a common gate. The gate of the fifth MOSFET M5 is connected to its drain and the drain of the third MOSFET M3, while the drain of the sixth MOSFET M6 is connected to the drain of the fourth MOSFET M4. The source of the fifth MOSFET M5 is connected to a reference voltage, and the source of the sixth MOSFET M6 is connected to the first terminal of the third resistor R3. The second terminal of the third resistor R3 is connected to the reference voltage. The gate of the seventh MOSFET M7 in the second current mirror 30 is connected to the gate of the sixth MOSFET M6.

[0115] Example 4

[0116] like Figure 10 As shown, the structure of the constant transconductance bias circuit in one embodiment is different from that in Embodiments 1, 2 and 3.

[0117] Specifically, the constant transconductance bias circuit includes a first current mirror 21, a third current mirror 22 and a third resistor R3. The first current mirror 21 and the third current mirror 22 are connected, forming two current branches. The first end of the third resistor R3 is connected to the third current mirror 22, and the second end of the third resistor R3 is connected to the power supply voltage VDD.

[0118] The first current mirror 21 includes a fifth MOSFET M5 and a sixth MOSFET M6, and the third current mirror 22 includes a third MOSFET M3 and a fourth MOSFET M4. The third MOSFET M3 and the fourth MOSFET M4 are connected via a common gate. The source of the third MOSFET M3 is connected to the power supply voltage VDD. The source of the fourth MOSFET M4 is connected to the first terminal of the third resistor R3, and the second terminal of the third resistor R3 is connected to the power supply voltage VDD. The gate of the third MOSFET M3 is connected to the drain of the third MOSFET M3.

[0119] The fifth MOSFET M5 and the sixth MOSFET M6 are connected via a common gate. The drain of the fifth MOSFET M5 is connected to the drain of the third MOSFET M3, and the drain of the sixth MOSFET M6 is connected to its gate. The drain of the sixth MOSFET M6 is also connected to the drain of the fourth MOSFET M4. The sources of both the fifth MOSFET M5 and the sixth MOSFET M6 are connected to a reference voltage. The gate of the seventh MOSFET M7 in the second current mirror 30 is connected to the gate of the sixth MOSFET M6.

[0120] Example 5

[0121] like Figure 11 As shown, in one embodiment, a mobility follower circuit with a different structure can be used instead of the mobility follower circuits in embodiments 1 to 4.

[0122] Specifically, the mobility follower circuit includes a thirteenth current mirror 81, a fourteenth current mirror 82, a fifteenth current mirror 83, a sixteenth current mirror 84, a seventeenth current mirror 85, and a third load 86. The thirteenth current mirror 81 is used to receive the bias current Ib. The fourteenth current mirror 82 is connected to the thirteenth current mirror 81, the fifteenth current mirror 83 is connected to the fourteenth current mirror 82, the first terminal of the third load 86 is connected to the fifteenth current mirror 83, and the second terminal of the third load 86 is connected to a reference voltage. In one embodiment, the reference voltage is ground voltage. The sixteenth current mirror 84 is connected to the fifteenth current mirror 83 and is used to receive the compensation current Iin. The seventeenth current mirror 85 is connected to the fourteenth current mirror 82, the fifteenth current mirror 83, and the sixteenth current mirror 84 and outputs the regulating current Iout.

[0123] The thirteenth current mirror includes the forty-first MOSFET M41 and the forty-second MOSFET M42. The forty-first MOSFET M41 and the forty-second MOSFET M42 are connected in a common-gate configuration. The sources of the forty-first MOSFET M41 and the forty-second MOSFET M42 are connected to a reference voltage. The gate and drain of the forty-first MOSFET M41 are connected to receive the bias current Ib. The drain of the forty-second MOSFET M42 is connected to the fourteenth current mirror 82 to output the bias current Ib.

[0124] The fourteenth current mirror 82 includes a forty-third MOSFET M43, a forty-fourth MOSFET M44, and a forty-fifth MOSFET M45. The forty-third MOSFET M43, forty-fourth MOSFET M44, and forty-fifth MOSFET M45 are connected via a common gate, and their sources are all connected to the power supply voltage VDD. The gate of the forty-third MOSFET M43 is connected to its drain and the drain of the forty-second MOSFET M42 to receive a bias current Ib. The drain of the forty-fourth MOSFET M44 is connected to the fifteenth current mirror 83 to output a bias current Ib, and the drain of the forty-fifth MOSFET M45 is connected to both the fifteenth and seventeenth current mirrors 83 to output a bias current Ib. In one embodiment, the width-to-length ratio of the forty-fourth MOSFET M44 and the forty-fifth MOSFET M45 is 1:2.

[0125] The fifteenth current mirror 83 includes a forty-sixth MOSFET M46 and a forty-seventh MOSFET M47. The forty-sixth MOSFET M46 and the forty-seventh MOSFET M47 are connected via a common gate. The gate of the forty-sixth MOSFET M46 is connected to its drain and the drain of the forty-fourth MOSFET M44. The drain of the forty-seventh MOSFET M47 is connected to the drain of the forty-fifth MOSFET M45 and the seventeenth current mirror 85. The source of the forty-sixth MOSFET M46 is connected to the third load 86. The source of the forty-seventh MOSFET M47 is connected to the sixteenth current mirror 84 and simultaneously receives the compensation current Iin. In one embodiment, the compensation current Iin can be the compensation current generated by the reference circuit BG or the compensation current generated by the compensation current generating circuit 70 in conjunction with the constant transconductance bias circuit. The compensation current Iin can be any one of the two compensation currents Ix and Iy.

[0126] The third load 86 includes a forty-eighth MOSFET M48, the gate and drain of which are connected to the source of a forty-sixth MOSFET M46. The source of the forty-eighth MOSFET M48 is connected to a reference voltage. In other embodiments, the forty-eighth MOSFET M48 may be replaced by a diode or a resistor.

[0127] The sixteenth current mirror 84 includes the forty-ninth MOSFET M49 and the fiftieth MOSFET M50. The forty-ninth MOSFET M49 and the fiftieth MOSFET M50 are connected in a common-gate configuration. The drain of the forty-ninth MOSFET M49 is connected to its gate and the source of the forty-seventh MOSFET M47 to receive the compensation current Iin. The sources of both the forty-ninth MOSFET M49 and the fiftieth MOSFET M50 are connected to a reference voltage.

[0128] The seventeenth current mirror 85 includes the fifty-first MOSFET M51 and the fifty-second MOSFET M52. The fifty-first MOSFET M51 and the fifty-second MOSFET M52 are connected in a common-gate configuration. The sources of the fifty-first MOSFET M51 and the fifty-second MOSFET M52 are connected to the power supply voltage VDD. The gate and drain of the fifty-first MOSFET M51 are connected to the drains of the forty-fifth MOSFET M45 and the forty-seventh MOSFET M47. The drain of the fifty-second MOSFET M52 is used to output the regulating current Iout.

[0129] It is important to note that numerous current mirrors appear in the various embodiments. Although corresponding solutions are listed for each current mirror, the architecture of each current mirror is not limited to the listed solutions. In addition to variations resulting from adjusting the channel type of the MOSFET (interchanging N-channel and P-channel MOSFETs), other solutions include cascode current mirrors with multi-layer structures formed by stacking multiple MOSFETs. Furthermore, the width-to-length ratio of the MOSFETs in all current mirrors can be changed according to the required current magnitude.

[0130] The foregoing description of specific exemplary embodiments of the invention is for illustrative and explanatory purposes. These descriptions are not intended to limit the invention to the precise forms disclosed, and it will be apparent that many changes and variations can be made in accordance with the foregoing teachings; the invention can be implemented in other forms, structures, arrangements, proportions, and with other components, materials, and parts. The exemplary embodiments were chosen and described in order to explain the specific principles of the invention and its practical application, thereby enabling those skilled in the art to implement and utilize various different exemplary embodiments and various different choices and modifications of the invention without departing from the scope and spirit of the invention. The scope of the invention is intended to be defined by the claims and their equivalents.

Claims

1. A differential circuit, characterized by The differential circuit comprises: a set of input pair transistors having a pair of input terminals, a pair of first terminals and a pair of second terminals, the pair of input terminals of the input pair transistors being configured to receive a differential signal, the pair of first terminals of the input pair transistors being configured to output a signal; a pair of first loads connected to the pair of first terminals of the input pair transistors; a regulation circuit configured to generate a regulation current to be delivered to the first and / or second terminals of the input pair transistors; the regulation circuit comprises: one or more constant transconductance biasing circuits configured to generate a bias current; a current generating circuit configured to generate a compensation current, the current generating circuit comprising a reference circuit configured to generate one or more compensation currents or comprising a compensation current generating circuit configured to generate one or more compensation currents based on the bias current; a mobility following circuit configured to generate the regulation current based on the bias current and the compensation current or configured to generate the regulation current based on the bias current and the compensation current; the differential circuit further comprises a second current mirror connected to the constant transconductance biasing circuit and the mobility following circuit, the second current mirror being configured to deliver the bias current to the mobility following circuit.

2. The differential circuit of claim 1, wherein, the constant transconductance biasing circuit comprises a first current mirror, a third MOS transistor, a fourth MOS transistor and a third resistor, a first terminal of the third resistor being connected to a drain of the third MOS transistor and a gate of the fourth MOS transistor, a second terminal of the third resistor being connected to a gate of the third MOS transistor and the first current mirror, a drain of the fourth MOS transistor being connected to the first current mirror, a source of the third MOS transistor and a source of the fourth MOS transistor being connected to a power supply voltage.

3. The differential circuit of claim 1, wherein, the constant transconductance biasing circuit comprises a first current mirror, a third current mirror and a third resistor, the first current mirror and the third current mirror being connected, a first terminal of the third resistor being connected to the first current mirror, a second terminal of the third resistor being connected to a reference voltage.

4. The differential circuit of claim 1, wherein, the constant transconductance biasing circuit comprises a first current mirror, a third current mirror and a third resistor, the first current mirror and the third current mirror being connected, a first terminal of the third resistor being connected to the third current mirror, a second terminal of the third resistor being connected to a power supply voltage.

5. The differential circuit of claim 1, wherein, the compensation current generating circuit comprises a tenth MOS transistor, an eleventh MOS transistor, a fourth resistor and a fourth current mirror, a drain of the tenth MOS transistor being connected to a gate of the eleventh MOS transistor to receive the bias current, a gate of the tenth MOS transistor being connected to a source of the eleventh MOS transistor and a first terminal of the fourth resistor, a second terminal of the fourth resistor being connected to a source of the tenth MOS transistor and a reference voltage, the fourth current mirror being connected to a drain of the eleventh MOS transistor, the fourth current mirror being configured to generate one or more compensation currents.

6. The differential circuit of claim 1, wherein, the differential circuit further comprises a calculation circuit connected to the current generating circuit and the mobility following circuit, the calculation circuit being configured to operate on the compensation current and deliver an operation result to the mobility following circuit.

7. The differential circuit of claim 6, wherein, the calculation circuit comprises a first calculation circuit and a second calculation circuit; the first calculation circuit comprises a fifth current mirror and a sixth current mirror connected, the fifth current mirror and the sixth current mirror being configured to receive the compensation current and generate an operation current proportional to a sum of the compensation current; The second calculation circuit comprises a seventh current mirror, an eighth current mirror, a ninth current mirror and a tenth current mirror, the seventh current mirror and the eighth current mirror are connected with the ninth current mirror, the tenth current mirror is connected with the ninth current mirror, the seventh current mirror and the eighth current mirror are used for receiving and transmitting compensation currents respectively, and the ninth current mirror and the tenth current mirror are used for generating an operation current proportional to the difference between the compensation currents.

8. The differential circuit of claim 1, wherein, The mobility follower circuit comprises an eleventh current mirror, a twelfth current mirror and a second load, the eleventh current mirror is connected with the twelfth current mirror to receive the operation current between the compensation currents and output an adjustment current, the twelfth current mirror simultaneously receives a bias current, and the twelfth current mirror is simultaneously connected with the second load to output the operation current between the compensation currents.

9. The differential circuit of claim 1, wherein, The mobility follower circuit comprises a thirteenth current mirror, a fourteenth current mirror, a fifteenth current mirror, a sixteenth current mirror, a seventeenth current mirror and a third load, the thirteenth current mirror is used for receiving a bias current, the fourteenth current mirror is connected with the thirteenth current mirror, the fifteenth current mirror is connected with the fourteenth current mirror, a first end of the third load is connected with the fifteenth current mirror, a second end of the third load is connected with a reference voltage, the sixteenth current mirror is connected with the fifteenth current mirror and used for receiving a compensation current, and the seventeenth current mirror is connected with the fourteenth current mirror, the fifteenth current mirror and the sixteenth current mirror and outputs an adjustment current.

10. The differential circuit of claim 1, wherein, The differential circuit further comprises an eighteenth current mirror, and the eighteenth current mirror is used for proportionally copying the adjustment current to be delivered to the first end and / or the second end of the input pair tube.

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