System and method for broadband distributed amplification

Abstract

This application relates to systems and methods of broadband distributed amplification. An amplification device can include a cell including a first cell and a second cell, and a transmission line including a first line and a second line. The first cell is coupled to the first line and the second cell is coupled to the second line. The first line is configured to provide a first delay related to a delay between the first cell and the second cell. The device also includes a summer including a first input coupled to the first line and a second input coupled to the second line. The summer is configured to provide an output signal.

Description

Technical Field

[0001] This disclosure generally relates to a communication system or data processing system, including but not limited to communication or computing systems that include transmitters, receivers, or analog-to-digital converters (ADCs). Background Technology

[0002] Recent advancements in communication and computing devices demand high data rates. For example, network switches, routers, hubs, or any communication device can exchange data at high speeds (e.g., 1 megabit per second (Mbps) to 100 gigabits per second (Gbps)) to stream data in real time or process large volumes of data seamlessly. High-speed data communication and processing systems (including, but not limited to, analog-to-digital converters, serializers / deserializers (SERDES), Ethernet physical layer (PHY), and optical transceivers) typically deliver high-frequency signals. These high-frequency signals are often amplified and / or buffered at the input and / or output stages. Due to large load capacitance, multistage amplifiers have been used to increase bandwidth. However, some multistage amplifier schemes may exhibit performance limitations at higher frequencies (e.g., above 50 GHz). Summary of the Invention

[0003] In one aspect, this application relates to an apparatus comprising: a plurality of cells including a first cell and a second cell; a plurality of transmission lines including a first line and a second line, wherein the first cell is coupled to the first line and the second cell is coupled to the second line, wherein the first line is configured to provide a first delay related to a delay between the first cell and the second cell; and a summer including a first input coupled to the first line and a second input coupled to the second line, wherein the summer is configured to provide an output signal.

[0004] In another aspect, this application relates to an amplifier in an integrated circuit, the amplifier comprising: a first network including a transmission line and a plurality of cells, each of the cells having a cell input coupled to a node on the transmission line; a plurality of circuits, each of the circuits coupled to a corresponding cell of the cell, wherein at least one of the circuits includes a second network including a capacitor and an inductor; and a summer coupled to the circuits, wherein the summer is configured to provide an output signal, wherein the summer includes at least one transistor having a transconductance inversely related to the quotient of the inductance and the capacitance.

[0005] In another aspect, this application relates to a method for providing an output signal, the method comprising: providing a first signal to a first cell at a first node on an input transmission line; amplifying the first signal to provide a first amplified signal; providing a second signal to a second cell at a second node on the input transmission line, the second signal being delayed by a first delay relative to the first signal; amplifying the second signal to provide a second amplified signal; delaying the first amplified signal relative to the second amplified signal to compensate for the first delay; and summing the first amplified signal and the second amplified signal to provide the output signal. Attached Figure Description

[0006] The various objectives, aspects, features, and advantages of this disclosure will become more apparent and better understood through a detailed description taken in conjunction with the accompanying drawings. In the drawings, similar reference numerals generally indicate equal, functionally similar, and / or structurally similar elements.

[0007] Figure 1A It is a general block diagram depicting a network environment comprising one or more access points communicating with one or more devices or stations, according to one or more embodiments.

[0008] Figure 1B and 1C This is a general block diagram depicting a computing device that can be used in conjunction with the methods and systems described herein, according to one or more embodiments;

[0009] Figure 2 It is a general block diagram of a distributed amplifier according to one or more embodiments;

[0010] Figure 3 This is an electrical schematic diagram of a distributed amplifier according to one or more embodiments;

[0011] Figure 4 This is a plan view of a distributed amplifier according to one or more embodiments;

[0012] Figure 5 This is to illustrate according to one or more embodiments Figure 3 The diagram illustrates the voltage versus frequency curve (in dB) of the output signal of the distributed amplifier; and

[0013] Figure 6 This is to illustrate according to one or more embodiments Figure 3 The output signal of the distributed amplifier described in the text is in dB. 11 A graph showing the frequency.

[0014] Details of various embodiments of the method and system are set forth in the accompanying drawings and the description below. Detailed Implementation

[0015] To facilitate reading the description of the various embodiments below, the following description of the paragraphs and corresponding contents of the specification may be helpful:

[0016] Paragraph A describes the network and computing environments that can be used to implement the embodiments described herein; and

[0017] Paragraph B describes embodiments of the amplification system and amplification method according to one or more embodiments.

[0018] The various embodiments disclosed herein relate to distributed amplifiers or distributed amplification. In some embodiments, the distributed amplifier operates at high frequencies (e.g., 50 GHz or higher) and overcomes the bandwidth limitations associated with conventional architectures. In some embodiments, the distributed amplifier achieves both significant bandwidth extension (above 50 GHz) (e.g., 65 GHz or higher) and excellent return loss. In some embodiments, the distributed amplifier is used in coherent optical transceivers with 1 terabits per second (Tb / s) or greater, pulse amplitude modulation 4-level (PAM40) devices with 100 gigabits per second (Gb / s) or greater, SERDES with 100 gigabits per second (Gb / s) or greater, PHYs with 100 gigabits per second (Gb / s) or greater, and / or switching integrated circuits (ICs) with 100 gigabits per second (Gb / s) or greater.

[0019] In some embodiments, a larger amplifier is divided into multiple smaller amplifiers or cells (e.g., two or more cells) such that its associated capacitance can be absorbed into an artificial transmission line or other circuitry. In some embodiments, multiple G... m Cellular input networks can provide large total G m G m It is either transconductance or gain. In some embodiments, the distributed amplification system and method cause the signal from G... m The currents in the cell are phase-aligned and summed in a current summer. The current summer is coupled to multiple branches, each corresponding to G. m Cell. Each branch contains an artificial transmission line or other circuitry configured in some embodiments to align the current phase. In some embodiments, each branch is terminated in a current summator with a current phase of 1 / g. m At the transconductance common-gate transistor, where 1 / g m Equal to the characteristic impedance of an artificial transmission line, for example, L D / C D The square root of L, where L D It is the inductance and C in the artificial transmission line. D It is a capacitor in an artificial transmission line.

[0020] In some embodiments, 1 / g mThe common-gate transistor's transconductance provides proper termination for the artificial transmission line at the transistor's source (e.g., N-channel) and exhibits high output impedance at the transistor's drain, a beneficial characteristic of current summers. In some embodiments, the currents are summed in phase and pumped into the load resistor (R). L ) and load capacitor (C L In some embodiments, bandwidth extension techniques (such as parallel peaking and Tcoil peaking) are used to enhance the bandwidth of the output network coupled to the summer.

[0021] The various embodiments disclosed herein relate to an apparatus. The apparatus includes: a cell comprising a first cell and a second cell; and a transmission line comprising a first line and a second line. The first cell is coupled to the first line, and the second cell is coupled to the second line. The first line is configured to provide a first delay related to a delay between the first cell and the second cell. The apparatus further includes a summer comprising a first input coupled to the first line and a second input coupled to the second line. The summer is configured to provide an output signal.

[0022] In some embodiments, the first cell is configured to provide a first signal to the first line, and the second cell is configured to provide a second signal to the second line. In some embodiments, the output signal is a summation signal comprising a combination of the first signal and the second signal. In some embodiments, the summer includes a first transistor having transconductance related to the reciprocal of the inductance associated with the first line divided by the capacitance associated with the first line. In some embodiments, the summer includes a first transistor having transconductance related to the reciprocal of the square root of the inductance of the first line divided by the capacitance of the first line. In some embodiments, the first line includes a network including a pair of capacitors coupled to ground and an inductor coupled between the pair of capacitors. In some embodiments, the first line includes a network including a pair of capacitors coupled to ground and an inductor coupled between the pair of capacitors, and the summer includes a first transistor having transconductance related to the reciprocal of the square root of the inductance of the inductor divided by the capacitance of the pair of capacitors.

[0023] In some embodiments, the output network is coupled to the summer. In some embodiments, the output network includes a network configured to perform inductance peaking.

[0024] The various embodiments disclosed herein relate to amplifiers in integrated circuits. The amplifier includes a first network comprising a transmission line and a plurality of cells. Each of the cells has an input coupled to a node on the transmission line. The amplifier also includes circuitry, each of the circuits coupled to a corresponding cell of the cell. At least one of the circuits includes a second network having inductance and capacitance. The amplifier further includes a summer coupled to the circuitry. The summer is configured to provide an output signal and includes at least one transistor having transconductance inversely related to the quotient of the inductance and capacitance.

[0025] In some embodiments, the amplifier further includes an output network configured to receive the output signal from the summer. In some embodiments, the output network is configured to perform inductance peaking. In some embodiments, the first network is configured to provide a first delay related to the delay between the cells. In some embodiments, the transconductance of the transistor is inversely correlated with the square root of the quotient of the inductance and the capacitance. In some embodiments, one of the circuits is a direct connection between one of the cells and the input of the summer. In some embodiments, the summer includes at least two transistors, with a first input of the transistors coupled to a corresponding transmission circuit, a second input of the transistors coupled together, and gate inputs of the transistors coupled together.

[0026] The various embodiments disclosed herein relate to a method for providing an output signal. The method includes providing a first signal to a first cell at a first node on an input transmission line, amplifying the first signal to provide a first amplified signal, providing a second signal to a second cell at a second node on the input transmission line, and amplifying the second signal to provide a second amplified signal. The second signal is delayed relative to the first signal by a first delay. The method further includes delaying the first amplified signal relative to the second amplified signal to compensate for the first delay, and summing the first amplified signal and the second amplified signal to provide the output signal.

[0027] In some embodiments, the summation uses a transistor having transconductance related to the quotient of the inductance of the inductor and the capacitance of the capacitor for delaying the first signal. In some embodiments, the method further includes providing the output signal to an output network configured to perform series peaking, parallel-series peaking, or Tcoil peaking.

[0028] In some embodiments, the method further includes providing a third signal to a third cell at a third node on the input transmission line, the third signal being delayed by a second delay relative to the first signal. In some embodiments, delaying the first amplified signal relative to the second amplified signal includes delaying both the second amplified signal and the first amplified signal to compensate for the second delay. In some embodiments, summing the first amplified signal and the second amplified signal includes summing the first amplified signal, the second amplified signal, and the third amplified signal to provide the output signal.

[0029] A. Computing and Networking Environment

[0030] Before discussing specific embodiments of this solution, it may be helpful to describe the operating environment and associated system components (e.g., hardware elements) in conjunction with the methods and systems described herein. References Figure 1A This describes an embodiment of a network environment. In simple terms, the network environment includes a wireless communication system comprising one or more network devices 106 or access points (APs), one or more wireless communication devices 102, and network hardware components or nodes 192. The wireless communication device 102 may, for example, include a laptop computer, tablet computer, personal computer, and / or cellular phone device. Reference Figure 1B and 1C More detailed descriptions are provided for embodiments of each wireless communication device 102 and / or AP or network device 106. In one embodiment, the network environment may be an ad hoc network environment, an infrastructure wireless network environment, a subnet environment, etc. Network device 106 or AP may be operatively coupled to network hardware or node 192 via a local area network connection. Node 192, which may include routers, gateways, switches, bridges, modems, system controllers, appliances, etc., may provide local area network connectivity for the communication system. Each of network device 106 or AP may have an associated antenna or antenna array to communicate with wireless communication devices in its area. Wireless communication device 102 may register with a specific network device 106 or AP to receive services from the communication system (e.g., via SU-MIMO or MU-MIMO configuration). For direct connections (e.g., point-to-point communication), some wireless communication devices may communicate directly via assigned channels and communication protocols. Some of the wireless communication devices 102 may be mobile or relatively stationary relative to network device 106 or AP.

[0031] In some embodiments, network device 106 or AP includes means or modules (comprising a combination of hardware and software) that allow wireless communication device 102 to connect to a wired network using Wi-Fi or other standards. Network device 106 or AP may sometimes be referred to as a Wireless Access Point (WAP). Network device 106 or AP may be implemented (e.g., configured, designed, and / or built) for operation in a Wireless Local Area Network (WLAN). In some embodiments, network device 106 or AP may be connected as a standalone device to a router (e.g., via a wired network). In other embodiments, network device 106 or AP may be a component of a router. Network device 106 or AP provides access to multiple devices on the network. Network device 106 or AP may, for example, connect to a wired Ethernet connection and use a radio frequency link to provide wireless connectivity for other devices 102 to utilize the wired connection. Network device 106 or AP may be implemented to support standards for transmitting and receiving data using one or more radio frequencies. These standards and the frequencies they use may be defined by IEEE (e.g., the IEEE 802.11 standard). Network device 106 or AP can be configured and / or used to support public Internet hotspots and / or extend the Wi-Fi signal range of a network over a network.

[0032] In some embodiments, network device 106 or AP can be used (e.g., within a home or building) for wireless networks (e.g., IEEE 802.11, Bluetooth, ZigBee, any other type of radio frequency-based network protocol and / or variations thereof). Each of the wireless communication devices 102 may include a built-in radio and / or be coupled to a radio. Such wireless communication devices 102 and / or access points or network devices 106 may operate according to various aspects of this disclosure presented herein to enhance performance, reduce cost and / or size, and / or enhance broadband applications. Each wireless communication device 102 may have the ability to act as a client node seeking access to resources (e.g., data, and connections to networked nodes such as servers) via one or more network devices 106 or APs.

[0033] The network connection may include any type and / or form of network, and may include any of the following: point-to-point network, broadcast network, telecommunications network, data communication network, computer network. The network topology may be a bus, star, or ring network topology. The network may have any such network topology known to those skilled in the art capable of supporting the operations described herein. In some embodiments, different types of data may be transmitted via different protocols. In other embodiments, the same type of data may be transmitted via different protocols.

[0034] The communication device 102 and the access point or network device 106 can be deployed as any type and form of computing device and / or executed on any type and form of computing device, such as a computer, network device or appliance capable of communicating and performing the operations described herein on any type and form of network. Figure 1B and 1C A block diagram depicting a computing device 100 that can be used to implement embodiments of wireless communication device 102 or network device 106. (See diagram for reference.) Figure 1B and 1C As shown, each computing device 100 includes a processor 121 (central processing unit) and a main memory unit 122. For example... Figure 1B As shown, the computing device 100 may include a storage device 128, a mounting device 116, a network interface 118, an I / O controller 123, display devices 124a to 124n, a keyboard 126, and a pointing device 127 (e.g., a mouse). The storage device 128 may include an operating system and / or software. Figure 1C As shown, each computing device 100 may also include additional optional components such as memory port 103, bridge 170, one or more input / output devices 130a to 130n, and cache memory 140 that communicates with the central processing unit or process 121.

[0035] The central processing unit or processor 121 is any logical circuit system that responds to and processes instructions fetched from main memory unit 122. In many embodiments, the central processing unit or processor 121 is provided by a microprocessor unit, such as a microprocessor unit manufactured by Intel Corporation of Santa Clara, California; a microprocessor unit manufactured by International Business Machines of White Plains, New York; or a microprocessor unit manufactured by Advanced Micro Devices of Sunnyvale, California. The computing device 100 may be based on any of these processors, or any other processor capable of operating as described herein.

[0036] Main memory cell 122 may be one or more memory chips capable of storing data and allowing direct access to any memory location by a microprocessor or processor, such as any type or variant of static random access memory (SRAM), dynamic random access memory (DRAM), ferroelectric RAM (FRAM), NAND flash memory, NOR flash memory, and solid-state drive (SSD). Main memory 122 may be based on any of the aforementioned memory chips, or any other available memory chip capable of operating as described herein. Figure 1B In the illustrated embodiment, processor 121 communicates with main memory 122 via system bus 150 (described in more detail below). Figure 1C An embodiment of computing device 100 is depicted, wherein the processor communicates directly with main memory 122 via memory port 103. For example, in Figure 1C In this context, the main memory 122 can be dynamic random access memory (DRAM).

[0037] Figure 1C An embodiment is depicted in which the main processor or processor 121 communicates directly with the cache memory 140 via a secondary bus (sometimes referred to as a back-side bus). In other embodiments, the main processor or processor 121 communicates with the cache memory 140 using a system bus 150. The cache memory 140 typically has a faster response time than the main memory 122 and is provided by, for example, SRAM, BSRAM, or EDRAM. Figure 1C In the illustrated embodiment, processor 121 communicates with various I / O devices 130 via local system bus 150. Various buses can be used to connect the central processing unit or processor 121 to any of the I / O devices 130, such as VESA VL bus, ISA bus, EISA bus, Microchannel Architecture (MCA) bus, PCI bus, PCI-X bus, PCI-Express bus, or Nubus. In embodiments where the I / O device is a video display 124, processor 121 may use an Advanced Graphics Port (AGP) to communicate with the display 124. Figure 1C An embodiment of computing device 100 is described, wherein the main processor or processor 121 may communicate directly with I / O device 130b, for example, via HYPERTRANSPORT, RAPIDIO, or INFINIBAND communication technologies. Figure 1C An embodiment in which a combination of local bus and direct communication is also depicted: processor 121 communicates with I / O device 130a using a local interconnect bus, while simultaneously communicating directly with I / O device 130b.

[0038] The computing device 100 may contain various I / O devices 130a to 130n. Input devices include keyboards, mice, trackpads, trackballs, microphones, dials, touchpads, touchscreens, and drawing tablets. Output devices include video displays, speakers, inkjet printers, laser printers, projectors, and dye-to-sublimation printers. I / O devices can be, for example... Figure 1B The illustrated I / O controller 123 controls one or more I / O devices, such as a keyboard 126 and pointing devices 127 (e.g., a mouse or optical pen). Additionally, the I / O devices may also provide storage and / or mounting media or devices 116 for the computing device 100. In other embodiments, the computing device 100 may provide USB connectivity (not shown) to receive handheld USB storage devices, such as the USB flash drive series devices manufactured by Twintech Industry, Inc., Los Alamitos, California.

[0039] Refer again Figure 1B The computing device 100 may support any suitable installation device 116, such as a disk drive, CD-ROM drive, CD-R / RW drive, DVD-ROM drive, flash memory drive, tape drive of various formats, USB device, hard disk drive, network interface, or any other device suitable for installing software and programs. The computing device 100 may further include a storage device, such as one or more hard disk drives or a redundant array of independent disks, for storing the operating system and other related software, and for storing application software programs, such as any program or software 120 used to implement (e.g., configured and / or designed for) the systems and methods described herein. Optionally, any installation device 116 may also be used as a storage device. Additionally, the operating system and software may be run from a bootable media.

[0040] Furthermore, the computing device 100 may include a network interface 118 for interfacing with a network via various connections, including but not limited to standard telephone lines, LAN or WAN links (e.g., 802.11, T1, T3, 56kb, X.25, SNA, DECNET), broadband connections (e.g., ISDN, Frame Relay, ATM, Gigabit Ethernet, Ethernet over SONET), wireless connections, or any or a combination of the foregoing. Various communication protocols (e.g., TCP / IP, IPX, SPX, NetBIOS, Ethernet, ARCNET, SONET, SDH, Fiber Distributed Data Interface (FDDI), RS232, IEEE 802.11, IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, IEEE 802.11n, IEEE 802.11ac, IEEE 802.11ad, CDMA, GSM, WiMax, and Direct Asynchronous Connection) can be used to establish the connection. In one embodiment, computing device 100 communicates with other computing devices 100' via any type and / or form of gateway or tunneling protocol, such as Secure Sockets Layer (SSL) or Transport Layer Security (TLS). Network interface 118 may include a built-in network adapter, network interface card, PCMCIA network card, card bus network adapter, wireless network adapter, USB network adapter, modem, or any other means suitable for connecting computing device 100 to any type of network capable of communication and performing the operations described herein.

[0041] In some embodiments, computing device 100 may include or be connected to one or more display devices 124a to 124n. Therefore, any of the I / O devices 130a to 130n and / or I / O controller 123 may include any type and / or form of suitable hardware, software, or a combination of hardware and software to support, enable, or provide connectivity and use of display devices 124a to 124n by computing device 100. For example, computing device 100 may include any type and / or form of video adapter, video card, driver, and / or library to dock, communicate, connect, or otherwise use display devices 124a to 124n. In one embodiment, a video adapter may include multiple connectors to dock with display devices 124a to 124n. In other embodiments, computing device 100 may include multiple video adapters, each connected to display devices 124a to 124n. In some embodiments, any portion of the operating system of computing device 100 may be configured to use multiple displays 124a to 124n. In other embodiments, I / O device 130 may be a bridge between system bus 150 and external communication buses (e.g., USB bus, Apple Desktop bus, RS-232 serial connection, SCSI bus, FireWire bus, FireWire 800 bus, Ethernet bus, AppleTalk bus, Gigabit Ethernet bus, Asynchronous Transfer Mode bus, FibreChannel bus, Fiber optic bus, Serial Attached Small Computer System Interface bus, USB connection, or HDMI bus).

[0042] Figure 1B and 1CThe computing device 100 of the type described herein can operate under the control of an operating system that controls task scheduling and access to system resources. The computing device 100 can run any operating system, such as any version of Microsoft Windows, different versions of Unix and Linux, any version of MAC OS for Macintosh computers, any embedded operating system, any real-time operating system, any open-source operating system, any proprietary operating system, any operating system for mobile computing devices, or any other operating system capable of running on a computing device and performing the operations described herein. Typical operating systems include (but are not limited to): Android, manufactured by Google Inc.; Windows 7, 8, and 10, manufactured by Microsoft Corporation of Redmond, Washington; MAC OS, manufactured by Apple Computer of Cupertino, California; WebOS, manufactured by Research In Motion (RIM); OS / 2, manufactured by International Business Machines of Armonk, New York; and Linux, a free operating system distributed by Caldera Corp. of Salt Lake City, Utah, or any type and / or form of Unix operating system, etc.

[0043] The computer system or device 100 may be any workstation, telephone, desktop computer, laptop or notebook computer, server, handheld computer, mobile phone or other portable telecommunications device, media playback device, gaming system, mobile computing device, or any other type and / or form of communicable computing, telecommunications, or media device. In some embodiments, the computing device 100 may have a different processor, operating system, and input device consistent with the device. For example, in one embodiment, the computing device 100 is a smartphone, mobile device, tablet, or personal digital assistant. Furthermore, the computing device 100 may be any workstation, desktop computer, laptop or notebook computer, server, handheld computer, mobile phone, any other computer, or other form of computing or telecommunications device that is communicable and has sufficient processor power and memory capacity to perform the operations described herein.

[0044] The aforementioned aspects of the operating environment and components will become apparent within the context of the systems and methods revealed in this paper.

[0045] B. Distributed amplification system

[0046] Figure 2 This is a block diagram depicting a communication device 200 according to one or more embodiments. In some embodiments, the communication device 200 is a system, apparatus, or device for network communication or computing and includes a distributed amplifier 201. For example, the communication device 200 may be part of a network device implemented as network device 106, node 192, or network hardware, device 102, or a network serving a network communicating with device 102. In some embodiments, the device 200 is or includes an analog-to-digital converter, a serializer / deserializer (SERDES), an Ethernet physical layer (PHY), a pulse amplitude modulation 4-level (PAM4) device, and / or an optical transceiver, and is configured for distributed amplification using the distributed amplifier 201. The device 200 including the distributed amplifier 201 may be fabricated in a CMOS process using CMOS components and disposed on an IC substrate within an IC package.

[0047] In some embodiments, the distributed amplifier 201 includes an input network 202, transmission lines 206A to 206C (e.g., additional or artificial transmission lines), a summer 208, and an output network 212. In some embodiments, the output network 212 drives a load 216 (e.g., a large load capacitor). These components can operate together to communicate with another communication device via a network cable (e.g., Ethernet, USB, Firewire, fiber optic cable, etc.) and / or via wireless media (e.g., Wi-Fi, Bluetooth, 60GHz link, cellular network, etc.). In some embodiments, the communication device 200 includes a... Figure 2 It can display more, fewer, or different components.

[0048] Input network 202 includes cells 204A to 204C, transmission lines or artificial transmission lines 226, terminating resistors 207, and nodes 205A to 205C. Nodes 205A to 205C are locations on transmission lines 226 associated with the corresponding inputs of cells 204A to 204C. Cells 204A to 204C can be any number of amplifier or transconductance cells greater than 1 (e.g., 2, 3, 4, etc.). A corresponding number of transmission lines 206A to 206C are provided for the number of cells 204A to 204C. Summer 208 includes several inputs 218A to 218C corresponding to the number of transmission lines 206A to 206C. Summer 208 provides a single output 220 to output network 212.

[0049] The input transmission line or artificial transmission line 226 is coupled to cells 204A to 204C at respective nodes 205A to 205C, and in some embodiments is an IC trace conductor or a metal layer inductor. The input transmission line or artificial transmission line 226 comprises multiple segments, each segment having an inductor element L. G and capacitor element C G Component L G and C G Designed to achieve characteristic impedance Matching the terminating resistor 207 at the end of line 226. Inductor and capacitor elements L G and C G These can be capacitors and inductors, or other circuit structures with capacitive and inductive characteristics. Resistive elements can be resistors or other circuit structures with resistive characteristics. For example, conductors or IC traces can have length, width, number of turns, and other materials configured to provide resistance, inductance, or capacitance. Resistors, capacitors, and inductors of this type can be... Figure 3 The numbers represent discrete resistors, capacitors, and inductors.

[0050] Cells 204A to 204C are configured as transconductance cells, each contributing to the total transconductance G. m The gain or transconductance. In some embodiments, the input network 202 is configured to provide a large total G using cells 204A to 204C. m In some embodiments, cells 204A to 204C are configured to supply a high-frequency voltage signal to a current signal amplifier. Cells 204A to 204C include one or more active devices, such as transistors, configured to provide an arrangement with desired transconductance. The inputs to cells 204A to 204C at corresponding nodes 205A to 205C have a time or phase delay τ relative to each other. For example, the signal at the input of cell 342A is attributed to the inductance between the inputs (e.g., L). G This is in contrast to the input delay of cell 342B. Artificial transmission lines 226, cells 204A to 204C, and transmission lines 206A to 206C are configured to align the phase at inputs 218A to 218C, thereby compensating for the delay of τ. In some embodiments, the currents from cells 204A to 204C are aligned in phase to obtain maximum output bandwidth. In some embodiments, the currents from cells 204A to 204C are aligned to prevent the currents from canceling each other out at high frequencies.

[0051] Each of transmission lines 206A to 206C includes inductive and capacitive elements configured to provide phase alignment at inputs 218A to 218C. In some embodiments, the delay of each of transmission lines 206A to 206C is matched to the delay of the inputs of cells 204A to 204C. In some embodiments, one of transmission lines 206A to 206C is a direct connection; for example, transmission line 206C is a direct connection between cell 204C and input 218C. Transmission lines 206A to 206C are any circuitry used to connect the inputs 218A to 218C of the summer 208 to cells 204A to 204C, and may include conductors, resistive elements, capacitive elements, and inductive elements. In some embodiments, transmission lines 206A to 206C are configured as artificial transmission lines, buffers, delay paths, or circuit networks. The circuit network may be embodied as IC circuit traces or metal layer conductors configured to have appropriate resistance, inductance, and capacitance, and / or may include discrete resistors, capacitors, or inductors. The respective transmission lines 206A to 206C may provide a phase delay τ to match the corresponding phase delay τ at nodes 205A to 205C associated with cells 204A to 204C. In some embodiments, artificial transmission lines 226 and 206A to 206C are any circuit configured with inductance and capacitance (e.g., lumped elements, such as lumped capacitors and inductors).

[0052] Summer 208 is a component that receives signals (e.g., amplified current signals) from transmission lines 206A to 206C and provides a combined signal at output 220. Summer 208 can be any means for providing a summation operation, and in some embodiments is a set of common-gate transistors (e.g., one transistor for each input 218A to 218C). In some embodiments, summer 208 is a current summer. The common-gate transistor has 1 / g m The transconductance is used to provide a matching termination to transmission lines 206A to 206C to prevent 1 / g m The reflections below, in some embodiments, disrupt phase alignment (e.g., independent impedance matching). For each input 218A to 218C, term 1 / g m It is equal to the characteristic impedance of the artificial transmission lines 206A to 206C, that is, the square root of the inductance of the corresponding transmission lines 206A to 206C divided by the square root (inductance / capacitance) of the corresponding transmission lines 206A to 206C.

[0053] Output network 212 delivers the output current signal of summer 208 to load circuitry or load 216. In some embodiments, load 216 is a large capacitor (e.g., 600 fF or larger). Output network 212 includes resistors, capacitors, and inductors, and in some embodiments is configured to utilize inductor peaking techniques (e.g., series peaking, parallel-series peaking, and / or Tcoil peaking). In some embodiments, inductor peaking techniques utilize the resonant characteristics of an inductor-capacitor network to improve bandwidth. In some embodiments, parallel-series peaking is a passive filtering technique or bandwidth extension technique using parallel inductors (e.g., where an inductor connected in series with the load resistor is connected in parallel with the output capacitor). In some embodiments, series peaking is a passive filtering technique or bandwidth extension technique using series-coupled inductors (e.g., where an inductor is connected in series with the output capacitor). In some embodiments, Tcoil peaking is a passive filtering technique or bandwidth extension technique using coupled inductors (e.g., a transformer with three leads, where one lead is connected in series with the load resistor and another lead is coupled in series with the load capacitor).

[0054] refer to Figure 3 The distributed amplifier 300 can be used in device 200 ( Figure 2 The distributed amplifier 300 is similar to distributed amplifier 201. Distributed amplifier 300 includes an input network 301, transconductance cells 342A to 342B, transmission lines 350A to 350B (e.g., additional or artificial transmission lines, circuitry, etc.), a summer 360, and an output network 380. Distributed amplifier 300 is described below as having two cells 342A to 342B and two transmission lines 350A to 350B. However, depending on design criteria and system parameters, distributed amplifier 300 may employ more than two cells 342A to 342B and two transmission lines 350A to 350B. Cells 342A to 342B and transmission lines 350A to 350B can be any number of amplifiers greater than 1 (e.g., 2, 3, 4, etc.).

[0055] Input network 301 includes input transmission line 307 and resistor 302 (e.g., representing the output resistance R of the signal source). s (e.g., 50 ohms)), capacitor 304 (e.g., representing a pad capacitor), inductor 306, capacitor 308 (e.g., representing an electrostatic discharge diode capacitor), capacitor 312 (e.g., representing a parasitic capacitance), inductor 314, capacitor 316 (e.g., representing a gate capacitance C) G ), Inductor 318 (e.g., representing gate inductance L) G ), capacitor 320 (for example, representing gate capacitance C) G ), capacitor 324 and resistor 326 (e.g., indicating equal to R) s(Termination resistors). Cells 342A and 342B each have outputs coupled to corresponding transmission lines 350A and 350B. Cell 342A is coupled at the node between inductors 314 and 318, and cell 342B is coupled at the node between inductors 318 and 322. Capacitor 316 is coupled between the input of cell 342A and ground. Capacitor 320 is coupled between the input of cell 342B and ground. Cells 342A to 342B can be similar to cells 204A to 204C ( Figure 2 Transconducting cells 342A to 342B may be part of the input network 301.

[0056] A corresponding number of transmission lines 350A to 350B are provided for the number of cells 342A to 342B. Transmission lines 350A to 350B are similar to transmission lines 206A to 206C and can be any type of circuit used to provide a connection between the summer 360 and cells 342A to 342B. In some embodiments, transmission line 350A is a circuit containing a network of capacitors 352 (e.g., representing 0.5C). D (capacitor), inductor 354 (e.g., representing L) D The inductor) and capacitor 356 (e.g., indicating 0.5C) D The transmission line 350B is a circuit (e.g., a conductor) that provides a direct connection to the summer 360. In some embodiments, the signal at the input of cell 342B is at least partially attributed to the inductor 313 (e.g., L). G This is relative to the input delay of cell 342A. Transmission lines 350A to 350B receive amplified signals from cells 342A to 342B and are configured to compensate for the delay.

[0057] The summer 360 may be a multi-transistor current summer. In some embodiments, the summer 360 includes transistors 364A to 364B (e.g., cascode NMOS transistors), with their drains connected to node 361, their sources coupled to corresponding transmission lines 350A to 350B, and their gates coupled together and biased to a desired voltage. Transistors 364A to 364B are configured and driven to provide appropriate gain or transconductance (e.g., 1 / g). m Supplementary versions of transistors 364A to 364B can be implemented by replacing the PMOS transistors with NMOS transistors and swapping ground and VDD. In some embodiments, the number of transistors 364A to 364B (e.g., in cascode configuration) corresponds to the number of transmission lines 350A to 350B.

[0058] The summer 208 provides a single output 220 as a current signal to the output network 380. The current signal is a combination of amplified signals received at the sources of transistors 364A to 364B. Transistors 364A to 364B have g m The transconductance, where 1 / g m = square root (L D / C D And τ = square root (L) D C D )<<1 / f o , where f o It is the output frequency, and R is the output frequency. s = square root (L G / C G And τ = square root (L) G C G )<<1 / f o Transmission line 350A provides a delay τ for phase alignment. In some embodiments, C G It is 90fF, and L G The pH is 150 to 170 picohens. In some embodiments, C D It is 35fF, and L d Approximately 80 picohenries (pH). Transmission line 350B provides a direct connection to the source of transistor 364B (e.g., with little or no delay).

[0059] Output network 380 includes an inductor-capacitor network comprising inductors 382, ​​384, and 386, capacitor 388, capacitor 392, and resistor 394. In some embodiments, inductors 382, ​​384, and 386 are multi-core inductors. Capacitor 392 and resistor 394 represent the load capacitance (C). L (e.g., 600fF) and load resistance (R) L (e.g., 12 ohms). Output network 380 is configured to drive a large load capacitance (e.g., capacitor 392). In some embodiments, output network 380 is configured for Tcoil peaking. In some embodiments, an output transmission line is coupled to output network 380. In some embodiments, load resistor 394 and load capacitor 392 represent the output transmission line resistance and capacitance. Figure 3 The various capacitors, resistors, and inductors shown can represent the electrical characteristics of transmission lines and other circuit structures, and are not necessarily discrete components.

[0060] refer to Figure 4In some embodiments, the distributed amplifier 400 may be part of a coherent optical transceiver operating at a 65 GHz bandwidth. The distributed amplifier 400 includes an input 402 and an output 412. The distributed amplifier 400 is disposed on an integrated circuit (IC) substrate 401 for inclusion in an IC package. The distributed amplifier 400 includes a distributed input network 404 coupled to the input 402, a current summer and phase alignment circuit 408, and an output network 410 coupled to the output 412.

[0061] Distributed input network 404 can be similar to input network 301 ( Figure 3 The distributed input network 404 may include active elements, such as transistors, for amplification operations. The distributed input network 404 may include passive elements 426 on a metal layer above the IC substrate 401 for input transmission line circuitry. The current summer and phase alignment circuitry 408 may be similar to transmission lines 350A to 350B and summer 360. Figure 3 It may also include active elements, such as transistors, for current summation operations.

[0062] The current summer and phase alignment circuit 408 may include passive components 422 on a metal layer above the IC substrate 401 for use in artificial transmission line circuitry. Phase alignment can be achieved using various circuit structures, including but not limited to transmission lines, artificial transmission lines, and buffers.

[0063] Output network 410 is similar to output network 380 ( Figure 3 In some embodiments, it is configured to provide inductance peaking. Output network 410 may include passive elements 438 disposed on a metal layer above IC substrate 401. Output network 410 may be a circuit system configured to receive signals from current summer and phase alignment circuit 408, including but not limited to passive circuits (e.g., resistor-capacitor-inductor networks, inductor networks, resistor-inductor networks, resistor-capacitor networks, and / or inductor-capacitor networks).

[0064] Reference Figure 5 The graph 500 includes a Y-axis 502 representing voltage in dB and an X-axis 504 representing frequency. The graph 500 also includes a display of the distributed amplifier 300. Figure 3 Curve 508 shows the frequency response of the amplifier. Curve 508 illustrates the bandwidth at -3dB at 68 GHz and robust performance across the process, voltage, and temperature variation inflection points represented by each of curves in 508. In some embodiments, curve 508 represents a distributed amplifier 300 driving a large capacitive load of 600 nanofarads (fF) from a large analog-to-digital converter array. In some embodiments, the distributed amplifier 300 achieves low power and low noise compared to conventional multistage amplifiers.

[0065] Reference Figure 6 The graph 600 contains S values ​​expressed in dB. 11 The Y-axis 602 represents the input return loss (i.e., input return loss), and the X-axis 604 represents the frequency. Graph 600 includes curve 608, which illustrates the distributed amplifier 300 (…). Figure 3 The return loss is less than -16dB. Demonstration is provided for frequencies up to 65GHz for S... 11 The absolute value is represented by curve 608, indicating robust performance across process variations and temperature inflection points. In some embodiments, curve 608 represents a distributed amplifier 300 driving a large capacitive load of 600 nanofarads (fF) from a large analog-to-digital converter array. The resistance, capacitance, and inductance values ​​given throughout this disclosure are merely exemplary. Other values ​​may be used according to design guidelines.

[0066] It should be noted that certain paragraphs of this disclosure may use terms such as those relating to means or operations (e.g., “first” and “second”) for the purpose of identifying or distinguishing one another or for other purposes. These terms are not intended to relate entities (e.g., first means and second means) merely in time or according to sequence, although in some cases these entities may contain such a relationship. These terms also do not limit the number of possible entities that can operate within a system or environment. It should be understood that the systems described above may provide multiples of any or each of those components, and these components may be disposed on separate devices or, in some embodiments, on multiple devices in a separate package or on a multi-chip module. Furthermore, the systems and methods described above may utilize different capacitance, resistance, and inductance values ​​than those given herein, depending on application requirements and design guidelines. Additionally, certain components may be coupled together with intermediary components disposed therebetween (e.g., buffers, inverters, pads, passive components, etc.).

[0067] While the foregoing written description of the methods and systems enables those skilled in the art to make and use embodiments thereof, it should be understood and appreciated that variations, combinations, and equivalents of specific embodiments, methods, and examples exist herein. Therefore, these methods and systems should not be limited to the embodiments, methods, and examples described above, but rather to all embodiments and methods within the scope and spirit of the invention.

Claims

1. An apparatus comprising: Multiple cells, including a first cell and a second cell; Multiple transmission lines, including a first line and a second line, wherein a first cell is coupled to the first line and a second cell is coupled to the second line, wherein the first line is configured to provide a first delay related to the delay between the first cell and the second cell; as well as A summer includes a first input coupled to the first line and a second input coupled to the second line, wherein the summer is configured to provide an output signal, wherein the summer includes a first transistor having a transconductance that is correlated with the inductance associated with the first line divided by the reciprocal of the capacitance associated with the first line.

2. The apparatus of claim 1, wherein the first cell is configured to provide a first signal to the first line, and the second cell is configured to provide a second signal to the second line.

3. The apparatus of claim 2, wherein the output signal is a summation signal comprising a combination of the first signal and the second signal.

4. The apparatus of claim 1, further comprising an output network, wherein the output network is configured to perform inductance peaking.

5. The apparatus of claim 1, wherein the transconductance is related to the inductance associated with the first line divided by the reciprocal of the square root of the capacitance associated with the first line.

6. The apparatus of claim 1, wherein the first line comprises a network including a pair of capacitors coupled to ground and an inductor coupled between the pair of capacitors.

7. The apparatus of claim 1, wherein the first line comprises a network including a pair of capacitors coupled to ground and an inductor coupled between the pair of capacitors, and wherein the transconductance is related to the inductance of the inductor divided by the reciprocal of the square root of the capacitance of the pair of capacitors.

8. The apparatus according to claim 1, further comprising: The output network is coupled to the summer.

9. The apparatus of claim 8, wherein the output network includes a network configured to perform inductance peaking.

10. An amplifier in an integrated circuit, the amplifier comprising: A first network includes a transmission line and a plurality of cells, each of which has a cell input coupled to a node on the transmission line; Multiple circuits, each of which is coupled to a corresponding cell of the cell, wherein at least one of the circuits includes a second network comprising capacitors and inductors; and A summer coupled to the circuit, wherein the summer is configured to provide an output signal, wherein the summer includes at least one transistor having a transconductance inversely related to the quotient of the inductance divided by the capacitance.

11. The amplifier of claim 10, further comprising: An output network configured to receive the output signal from the summer.

12. The amplifier of claim 11, wherein the output network is configured to perform inductance peaking.

13. The amplifier of claim 10, wherein the second network includes capacitors and inductors and is configured to provide a first delay related to the delay between the cells.

14. The amplifier of claim 10, wherein the transconductance is inversely related to the square root of the quotient of the inductance and the capacitance.

15. The amplifier of claim 10, wherein one of the circuits is a direct connection between one of the cells and the input of the summer.

16. The amplifier of claim 10, wherein the summer comprises at least two transistors, and a first input of the transistors is coupled to a corresponding circuit, a second input of the transistors is coupled together, and the gates of the transistors are coupled together.

17. A method for providing an output signal, the method comprising: A first signal is provided to the first cell at the first node on the input transmission line; Amplify the first signal to provide a first amplified signal; A second signal is provided to the second cell at the second node on the input transmission line, the second signal being delayed by a first delay relative to the first signal; Amplify the second signal to provide a second amplified signal; The first amplified signal is delayed relative to the second amplified signal to compensate for the first delay; as well as The first amplified signal and the second amplified signal are summed to provide the output signal, wherein the summation uses a transistor with transconductance, the transconductance being related to the quotient of the inductance of the inductor used to delay the first amplified signal divided by the capacitance of the capacitor.

18. The method of claim 17, further comprising providing the output signal to an output network configured to perform serial peaking, parallel-to-serial peaking, or Tcoil peaking.

19. The method of claim 18, wherein the output network is configured to perform Tcoil peaking.

20. The method of claim 17, further comprising: A third signal is provided to the third cell at the third node on the input transmission line, the third signal being delayed by a second delay relative to the first signal; The delay of the first amplified signal relative to the second amplified signal includes delaying both the second amplified signal and the first amplified signal to compensate for the second delay; and The summation of the first amplified signal and the second amplified signal includes summing the first amplified signal, the second amplified signal, and the third amplified signal to provide the output signal.

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