Dma transmission method, device and equipment based on pcie bridging mode

Abstract

The application relates to the field of data services, and provides a PCIE bridging mode-based DMA transmission method, device and equipment. The PCIE bridging mode-based DMA transmission method comprises the following steps: configuring an IP core of a high-speed serial computer expansion bus standard PCIE as a bridging mode; querying a register on a logic side through a master interface, obtaining an idle / busy state, and issuing information to be moved to the logic side; and initiating a memory read operation through a slave interface, and receiving data corresponding to the memory read operation through the logic side and the slave interface. The application reduces logical resource consumption, reduces development and post-maintenance difficulty, and is suitable for multi-service type scenes.

Description

Technical Field

[0001] This application relates to the field of data services, specifically to a DMA transfer method, apparatus, and device based on PCIe bridging mode. Background Technology

[0002] PCIe (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard) is a high-speed serial point-to-point dual-channel high-bandwidth transmission standard. Each connected device is allocated its own dedicated channel bandwidth and does not share the bus bandwidth. It primarily supports active power management, error reporting, end-to-end reliable transmission, hot-plugging, and Quality of Service (QoS) functions. DMA (Direct Memory Access) refers to a high-speed data transfer operation that allows direct reading and writing of data between external devices and memory, without the CPU (central processing unit) or CPU intervention.

[0003] DMA (Direct Memory Access) refers to an interface technology that allows external devices to exchange data directly with system memory without going through the CPU. Reading data from a peripheral device into memory or transferring data from memory to a peripheral device typically requires CPU control, such as through CPU polling or interrupts. Using interrupts for data transfer can significantly improve CPU utilization. However, interrupt-based transfers have their drawbacks. For high-speed I / O (Input / Output) devices and in situations involving bulk data exchange, only DMA can address both efficiency and speed issues. Since DMA directly exchanges data between the peripheral and memory without going through the CPU, the data transfer speed depends on the operating speed of both the memory and the peripheral.

[0004] Existing Solution 1: Based on existing mature PCIe interface IP, users implement protocol parsing and design DMA interaction mechanisms themselves. Existing Solution 2: Based on the Xilinx XDMA IP solution, users only need to focus on the interface between business logic and XDMA. The disadvantages of the existing solutions are as follows: Existing Solution 1: This solution offers a flexible user interface design and high transmission efficiency, but it is difficult to develop, has complex logic design, and requires consideration of parameter compatibility across different platforms. Maintenance is a significant undertaking. Existing Solution 2: This solution encapsulates the core DMA logic within IP, making overall implementation simple and requiring only consideration of business data interface integration. However, it consumes more resources and only supports a maximum of four transmission channels, making it unsuitable for scenarios with multiple service types. Summary of the Invention

[0005] This application provides a DMA transfer method, apparatus, and device based on PCIe bridging mode to solve the technical problems of existing DMA transfer schemes based on PCIe bridging mode being difficult to develop and maintain, consuming a lot of resources, and not applicable to multiple service types.

[0006] In a first aspect, embodiments of this application provide a DMA transfer method based on PCIe bridge mode, including: Configure the IP core of the high-speed serial computer expansion bus standard PCIe to bridge mode; The main interface queries the registers on the logic side to obtain the idle / busy status. If the idle / busy status is an idle state, the information of the downlink data to be moved is sent to the logic side. By initiating a memory read operation from the interface, the data corresponding to the memory read operation is received through the logic side and the slave interface.

[0007] In one embodiment, configuring the IP core of the high-speed serial computer expansion bus standard PCIe to bridge mode includes: In bridged mode, PCIe has a master interface and a slave interface. The master interface is used to access registers on the logic side to pass parameters and control messages; the slave interface is used to read and write the host-side main memory. The data migration is performed based on the parameters issued by the host side.

[0008] In one embodiment, the step of querying the registers on the logic side through the main interface to obtain the idle / busy status and sending the information of the downlink data to be moved to the logic side includes: The idle / busy status is obtained by querying the registers on the logical side through the driver and the main interface; When the idle / busy state is in an idle state, the length of the downlink data to be moved and the physical address where it is stored are sent to the logical side.

[0009] In one embodiment, after sending the length of the downlink data to be moved and its physical address to the logical side, the following steps are included: The logic side is notified via the target register to initiate data transmission; If the enable flag corresponding to the target register is detected on the logic side, the length of the downlink data to be moved and its physical address are retrieved from the register on the logic side.

[0010] In one embodiment, initiating a memory read operation via the slave interface and receiving data corresponding to the memory read operation via the logic side and the slave interface includes: Receive memory read messages by directly accessing the DMA engine through the host-side memory; The data corresponding to the memory read operation is packaged into the read complete message through the PCIe and read complete message.

[0011] In one embodiment, the step of packaging the data corresponding to the memory read operation into the read completion message via the PCIe and the read completion message includes: The data corresponding to the memory read operation is extracted using the bridging mode and the read completion message. The data corresponding to the memory read operation is sent to the logic side through the slave interface, and the data corresponding to the memory read operation is received by the logic side and the slave interface.

[0012] In one embodiment, the step of querying the registers on the logic side through the main interface to obtain the idle / busy status includes: Determine the service type corresponding to the uplink data to be moved and the physical address corresponding to the service type; The driver writes the physical address corresponding to the service type into the register on the logical side; Data transmission is initiated via the logical side and the slave interface; If the driver queries the register corresponding to the uplink completion flag on the logic side, the uplink data to be moved is read. Once the driver has finished reading the uplink data to be moved, the reporting completion flag is cleared.

[0013] Secondly, embodiments of this application provide a DMA transfer device based on PCIe bridge mode, comprising: The bridge mode configuration module is used to configure the IP cores of the high-speed serial computer expansion bus standard PCIe into bridge mode. The data delivery module is used to query the registers on the logic side through the main interface to obtain the idle / busy status. When the idle / busy status is an idle state, the information of the downlink data to be moved is sent to the logic side. The data receiving module is used to initiate a memory read operation through the slave interface and receive the data corresponding to the memory read operation through the logic side and the slave interface.

[0014] Thirdly, embodiments of this application provide a device including a processor and a memory storing a computer program, wherein the processor executes the computer program to implement the DMA transfer method based on PCIe bridge mode as described in the first aspect.

[0015] Fourthly, embodiments of this application provide a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the DMA transfer method based on PCIe bridge mode as described above.

[0016] The DMA transfer method, apparatus, and device based on PCIE bridge mode provided in this application configures the IP core of the high-speed serial computer expansion bus standard PCIE in bridge mode; then, it queries the registers on the logic side through the main interface to obtain the idle / busy status, and sends the information of the downlink data to be transferred to the logic side; it initiates a memory read operation through the slave interface, and receives the data corresponding to the memory read operation through the logic side and the slave interface to complete the data transfer, reducing the consumption of logic resources, reducing the difficulty of development and later maintenance, and being applicable to multiple service types. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is one of the flowcharts illustrating the DMA transfer method based on PCIe bridge mode provided in the embodiments of this application; Figure 2 This is a schematic diagram of a DMA transfer structure based on PCIE bridge mode provided in an embodiment of this application; Figure 3 This is the second flowchart illustrating the DMA transfer method based on PCIE bridge mode provided in the embodiments of this application; Figure 4 This is a schematic diagram of the structure of the DMA transfer device based on PCIE bridge mode provided in the embodiments of this application; Figure 5 This is a schematic diagram of the structure of the electronic device provided in the embodiments of this application. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0020] Reference Figure 1 , Figure 1 This is one of the flowcharts illustrating the DMA transfer method based on PCIe bridge mode in the embodiments of this application. The DMA transfer method based on PCIe bridge mode provided in the embodiments of this application may include: Step 100: Configure the IP core of the high-speed serial computer expansion bus standard PCIE to bridged mode; Specifically, the DMA transfer method based on PCIe bridge mode provided in this embodiment adopts the bridge interface mode based on the PCIe IP core, that is, the bridge mode in this embodiment. It uses the AXI (Advanced eXtensible Interface, a bus protocol)-MM interface to connect the PCIe interface module and the user logic module, thus realizing DMA transfer. For example... Figure 2 As shown, the PCIe IP core is configured in bridged mode. The PCIe IP core includes a bridge switching function module, which implements downlink parsing and uplink encapsulation of TLP (Data Message Protocol) messages, and completes the reception and transmission of data in AXI-MM interface format.

[0021] In PCIe bridge interface mode, there are AXI-MM master interfaces and AXI-MM slave interfaces. The DMA transfer method based on PCIe bridge mode provided in this embodiment adopts a coexistence of AXI-MM master and AXI-MM slave interfaces to separate control messages and service data. The AXI-MM master interface is used by the host side (CPU) to access the registers on the logic side to realize the transmission of parameters and control messages; the AXI-MM slave interface is used by the logic side to read and write the main memory of the host side (CPU) and complete the data transfer according to the parameters issued by the host side (CPU).

[0022] Step 200: Query the registers on the logic side through the main interface to obtain the idle / busy status, and send the information of the downlink data to be moved to the logic side; Specifically, taking downstream transmission as an example, the process of message interaction, parameter control, and data migration when transmitting business data is as follows: Step 1, Driver access Figure 2 The AXI-MM master interface queries the register inside the logic side to obtain the idle / busy status, and judges the idle / busy status. If it is in a busy state, it waits; if it is in an idle state, it proceeds to step 2. Step 2, Driver Access Figure 2 The AXI-MM master interface writes to the registers inside the logic side, sending the length of the data to be moved (i.e., the downlink data to be moved in this embodiment) and the physical address where it is stored to the logic side.

[0023] Step 300: Initiate a memory read operation through the slave interface, and receive the data corresponding to the memory read operation through the logic side and the slave interface; Specifically, taking downstream transmission as an example, the process of message interaction, parameter control, and data transfer during business data transmission also includes: The logic side is notified to start the transmission by enabling the flag register; Step 3: After the logic side detects the transmission enable flag, it retrieves the length of the downlink data to be moved and the physical address of the data to be stored from the register inside the logic side, and initiates a memory read operation (i.e., the memory read operation in this embodiment) through the AXI-MM slave interface. Step 4: After receiving the memory read message, the host-side DMA engine packages the data (corresponding to the memory read operation) into a read complete message and sends it via PCIe. The read complete message undergoes TLP parsing and data extraction via the bridge interface module and is then sent to the user logic via the AXI-MM slave interface. Step 5: The user-side logic receives data through the AXI-MM slave interface, thus completing the downlink data transfer.

[0024] This embodiment configures the IP core of the high-speed serial computer expansion bus standard PCIe in bridge mode; then, it queries the registers on the logic side through the main interface to obtain the idle / busy status, and sends the information of the downlink data to be moved to the logic side; it initiates a memory read operation through the slave interface, and receives the data corresponding to the memory read operation through the logic side and the slave interface to complete the data transfer, thereby reducing the consumption of logic resources, reducing the difficulty of development and later maintenance, and being applicable to multiple service types.

[0025] In one embodiment, the DMA transfer method based on PCIe bridge mode provided in this application may further include: Step 110: In bridged mode, PCIe has a master interface and a slave interface. The master interface is used to access registers on the logic side to transmit parameters and control messages. The slave interface is used to read and write the main memory on the host side. Step 120: Perform data migration according to the parameters sent by the host side.

[0026] Specifically, in the PCIe bridge interface mode, there is an AXI-MM master interface (i.e., the master interface in this embodiment) and an AXI-MM slave interface (i.e., the slave interface in this embodiment). The DMA transfer method based on PCIe bridge mode provided in this embodiment adopts the coexistence of AXI-MM master and AXI-MM slave interfaces to separate control messages and service data. The AXI-MM master interface is used by the host side (CPU) to access the registers on the logic side to realize the transmission of parameters and control messages; the AXI-MM slave interface is used by the logic side to read and write the main memory of the host side (CPU) and complete the data transfer according to the parameters issued by the host side (CPU).

[0027] This embodiment completes data transfer by transmitting parameters and control messages, as well as by sending parameters from the host side.

[0028] In one embodiment, the DMA transfer method based on PCIe bridge mode provided in this application may further include: Step 210: Query the registers on the logic side through the driver and the main interface to obtain the idle / busy status; Step 220: When the idle / busy state is an idle state, the length of the downlink data to be moved and the physical address where it is stored are sent to the logical side.

[0029] Specifically, the drive is through Figure 2 The AXI-MM master interface queries the register inside the logic side to obtain the idle / busy status, and judges the idle / busy status. If it is in a busy state, it waits; if it is in an idle state, it proceeds to step 2. Step 2, Driver Access Figure 2 The AXI-MM master interface writes to the registers inside the logic side, sending the length of the data to be moved (i.e., the downlink data to be moved in this embodiment) and the physical address where it is stored to the logic side.

[0030] In this embodiment, the registers on the logic side are queried through the driver and main interface, and the length of the downlink data to be moved and the physical address where it is stored are sent to the logic side.

[0031] In one embodiment, the DMA transfer method based on PCIe bridge mode provided in this application may further include: Step 230: Notify the logic side to initiate data transmission via the target register; Step 240: If the enable flag corresponding to the target register is detected on the logic side, the length of the downlink data to be moved and the physical address where it is stored are retrieved from the register on the logic side.

[0032] Specifically, the logic side is notified to start data transmission by enabling the flag register (i.e., the target register in this embodiment); Step 3: After the logic side detects the transmission enable flag, it retrieves the length of the downlink data to be moved and the physical address of its storage from the register inside the logic side.

[0033] In this embodiment, the length of the downlink data to be moved and its physical address are retrieved from the register on the logic side.

[0034] In one embodiment, the DMA transfer method based on PCIe bridge mode provided in this application may further include: Step 310: Receive memory read messages by directly accessing the DMA engine through the host-side memory; Step 320: Pack the data corresponding to the memory read operation into a read completion message using the PCIe and read completion message.

[0035] Specifically, the logic side is notified to start the transmission by enabling the flag register; Step 3: After the logic side detects the transmission enable flag, it retrieves the length of the downlink data to be moved and the physical address of its storage from the register inside the logic side, and initiates a memory read operation through the AXI-MM slave interface. Step 4: After receiving the memory read message, the host-side DMA engine packages the data corresponding to the memory read operation into the read complete message.

[0036] In this embodiment, the data corresponding to the memory read operation is packaged into the read complete message through PCIe and read complete message.

[0037] In one embodiment, the DMA transfer method based on PCIe bridge mode provided in this application may further include: Step 330: Extract the data corresponding to the memory read operation through the bridging mode and the read completion message; Step 340: Send the data corresponding to the memory read operation to the logic side through the slave interface, and receive the data corresponding to the memory read operation through the logic side and the slave interface.

[0038] Specifically, the data corresponding to the memory read operation is packaged into a read completion message and then sent via PCIe. The read completion message undergoes TLP parsing and data extraction via the bridge interface module and is then sent to the user logic via the AXI-MM slave interface. Step 5: The user-side logic receives data through the AXI-MM slave interface, thus completing the downlink data transfer.

[0039] This embodiment reduces the consumption of logical resources, lowers the difficulty of development and later maintenance, and is applicable to multiple business types by completing data reception from the interface.

[0040] Reference Figure 3 , Figure 3 This is a second schematic flowchart of the DMA transfer method based on PCIe bridge mode in the embodiments of this application. In one embodiment, the DMA transfer method based on PCIe bridge mode provided in the embodiments of this application may further include: Step 400: Determine the service type corresponding to the uplink data to be moved and the physical address corresponding to the service type; Step 500: Write the physical address corresponding to the service type into the register on the logical side via the driver; Step 600: Initiate data transmission through the logical side and the slave interface; Step 700: If the driver finds the reporting completion flag corresponding to the register on the logic side, read the uplink data to be moved. Step 800: After the driver has finished reading the uplink data to be moved, clear the reporting completion flag.

[0041] Specifically, the uplink data migration process is basically the same as the downlink process. The difference lies in the fact that the logic side needs to differentiate physical addresses based on different service types when performing uplink data transmission. Physical addresses are divided according to different service types. Different types of service data are stored in the physical address space using address offsets. Different service data correspond to different physical addresses, and the driver writes the physical addresses corresponding to each service into pre-defined logic registers. When the logic receives uplink service data, it first determines the data type, then queries the register to obtain the corresponding physical address, and then completes the data reporting migration from the interface and sets the reporting completion flag for the corresponding service. After the driver finds the reporting completion flag, it can read the data at the corresponding physical address. After the driver completes the reading, it clears the reporting completion flag, thus completing the uplink data migration.

[0042] This embodiment completes the uplink data migration by mapping service type to physical address.

[0043] refer to Figure 4 , Figure 4This is a schematic diagram of the DMA transfer device based on PCIe bridging mode in the embodiments of this application. The DMA transfer device based on PCIe bridging mode provided in the embodiments of this application will be described below. The DMA transfer device based on PCIe bridging mode described below and the DMA transfer method based on PCIe bridging mode described above can be referred to in correspondence with each other.

[0044] The bridge mode configuration module 401 is used to configure the IP core of the high-speed serial computer expansion bus standard PCIE into bridge mode. The data delivery module 402 is used to query the registers on the logic side through the main interface to obtain the idle / busy status. When the idle / busy status is an idle state, the information of the downlink data to be moved is sent to the logic side. The data receiving module 403 is used to initiate a memory read operation through the slave interface and receive the data corresponding to the memory read operation through the logic side and the slave interface.

[0045] In one embodiment, the bridging mode configuration module includes: An interface implementation unit is used in bridged mode, where PCIe has a master interface and a slave interface, wherein the master interface is used to access registers on the logical side to transmit parameters and control messages; and the slave interface is used to read and write the main memory on the host side. The data migration execution unit is used to perform data migration according to the parameters sent by the host side.

[0046] In one embodiment, the data delivery module includes: The idle / busy status acquisition unit is used to query the registers on the logic side through the driver and the main interface to obtain the idle / busy status; The data delivery unit is used to send the length of the downlink data to be moved and the physical address where it is stored to the logical side when the idle / busy state is an idle state.

[0047] In one embodiment, the DMA transfer device based on PCIe bridge mode includes: The first data transmission initiation module is used to notify the logic side to initiate data transmission via the target register; The first data extraction module is used to extract the length of the downlink data to be moved and its physical address from the register on the logic side when the enable flag corresponding to the target register is detected on the logic side.

[0048] In one embodiment, the data receiving module includes: The memory read message receiving unit is used to directly access the DMA engine through the host-side memory to receive memory read messages; The data packaging unit is used to package the data corresponding to the memory read operation into the read completion message via the PCIe and the read completion message.

[0049] In one embodiment, the DMA transfer device based on PCIe bridge mode includes: The second data extraction module is used to extract the data corresponding to the memory read operation through the bridging mode and the read completion message; The data sending module is used to send the data corresponding to the memory read operation to the logic side through the slave interface, and to receive the data corresponding to the memory read operation through the logic side and the slave interface.

[0050] In one embodiment, the DMA transfer device based on PCIe bridge mode includes: The service type determination module is used to determine the service type corresponding to the uplink data to be moved and the physical address corresponding to the service type. The physical address writing module is used to write the physical address corresponding to the service type into the register on the logical side through the driver; The second data transmission initiation module is used to initiate data transmission through the logical side and the slave interface; The uplink data to be moved module is used to read the uplink data to be moved when the driver queries the uplink completion flag bit corresponding to the register on the logic side; The reporting completion flag clearing module is used to clear the reporting completion flag when the driver has finished reading the uplink data to be moved.

[0051] Figure 5 An example is a schematic diagram of the physical structure of a device, such as... Figure 5 As shown, the device may include a processor 510, a communication interface 520, a memory 530, and a communication bus 540, wherein the processor 510, the communication interface 520, and the memory 530 communicate with each other through the communication bus 540. The processor 510 can call a computer program in the memory 530 to execute a DMA transfer method based on PCIe bridge mode.

[0052] Furthermore, the logical instructions in the aforementioned memory 530 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0053] On the other hand, embodiments of this application also provide a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, is implemented to perform the DMA transfer method based on PCIe bridge mode provided by the above methods.

[0054] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0055] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., including several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the DMA transfer method based on PCIe bridge mode described in various embodiments or some parts of embodiments.

[0056] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A DMA transfer method based on PCIe bridge mode, characterized in that, include: Configure the IP core of the high-speed serial computer expansion bus standard PCIe to bridge mode; The main interface queries the registers on the logic side to obtain the idle / busy status. If the idle / busy status is an idle state, the information of the downlink data to be moved is sent to the logic side. By initiating a memory read operation from the interface, the data corresponding to the memory read operation is received through the logic side and the slave interface.

2. The DMA transfer method based on PCIe bridge mode according to claim 1, characterized in that, The configuration of the PCIe IP core in bridged mode includes: In bridged mode, PCIe has a master interface and a slave interface. The master interface is used to access registers on the logic side to pass parameters and control messages; the slave interface is used to read and write the host-side main memory. The data migration is performed based on the parameters issued by the host side.

3. The DMA transfer method based on PCIe bridge mode according to claim 2, characterized in that, The step of querying the registers on the logic side through the main interface to obtain the idle / busy status and sending the information of the downlink data to be moved to the logic side includes: The idle / busy status is obtained by querying the registers on the logical side through the driver and the main interface; When the idle / busy state is in an idle state, the length of the downlink data to be moved and the physical address where it is stored are sent to the logical side.

4. The DMA transfer method based on PCIe bridge mode according to claim 3, characterized in that, After sending the length of the downlink data to be moved and its physical address to the logical side, the process includes: The logic side is notified via the target register to initiate data transmission; If the enable flag corresponding to the target register is detected on the logic side, the length of the downlink data to be moved and its physical address are retrieved from the register on the logic side.

5. The DMA transfer method based on PCIe bridge mode according to claim 1, characterized in that, The step of initiating a memory read operation via the interface and receiving data corresponding to the memory read operation via the logic side and the interface includes: Receive memory read messages by directly accessing the DMA engine through the host-side memory; The data corresponding to the memory read operation is packaged into the read complete message through the PCIe and read complete message.

6. The DMA transfer method based on PCIe bridge mode according to claim 5, characterized in that, The step of packaging the data corresponding to the memory read operation into the read completion message via the PCIe and the read completion message includes: The data corresponding to the memory read operation is extracted using the bridging mode and the read completion message; The data corresponding to the memory read operation is sent to the logic side through the slave interface, and the data corresponding to the memory read operation is received by the logic side and the slave interface.

7. The DMA transfer method based on PCIe bridge mode according to claim 2, characterized in that, Also includes: Determine the service type corresponding to the uplink data to be moved and the physical address corresponding to the service type; The driver writes the physical address corresponding to the service type into the register on the logical side; Data transmission is initiated via the logical side and the slave interface; If the driver queries the register corresponding to the uplink completion flag on the logic side, the uplink data to be moved is read. Once the driver has finished reading the uplink data to be moved, the reporting completion flag is cleared.

8. A DMA transfer device based on PCIe bridge mode, characterized in that, include: The bridge mode configuration module is used to configure the IP cores of the high-speed serial computer expansion bus standard PCIe into bridge mode. The data delivery module is used to query the registers on the logic side through the main interface to obtain the idle / busy status. When the idle / busy status is an idle state, the information of the downlink data to be moved is sent to the logic side. The data receiving module is used to initiate a memory read operation through the slave interface and receive the data corresponding to the memory read operation through the logic side and the slave interface.

9. An electronic device comprising a processor and a memory storing a computer program, characterized in that, When the processor executes the computer program, it implements the DMA transfer method based on PCIe bridge mode as described in any one of claims 1 to 7.

10. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the DMA transfer method based on PCIe bridge mode as described in any one of claims 1 to 7.

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