Analog circuit symmetry constraint determination method, training method, device and electronic equipment

Abstract

The present disclosure provides a method for determining symmetric constraints of analog circuits, a training method, a device and an electronic device, and relates to the field of artificial intelligence and analog circuit technology. The method includes: inputting a feature matrix of a circuit to be detected into a trained analog circuit symmetric constraint extraction model to obtain a symmetric constraint value, the feature matrix of the circuit to be detected is obtained by extracting features from a circuit diagram to be detected, and the feature matrix of the circuit to be detected includes a node feature matrix and an edge feature matrix; matching the symmetric constraint value to obtain a matching result; determining the symmetric constraint result according to the symmetric constraint value and the matching result, and obtaining the symmetric constraint value includes: processing the node feature matrix to obtain a standardized node feature matrix; processing the edge feature matrix to obtain a standardized edge feature matrix; obtaining a weight node feature matrix according to the standardized node feature matrix and the standardized edge feature matrix; obtaining a symmetric constraint value according to the weight node feature matrix and the node feature matrix.

Description

Technical Field

[0001] The present disclosure relates to the fields of artificial intelligence and analog circuits, and in particular to a method for determining symmetry constraints of analog circuits, a training method, a device, and an electronic device. Background Art

[0002] With the rapid development of the integrated industry, analog circuit design has gained attention in many application fields. As demand continues to grow, the design cycle of analog circuit design has increased. Acquiring analog circuit constraints is a more important operation to shorten the circuit design cycle. Among analog circuit constraints, symmetry constraints are one of the most extensive and representative constraints in analog circuits.

[0003] In the process of determining symmetry constraints in analog circuits, there is a problem of low recognition accuracy for the symmetry constraints. Summary of the invention

[0004] In view of the above problems, the present disclosure provides a method for determining symmetry constraints of an analog circuit, a training method, an apparatus, an electronic device, a medium, and a computer-readable storage medium.

[0005] One aspect of an embodiment of the present disclosure provides a method for determining symmetry constraints of an analog circuit.

[0006] A method for determining symmetry constraints of an analog circuit, comprising:

[0007] Inputting the feature matrix of the circuit to be detected into the trained analog circuit symmetry constraint extraction model to obtain the symmetry constraint value, wherein the analog circuit symmetry constraint extraction model includes a normalization layer, a calculation layer and an output layer, the feature matrix of the circuit to be detected is obtained by extracting features from the circuit diagram to be detected, and the feature matrix of the circuit to be detected includes a node feature matrix and an edge feature matrix;

[0008] Perform matching processing on the above symmetric constraint values ​​to obtain matching results; and

[0009] According to the above symmetry constraint value and the above matching result, the symmetry constraint result is determined, where

[0010] The above-mentioned circuit diagram to be detected is input into the trained analog circuit symmetry constraint extraction model to obtain the symmetry constraint value, including:

[0011] Processing the node feature matrix using the standardization layer to obtain a standardized node feature matrix;

[0012] Processing the edge feature matrix using the normalization layer to obtain a normalized edge feature matrix;

[0013] Using the computing layer, weight calculation is performed on the standardized node feature matrix and the standardized edge feature matrix to obtain a weighted node feature matrix;

[0014] The output layer is used to calculate the weight node feature matrix and the node feature matrix to obtain the symmetric constraint value.

[0015] According to an embodiment of the present disclosure, the above-mentioned circuit characteristic matrix to be detected includes first node information and second node information, the above-mentioned first node information includes first node parameter information and first global position information, the above-mentioned second node information includes second node parameter information and second global position information, and the above-mentioned symmetric constraint value includes first symmetric constraint value and second symmetric constraint value;

[0016] The above symmetric constraint values ​​are matched to obtain matching results, including:

[0017] Mapping the first symmetry constraint value and the circuit diagram to be detected to obtain the corresponding first node information;

[0018] Mapping the second symmetry constraint value and the circuit diagram to be detected to obtain the corresponding second node information;

[0019] Performing matching processing on the first node parameter information and the second node parameter information to obtain a first matching result;

[0020] Performing matching processing on the first global location information and the second global location information to obtain a second matching result; and

[0021] The matching result is obtained based on the first matching result and the second matching result.

[0022] According to an embodiment of the present disclosure, the computing layer is used to perform weight calculation on the standardized node feature matrix and the standardized edge feature matrix to obtain a weighted node feature matrix, including:

[0023] According to the first adjustable weight moment and the above-mentioned standardized node feature matrix, an intermediate weight node feature matrix is ​​obtained, wherein the above-mentioned first adjustable weight feature matrix represents the weight information of the above-mentioned standardized node feature matrix;

[0024] According to the second adjustable weight matrix and the above-mentioned standardized edge feature matrix, an intermediate weight edge feature matrix is ​​obtained, wherein the above-mentioned second adjustable weight feature matrix represents the weight information of the above-mentioned standardized edge feature matrix;

[0025] According to the intermediate weight node feature matrix and the intermediate weight edge feature matrix, a fusion feature matrix is ​​obtained;

[0026] The weight node feature matrix is ​​obtained according to the third adjustable weight matrix and the fused feature matrix, wherein the third adjustable weight matrix represents the weight information of the fused feature matrix.

[0027] According to an embodiment of the present disclosure, the above-mentioned intermediate weight node characteristic matrix includes a first intermediate weight node characteristic matrix, a second intermediate weight node characteristic matrix and a third intermediate weight node characteristic matrix;

[0028] The above-mentioned intermediate weight edge feature matrix includes a first intermediate weight edge feature matrix and a second intermediate weight edge feature matrix;

[0029] The above-mentioned fusion feature matrix is ​​obtained according to the above-mentioned intermediate weight node feature matrix and the above-mentioned intermediate weight edge feature matrix, including:

[0030] Obtaining an intermediate fusion feature matrix according to the first intermediate weight node feature matrix, the second intermediate weight node feature matrix, and the first intermediate weight edge feature matrix; and

[0031] The fused feature matrix is ​​obtained according to the third intermediate weight node feature matrix, the second intermediate weight edge feature matrix and the intermediate fused feature matrix.

[0032] Another aspect of an embodiment of the present disclosure provides a method for training an analog circuit symmetry constraint extraction model.

[0033] Training methods include:

[0034] Obtain a training sample set;

[0035] Input the above training sample set into the deep learning model to be trained to obtain the sample symmetry constraint value; and

[0036] The above-mentioned deep learning model is trained using the above-mentioned sample symmetry constraint values ​​and sample labels to obtain the above-mentioned analog circuit symmetry constraint extraction model.

[0037] According to an embodiment of the present disclosure, the above-mentioned obtaining of a training sample set includes:

[0038] According to the sample circuit diagram, sample node parameters of the sample circuit diagram are obtained;

[0039] According to the above sample node parameters, a sample node feature matrix and a sample edge feature matrix are obtained; and

[0040] The training sample set is obtained according to the sample node feature matrix and the sample edge feature matrix.

[0041] According to an embodiment of the present disclosure, the deep learning model is trained using the sample symmetry constraint values ​​and sample labels to obtain the analog circuit symmetry constraint extraction model, including:

[0042] Input the sample symmetry constraint value and the sample label into the loss function and output the loss result;

[0043] Iteratively adjusting the network parameters of the deep learning model according to the loss results until an iterative convergence condition is met; and

[0044] The above-mentioned analog circuit symmetry constraint extraction model is generated based on the network parameters of the above-mentioned deep learning model that meets the iterative convergence conditions.

[0045] Another aspect of an embodiment of the present disclosure provides an apparatus for determining symmetry constraints of an analog circuit.

[0046] The analog circuit symmetry constraint determination device comprises:

[0047] A first acquisition module is used to input a feature matrix of a circuit to be detected into a trained analog circuit symmetry constraint extraction model to obtain a symmetry constraint value, wherein the analog circuit symmetry constraint extraction model includes a normalization layer, a calculation layer and an output layer, the feature matrix of the circuit to be detected is obtained by extracting features from a circuit diagram to be detected, and the feature matrix of the circuit to be detected includes a node feature matrix and an edge feature matrix;

[0048] A second acquisition module is used to perform matching processing on the above symmetric constraint value to obtain a matching result;

[0049] A third acquisition module is used to determine the symmetry constraint result according to the symmetry constraint value and the matching result;

[0050] The first acquisition module includes: a first processing submodule, a second processing submodule, a third processing submodule and a first output submodule;

[0051] The first processing submodule is used to process the node feature matrix using a standardization layer to obtain a standardized node feature matrix;

[0052] The second processing submodule is used to process the edge feature matrix using a normalization layer to obtain a normalized edge feature matrix;

[0053] The third processing submodule is used to perform weight calculation on the standardized node feature matrix and the standardized edge feature matrix using the calculation layer to obtain a weighted node feature matrix;

[0054] The first output submodule is used to calculate the weight node feature matrix and the above-mentioned node feature matrix using the output layer to obtain the above-mentioned symmetric constraint value.

[0055] Another aspect of an embodiment of the present disclosure provides a training device for an analog circuit symmetry constraint extraction model.

[0056] A training device for analog circuit symmetry constraint extraction model, comprising:

[0057] A first acquisition module is used to acquire a training sample set;

[0058] A second acquisition module is used to input the training sample set into the deep learning model to be trained to obtain the sample symmetry constraint value; and

[0059] The third acquisition module is used to train the above-mentioned deep learning model using the above-mentioned sample symmetry constraint values ​​and sample labels to obtain the above-mentioned analog circuit symmetry constraint extraction model.

[0060] Another aspect of the present disclosure provides an electronic device, including one or more processors and a storage device, wherein the storage device is used to store executable instructions, and the executable instructions implement the method when executed by the processor.

[0061] Another aspect of the present disclosure provides a computer-readable storage medium storing computer-executable instructions, which are used to implement the above method when executed.

[0062] According to an embodiment of the present disclosure, in the process of determining the symmetry constraint result, the symmetry constraint result can be obtained according to the symmetry constraint value and the matching result; wherein, the feature matrix of the circuit to be detected includes a node feature matrix and an edge feature matrix, and a weighted node feature matrix is ​​obtained by standardizing and weighting the node feature matrix and the edge feature matrix, and the weighted node feature matrix and the node feature matrix are calculated to obtain the symmetry constraint value, which can effectively characterize the node characteristics of the feature matrix of the circuit to be detected; the matching result can be obtained by matching the information obtained by mapping the symmetry constraint value to the circuit diagram to be detected, and the matching result can characterize the matching relationship between the components included in the circuit diagram to be detected; the symmetry constraint relationship of the analog circuit is determined jointly by the symmetry constraint value and the matching result, thereby improving the recognition accuracy of the symmetry constraint. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] The above and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0064] Figure 1 The flowchart of the method for determining symmetry constraints of an analog circuit according to an embodiment of the present disclosure is schematically shown.

[0065] Figure 2a The figure schematically shows a connection diagram of a circuit diagram to be detected according to an embodiment of the present disclosure.

[0066] Figure 2bA schematic diagram of a directed edge graph of a circuit diagram to be detected according to an embodiment of the present disclosure is schematically shown.

[0067] Figure 2c The schematic diagram schematically shows a circuit diagram to be detected after feature vector embedding according to an embodiment of the present disclosure.

[0068] Figure 3 A block diagram of a symmetry constraint extraction model for an analog circuit according to an embodiment of the present disclosure is schematically shown.

[0069] Figure 4 The flowchart for obtaining the matching result according to the embodiment of the present disclosure is schematically shown.

[0070] Figure 5a The figure schematically shows a connection diagram of a circuit diagram to be detected according to another embodiment of the present disclosure.

[0071] Figure 5b The diagram schematically shows the global position of a circuit diagram to be detected according to an embodiment of the present disclosure.

[0072] Figure 6 The flowchart of the training method of the analog circuit symmetry constraint extraction model according to the embodiment of the present disclosure is schematically shown.

[0073] Figure 7 A block diagram of an analog circuit symmetry constraint determination device according to an embodiment of the present disclosure is schematically shown.

[0074] Figure 8 A block diagram of a training device for an analog circuit symmetry constraint extraction model according to an embodiment of the present disclosure is schematically shown.

[0075] Fig. 9 A block diagram of an electronic device according to an embodiment of the present disclosure is schematically shown. DETAILED DESCRIPTION

[0076] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present disclosure. In the following detailed description, for ease of explanation, many specific details are set forth to provide a comprehensive understanding of the embodiments of the present disclosure. However, it is apparent that one or more embodiments may also be implemented without these specific details. In addition, in the following description, descriptions of known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0077] The terms used herein are only for describing specific embodiments and are not intended to limit the present disclosure. The terms "comprise", "include", etc. used herein indicate the existence of features, steps, operations and / or components, but do not exclude the existence or addition of one or more other features, steps, operations or components.

[0078] All terms (including technical and scientific terms) used herein have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification, and should not be interpreted in an idealized or overly rigid manner.

[0079] In the case of using expressions such as "at least one of A, B, and C, etc.", it should generally be interpreted in accordance with the meaning of the expression generally understood by those skilled in the art (for example, "a system having at least one of A, B, and C" should include but is not limited to a system having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, C, etc.). In the case of using expressions such as "at least one of A, B, or C, etc.", it should generally be interpreted in accordance with the meaning of the expression generally understood by those skilled in the art (for example, "a system having at least one of A, B, or C" should include but is not limited to a system having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, C, etc.).

[0080] In the technical solution of the present disclosure, the collection, storage, use, processing, transmission, provision, disclosure and application of the data involved are in compliance with the provisions of relevant laws and regulations, necessary confidentiality measures are taken, and do not violate public order and good morals.

[0081] With the rapid development of the integrated circuit industry, integrated circuit design has gained attention in a variety of application fields. In integrated circuits, power supply, amplification, oscillation and modulation circuits can be called analog circuits, and analog circuits can process and handle continuously changing analog signals.

[0082] As demand continues to grow, the design cycle of analog circuit design is increasing. Therefore, the analog integrated circuit design process needs to be accelerated. In the automation of analog circuit design, it is necessary to rely on well-defined constraints in the circuit for layout design. Automatic extraction of analog circuit constraints is a more important operation to shorten the circuit design cycle.

[0083] Constraints can include symmetry, matching, etc., among which symmetry constraints are one of the most widely used and representative constraints in analog circuits. Symmetry constraints can refer to the constraints that design the layout, connection and characteristics of components in the circuit as symmetry. When symmetry constraints are placed on the analog circuit layout, the performance of the circuit can be effectively enhanced, the reliability of the circuit can be improved, the power consumption and noise can be reduced, and the design of the circuit can be made simpler. Therefore, it is very necessary to determine the symmetry constraints in analog circuits.

[0084] In the process of determining symmetry constraints in a circuit, there is a problem of low recognition accuracy for the symmetry constraints.

[0085] Figure 1 The diagram schematically illustrates a method for extracting symmetry constraints of an analog circuit according to an embodiment of the present disclosure.

[0086] like Figure 1 As shown, the analog circuit symmetry constraint extraction method 100 may include operations S110 to S130.

[0087] In operation S110, the feature matrix of the circuit to be detected is input into the trained analog circuit symmetry constraint extraction model to obtain a symmetry constraint value, wherein the analog circuit symmetry constraint extraction model includes a normalization layer, a calculation layer and an output layer, and the feature matrix of the circuit to be detected is obtained by extracting features from the circuit diagram to be detected, and the feature matrix of the circuit to be detected includes a node feature matrix and an edge feature matrix.

[0088] In operation S120, the symmetry constraint value is matched to obtain a matching result.

[0089] In operation S130, a symmetry constraint result is determined according to the symmetry constraint value and the matching result.

[0090] According to an embodiment of the present disclosure, inputting a circuit diagram to be detected into a trained analog circuit symmetry constraint extraction model to obtain a symmetry constraint value may include the following operations.

[0091] The node feature matrix is ​​processed by the normalization layer to obtain the normalized node feature matrix. The edge feature matrix is ​​processed by the normalization layer to obtain the normalized edge feature matrix. The weighted node feature matrix and the normalized edge feature matrix are calculated by the calculation layer to obtain the weighted node feature matrix. The weighted node feature matrix and the node feature matrix are calculated by the output layer to obtain the symmetric constraint value.

[0092] According to an embodiment of the present disclosure, the circuit diagram to be detected may be a circuit diagram obtained by model extraction based on an actual analog circuit structure. Elements included in the analog circuit may be extracted as node information for storage, and connection relationships between elements included in the analog circuit may be extracted as edge information for storage.

[0093] According to an embodiment of the present disclosure, through a simulation program with integrated circuit emphasis (SPICE), the actual simulation circuit structure can be output as a SPICE diagram, that is, a circuit diagram to be detected, and the SPICE diagram has node information and edge information. A characteristic matrix of the circuit to be detected is obtained based on the node information and edge information.

[0094] According to an embodiment of the present disclosure, the circuit feature matrix to be detected may include a node feature matrix and an edge feature matrix. The node feature matrix may be an N-row matrix, and each row of the node feature matrix may correspond to node information corresponding to an element included in the circuit diagram to be detected. The edge feature matrix may be an E-row matrix, and each row of the edge feature matrix may correspond to edge information corresponding to a connection relationship of an element included in the circuit diagram to be detected.

[0095] According to an embodiment of the present disclosure, the trained analog circuit symmetry constraint extraction model can be an analog circuit symmetry constraint extraction model obtained after parameter optimization by a deep learning model, and the node feature matrix and the edge feature matrix can be processed by the trained analog circuit symmetry constraint extraction model to obtain a symmetry constraint value. The symmetry constraint value can be a value obtained according to the characteristics of the circuit feature matrix to be detected, which characterizes the symmetry constraint relationship of the components in the circuit diagram to be detected.

[0096] According to an embodiment of the present disclosure, mapping is performed according to the symmetry constraint value, node information is obtained from the corresponding circuit diagram to be detected, and a matching result is obtained according to the node information, and the matching result represents the result of the symmetry constraint relationship of the components in the circuit diagram to be detected. For example, node information can be obtained in the circuit diagram to be detected according to the symmetry constraint value, and the node information includes size information or position information. The symmetry constraint relationship of the components in the circuit diagram to be detected is further determined through the size information or position information of the components, and a matching result is obtained.

[0097] According to an embodiment of the present disclosure, in the process of determining the symmetry constraint result, the symmetry constraint result can be obtained according to the symmetry constraint value and the matching result; wherein, the feature matrix of the circuit to be detected includes a node feature matrix and an edge feature matrix, and a weighted node feature matrix is ​​obtained by standardizing and weighting the node feature matrix and the edge feature matrix, and the weighted node feature matrix and the node feature matrix are calculated to obtain the symmetry constraint value, which can effectively characterize the node characteristics of the feature matrix of the circuit to be detected; the matching result can characterize the matching relationship between the symmetry constraint values; the symmetry constraint relationship of the analog circuit is determined jointly by the symmetry constraint value and the matching result, thereby improving the recognition accuracy of the symmetry constraint.

[0098] Figure 2a The figure schematically shows a connection diagram of a circuit diagram to be detected according to an embodiment of the present disclosure.

[0099] Figure 2b A schematic diagram of a directed edge graph of a circuit diagram to be detected according to an embodiment of the present disclosure is schematically shown.

[0100] Figure 2c The schematic diagram schematically shows a circuit diagram to be detected after feature vector embedding according to an embodiment of the present disclosure.

[0101] like Figure 2a The circuit diagram to be detected shown may include a power port (V dd , that is, transistor V 3 and transistor V 4 connected to the power port), and 4 transistors (V 3 、V 4 、V 8 and V 9 ). Figure 2a The circuit diagram to be tested shown in FIG. 1 is subjected to directed edge graph conversion operation, and the following Figure 2b The directed edge graph of the circuit diagram to be tested is shown in . Figure 2b The directed edge graph of the circuit diagram to be tested is shown in Figure 1. dd ) and 4 transistors (V 3 、V 4 、V 8 and V 9 ) are converted into nodes, and these five nodes are connected by directed edges.

[0102] According to an embodiment of the present disclosure, a node feature matrix can be obtained according to a circuit diagram to be detected. The node feature matrix can characterize the node information of the components in the circuit, and the node information may include the size and type of the components. Considering that the size and type of the components are more important factors for effectively identifying symmetry constraints, the type information of the components is converted into a 7-dimensional feature vector representation. For example, the 7-dimensional feature vector is written in the following order: (IO (power supply) NMOS (N-type transistor) PMOS (P-type transistor) NPN (N-type triode) PNP (P-type triode) diode (diode) passive (passive device)). The corresponding type is set to 1, otherwise it is 0.

[0103] According to an embodiment of the present disclosure, after the 7-dimensional feature vector representing the type information of the component, a 2-dimensional feature vector representing the size information of the component can be connected. The 2-dimensional feature vector is the width and length values ​​of the component in the order of writing.

[0104] According to the embodiments of the present disclosure, due to the common existence of differential pairs and current mirrors in analog circuits, and the obvious difference in the gate connection relationship between differential pairs and current mirrors for transistor elements, differential pairs and current mirror circuits can be distinguished by the gate connection relationship of transistor elements. Therefore, after the above 9-dimensional feature vector, a 1-dimensional feature vector is added to characterize the gate connection relationship of transistor elements. That is, when the gate of the transistor element node is connected to the IO port, this 1-dimensional feature vector is set to 1, otherwise it is 0. For non-transistors, this dimension is directly set to 0.

[0105] According to an embodiment of the present disclosure, a 10-dimensional feature vector of a component is used as a row of a matrix, and a node feature matrix is ​​obtained according to the components included in the circuit diagram to be detected.

[0106] According to an embodiment of the present disclosure, the node feature matrix can be a matrix of size N×10, where N is the number of components included in the circuit diagram to be detected corresponding to the node feature matrix, and 10 is the number of feature vectors, that is, the number of component information corresponding to the components.

[0107] According to an embodiment of the present disclosure, the length and width of the IO (power) port are both -1.

[0108] According to an embodiment of the present disclosure, an edge feature matrix can be obtained according to the circuit diagram to be detected. The edge feature matrix can characterize the edge information of the components in the circuit. The connection relationship of the edge of the component can be represented by a 5-dimensional feature vector, which is represented in the order of writing (gate (gate pin connection) drain (drain pin connection) source (source pin connection) passive (passive port pin connection) other possible pin connections). When the current node has a connection relationship with a pin of another node, the corresponding vector in the directed edge of the current node pointing to the other node is represented by 1, otherwise it is 0.

[0109] According to an embodiment of the present disclosure, the edge feature matrix may be a matrix of size E×5, where E is the number of edges of the components included in the circuit diagram to be detected corresponding to the edge feature matrix, and 5 is the number of edge information included.

[0110] According to the embodiments of the present disclosure, according to the above settings, the following can be obtained: Figure 2c The schematic diagram of the circuit diagram to be detected after feature vector embedding is shown. Figure 2c Each node in has a node feature matrix, and any nodes have an edge feature matrix.

[0111] According to the embodiments of the present disclosure, in practical applications, the symmetry constraint determination method of the analog circuit is used to determine the symmetry constraint of the complete circuit. The complete circuit is a circuit that can operate normally.

[0112] Figure 3 A block diagram of a symmetry constraint extraction model for an analog circuit according to an embodiment of the present disclosure is schematically shown.

[0113] like Figure 3 As shown, in the case of the circuit feature matrix to be detected obtained by extracting features from the circuit diagram to be detected, the node feature matrix and the edge feature matrix included in the circuit feature matrix to be detected are respectively input into the standardization layer of the analog circuit symmetry constraint extraction model to obtain the standardized node feature matrix n corresponding to the node feature matrix nfeats L, and obtain the standardized node feature matrix e corresponding to the edge feature matrix efeats L .

[0114] According to the embodiments of the present disclosure, the node feature matrix nfeats and the edge feature matrix efeats are standardized respectively, which can compress the numerical sizes of the node feature matrix nfeats and the edge feature matrix efeats, effectively reduce the amount of calculation in the operation, and speed up the processing speed of the analog circuit symmetry constraint extraction model.

[0115] According to an embodiment of the present disclosure, the node feature matrix nfeats is standardized to obtain a standardized node feature matrix n L It can be expressed by the following formula (1).

[0116] n L =LN(nfeats)(1)

[0117] Among them, n L is the standardized node feature matrix, n L ∈R N×10 , R is a real number type, and its superscript indicates that the standardized node feature matrix is ​​a real number type matrix of size N×10; LN() is the standardization function; nfeats is the node feature matrix.

[0118] According to an embodiment of the present disclosure, the edge feature matrix efeats is standardized to obtain a standardized edge feature matrix e L It can be expressed by the following formula (2).

[0119] e L =LN(efeats)(2)

[0120] Among them, e L is the standardized node feature matrix, e L ∈R E×5 , R is a real number type, and its superscript indicates that the standardized edge feature matrix is ​​a real number type matrix of size E×5; LN() is the standardization function; efeats is the edge feature matrix.

[0121] According to an embodiment of the present disclosure, weight calculation is performed on a standardized node feature matrix and a standardized edge feature matrix using a computing layer to obtain a weighted node feature matrix, which may include the following operations.

[0122] According to the first adjustable weight matrix and the standardized node feature matrix, an intermediate weight node feature matrix is ​​obtained, wherein the first adjustable weight feature matrix represents the weight information of the standardized node feature matrix. According to the second adjustable weight matrix and the standardized edge feature matrix, an intermediate weight edge feature matrix is ​​obtained, wherein the second adjustable weight feature matrix represents the weight information of the standardized edge feature matrix. According to the intermediate weight node feature matrix and the intermediate weight edge feature matrix, a fused feature matrix is ​​obtained. According to the third adjustable weight matrix and the fused feature matrix, a weight node feature matrix is ​​obtained, wherein the third adjustable weight matrix represents the weight information of the fused feature matrix.

[0123] According to an embodiment of the present disclosure, the intermediate weight node feature matrix includes a first intermediate weight node feature matrix, a second intermediate weight node feature matrix, and a third intermediate weight node feature matrix.

[0124] According to an embodiment of the present disclosure, the first adjustable weight feature matrix may include three learnable first weight matrices, and the three learnable first weight matrices may be matrices of size 10×10 with different and adjustable parameters, represented by Q, K and V respectively.

[0125] like Figure 3 As shown, after obtaining the node feature matrix nfeats and the edge feature matrix efeats, the node feature matrix nfeats is multiplied by Q, K and V respectively to obtain the first intermediate weight node feature matrix, the second intermediate weight node feature matrix and the third intermediate weight node feature matrix which can be expressed by the following formula (3).

[0126]

[0127] Among them, n Q is the first intermediate weight node feature matrix, n Q ∈R N×10 ;n K is the feature matrix of the second intermediate weight node, n K ∈R N×10 ;n V is the feature matrix of the third intermediate weight node, n V ∈R N×10 .

[0128] According to an embodiment of the present disclosure, the parameters of the first adjustable weight feature matrix can be adjusted. The parameters of the first adjustable weight feature matrix can be adjusted by training the analog circuit symmetry constraint extraction model using a training sample set to obtain the first adjustable weight feature matrix related to the training sample set.

[0129] According to an embodiment of the present disclosure, the intermediate weight edge feature matrix includes a first intermediate weight edge feature matrix and a second intermediate weight edge feature matrix. According to an embodiment of the present disclosure, the second adjustable weight matrix may include two learnable second weight matrices, and the two learnable second weight matrices may be matrices of size 5×5, with different and adjustable parameters, represented by D and B respectively.

[0130] like Figure 3 As shown, after obtaining the node feature matrix nfeats and the edge feature matrix efeats, the edge feature matrix efeats is multiplied by D and BV respectively to obtain the first intermediate weight edge feature matrix and the second intermediate weight edge feature matrix which can be expressed by the following formula (4).

[0131]

[0132] Among them, e D is the first intermediate weight edge feature matrix, e D ∈R E×5 ;e B is the second intermediate weight edge feature matrix, e B ∈R E×5 .

[0133] According to an embodiment of the present disclosure, the parameters of the second adjustable weight feature matrix can be adjusted. The parameters of the second adjustable weight feature matrix can be adjusted by training the analog circuit symmetry constraint extraction model using a training sample set to obtain a second adjustable weight feature matrix related to the training sample set.

[0134] According to the intermediate weight node feature matrix and the intermediate weight edge feature matrix, obtaining the fused feature matrix includes the following operations.

[0135] According to the embodiments of the present disclosure, in practical applications, the first intermediate weight node feature matrix, the second intermediate weight node feature matrix, and the third intermediate weight node feature matrix can be rewritten through a multi-head attention mechanism, and the number of heads is set to 5 to keep consistent with the number of edges, so n Q 、n K and n V The dimension can be changed to N×5×2, and e D The dimension of is also converted to E×5×1.

[0136] like Figure 3 As shown, the first intermediate weight node feature matrix n Q and the second intermediate weight node feature matrix n K Multiply and scale, and then fuse with the second intermediate weight edge feature matrix to obtain the intermediate fusion feature matrix, which can be expressed by the following formula (5).

[0137] Dot vals =(Dot val / s)+e B (5)

[0138] Among them, Dot vals is the intermediate fusion feature matrix, Dot vals ∈R E×5 ; Dot val To scale the node feature matrix, Dot val =n Q ⊙n K , s is the scaling factor.

[0139] According to an embodiment of the present disclosure, the scaling node feature matrix may be a first intermediate weight node feature matrix n with different weights. Q and the second intermediate weight node feature matrix n K The scaling node feature matrix can have the first intermediate weight node feature matrix n Q and the second intermediate weight node feature matrix n K Corresponding feature information, further processing of the scaled node feature matrix is ​​beneficial to obtain multiple information of the node feature matrix, thereby improving the recognition accuracy of the symmetric constraint.

[0140] According to an embodiment of the present disclosure, in actual operation, the scaling factor s may be set to 2.

[0141] like Figure 3 As shown, according to the third intermediate weight node feature matrix, the second intermediate weight edge feature matrix and the intermediate fusion feature matrix, a fusion feature matrix is ​​obtained, which can be expressed by the following formula (6).

[0142] a f =e C ⊙atten(6)

[0143] Among them, a f is the fusion feature matrix; e C is the concatenation matrix; atten is the category information of the intermediate fusion feature matrix.

[0144] like Figure 3 As shown, the concatenation matrix can be expressed by the following formula (7).

[0145] e c =cat(n V ,e D )(7)

[0146] According to an embodiment of the present disclosure, the category information of the intermediate fusion feature matrix can be expressed by the following formula (8).

[0147] Among them, cat() is the concatenation function; n V is the feature matrix of the third intermediate weight node; e D is the first intermediate weight edge feature matrix.

[0148] atten=softmax(Dot vals )(8)

[0149] Among them, softmax() is the activation function.

[0150] According to an embodiment of the present disclosure, the third adjustable weight matrix may include one learnable third weight matrix, and the third weight matrix may be a matrix with a size of 15×10 and adjustable parameters, represented by w.

[0151] According to an embodiment of the present disclosure, the parameters of the third adjustable weight feature matrix can be adjusted. The parameters of the third adjustable weight feature matrix can be adjusted by training the analog circuit symmetry constraint extraction model using a training sample set to obtain a third adjustable weight feature matrix related to the training sample set.

[0152] like Figure 3 As shown, according to the third adjustable weight matrix and the fusion feature matrix, the weight node feature matrix can be expressed by the following formula (9).

[0153]

[0154] Among them, h a is the weight node feature matrix; K is the second intermediate weight node feature matrix n K Corresponding position, i is an integer; w is the third adjustable weight matrix; a f is the fusion feature matrix.

[0155] According to an embodiment of the present disclosure, the weight node feature matrix and the node feature matrix are added in the output layer, and the values ​​of the elements at corresponding positions of the weight node feature matrix and the node feature matrix are added to obtain a symmetry constraint value, which is a matrix with the same size as the weight node feature matrix and the node feature matrix. By adding the weight node feature matrix and the node feature matrix, the loss of node feature information due to model calculation can be suppressed, thereby improving the recognition accuracy of the symmetry constraint.

[0156] like Figure 3 As shown, after the calculation layer outputs the weight node feature matrix, the symmetric constraint value obtained by the weight node feature matrix and the node feature matrix can be expressed by the following formula (10).

[0157] h out =MLP(h)+h(10)

[0158] Among them, h out is the symmetry constraint value, h out ∈R N×10 ;

[0159] According to an embodiment of the present disclosure, the circuit characteristic matrix to be detected may include first node information and second node information. The first node information may include first node parameter information and first global position information. The second node information may include second node parameter information and second global position information, and the symmetric constraint value may include a first symmetric constraint value and a second symmetric constraint value.

[0160] According to an embodiment of the present disclosure, matching the symmetry constraint value to obtain a matching result may include the following operations.

[0161] The first symmetric constraint value and the circuit diagram to be detected are mapped to obtain the first node information of the circuit diagram element to be detected corresponding to the first symmetric constraint value. The second symmetric constraint value and the circuit diagram to be detected are mapped to obtain the second node information corresponding to the circuit diagram element to be detected corresponding to the second symmetric constraint value. The first node parameter information and the second node parameter information are matched to obtain a first matching result. The first global position information and the second global position information are matched to obtain a second matching result. A matching result is obtained according to the first matching result and the second matching result.

[0162] According to an embodiment of the present disclosure, the first node parameter information and the second node parameter information can respectively represent the size information of the two elements and the category information of the two elements. When the sizes of the two elements are consistent and the categories of the two elements are consistent, a first matching result representing that the two elements match is obtained. On the contrary, when at least one of the size and category of the two elements does not match, a first matching result representing that the two elements do not match is obtained.

[0163] According to an embodiment of the present disclosure, by matching the first node information and the second node information, two elements whose symmetry constraint values ​​meet the symmetry constraint conditions are further matched, thereby obtaining two elements of the same size and type.

[0164] According to an embodiment of the present disclosure, Figure 4 The flowchart for obtaining the matching result according to the embodiment of the present disclosure is schematically shown.

[0165] like Figure 4 As shown, obtaining the matching result may include operations S410 to S480.

[0166] In operation S410, a symmetric constraint value is obtained. The symmetric constraint value may be a matrix of size N×10, and any two rows of information are obtained from the symmetric constraint value to obtain a first symmetric constraint value and a second symmetric constraint value, respectively.

[0167] In operation S420, it is determined whether the symmetric constraint values ​​match. The cosine similarity of the first symmetric constraint value and the second symmetric constraint value is calculated to obtain the cosine similarity value corresponding to the first symmetric constraint value and the second symmetric constraint value. If the cosine similarity value is less than a preset threshold, operation S430 is performed, and if the cosine similarity value is not less than the preset threshold, operation S440 is performed.

[0168] According to an embodiment of the present disclosure, the preset threshold may be set to 0.6.

[0169] In operation S430, a non-matching result is output.

[0170] In operation S440, node parameter information is obtained. According to the corresponding position of the symmetry constraint value, first node parameter information and second node parameter information of the corresponding element in the circuit diagram to be detected are obtained.

[0171] In operation S450, it is determined whether the node parameter information matches. When the first node parameter information and the second node parameter information are consistent, the node parameter information matches, and operation S460 is performed, otherwise operation S430 is performed.

[0172] According to an embodiment of the present disclosure, the two-dimensional feature vectors of size information of connection characterization elements in the node feature matrix can be matched. When the feature vectors of the first node parameter information and the second node parameter are consistent, the two elements corresponding to the first symmetry constraint value and the second symmetry constraint value are matched.

[0173] According to an embodiment of the present disclosure, the categories of the components corresponding to the first symmetry constraint value and the second symmetry constraint value can also be matched by comparing the circuit diagram to be detected. When the categories of the components are consistent, a result indicating that the two components match is obtained. On the contrary, when the categories of the two components do not match, a result indicating that the two components do not match is obtained.

[0174] In operation S460, global position information is obtained. According to the corresponding position of the symmetry constraint value, first global position information and second global position information of the corresponding element in the circuit diagram to be detected are obtained.

[0175] In operation S470, it is determined whether the global position information matches. When the first global position information and the second global position information are consistent, the global position information matches, and operation S480 is performed, otherwise operation S430 is performed.

[0176] According to an embodiment of the present disclosure, the global position may represent the positional relationship between the elements included in the circuit diagram to be detected and the overall structure of the circuit diagram to be detected.

[0177] According to the embodiments of the present disclosure, for any P-type transistor, the global position can be set to the sum of the weights of the shortest path from the power supply terminal to the P-type transistor. For any N-type transistor, the global position can be set to the sum of the weights of the shortest path from the ground terminal to the N-type transistor.

[0178] According to an embodiment of the present disclosure, the weight may be the weight of an edge connecting two components, and the specific value of the weight may be defined as follows: when the components connected at both ends of the edge are passive components, the weight is 0. When any end of the components connected at both ends of the edge includes a passive device, the weight is 0.5, and when the components connected at both ends of the edge are active components, the weight is 1.

[0179] Figure 5a The figure schematically shows a connection diagram of a circuit diagram to be detected according to another embodiment of the present disclosure.

[0180] Figure 5b The diagram schematically shows the global position of a circuit diagram to be detected according to an embodiment of the present disclosure.

[0181] like Figure 5a The circuit diagram to be tested shown in FIG. 1 can be obtained through global position weighted calculation as follows: Figure 5b The global position diagram of the circuit diagram to be detected is shown.

[0182] According to the embodiments of the present disclosure, for example, V14 is an N-type transistor, and through SPICE identification, it can be obtained that the shortest path of V14 from the ground terminal is from the ground terminal to V19, and then to V14 through V19. Since V19 is also an N-type transistor, the shortest path of V19 from the ground terminal is directly grounded, and the weight corresponding to the edge connecting the ground and V19 is 1, and the weight corresponding to the edge connecting V14 and V19 is also 1, so the global position of V14 is that the sum of the weights is 2.

[0183] Figure 6 The flowchart of the training method of the analog circuit symmetry constraint extraction model according to the embodiment of the present disclosure is schematically shown.

[0184] like Figure 6 As shown, the training method 600 of the analog circuit symmetry constraint extraction model may include operations S610 to S630.

[0185] In operation S610, a training sample set is acquired.

[0186] In operation S620, a training sample set is input into a deep learning model to be trained to obtain a sample symmetry constraint value.

[0187] In operation S630, a deep learning model is trained using sample symmetry constraint values ​​and sample labels to obtain an analog circuit symmetry constraint extraction model.

[0188] According to an embodiment of the present disclosure, obtaining a training sample set may include the following operations.

[0189] According to the sample circuit diagram, the sample node parameters of the sample circuit diagram are obtained. According to the sample node parameters, the sample node feature matrix and the sample edge feature matrix are obtained. According to the sample node feature matrix and the sample edge feature matrix, a training sample set is obtained.

[0190] According to the embodiments of the present disclosure, the process of extracting features from a sample circuit diagram to obtain a training sample set may correspond to the operation of obtaining a feature matrix of a circuit to be detected based on a circuit diagram to be detected, which will not be described in detail herein.

[0191] According to an embodiment of the present disclosure, training a deep learning model using sample symmetry constraint values ​​and sample labels to obtain an analog circuit symmetry constraint extraction model includes the following operations.

[0192] The sample node symmetry constraint value and sample label are input into the loss function, and the loss result is output. The network parameters of the deep learning model are iteratively adjusted according to the loss result until the iterative convergence condition is met. The analog circuit symmetry constraint extraction model is generated according to the network parameters of the deep learning model that meets the iterative convergence condition.

[0193] According to an embodiment of the present disclosure, the sample label may be a symmetry constraint relationship corresponding to components included in a preset sample circuit diagram.

[0194] According to an embodiment of the present disclosure, LogisticsLoss can be used as a loss function, the sample symmetry constraint value and the sample label can be calculated, and the network parameters of the deep learning model can be adjusted through reverse gradient.

[0195] According to an embodiment of the present disclosure, the gradient descent algorithm with Adam adaptive learning rate is used as the optimizer, and the initial learning rate can be 0.002.

[0196] According to an embodiment of the present disclosure, training may be stopped when the number of training rounds reaches 450 rounds.

[0197] According to an embodiment of the present disclosure, training may also be stopped when the number of training rounds does not meet 450 rounds and the loss function converges.

[0198] According to an embodiment of the present disclosure, the analog circuit symmetry constraint extraction model can also obtain the side information output, and the side information output can be expressed by the following formula (11).

[0199] e out =MLP(e)+e(11)

[0200] Among them, e outis the side information output, e out ∈R E×5 ; e is the intermediate quantity of the side information output e = Dot vals +efeats,e∈R E×5 .

[0201] According to the embodiments of the present disclosure, during the training process, the following can be used: Figure 3 The analog circuit symmetry constraint extraction model shown in the figure is cycled three times to obtain the sample symmetry constraint value h out .

[0202] According to an embodiment of the present disclosure, for example, after the node feature matrix nfeats and the edge feature matrix efeats are input into the analog circuit symmetry constraint extraction model, the sample symmetry constraint value and the edge information output of the first output are obtained, and the sample symmetry constraint value and the edge information output of the first output are used as the second input in three cycles, that is, the sample symmetry constraint value output for the first time is used as the node feature matrix nfeats, and the edge information output of the first output is used as the edge feature matrix efeats, and processed, and finally the sample symmetry constraint value after completing three cycles is used as the sample symmetry constraint value h obtained in one training. out .

[0203] According to an embodiment of the present disclosure, the sample symmetry constraint value h obtained by looping out , can better represent the characteristics of the circuit diagram to be detected, according to the sample symmetry constraint value h out The trained analog circuit symmetry constraint extraction model can improve the accuracy of symmetry constraint recognition in actual use.

[0204] Figure 7 A block diagram of an analog circuit symmetry constraint determination device according to an embodiment of the present disclosure is schematically shown.

[0205] like Figure 7 As shown, the analog circuit symmetry constraint determination device 700 may include a first acquisition module 710 , a second acquisition module 720 and a third acquisition module 730 .

[0206] The first acquisition module 710 can be used to input the feature matrix of the circuit to be detected into the trained analog circuit symmetry constraint extraction model to obtain the symmetry constraint value, wherein the analog circuit symmetry constraint extraction model includes a normalization layer, a calculation layer and an output layer, the feature matrix of the circuit to be detected is obtained by extracting features from the circuit diagram to be detected, and the feature matrix of the circuit to be detected includes a node feature matrix and an edge feature matrix;

[0207] The second acquisition module 720 may be used to perform matching processing on the symmetry constraint value to obtain a matching result.

[0208] The third acquisition module 730 may be used to determine the symmetry constraint result according to the symmetry constraint value and the matching result.

[0209] The first acquisition module 710 may include: a first processing submodule 711 , a second processing submodule 712 , a third processing submodule 713 and a first output submodule 714 .

[0210] The first processing submodule 711 may be used to process the node feature matrix using a normalization layer to obtain a normalized node feature matrix.

[0211] The second processing submodule 712 may be used to process the edge feature matrix using a normalization layer to obtain a normalized edge feature matrix.

[0212] The third processing submodule 713 may be used to perform weight calculation on the standardized node feature matrix and the standardized edge feature matrix using the calculation layer to obtain a weighted node feature matrix.

[0213] The first output submodule 714 can be used to calculate the weight node feature matrix and the node feature matrix using the output layer to obtain the symmetric constraint value.

[0214] According to an embodiment of the present disclosure, the third acquisition module 730 may include a first acquisition submodule, a second acquisition submodule, a third acquisition submodule, a fourth acquisition submodule and a fifth acquisition submodule.

[0215] The first acquisition submodule can be used to map the first symmetry constraint value and the circuit diagram to be detected to obtain corresponding first node information.

[0216] The second acquisition submodule can be used to map the second symmetry constraint value and the circuit diagram to be detected to obtain corresponding second node information.

[0217] The third acquisition submodule can be used to perform matching processing on the first node parameter information and the second node parameter information to obtain a first matching result.

[0218] The fourth acquisition submodule can be used to perform matching processing on the first global position information and the second global position information to obtain a second matching result.

[0219] The fifth acquisition submodule can be used to obtain a matching result according to the first matching result and the second matching result.

[0220] According to an embodiment of the present disclosure, the third processing submodule 713 may include a first acquisition unit, a second acquisition unit, a third acquisition unit, and a fourth acquisition unit.

[0221] The first acquisition unit can be used to obtain an intermediate weight node feature matrix according to the first adjustable weight matrix and the standardized node feature matrix, wherein the first adjustable weight feature matrix can represent weight information of the standardized node feature matrix.

[0222] The second acquisition unit can be used to obtain an intermediate weight edge feature matrix according to the second adjustable weight matrix and the standardized edge feature matrix, wherein the second adjustable weight feature matrix can represent the weight information of the standardized edge feature matrix.

[0223] The third acquisition unit can be used to obtain a fused feature matrix according to the intermediate weight node feature matrix and the intermediate weight edge feature matrix.

[0224] The fourth acquisition unit can be used to obtain a weight node feature matrix according to the third adjustable weight matrix, the fusion feature matrix and the node feature matrix. The third adjustable weight matrix can represent the weight information of the fusion feature matrix.

[0225] According to an embodiment of the present disclosure, the third acquisition unit may include a first acquisition subunit and a second acquisition subunit.

[0226] The first acquisition subunit can be used to obtain an intermediate fusion feature matrix according to the first intermediate weight node feature matrix, the second intermediate weight node feature matrix and the first intermediate weight edge feature matrix.

[0227] The second acquisition subunit can be used to obtain a fused feature matrix according to the third intermediate weight node feature matrix, the second intermediate weight edge feature matrix and the intermediate fused feature matrix.

[0228] Figure 8 A block diagram of a training device for an analog circuit symmetry constraint extraction model according to an embodiment of the present disclosure is schematically shown.

[0229] like Figure 8 As shown, the analog circuit symmetry constraint determination device 800 may include a first acquisition module 810 , a second acquisition module 820 and a third acquisition module 830 .

[0230] The first acquisition module 810 may be used to acquire a training sample set.

[0231] The second acquisition module 820 can be used to input the training sample set into the deep learning model to be trained to obtain the sample symmetry constraint value.

[0232] The third acquisition module 830 is used to train the deep learning model using the sample symmetry constraint values ​​and sample labels to obtain the analog circuit symmetry constraint extraction model.

[0233] According to an embodiment of the present disclosure, the first acquisition module 810 may include a sixth acquisition submodule, a seventh acquisition submodule and an eighth acquisition submodule.

[0234] The sixth acquisition submodule can be used to obtain sample node parameters of the sample circuit diagram according to the sample circuit diagram.

[0235] The seventh acquisition submodule can be used to obtain a sample node feature matrix and a sample edge feature matrix according to the sample node parameters.

[0236] The eighth acquisition submodule can be used to obtain a training sample set according to the sample node feature matrix and the sample edge feature matrix.

[0237] According to an embodiment of the present disclosure, the eighth acquisition submodule may include a second output submodule, a regulation submodule and a generation submodule.

[0238] The second output submodule can be used to input the sample symmetry constraint value and sample label into the loss function and output the loss result.

[0239] The adjustment submodule can be used to iteratively adjust the network parameters of the deep learning model according to the loss results until the iterative convergence conditions are met.

[0240] The generation submodule can be used to generate an analog circuit symmetry constraint extraction model based on the network parameters of the deep learning model that meets the iterative convergence conditions.

[0241] Fig. 9 A block diagram of an electronic device suitable for implementing a method for determining a symmetry constraint of an analog circuit and a method for training an analog circuit symmetry constraint extraction model according to an embodiment of the present disclosure is schematically shown.

[0242] like Fig. 9 As shown, the electronic device 900 according to an embodiment of the present application includes a processor 901, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 902 or a program loaded from a storage part 908 into a random access memory (RAM) 903. The processor 901 may include, for example, a general-purpose microprocessor (e.g., a CPU), an instruction set processor and / or a related chipset and / or a special-purpose microprocessor (e.g., an application-specific integrated circuit (ASIC)), etc. The processor 901 may also include an onboard memory for caching purposes. The processor 901 may include a single processing unit or multiple processing units for performing different actions of the method flow according to an embodiment of the present application.

[0243] In RAM903, various programs and data required for the operation of electronic device 900 are stored. Processor 901, ROM902 and RAM903 are connected to each other via bus 904. Processor 901 performs various operations of the method flow according to the embodiment of the present application by executing the program in ROM902 and / or RAM903. It should be noted that the program can also be stored in one or more memories other than ROM902 and RAM903. Processor 901 can also perform various operations of the method flow according to the embodiment of the present application by executing the program stored in one or more memories.

[0244] According to an embodiment of the present application, the electronic device 900 may further include an input / output (I / O) interface 905, which is also connected to the bus 904. The electronic device 900 may further include one or more of the following components connected to the I / O interface 905: an input portion 906 including a keyboard, a mouse, etc.; an output portion 907 including a cathode ray tube (CRT), a liquid crystal display (LCD), etc., and a speaker, etc.; a storage portion 908 including a hard disk, etc.; and a communication portion 909 including a network interface card such as a LAN card, a modem, etc. The communication portion 909 performs communication processing via a network such as the Internet. A drive 910 is also connected to the I / O interface 905 as needed. A removable medium 911, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed on the drive 910 as needed, so that a computer program read therefrom is installed into the storage portion 908 as needed.

[0245] The present application also provides a computer-readable storage medium, which may be included in the device / apparatus / system described in the above embodiments; or may exist independently without being assembled into the device / apparatus / system. The above computer-readable storage medium carries one or more programs, and when the above one or more programs are executed, the method according to the embodiment of the present application is implemented.

[0246] According to an embodiment of the present application, a computer-readable storage medium may be a non-volatile computer-readable storage medium, for example, may include but is not limited to: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present application, a computer-readable storage medium may be any tangible medium containing or storing a program, which may be used by or in combination with an instruction execution system, an apparatus or a device. For example, according to an embodiment of the present application, a computer-readable storage medium may include the ROM902 and / or RAM903 described above and / or one or more memories other than ROM902 and RAM903.

[0247] The embodiments of the present application also include a computer program product, which includes a computer program, and the computer program includes a program code for executing the method shown in the flowchart. When the computer program product is run in a computer system, the program code is used to enable the computer system to implement the item recommendation method provided in the embodiments of the present application.

[0248] The computer program executes the above functions defined in the system / device of the embodiment of the present application when the processor 901 executes the computer program. According to the embodiment of the present application, the system, device, module, unit, etc. described above can be implemented by a computer program module.

[0249] In one embodiment, the computer program may be based on a tangible storage medium such as an optical storage device, a magnetic storage device, etc. In another embodiment, the computer program may also be transmitted and distributed in the form of a signal on a network medium, and downloaded and installed through the communication part 909, and / or installed from a removable medium 911. The program code contained in the computer program may be transmitted using any appropriate network medium, including but not limited to: wireless, wired, etc., or any suitable combination of the above.

[0250] In such an embodiment, the computer program can be downloaded and installed from the network through the communication part 909, and / or installed from the removable medium 911. When the computer program is executed by the processor 901, the above functions defined in the system of the embodiment of the present application are performed. According to the embodiment of the present application, the system, device, means, module, unit, etc. described above can be implemented by a computer program module.

[0251] According to an embodiment of the present application, the program code for executing the computer program provided in the embodiment of the present application can be written in any combination of one or more programming languages, specifically, these computing programs can be implemented using high-level processes and / or object-oriented programming languages, and / or assembly / machine languages. Programming languages ​​include, but are not limited to, such as Java, C++, python, "C" language or similar programming languages. The program code can be executed completely on the user computing device, partially on the user device, partially on the remote computing device, or completely on the remote computing device or server. In the case of a remote computing device, the remote computing device can be connected to the user computing device through any type of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computing device (e.g., using an Internet service provider to connect through the Internet).

[0252] The flow chart and block diagram in the accompanying drawings illustrate the possible architecture, function and operation of the system, method and computer program product according to various embodiments of the present application. In this regard, each box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the above-mentioned module, program segment or a part of a code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flow chart, and the combination of the boxes in the block diagram or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0253] It will be appreciated by those skilled in the art that the features described in the various embodiments and / or claims of the present application may be combined in a variety of ways and / or combinations, even if such combinations or combinations are not explicitly described in the present application. In particular, without departing from the spirit and teachings of the present application, the features described in the various embodiments and / or claims of the present application may be combined in a variety of ways and / or combinations. All of these combinations and / or combinations fall within the scope of the present application.

[0254] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0255] The embodiments of the present application are described above. However, these embodiments are only for the purpose of illustration, and are not intended to limit the scope of the present application. Although the embodiments are described above, this does not mean that the measures in the various embodiments cannot be used in combination. The scope of the present application is limited by the attached claims and their equivalents. Without departing from the scope of the present application, those skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present application.

Claims

1. A method for determining symmetry constraints of an analog circuit, comprising: Inputting a feature matrix of a circuit to be detected into a trained analog circuit symmetry constraint extraction model to obtain a symmetry constraint value, wherein the analog circuit symmetry constraint extraction model includes a normalization layer, a calculation layer, and an output layer, and the feature matrix of the circuit to be detected is obtained by extracting features from a circuit diagram to be detected, and the feature matrix of the circuit to be detected includes a node feature matrix and an edge feature matrix; Performing matching processing on the symmetric constraint value to obtain a matching result; and A symmetric constraint result is determined according to the symmetric constraint value and the matching result, wherein The step of inputting the circuit diagram to be detected into a trained analog circuit symmetry constraint extraction model to obtain a symmetry constraint value comprises: Processing the node feature matrix using the standardization layer to obtain a standardized node feature matrix; Processing the edge feature matrix using the normalization layer to obtain a normalized edge feature matrix; Using the computing layer to perform weight calculation on the standardized node feature matrix and the standardized edge feature matrix to obtain a weighted node feature matrix; The output layer is used to calculate the weight node feature matrix and the node feature matrix to obtain the symmetric constraint value.

2. The method according to claim 1, wherein: The circuit diagram to be detected includes first node information and second node information, the first node information includes first node parameter information and first global position information, the second node information includes second node parameter information and second global position information, and the symmetry constraint value includes a first symmetry constraint value and a second symmetry constraint value; The matching process of the symmetric constraint value to obtain a matching result includes: Mapping the first symmetry constraint value and the circuit diagram to be detected to obtain corresponding first node information; Mapping the second symmetry constraint value and the circuit diagram to be detected to obtain corresponding second node information; Performing matching processing on the first node parameter information and the second node parameter information to obtain a first matching result; performing matching processing on the first global location information and the second global location information to obtain a second matching result; and The matching result is obtained according to the first matching result and the second matching result.

3. The method according to claim 1 or 2, wherein: The using the computing layer to perform weight calculation on the standardized node feature matrix and the standardized edge feature matrix to obtain a weighted node feature matrix includes: Obtaining an intermediate weight node feature matrix according to a first adjustable weight matrix and the standardized node feature matrix, wherein the first adjustable weight feature matrix represents weight information of the standardized node feature matrix; Obtaining an intermediate weight edge feature matrix according to a second adjustable weight matrix and the standardized edge feature matrix, wherein the second adjustable weight feature matrix represents weight information of the standardized edge feature matrix; Obtaining a fusion feature matrix according to the intermediate weight node feature matrix and the intermediate weight edge feature matrix; and The weight node feature matrix is ​​obtained according to a third adjustable weight matrix and the fused feature matrix, wherein the third adjustable weight matrix represents weight information of the fused feature matrix.

4. The method according to claim 3, wherein: The intermediate weight node feature matrix includes a first intermediate weight node feature matrix, a second intermediate weight node feature matrix and a third intermediate weight node feature matrix; The intermediate weight edge feature matrix includes a first intermediate weight edge feature matrix and a second intermediate weight edge feature matrix; The step of obtaining a fusion feature matrix according to the intermediate weight node feature matrix and the intermediate weight edge feature matrix includes: Obtaining an intermediate fusion feature matrix according to the first intermediate weight node feature matrix, the second intermediate weight node feature matrix, and the first intermediate weight edge feature matrix; as well as The fused feature matrix is ​​obtained according to the third intermediate weight node feature matrix, the second intermediate weight edge feature matrix and the intermediate fused feature matrix.

5. A training method for an analog circuit symmetry constraint extraction model, comprising: Obtain a training sample set; Inputting the training sample set into the deep learning model to be trained to obtain sample symmetry constraint values; as well as Using the sample symmetry constraint values ​​and sample labels to train the deep learning model to obtain the analog circuit symmetry constraint extraction model; Wherein, the analog circuit symmetry constraint extraction model is used to execute the analog circuit symmetry constraint determination method as claimed in claim 1.

6. The method according to claim 5, wherein: The obtaining of the training sample set comprises: According to the sample circuit diagram, obtaining sample node parameters of the sample circuit diagram; According to the sample node parameters, a sample node feature matrix and a sample edge feature matrix are obtained; and The training sample set is obtained according to the sample node feature matrix and the sample edge feature matrix.

7. The method according to claim 5 or 6, wherein: The method of training the deep learning model by using the sample symmetry constraint values ​​and sample labels to obtain the analog circuit symmetry constraint extraction model includes: Input the sample symmetry constraint value and the sample label into the loss function, and output the loss result; Iteratively adjusting the network parameters of the deep learning model according to the loss result until an iterative convergence condition is met; and The analog circuit symmetry constraint extraction model is generated according to the network parameters of the deep learning model under the condition of satisfying the iterative convergence condition.

8. A device for determining symmetry constraints of an analog circuit, comprising: A first acquisition module is used to input a feature matrix of a circuit to be detected into a trained analog circuit symmetry constraint extraction model to obtain a symmetry constraint value, wherein the analog circuit symmetry constraint extraction model includes a normalization layer, a calculation layer and an output layer, the feature matrix of the circuit to be detected is obtained by extracting features from a circuit diagram to be detected, and the feature matrix of the circuit to be detected includes a node feature matrix and an edge feature matrix; A second acquisition module is used to perform matching processing on the symmetry constraint value to obtain a matching result; A third acquisition module, used to determine a symmetry constraint result according to the symmetry constraint value and the matching result; The first acquisition module includes: a first processing submodule, a second processing submodule, a third processing submodule and a first output submodule; The first processing submodule is used to process the node feature matrix using a standardization layer to obtain a standardized node feature matrix; The second processing submodule is used to process the edge feature matrix using a normalization layer to obtain a normalized edge feature matrix; The third processing submodule is used to perform weight calculation on the standardized node feature matrix and the standardized edge feature matrix using a computing layer to obtain a weighted node feature matrix; and The first output submodule is used to calculate the weight node feature matrix and the node feature matrix using the output layer to obtain the symmetric constraint value.

9. A training device for extracting a model of analog circuit symmetry constraints, comprising: A first acquisition module is used to acquire a training sample set; A second acquisition module is used to input the training sample set into the deep learning model to be trained to obtain the sample symmetry constraint value; as well as A third acquisition module is used to train the deep learning model using the sample symmetry constraint value and the sample label to obtain the analog circuit symmetry constraint extraction model; Wherein, the analog circuit symmetry constraint extraction model is used to execute the analog circuit symmetry constraint determination method as claimed in claim 1.

10. An electronic device comprising: one or more processors; as well as a memory for storing one or more instructions, Wherein, when the one or more instructions are executed by the one or more processors, the one or more processors implement the method according to any one of claims 1 to 7.

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