Time-to-digital conversion device and time interval measurement method

Abstract

The application provides a time-to-digital conversion device and a time interval measurement method, and relates to the technical field of time precision measurement. The application counts the number of clock signal rising edges after the rising edge of a start measurement signal arrives through a coarse time measurement unit. A fine time measurement unit calibrates the delay time of a single delay module in a delay chain unit in real time according to the transmission state of a delay calibration signal at the delay chain unit when the delay chain unit transmits the delay calibration signal. The fine time measurement unit measures the target time length between the rising edge of a stop measurement signal and the rising edge of a target clock signal according to the calibrated delay time of the single delay module when the delay chain unit transmits the stop measurement signal. Then, a time interval between the rising edges of the start / stop measurement signals is calculated by a time interval output unit, so that the time measurement precision and efficiency are effectively ensured while the delay time calibration cost is reduced and the delay time calibration precision is improved.

Description

Technical Field

[0001] This application relates to the field of precise time measurement technology, and more specifically, to a time-to-digital conversion device and a time interval measurement method. Background Technology

[0002] With the continuous development of science and technology, many fields such as space science, medical diagnosis and imaging, nuclear physics, quantum communication, and laser detection require the measurement of speed or distance. A time-to-digital converter (TDC) is typically used to convert speed or distance measurements into time measurements, so that the measured time represents the specific speed or distance magnitude. With the rapid development and increasing cost-effectiveness of FPGA (Field-Programmable Gate Array) technology, designing TDCs using FPGA technology not only achieves high time resolution but also offers significant advantages in low cost and rapid development cycle, thus possessing profound application prospects.

[0003] However, it is worth noting that due to the special nature of the internal structure of an FPGA, the delay time of the delay chain unit inside the FPGA will change with the changes in internal temperature and / or internal voltage, resulting in measurement deviations in the final time measurement results of the corresponding time-to-digital converter.

[0004] Currently, the industry mainstream approach typically improves the time measurement accuracy of FPGA-based time-to-digital converters by adding an external calibration circuit to perform time delay calibration on the time measurement results. However, this time measurement calibration scheme incurs high delay calibration costs, and the corresponding delay calibration accuracy and time measurement efficiency are not high. Summary of the Invention

[0005] In view of this, the purpose of this application is to provide a time-to-digital conversion device and a time interval measurement method, which can realize the real-time calibration function of the delay time of the delay chain unit and the fine-time delay measurement function of the measured stop signal by reusing the fine-time measurement unit without the need for an external calibration circuit. This reduces the cost of delay time calibration, improves the accuracy of delay time calibration, and effectively ensures the accuracy and efficiency of time measurement.

[0006] To achieve the above objectives, the technical solutions adopted in the embodiments of this application are as follows:

[0007] In a first aspect, this application provides a time-to-digital conversion device, the device comprising a delay chain unit, a coarse time measurement unit, a fine time measurement unit, a time interval output unit, and a signal switching unit;

[0008] The delay chain unit is connected to an external clock signal, the coarse time measurement unit is electrically connected to the delay chain unit, and the coarse time measurement unit is connected to an external start measurement signal. The coarse time measurement unit is used to count the number of rising edges of the clock signal after the rising edge of the start measurement signal arrives.

[0009] The signal switching unit is externally connected to a delay calibration signal and a stop measurement signal. The signal switching unit is electrically connected to the delay chain unit. The signal switching unit is used to switch the input of the delay calibration signal or the stop measurement signal to the delay chain unit for transmission.

[0010] The fine time measurement unit is electrically connected to the delay chain unit and is used to calibrate the delay time of a single delay module in the delay chain unit in real time according to the transmission status of the delay calibration signal at the delay chain unit when the delay chain unit transmits the delay calibration signal, and to measure the target time length between the rising edge of the stop measurement signal and the rising edge of the target clock signal according to the calibrated delay time of the single delay module when the delay chain unit transmits the stop measurement signal; wherein the rising edge of the target clock signal is the first rising edge of the clock signal after the rising edge of the stop measurement signal arrives.

[0011] The time interval output unit is electrically connected to both the fine time measurement unit and the coarse time measurement unit, and is used to calculate the time interval between the rising edge of the start measurement signal and the rising edge of the stop measurement signal based on the number of rising edges of the clock signal counted by the coarse time measurement unit and the target time length measured by the fine time measurement unit.

[0012] In an optional implementation, the delay chain unit includes a trigger array, an encoder, and multiple delay modules;

[0013] The multiple delay modules are cascaded together to delay the transmission of the input signal of the delay chain unit;

[0014] The trigger array includes multiple triggers, each trigger being connected to one of the delay modules, used to latch the signal output of each delay module when the rising edge of the clock signal arrives, to obtain the signal transmission status of the input signal in the delay chain unit when the rising edge of the clock signal arrives;

[0015] The encoder is electrically connected to the trigger array and is used to encode and convert the signal transmission status of the input signal in the delay chain unit when the rising edge of the clock signal arrives, so as to obtain binary code data that can be recognized by both the fine time measurement unit and the coarse time measurement unit.

[0016] In an optional implementation, the sum of the delay times of all delay modules in the delay chain unit is greater than a single clock cycle of the clock signal, and all delay modules in the delay chain unit are a lead-fast carry logic structure inside the FPGA chip.

[0017] In an optional implementation, when the delay chain unit transmits the delay calibration signal, the fine time measurement unit obtains from the delay chain unit the target delay module position where the rising edge of the delay calibration signal is captured when two adjacent rising edges of clock signals arrive.

[0018] The fine time measurement unit calculates the number of delay modules that the delay chain unit needs to traverse within a single clock cycle to transmit the delay calibration signal based on the target delay module positions corresponding to the rising edges of two adjacent clock signals.

[0019] The fine time measurement unit performs a division operation between the clock period and the number of traversal delay modules to calibrate the delay time of a single delay module in the delay chain unit.

[0020] In an optional embodiment, the device further includes a clock calibration generation unit;

[0021] The clock calibration generation unit is electrically connected to the delay chain unit and is used to generate a clock signal and transmit the generated clock signal to the delay chain unit.

[0022] The clock calibration generation unit is also electrically connected to the signal switching unit, and is used to perform phase adjustment processing on the generated clock signal to obtain a corresponding delay calibration signal, and transmit the obtained delay calibration signal to the signal switching unit.

[0023] In an optional embodiment, the device further includes a measurement signal generation unit;

[0024] The measurement signal generation unit is electrically connected to the coarse time measurement unit and is used to generate a start measurement signal and transmit the generated start measurement signal to the coarse time measurement unit.

[0025] The measurement signal generation unit is also electrically connected to the signal switching unit, and is used to generate a stop measurement signal and transmit the generated stop measurement signal to the signal switching unit.

[0026] Secondly, this application provides a time interval measurement method, applied to the time-to-digital conversion device described in any of the foregoing embodiments, the method comprising:

[0027] The coarse time measurement unit controls the clock signal rising edge counting after the rising edge of the received start measurement signal arrives;

[0028] The control signal switching unit inputs the external stop measurement signal into the delay chain unit for transmission, so that the fine time measurement unit measures the target time length between the rising edge of the stop measurement signal and the rising edge of the target clock signal based on the delay time of a single delay module in the currently calibrated delay chain unit, wherein the rising edge of the target clock signal is the first rising edge of the clock signal after the rising edge of the stop measurement signal arrives.

[0029] The time interval output unit is controlled to calculate the time interval between the rising edge of the start measurement signal and the rising edge of the stop measurement signal based on the target time length measured by the fine time measurement unit and the number of rising edges of the clock signal counted by the coarse time measurement unit between the rising edge of the start measurement signal and the rising edge of the stop measurement signal.

[0030] In an optional implementation, the step of calculating the time interval between the rising edge of the start measurement signal and the rising edge of the stop measurement signal based on the target time length measured by the fine time measurement unit and the number of rising edges of the clock signal counted by the coarse time measurement unit between the rising edge of the start measurement signal and the rising edge of the stop measurement signal includes:

[0031] Calculate the time difference between a single clock cycle of the clock signal and the target time length to obtain the first time length to be superimposed;

[0032] Based on a single clock cycle of the clock signal, the time length corresponding to the number of rising edges of the clock signal counted by the coarse time measurement unit is calculated to obtain the second time length to be superimposed;

[0033] The first time length to be superimposed and the second time length to be superimposed are added together to obtain the time interval between the rising edge of the start measurement signal and the rising edge of the stop measurement signal.

[0034] In an optional implementation, the method further includes:

[0035] The signal switching unit controls the input of the external delay calibration signal into the delay chain unit for transmission;

[0036] The fine-time measurement unit is controlled to calibrate the delay time of a single delay module in the delay chain unit in real time according to the transmission status of the delay calibration signal at the delay chain unit.

[0037] In an optional implementation, the step of calibrating the delay time of a single delay module in the delay chain unit in real time based on the transmission status of the delay calibration signal at the delay chain unit includes:

[0038] The location of the target delay module is obtained when the delay chain unit captures the rising edge of the delay calibration signal at the arrival of two adjacent rising edges of clock signals.

[0039] Based on the target delay module positions corresponding to the rising edges of two adjacent clock signals, calculate the number of delay modules that the delay chain unit needs to traverse in a single clock cycle to transmit the delay calibration signal.

[0040] The clock period is divided by the number of traversed delay modules to calibrate the delay time of a single delay module in the delay chain unit.

[0041] In this case, the beneficial effects of the embodiments of this application may include the following:

[0042] This application electrically connects a coarse time measurement unit to a delay chain unit of an external clock signal. The coarse time measurement unit counts the number of rising edges of the clock signal after the rising edge of the external start measurement signal. A signal switching unit switches between an external delay calibration signal and a stop measurement signal for transmission into the delay chain unit. When the delay chain unit transmits the delay calibration signal, the fine time measurement unit calibrates the delay time of each individual delay module in the delay chain unit in real time based on the transmission status of the delay calibration signal at the delay chain unit. Finally, when the delay chain unit transmits the stop measurement signal, the fine time measurement unit measures the delay time of each individual delay module based on the calibrated delay time. The target time length between the rising edge of the stop measurement signal and the rising edge of the target clock signal is determined. Then, the time interval output unit calculates the time interval between the rising edge of the start measurement signal and the rising edge of the stop measurement signal based on the number of rising edges of the clock signal counted by the coarse time measurement unit and the target time length measured by the fine time measurement unit. Thus, without the need for an external calibration circuit, the fine time measurement unit can be reused to realize the real-time calibration function of the delay time of the delay chain unit and the fine time delay measurement function of the measured stop signal. This reduces the delay time calibration cost of the time-to-digital converter, improves the accuracy of delay time calibration, and effectively ensures the accuracy and efficiency of time measurement.

[0043] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0044] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0045] Figure 1 This is one of the schematic diagrams of the time-to-digital conversion device provided in the embodiments of this application;

[0046] Figure 2 A schematic diagram illustrating the composition of a delay chain unit provided in an embodiment of this application;

[0047] Figure 3 A second schematic diagram illustrating the composition of the time-to-digital conversion device provided in the embodiments of this application;

[0048] Figure 4 One of the flowcharts for the time interval measurement method provided in the embodiments of this application;

[0049] Figure 5 for Figure 4 A flowchart illustrating the sub-steps included in step S230;

[0050] Figure 6 A second schematic flowchart illustrating the time interval measurement method provided in this application embodiment;

[0051] Figure 7 for Figure 6 The flowchart of the sub-steps included in step S250 is shown below.

[0052] Icons: 10-Time to digital conversion device; 11-Signal switching unit; 12-Delay chain unit; 13-Coarse time measurement unit; 14-Fine time measurement unit; 15-Time interval output unit; 16-Clock calibration generation unit; 17-Measurement signal generation unit. Detailed Implementation

[0053] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0054] Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely to illustrate selected embodiments of the application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0055] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0056] In the description of this application, it should be understood that relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element. Those skilled in the art will understand the specific meaning of the above terms in this application based on the specific circumstances.

[0057] The following detailed description of some embodiments of this application is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0058] Please refer to Figure 1 , Figure 1 This is one of the schematic diagrams of the time-to-digital converter 10 provided in this application embodiment. In this application embodiment, the time-to-digital converter 10 has low delay time calibration cost and high overall delay time calibration accuracy, enabling it to achieve high-precision and high-efficiency time interval measurement for the measured signal. The time-to-digital converter 10 may include a signal switching unit 11, a delay chain unit 12, a coarse time measurement unit 13, a fine time measurement unit 14, and a time interval output unit 15.

[0059] In this embodiment, the delay chain unit 12 can be externally connected to a clock signal, and the coarse time measurement unit 13 can be externally connected to a start measurement signal. The coarse time measurement unit 13 is used to start counting the number of rising edges of the clock signal received by the delay chain unit 12 after the rising edge of the start measurement signal arrives, thereby realizing the coarse time counting function of the measured signal. The rising edge of the start measurement signal is used to indicate the starting time point for the time-to-digital converter 10 to perform time interval measurement.

[0060] In this embodiment, the signal switching unit 11 is externally connected to a delay calibration signal and a stop measurement signal. At the same time, the signal switching unit 11 is electrically connected to the delay chain unit 12 and is used to switch the delay calibration signal or the stop measurement signal input to the delay chain unit 12 for transmission.

[0061] If the signal switching unit 11 switches the delay calibration signal input to the delay chain unit 12 for transmission, the delay chain unit 12 will measure the delay value of the transmitted delay calibration signal to obtain the transmission status of the delay calibration signal under the action of the clock signal.

[0062] If the signal switching unit 11 switches the stop measurement signal input to the delay chain unit 12 for transmission, the delay chain unit 12 will measure the delay value of the transmitted stop measurement signal to obtain the transmission status of the stop measurement signal under the action of the clock signal. At this time, the delay chain unit 12 will inform the coarse time measurement unit 13 to stop counting when the rising edge of the stop measurement signal arrives, so as to ensure that the number of rising edges of the clock signal counted by the coarse time measurement unit 13 belongs to the number of clock cycles experienced in the time period from the rising edge of the start measurement signal to the rising edge of the stop measurement signal. The rising edge of the stop measurement signal is used to indicate the stop time point of the time interval measurement performed by the time-to-digital converter 10.

[0063] In this embodiment, the fine-time measurement unit 14 is electrically connected to the delay chain unit 12. When the delay chain unit 12 transmits a delay calibration signal, it calibrates the delay time of a single delay module in the delay chain unit 12 in real time based on the transmission status of the delay calibration signal at the delay chain unit 12, thereby achieving real-time delay time calibration of the delay chain unit 12. The aforementioned delay calibration signal instructs the fine-time measurement unit 14 to perform real-time calibration of the actual delay time of a single delay module in the delay chain unit 12 under the current operating environment.

[0064] In this embodiment, the fine-time measurement unit 14 is also used to measure the target time length between the rising edge of the stop measurement signal and the rising edge of the target clock signal, based on the delay time of the currently calibrated single delay module, when the delay chain unit 12 transmits the stop measurement signal, so as to realize the fine-time delay measurement function of the stop signal under test. The rising edge of the target clock signal is the first rising edge of the clock signal after the rising edge of the stop measurement signal arrives.

[0065] In this embodiment, the time interval output unit 15 is electrically connected to both the fine time measurement unit 14 and the coarse time measurement unit 13. It is used to directly calculate the time interval between the rising edge of the start measurement signal and the rising edge of the stop measurement signal based on the target time length measured by the fine time measurement unit 14 and the number of rising edges of the clock signal counted by the coarse time measurement unit 13 between the rising edge of the start measurement signal and the rising edge of the stop measurement signal.

[0066] The time interval output unit 15 can obtain the first time length to be superimposed by calculating the time difference between a single clock cycle of the clock signal and the target time length. Then, it can multiply the clock cycle with the number of rising edges of the clock signal counted by the coarse time measurement unit 13 to obtain the second time length to be superimposed. Finally, it can obtain the time interval between the rising edge of the start measurement signal and the rising edge of the stop measurement signal by adding the first time length to be superimposed and the second time length to be superimposed.

[0067] Therefore, this application can achieve the real-time calibration function of the delay time of the delay chain unit 12 and the fine time delay measurement function of the measured stop signal by reusing the fine time measurement unit 14 without the need for an external calibration circuit. By measuring the coarse time and fine time of the measured signal (including the start measurement signal and the stop measurement signal), the time interval corresponding to the measured signal is obtained. This reduces the delay time calibration cost of the time digital converter 10, improves the delay time calibration accuracy of the time digital converter 10, and effectively ensures the time measurement accuracy and time measurement efficiency of the time digital converter 10.

[0068] Alternatively, please refer to Figure 2 , Figure 2 This is a schematic diagram of the composition of the delay chain unit 12 provided in an embodiment of this application. In this embodiment, the delay chain unit 12 may include a trigger array, an encoder, and multiple delay modules.

[0069] In this embodiment, the delay chain unit 12 includes multiple delay modules that are cascaded together. The input terminal of the first cascaded delay module is connected to the corresponding input signal (i.e., the aforementioned delay calibration signal or the aforementioned stop measurement signal). The input terminals of other cascaded delay modules are connected to the output terminal of the previous cascaded delay module, thereby performing delay transmission measurement on the input signal corresponding to the delay chain unit 12 through multiple delay modules.

[0070] In this embodiment, the delay chain unit 12 includes a flip-flop array composed of multiple flip-flops, each flip-flop being connected to a corresponding delay module. This latches the signal output of each delay module in the delay chain unit 12 when the rising edge of the clock signal arrives, thus obtaining the signal transmission status of the input signal within the delay chain unit 12 when the rising edge of the clock signal arrives. The flip-flops involved in the flip-flop array can be D flip-flops, with the clock input terminal of the D flip-flop externally connected to a clock signal, and the signal input terminal of the D flip-flop connected to the output terminal of the corresponding delay module.

[0071] In this embodiment, the encoder included in the delay chain unit 12 is electrically connected to each flip-flop in the flip-flop array, and is used to encode and convert the signal transmission status of the input signal in the delay chain unit 12 when the rising edge of the clock signal arrives, so as to obtain binary code data that can be recognized by both the fine time measurement unit 14 and the coarse time measurement unit 13.

[0072] The signal transmission status of the aforementioned input signal in the delay chain unit 12 when the rising edge of the clock signal arrives can indicate which delay module the rising edge of the corresponding input signal is transmitted to when the rising edge of the corresponding clock signal arrives. At this time, the module position of the delay module (which can be described by the module number of the delay module) can be regarded as the target delay module position where the rising edge of the input signal is captured at the rising edge of the corresponding clock signal.

[0073] It is understandable that when the input signal is a stop measurement signal, the encoder will transmit specific binary code data to the coarse time measurement unit 13 when the rising edge of the stop measurement signal arrives, so as to inform the coarse time measurement unit 13 to stop counting when the rising edge of the stop measurement signal arrives, thereby ensuring that the number of rising edges of the clock signal actually counted by the coarse time measurement unit 13 belongs to the number of clock cycles experienced in the time period from the rising edge of the start measurement signal to the rising edge of the stop measurement signal.

[0074] In this embodiment, to ensure that the fine time measurement unit 14 can realize the real-time delay calibration function and the fine time delay measurement function through the delay chain unit 12, the total delay time involved in the delay chain unit 12 (i.e., the sum of the delay times of each delay module of the delay chain unit 12) needs to be maintained at a state greater than a single clock cycle of the clock signal, so as to ensure that the time interval between the rising edge of the start measurement signal and the rising edge of the stop measurement signal exceeding an integer multiple of the clock cycle can be measured by the fine time measurement unit 14.

[0075] Meanwhile, through painstaking research, the applicant discovered that existing FPGA-based time-to-digital converters construct delay chain units by treating each of the multiple carry logic structures within the FPGA chip (e.g., CARRY4 or CARRY8) as a separate delay module. This results in a significant difference (i.e., T) between two adjacent delay modules belonging to the same carry logic structure in the corresponding time-to-digital converter compared to the delay interval (T) between two adjacent delay modules belonging to different carry logic structures. Consequently, the delay time of each delay module in the existing delay chain unit is unevenly distributed, leading to significant errors in the final time measurement results.

[0076] To this end, this application directly uses each lead fast carry logic structure inside the FPGA chip as a delay module of the delay chain unit 12. By taking advantage of the fact that the trace length inside a single lead fast carry logic structure is basically the same, it ensures that the delay time of each lead fast carry logic structure is basically consistent when used as a delay module. This ensures that the delay time of each delay module in the delay chain unit 12 is evenly distributed, thereby improving the accuracy of the final time measurement result.

[0077] In this case, to ensure that the fine time measurement unit 14 can realize the real-time calibration function of the delay time of the delay chain unit 12, the delay calibration signal can be switched to the delay chain unit 12 through the control signal switching unit 11. The fine time measurement unit 14 can obtain the target delay module position captured by the delay chain unit 12 when the rising edge of the delay calibration signal arrives at the two adjacent clock signal rising edges. Then, based on the target delay module positions corresponding to the two adjacent clock signal rising edges, the number of delay modules between the two target delay module positions is calculated. The number of traversed delay modules required by the delay chain unit 12 to transmit the delay calibration signal in a single clock cycle under the current operating environment is obtained. Then, by dividing the single clock cycle by the number of traversed delay modules, the delay time of a single delay module in the delay chain unit 12 under the current operating environment is directly calibrated, thereby ensuring that the calibrated delay time substantially matches the current operating environment and ensuring the accuracy of the final time measurement result.

[0078] Alternatively, please refer to Figure 3 , Figure 3 This is a second schematic diagram of the composition of the time-to-digital conversion device 10 provided in this application embodiment. In this application embodiment, it is related to... Figure 1 Compared to the time-to-digital converter 10 shown, Figure 3 The time-to-digital converter 10 shown may also include a clock calibration generation unit 16.

[0079] In this embodiment, the clock calibration generation unit 16 can be electrically connected to the delay chain unit 12 to generate a clock signal and transmit the generated clock signal to the delay chain unit 12, so as to ensure that the delay chain unit 12, the fine time measurement unit 14 and the coarse time measurement unit 13 can normally realize the time measurement function.

[0080] In this embodiment, the clock calibration generation unit 16 can also be electrically connected to the signal switching unit 11 to perform phase adjustment processing on the generated clock signal to obtain a corresponding delay calibration signal, and transmit the obtained delay calibration signal to the signal switching unit 11 so that the signal switching unit 11 can output a delay calibration signal to the delay chain unit 12 when the delay time needs to be calibrated.

[0081] In one embodiment of this invention, the clock calibration generation unit 16 can step-adjust the signal phase of the delay calibration signal at a specific frequency (e.g., at a time interval of 15 picoseconds) until the rising edge of the adjusted delay calibration signal after being input to the delay chain unit 12 can be captured by the rising edges of two adjacent clock signals, so as to ensure that the corresponding fine time measurement unit 14 can normally realize the real-time delay time calibration function of the delay chain unit 12.

[0082] Optionally, in the embodiments of this application, the time-to-digital conversion device 10 may further include a measurement signal generation unit 17.

[0083] In this embodiment, the measurement signal generation unit 17 is electrically connected to the coarse time measurement unit 13. It is used to generate a start measurement signal when it is necessary to start time measurement of the signal under test, and transmit the generated start measurement signal to the coarse time measurement unit 13 so as to instruct the coarse time measurement unit 13 to start counting the rising edge of the clock signal through the rising edge of the start measurement signal.

[0084] The measurement signal generation unit 17 is also electrically connected to the signal switching unit 11. It is used to generate a stop measurement signal when it is necessary to stop the time measurement of the measured signal, and transmit the generated stop measurement signal to the signal switching unit 11. This allows the signal switching unit 11 to output a stop measurement signal to the delay chain unit 12 when it is necessary to stop the time measurement. The rising edge of the stop measurement signal instructs the coarse time measurement unit 13 to stop counting the rising edge of the clock signal, and instructs the fine time measurement unit 14 to run the fine time delay measurement function of the measured stop signal.

[0085] In this application, to ensure that the aforementioned time-to-digital converter 10 can perform time interval measurement for the measured signal (including start measurement signal and stop measurement signal), this application provides a time interval measurement method applied to the aforementioned time-to-digital converter 10 to achieve the aforementioned objective. The time interval measurement method provided in this application will be described in detail below.

[0086] Please refer to Figure 4 , Figure 4 This is one of the flowcharts illustrating the time interval measurement method provided in this application embodiment. In this application embodiment, the time interval measurement method is applied to the aforementioned time-to-digital converter 10, and the time interval measurement method may include steps S210 to S230.

[0087] Step S210: Control the coarse time measurement unit to count the rising edges of the clock signal after the rising edge of the received start measurement signal arrives.

[0088] In this embodiment, when the electronic device containing the time-to-digital converter 10 needs to perform time interval measurement, it can drive the start measurement signal to generate a rising edge, so that the coarse time measurement unit 13 included in the time-to-digital converter 10 can count the rising edges of the clock signal after the arrival of the received rising edge of the start measurement signal.

[0089] It is understood that the aforementioned time-to-digital converter 10 can be applied to the laser scanning process of a lidar. When the lidar emits a laser beam each time, it drives the start measurement signal to generate a rising edge, so that the coarse time measurement unit 13 included in the time-to-digital converter 10 can count the rising edges of the clock signal after the arrival of the received start measurement signal rising edge.

[0090] In step S220, the control signal switching unit inputs the external stop measurement signal into the delay chain unit for transmission, so that the fine time measurement unit measures the target time length between the rising edge of the stop measurement signal and the rising edge of the target clock signal based on the delay time of a single delay module in the currently calibrated delay chain unit.

[0091] In this embodiment, when the electronic device containing the aforementioned time-to-digital converter 10 needs to stop the time interval measurement, it can drive the signal switching unit 11 included in the time-to-digital converter 10 to switch the stop measurement signal input to the delay chain unit 12 for transmission, and drive the stop measurement signal to generate a rising edge. This allows the fine time measurement unit 14 included in the time-to-digital converter 10 to directly measure the target time length between the rising edge of the stop measurement signal and the rising edge of the target clock signal based on the delay time of a single delay module in the currently calibrated delay chain unit 12. The delay chain unit 12 then drives the coarse time measurement unit 13 to pause counting the rising edges of the clock signal after the arrival of the rising edge of the stop measurement signal. The target clock signal rising edge is the first rising edge of the clock signal after the arrival of the rising edge of the stop measurement signal.

[0092] The fine time measurement unit 14 can obtain the target delay module position captured by the delay chain unit 12 at the rising edge of the target clock signal and the rising edge of the stop measurement signal, then determine the number of delay modules between the first cascaded delay module in the delay chain unit 12 and the target delay module position, and then multiply the delay time of the single delay module currently measured by the current standard with the determined number of delay modules to obtain the target time length between the rising edge of the stop measurement signal and the rising edge of the target clock signal.

[0093] It is understood that when the aforementioned time-to-digital converter 10 is applied to a lidar, the lidar can drive the signal switching unit 11 included in the time-to-digital converter 10 to switch the stop measurement signal input to the delay chain unit 12 for transmission when emitting a laser beam. When the lidar receives the reflected laser beam, it drives the stop measurement signal to generate a rising edge, so that the fine time measurement unit 14 included in the time-to-digital converter 10 can directly measure the target time length between the rising edge of the stop measurement signal and the rising edge of the target clock signal based on the delay time of a single delay module in the currently calibrated delay chain unit 12. The delay chain unit 12 drives the coarse time measurement unit 13 to pause counting the rising edges of the clock signal after the arrival of the rising edge of the stop measurement signal.

[0094] Step S230: The control time interval output unit calculates the time interval between the rising edge of the start measurement signal and the rising edge of the stop measurement signal based on the target time length measured by the fine time measurement unit and the number of rising edges of the clock signal counted by the coarse time measurement unit between the rising edge of the start measurement signal and the rising edge of the stop measurement signal.

[0095] In this embodiment, when the fine time measurement unit 14 measures the target time length and the coarse time measurement unit 13 counts the number of rising edges of the clock signal between the rising edge of the start measurement signal and the rising edge of the stop measurement signal, the time interval output unit 15 included in the time digital conversion device 10 can obtain the time interval between the rising edge of the start measurement signal and the rising edge of the stop measurement signal by performing data processing on the aforementioned target time length and the aforementioned number of rising edges of the clock signal.

[0096] It is understandable that when the aforementioned time-to-digital conversion device 10 is applied to the laser scanning process of a lidar, the time interval between the laser emission time point and the laser reception time point can be calculated through the synergistic effect of the aforementioned steps S210 to S230.

[0097] Alternatively, please refer to Figure 5 , Figure 5 yes Figure 4 The flowchart of step S230 includes the sub-steps. In the embodiments of this application, step S230 may include sub-steps S231 to S233 to accurately measure the time interval between the rising edge of the start measurement signal and the rising edge of the stop measurement signal.

[0098] Sub-step S231: Calculate the time difference between a single clock cycle of the clock signal and the target time length to obtain the first time length to be superimposed.

[0099] The first time length to be superimposed can be obtained by subtracting the target time length from a single clock cycle of the clock signal.

[0100] Sub-step S232: Based on a single clock cycle of the clock signal, calculate the time length corresponding to the number of rising edges of the clock signal counted by the coarse time measurement unit, and obtain the second time length to be superimposed.

[0101] The second time length to be superimposed can be obtained by multiplying a single clock cycle of the clock signal by the number of rising edges of the clock signal counted by the coarse time measurement unit 13.

[0102] Sub-step S233: Add the first time length to be superimposed and the second time length to be superimposed to obtain the time interval between the rising edge of the start measurement signal and the rising edge of the stop measurement signal.

[0103] Therefore, this application can accurately measure the time interval between the rising edge of the start measurement signal and the rising edge of the stop measurement signal by executing the above sub-steps S231 to S233.

[0104] This application can perform time interval measurement function for the measured signal (including start measurement signal and stop measurement signal) by executing the above steps S210 to S230.

[0105] Alternatively, please refer to Figure 6 , Figure 6 This is a second schematic flowchart of the time interval measurement method provided in this application embodiment. In this application embodiment, with... Figure 4 Compared to the time interval measurement method shown, Figure 6 The time interval measurement method shown may also include steps S240 and S250 to ensure that the time-to-digital converter 10 can reuse the fine time measurement unit 14 to perform real-time delay time calibration for the delay chain unit 12.

[0106] In step S240, the control signal switching unit inputs the external delay calibration signal into the delay chain unit for transmission.

[0107] In this embodiment, when the electronic device containing the aforementioned time-to-digital converter 10 needs to perform delay time calibration, it can drive the signal switching unit 11 to switch the delay calibration signal input to the delay chain unit 12 for transmission, so that the delay chain unit 12 can capture the rising edge of the delay calibration signal when two adjacent clock signals arrive.

[0108] It is understood that when the aforementioned time-to-digital conversion device 10 is applied to a lidar, the signal switching unit 11 can be driven to switch the delay calibration signal input to the delay chain unit 12 for transmission during the laser charging idle period of the lidar, so as to perform the delay time calibration operation during the laser charging idle period.

[0109] Step S250: Control the fine time measurement unit to calibrate the delay time of a single delay module in the delay chain unit in real time according to the transmission status of the delay calibration signal at the delay chain unit.

[0110] In this embodiment, the fine time measurement unit 14 can, when the delay calibration signal is transmitted by the delay chain unit 12, calibrate the delay time of a single delay module of the delay chain unit 12 in real time under the current operating environment based on the signal transmission status captured by the delay calibration signal within the delay chain unit 12.

[0111] Alternatively, please refer to Figure 7 , Figure 7 yes Figure 6 The flowchart of step S250 is shown below. In this embodiment, step S250 may include sub-steps S251 to S253 to calibrate the delay time of a single delay module of the delay chain unit 12 in real time under the current operating environment.

[0112] Sub-step S251: Obtain the target delay module position when the delay chain unit captures the rising edge of the delay calibration signal when two adjacent clock signals arrive.

[0113] Sub-step S252: Based on the target delay module positions corresponding to the rising edges of two adjacent clock signals, calculate the number of delay modules that the delay chain unit needs to traverse within a single clock cycle to transmit the delay calibration signal.

[0114] The number of traversed delay modules is the number of delay modules between the positions of the two target delay modules mentioned above.

[0115] Sub-step S253 involves dividing the clock cycle by the number of traversed delay modules to calibrate the delay time of a single delay module in the delay chain unit.

[0116] Therefore, this application can calibrate the delay time of a single delay module of the delay chain unit 12 in the current operating environment in real time by executing the above sub-steps S251 to S253.

[0117] By performing the above steps S240 and S250, this application ensures that the time-to-digital converter 10 can reuse the fine time measurement unit 14 to achieve real-time delay time calibration for the delay chain unit 12.

[0118] In the embodiments provided in this application, it should be understood that the disclosed apparatus and methods can also be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code, which contains one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0119] Furthermore, the functional modules in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part. If a function is implemented as a software functional module and sold or used as an independent product, it can be stored in a readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a readable storage medium and includes several instructions to cause the main control chip in the aforementioned lidar system to execute all or part of the steps of the methods in the various embodiments of this application. The aforementioned readable storage medium includes: USB flash drives, mobile hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, optical disks, and other media capable of storing program code.

[0120] In summary, in the time-to-digital conversion device and time interval measurement method provided in this application, the coarse time measurement unit is electrically connected to the delay chain unit of the external clock signal. The coarse time measurement unit counts the number of rising edges of the clock signal after the rising edge of the external start measurement signal arrives. A signal switching unit switches between the external delay calibration signal and the stop measurement signal input to the delay chain unit for transmission. When the delay calibration signal is transmitted by the delay chain unit, the fine time measurement unit calibrates the delay time of a single delay module in the delay chain unit in real time based on the transmission status of the delay calibration signal at the delay chain unit. When the delay chain unit transmits the stop measurement signal, the fine time measurement unit calibrates the delay time of the individual delay modules in the delay chain unit according to the transmission status of the delay calibration signal at the delay chain unit. The target time length between the rising edge of the stop measurement signal and the rising edge of the target clock signal is measured by the calibration of a single delay module. Then, the time interval output unit calculates the time interval between the rising edge of the start measurement signal and the rising edge of the stop measurement signal based on the number of rising edges of the clock signal counted by the coarse time measurement unit and the target time length measured by the fine time measurement unit. Thus, without the need for an external calibration circuit, the fine time measurement unit is reused to realize the real-time calibration function of the delay time of the delay chain unit and the fine time delay measurement function of the measured stop signal. This reduces the delay time calibration cost of the time-to-digital converter, improves the accuracy of delay time calibration, and effectively ensures the accuracy and efficiency of time measurement.

[0121] The above descriptions are merely various embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A time-to-digital conversion device, characterized in that, The device includes a delay chain unit, a coarse time measurement unit, a fine time measurement unit, a time interval output unit, and a signal switching unit; The delay chain unit is connected to an external clock signal, the coarse time measurement unit is electrically connected to the delay chain unit, and the coarse time measurement unit is connected to an external start measurement signal. The coarse time measurement unit is used to count the number of rising edges of the clock signal after the rising edge of the start measurement signal arrives. The signal switching unit is externally connected to a delay calibration signal and a stop measurement signal. The signal switching unit is electrically connected to the delay chain unit. The signal switching unit is used to switch the input of the delay calibration signal or the stop measurement signal to the delay chain unit for transmission. The fine time measurement unit is electrically connected to the delay chain unit and is used to calibrate the delay time of a single delay module in the delay chain unit in real time according to the transmission status of the delay calibration signal at the delay chain unit when the delay chain unit transmits the delay calibration signal, and to measure the target time length between the rising edge of the stop measurement signal and the rising edge of the target clock signal according to the calibrated delay time of the single delay module when the delay chain unit transmits the stop measurement signal; wherein the rising edge of the target clock signal is the first rising edge of the clock signal after the rising edge of the stop measurement signal arrives. The time interval output unit is electrically connected to both the fine time measurement unit and the coarse time measurement unit, and is used to calculate the time interval between the rising edge of the start measurement signal and the rising edge of the stop measurement signal based on the number of rising edges of the clock signal counted by the coarse time measurement unit and the target time length measured by the fine time measurement unit.

2. The apparatus according to claim 1, characterized in that, The delay chain unit includes a trigger array, an encoder, and multiple delay modules; The multiple delay modules are cascaded together to delay the transmission of the input signal of the delay chain unit; The trigger array includes multiple triggers, each trigger being connected to one of the delay modules, used to latch the signal output of each delay module when the rising edge of the clock signal arrives, to obtain the signal transmission status of the input signal in the delay chain unit when the rising edge of the clock signal arrives; The encoder is electrically connected to the trigger array and is used to encode and convert the signal transmission status of the input signal in the delay chain unit when the rising edge of the clock signal arrives, so as to obtain binary code data that can be recognized by both the fine time measurement unit and the coarse time measurement unit.

3. The apparatus according to claim 2, characterized in that, The sum of the delay times of all delay modules in the delay chain unit is greater than a single clock cycle of the clock signal, and all delay modules in the delay chain unit are a lead-fast carry logic structure inside the FPGA chip.

4. The apparatus according to claim 1, characterized in that, When the delay chain unit transmits the delay calibration signal, the fine time measurement unit obtains from the delay chain unit the target delay module position where the rising edge of the delay calibration signal is captured when two adjacent rising edges of clock signals arrive; The fine time measurement unit calculates the number of delay modules that the delay chain unit needs to traverse within a single clock cycle to transmit the delay calibration signal based on the target delay module positions corresponding to the rising edges of two adjacent clock signals. The fine time measurement unit performs a division operation between the clock period and the number of traversal delay modules to calibrate the delay time of a single delay module in the delay chain unit.

5. The apparatus according to any one of claims 1-4, characterized in that, The device also includes a clock calibration generation unit; The clock calibration generation unit is electrically connected to the delay chain unit and is used to generate a clock signal and transmit the generated clock signal to the delay chain unit. The clock calibration generation unit is also electrically connected to the signal switching unit, and is used to perform phase adjustment processing on the generated clock signal to obtain a corresponding delay calibration signal, and transmit the obtained delay calibration signal to the signal switching unit.

6. The apparatus according to claim 5, characterized in that, The device also includes a measurement signal generation unit; The measurement signal generation unit is electrically connected to the coarse time measurement unit and is used to generate a start measurement signal and transmit the generated start measurement signal to the coarse time measurement unit. The measurement signal generation unit is also electrically connected to the signal switching unit, and is used to generate a stop measurement signal and transmit the generated stop measurement signal to the signal switching unit.

7. A method for measuring time intervals, characterized in that, The method, applied to the time-to-digital conversion apparatus according to any one of claims 1-6, comprises: The coarse time measurement unit controls the clock signal rising edge counting after the rising edge of the received start measurement signal arrives; The control signal switching unit inputs the external stop measurement signal into the delay chain unit for transmission, so that the fine time measurement unit measures the target time length between the rising edge of the stop measurement signal and the rising edge of the target clock signal based on the delay time of a single delay module in the currently calibrated delay chain unit, wherein the rising edge of the target clock signal is the first rising edge of the clock signal after the rising edge of the stop measurement signal arrives. The time interval output unit is controlled to calculate the time interval between the rising edge of the start measurement signal and the rising edge of the stop measurement signal based on the target time length measured by the fine time measurement unit and the number of rising edges of the clock signal counted by the coarse time measurement unit between the rising edge of the start measurement signal and the rising edge of the stop measurement signal.

8. The method according to claim 7, characterized in that, The step of calculating the time interval between the rising edge of the start measurement signal and the rising edge of the stop measurement signal based on the target time length measured by the fine time measurement unit and the number of rising edges of the clock signal counted by the coarse time measurement unit between the rising edge of the start measurement signal and the rising edge of the stop measurement signal includes: Calculate the time difference between a single clock cycle of the clock signal and the target time length to obtain the first time length to be superimposed; Based on a single clock cycle of the clock signal, the time length corresponding to the number of rising edges of the clock signal counted by the coarse time measurement unit is calculated to obtain the second time length to be superimposed; The first time length to be superimposed and the second time length to be superimposed are added together to obtain the time interval between the rising edge of the start measurement signal and the rising edge of the stop measurement signal.

9. The method according to claim 7 or 8, characterized in that, The method further includes: The signal switching unit controls the input of the external delay calibration signal into the delay chain unit for transmission; The fine-time measurement unit is controlled to calibrate the delay time of a single delay module in the delay chain unit in real time according to the transmission status of the delay calibration signal at the delay chain unit.

10. The method according to claim 9, characterized in that, The step of calibrating the delay time of a single delay module in the delay chain unit in real time based on the transmission status of the delay calibration signal at the delay chain unit includes: The location of the target delay module is obtained when the delay chain unit captures the rising edge of the delay calibration signal at the arrival of two adjacent rising edges of clock signals. Based on the target delay module positions corresponding to the rising edges of two adjacent clock signals, calculate the number of delay modules that the delay chain unit needs to traverse in a single clock cycle to transmit the delay calibration signal. The clock period is divided by the number of traversed delay modules to calibrate the delay time of a single delay module in the delay chain unit.

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