Chip crack detection method, system, storage medium and intelligent terminal

Abstract

The present application relates to a chip crack detection method, system, storage medium and intelligent terminal, and relates to the field of wafer chip detection technology, which includes sputtering a barrier layer and a seed layer on the surface of a wafer before passing through a DBG process, wherein a substrate and a passivation layer are provided on the wafer; setting a mark on the wafer; scanning the back side of the wafer before attaching a dicing film to the back side of the wafer and when the back side of the wafer faces upward in the DBG process to form a back side crack scanning map; mirroring the back side crack scanning map to form a mirrored back side crack scanning map; scanning the front side of the wafer after the DBG process is completed to form a front side crack scanning map; integrating the mirrored back side crack scanning map and the front side crack scanning map based on the mark to form a comprehensive crack scanning map; determining the crack result based on the comprehensive crack scanning map and outputting it. The present application has the effect of automatically analyzing the two scanned maps comprehensively to avoid causing greater losses and improve the accuracy of crack detection.

Description

Technical Field

[0001] The present application relates to the field of wafer chip detection technology, and in particular to a chip crack detection method, system, storage medium and intelligent terminal. Background Art

[0002] With the development of communication technology and the advent of the 5G era, the filter industry has also been greatly affected. With the increase in 5G frequency bands, the number of filters in a single device has increased significantly, and the requirements for the size and performance of the filters have also continued to increase. Limited by the volume requirements of the front-end module, the total thickness cannot be greater than 0.6mm, and the total thickness of the new filter cannot be greater than 0.4mm. The typical size of the filter in traditional packaging (1.1mmx0.9mmx0.5mm) can no longer meet the requirements, and advanced wafer-level packaging (WLCSP) must be used to reduce the volume. Wafer bonding is an important means to reduce the volume of WLCSP filter chips.

[0003] From the perspective of wafer material, lithium niobate crystals are widely used in the preparation of surface acoustic filters. Research progress in higher frequency filters is rapid, and material and device preparation technology still shows great potential. With the development of lithium niobate single crystal thin film materials and new acoustic device technologies, as one of the core devices of future 5G communications, front-end RF filters based on lithium niobate crystals have important application prospects. Bonded lithium niobate wafer packaging has a strong market. The process of thinning and cutting lithium niobate bonded wafers through DBG process is usually: first, the back of the wafer (without spherical surface) is attached with a cutting film, and the cutting is cut along the cutting path. The cutting exceeds the target thickness but does not cut through; peel off the dicing film, and then stick the BG film on the front side (with spherical surface), grind to the target thickness, and the chip becomes a single state; then reverse film TC: stick the film on the front side, and then stick the dicing film on the back side of the chip, and then peel off the front film and BG film. At this time, the front side of the wafer is facing up, and the chip is attached to the dicing film in a single state.

[0004] The following problems exist in the prior art: conventional AOI appearance inspection methods are usually carried out after the DBG process is completed. At this time, the front side can be inspected, but cracks on the back side cannot be detected and cannot be effectively inspected, resulting in yield loss. There is still room for improvement. Summary of the invention

[0005] In order to improve the problem that cracks on the back side cannot be detected and cannot be effectively detected, resulting in yield loss, the present application provides a chip crack detection method, system, storage medium and intelligent terminal.

[0006] In a first aspect, the present application provides a chip crack detection method, which adopts the following technical solution:

[0007] A chip crack detection method, comprising:

[0008] sputtering a barrier layer and a seed layer on the surface of a wafer before a DBG process, wherein a substrate and a passivation layer are provided on the wafer;

[0009] Setting marks on the wafer;

[0010] In the DBG process, before the wafer backside is attached with a dicing film and the backside of the wafer faces upward, a scan is performed to form a backside crack scan map;

[0011] mirroring the back crack scan map to form a mirrored back crack scan map;

[0012] After the DBG process is completed, the front side of the wafer is scanned to form a front crack scanning map;

[0013] Based on the mark, the back crack scanning map and the front crack scanning map of the mirror image are integrated to form a comprehensive crack scanning map;

[0014] The crack results are determined and output based on the comprehensive crack scanning map.

[0015] By adopting the above technical solution, the back side is scanned at the time node when the back side is facing up in the middle of the DBG process, and then the front side is photographed after the DBG process is completed. Then, the two scanned images are merged and automatically analyzed based on the marks, so as to avoid the occurrence of cracks on the back side without being detected and causing greater losses, thereby improving the accuracy of crack detection.

[0016] Optionally, the method for setting a mark includes:

[0017] Determine the light transmittance of the wafer;

[0018] When the light transmittance of the wafer is strong, a first bump is electroplated on the passivation layer to serve as a mark;

[0019] When the light transmittance of the wafer is weak or non-transparent, electroplating a first bump on the passivation layer;

[0020] In the DBG process, before attaching a dicing film to the back side of the wafer and when the back side of the wafer faces upward, a second bump is laser printed on the back side, and a mapping relationship between the first bump and the second bump is formed as a mark.

[0021] By adopting the above technical solution, when the wafer is light-transmitting, it is only necessary to electroplate bumps on the passivation layer, and the marks can be recognized by the scanned images on both sides. When the wafer itself is not light-transmitting, it is necessary to mark both sides, so that regardless of whether the wafer is light-transmitting or not, two images can be generated in one image for identification, thereby improving the efficiency of image combination.

[0022] Optionally, in the DBG process, before attaching a scribing film to the back side of the wafer and with the back side of the wafer facing upward, a method for laser printing a second bump on the back side includes:

[0023] In the DBG process, an infrared scanning pattern is formed before the dicing film is attached to the back of the wafer and the back of the wafer faces upward;

[0024] Determine the convex point coordinates of the first convex point based on the infrared scanning spectrum;

[0025] Determining a second convex point printing position based on the convex point coordinates and a preset printing scheme;

[0026] In the DBG process, before attaching a dicing film to the back side of the wafer and with the back side of the wafer facing upward, a second bump is laser printed at the second bump printing position.

[0027] By adopting the above technical solution, since the first bump is additionally electroplated, during the processing, the heat at the position of the first bump is always greater than the heat at other positions, so infrared scanning can be used to more clearly identify the point, and then the second bump is printed according to certain regulations, thereby improving the efficiency of printing the second bump.

[0028] Optionally, a method for modifying the convex point coordinates and the second convex point printing position is also included, the method comprising:

[0029] When a crack result is obtained for the first time, the crack region is analyzed, the crack result is defined as the first crack result, and the crack region is defined as the first crack region;

[0030] When the convex point coordinates and the second convex point printing position fall into the first crack area, a normal area is obtained based on the first crack area and a preset safety bandwidth;

[0031] Determine the test convex point coordinates and the test second convex point printing position based on the normal area and the convex point coordinates;

[0032] After testing according to the test convex point coordinates and the test second convex point printing position, the crack result is re-obtained and the crack area is analyzed, and the crack area is defined as the test crack area;

[0033] Outputting an abnormal electroplating step or an abnormal printing step when the test bump coordinates and the test second bump printing position fall into the test crack area;

[0034] When the test convex point coordinates and the test second convex point printing position do not fall into the test crack area, the convex point coordinates and the second convex point printing position are updated according to the test convex point coordinates and the test second convex point printing position respectively, and the obtained crack result is redefined as the first crack result.

[0035] By adopting the above technical solution, if the positions of cracks and bumps overlap during the first printing, it means that cracks may be generated in the subsequent work process due to internal damage caused by the bumps. In order to avoid cracks in the next work process, the corresponding position is replaced to reduce the impact caused by printing or electroplating bumps.

[0036] Optionally, the method for determining crack results based on the comprehensive crack scanning spectrum and outputting the results includes:

[0037] When the crack result is an existence crack result, the comprehensive crack scanning map is disassembled into a back crack scanning map and a front crack scanning map;

[0038] Separately analyzing the back crack scanning map and the front crack scanning map to obtain a map where the crack is located, and defining the map as a crack location map;

[0039] Accumulate the number of anomalies in each of the crack maps and calculate the percentage;

[0040] When the percentage is greater than a preset average qualified rate, the crack map is selected and the crack area is analyzed based on the crack map;

[0041] Based on the crack area and the crack location map, the corresponding abnormal process step is found from the preset process database;

[0042] The crack results are output along with the abnormal process steps.

[0043] By adopting the above technical solution, when cracks occur too frequently, it is very likely that it is not caused by the wafer itself but by the operation during the processing. Therefore, by querying the corresponding process steps and outputting them, the staff can check the corresponding equipment and processes according to the output process steps, avoiding the reduction of wafer yield due to problems with the equipment or process operation, thereby improving the accuracy of crack output.

[0044] Optionally, the method of outputting the abnormal process steps while outputting the crack results includes:

[0045] Determine the number of abnormal process steps and define the number as abnormal number;

[0046] When the number of abnormalities is one, the crack result is output and the abnormal process step is output at the same time;

[0047] When the number of abnormal process steps is greater than or equal to two, scanning is performed in a time period between two adjacent abnormal process steps to obtain an intermediate crack scanning map and an intermediate crack scanning map number;

[0048] Analyze the intermediate crack scanning atlas and obtain the intermediate crack result, forming a mapping relationship between the intermediate crack result and the intermediate crack scanning atlas number;

[0049] Analyze the scanning atlas of two adjacent middle cracks and obtain the difference crack result, forming a mapping relationship between the difference crack result and the number of the middle crack scanning atlas;

[0050] Analyze the intermediate crack results and phase difference crack results according to the intermediate crack scanning atlas number;

[0051] When the crack result first appears in the middle crack result, the middle crack scanning atlas number is defined as the first abnormal atlas number;

[0052] When a crack result exists in the phase difference crack result, the corresponding intermediate crack scanning atlas number is defined as the subsequent abnormal atlas number;

[0053] Determine the actual abnormal process step based on the first abnormal graph number and the subsequent abnormal graph number, and define the abnormal process step as the actual abnormal process step;

[0054] While outputting the crack results, the actual abnormal process steps are output in sequence.

[0055] By adopting the above technical solution, when there are multiple steps, the images are taken sequentially and the difference between two adjacent spectra is obtained, so as to analyze the result of each step and improve the accuracy of the output of abnormal process steps.

[0056] Optionally, the method of outputting the crack result and the actual abnormal process steps in sequence includes:

[0057] Based on the actual abnormal process steps, the influence degree and influence mode between any two actual abnormal process steps are found from a preset association database;

[0058] When the influence degree is greater than the preset close correlation degree, the actual abnormal process step carried out first is defined as the front process step, and the intermediate crack scanning map corresponding to the front process step is defined as the front crack scanning map, the actual abnormal process step carried out later is defined as the back process step, and the intermediate crack scanning map corresponding to the back process step is defined as the back crack scanning map;

[0059] Analyze the front crack scanning map to obtain the front crack area;

[0060] The predicted crack area is obtained based on the previous crack area and the impact mode;

[0061] Analyze the post-crack scanning map to obtain the post-crack area;

[0062] Analyze the predicted crack area and the post-crack area to obtain the degree of similarity;

[0063] When the degree of similarity is greater than a preset critical degree of similarity, the subsequent process step is deleted from the actual abnormal process steps;

[0064] When the similarity level is less than the critical sameness level, the preceding process step and the following process step are still output.

[0065] By adopting the above technical solution, although the spectrum changes occur after the two associated steps, the latter step is the result of the continued influence of the previous step, so there is actually no problem with the latter step. Therefore, in order to avoid the latter step being misjudged as an abnormal process step, the correlation between the two process steps is determined to obtain the associated steps, and then the estimated second step is obtained based on the first step. The two are then compared and analyzed to draw a conclusion on whether the latter step is normal, thereby improving the accuracy of the output of the actual abnormal process step.

[0066] In a second aspect, the present application provides a chip crack detection system, which adopts the following technical solution:

[0067] A chip crack detection system, comprising:

[0068] An acquisition module is used to acquire a back crack scanning map, a front crack scanning map, a wafer transmittance and an infrared scanning map;

[0069] A memory, used to store a program of a control method of any of the above chip crack detection methods;

[0070] The program in the processor memory can be loaded and executed by the processor and implements any of the above-mentioned chip crack detection methods.

[0071] By adopting the above technical solution, the back side is scanned at the time node when the back side is facing up in the middle of the DBG process, and then the front side is photographed after the DBG process is completed. Then, the two scanned images are merged and automatically analyzed based on the marks, so as to avoid the occurrence of cracks on the back side without being detected and causing greater losses, thereby improving the accuracy of crack detection.

[0072] In the third aspect, the present application provides a smart terminal, which adopts the following technical solution:

[0073] The intelligent terminal includes a memory and a processor, wherein the memory stores a computer program that can be loaded by the processor and execute any of the above chip crack detection methods.

[0074] On the fourth aspect, the present application provides a computer storage medium that can store corresponding programs and has the characteristics of high data processing and analysis efficiency.

[0075] Computer readable storage medium, using the following technical solution:

[0076] A computer-readable storage medium stores a computer program that can be loaded by a processor and execute any of the above-mentioned chip crack detection methods.

[0077] In summary, the present application includes at least the following beneficial technical effects:

[0078] By scanning the back side at the time point when the back side is facing upward in the middle of the DBG process, and then photographing the front side after the DBG process is completed, the two scanned images are combined and automatically analyzed based on the marks, so as to avoid the cracks on the back side from not being detected and causing greater losses, and improve the accuracy of crack detection;

[0079] When the wafer is light-transmitting, it is only necessary to electroplate bumps on the passivation layer. When the wafer itself is light-opaque, it is necessary to mark both sides. This allows two maps to be generated in one map for identification regardless of whether the wafer is light-transmitting or not, thus improving the efficiency of map combination.

[0080] When cracks occur too frequently, the corresponding process steps are queried and output, allowing staff to check the corresponding equipment and processes based on the output process steps, thereby avoiding a reduction in wafer yield due to problems with their own equipment or process operations, and improving the accuracy of crack output. BRIEF DESCRIPTION OF THE DRAWINGS

[0081] Figure 1 It is a flow chart of a chip crack detection method in an embodiment of the present application.

[0082] Figure 2 It is a schematic diagram of the chip integration steps in the embodiment of the present application.

[0083] Figure 3 It is a flowchart of the method for setting a mark in an embodiment of the present application.

[0084] Figure 4 It is a flow chart of a method for laser printing a second bump on the back side of a wafer before attaching a dicing film to the back side of the wafer and when the back side of the wafer faces upward in a DBG process in an embodiment of the present application.

[0085] Figure 5 It is a flow chart of the method for modifying the convex point coordinates and the second convex point printing position in the embodiment of the present application.

[0086] Figure 6 It is a flow chart of a method for determining crack results and outputting them based on a comprehensive crack scanning spectrum in an embodiment of the present application.

[0087] Figure 7 It is a flow chart of a method for outputting crack results and abnormal process steps at the same time in an embodiment of the present application.

[0088] Figure 8 It is a flow chart of a method for outputting crack results and outputting actual abnormal process steps in sequence in an embodiment of the present application.

[0089] Fig. 9 It is a system module diagram of a chip crack detection method in an embodiment of the present application. DETAILED DESCRIPTION

[0090] In order to make the purpose, technical solutions and advantages of this application more clear, the following Figure 1-Figure 9 It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0091] The present application embodiment discloses a chip crack detection method. Figure 1 , a chip crack detection method comprises:

[0092] Step 100: sputtering a barrier layer and a seed layer on a surface of a wafer before a DBG process, wherein a substrate and a passivation layer are provided on the wafer.

[0093] The purpose of the sputtering barrier layer is to prevent subsequent operations from causing damage to the interior. The seed layer is a layer that provides conductivity to allow the electroplating process to proceed smoothly. The substrate is a thin sheet of silicon-based material, usually made of single crystal silicon or polycrystalline silicon. It has a high degree of purity and good electrical properties. It is the basic material for manufacturing semiconductor chips and provides a stable substrate. The passivation layer is a layer on the surface of the substrate that is passivated, that is, the metal surface is converted into a state that is not easily oxidized. The substrate and passivation layer are provided by the wafer material.

[0094] Step 101: Setting a mark on a wafer.

[0095] The method of setting the mark is described in the following steps and will not be described here. The purpose of the mark is to facilitate system identification.

[0096] Step 102: In the DBG process, before attaching a dicing film to the back side of the wafer and when the back side of the wafer faces upward, scanning is performed to form a back side crack scanning map.

[0097] DBG is a technology that reverses the original "back grinding → wafer cutting" process, first half-cutting the wafer, and then dividing the wafer into chips through back grinding.

[0098] The back crack scanning map is the map after scanning the back of the wafer. It can be obtained by scanning through conventional AOI (Automated Optical Inspection) appearance inspection means. Although the back crack scanning map is obtained at this time, it is not analyzed to reduce the workload of the computer. The image after scanning is as follows Figure 2 As shown in the figure on the left.

[0099] Step 103: Mirror the back crack scanning map to form a mirrored back crack scanning map.

[0100] The mirrored back crack scan map is a map that is mirrored to the back crack scan map. Figure 2 As shown in the middle, the graph is flipped.

[0101] Step 104: After the DBG process is completed, a scan is performed on the front side of the wafer to form a front side crack scan map.

[0102] The front crack scanning map is a map scanned on the front side of the wafer. The scanning method is the same as step 101 and can be performed by conventional AOI means. When DBG is completed, the wafer is turned to face up, so the front crack scanning map can be obtained by scanning at this time.

[0103] Step 105: Based on the mark, the back crack scanning map and the front crack scanning map of the mirror image are integrated to form a comprehensive crack scanning map.

[0104] The comprehensive crack scanning map is a map including the mirror image back crack scanning map and the front crack scanning map. Due to the presence of the mark, the relative position of the mirror image back crack scanning map and the front crack scanning map is known, so the marks can be used to make the two overlap each other to form a comprehensive crack scanning map.

[0105] Step 106: Determine the crack result based on the comprehensive crack scanning map and output it.

[0106] The crack result is the result of whether a crack exists and the orientation of the crack. Here, only one spectrum needs to be analyzed, and there is no need to analyze two spectra separately, which improves the detection efficiency of the spectrum.

[0107] Reference Figure 3 , the methods for setting tags include:

[0108] Step 200: Determine the light transmittance of the wafer.

[0109] Wafer light transmittance is the light transmittance performance of the wafer. The user can input the material of the wafer, and then the system automatically searches for the corresponding light transmittance from the preset database to obtain it.

[0110] Step 201: When the light transmittance of the wafer is strong, a first bump is electroplated on the passivation layer to serve as a mark.

[0111] The first bump is a protruding mark point formed by electroplating. When the wafer has strong light transmittance, such as lithium niobate wafer, the alignment pattern on the front can also be identified from the back, so only one mark is needed to be identified on both sides, so only the first bump needs to be electroplated. In order to identify the placement direction, Figure 2 As shown, the number of the first convex points is three to ensure that the first convex points can accurately identify the direction of the spectrum.

[0112] Step 202: electroplating a first bump on the passivation layer when the wafer has low light transmittance or no light transmittance.

[0113] When the light transmittance is weak or opaque, such as a silicon-based wafer, the bumps on the front cannot be scanned from the back, so both sides need to be marked. Here, the first bump is electroplated on the passivation layer.

[0114] Step 203: In the DBG process, before attaching a dicing film to the back side of the wafer and when the back side of the wafer faces upward, laser print the second bumps on the back side, and form a mapping relationship between the first bumps and the second bumps as a mark.

[0115] The second convex point is the second convex point on the back side. The convex point here can be the same pattern as the first convex point, or can be a different pattern, as long as the two can be mapped and related together.

[0116] Reference Figure 4 In a DBG process, before attaching a scribing film to the back side of a wafer and when the back side of the wafer faces upward, a method for laser printing a second bump on the back side includes:

[0117] Step 300: In the DBG process, before attaching a dicing film to the back side of the wafer and when the back side of the wafer faces upward, an infrared scanning pattern is formed.

[0118] Infrared scanning spectrum is a spectrum scanned by infrared rays, and the colors in the spectrum are distinguished according to the heat. The scanning process can be obtained by scanning with an infrared IR microscope.

[0119] Step 301: Determine the salient point coordinates of the first salient point based on the infrared scanning spectrum.

[0120] The bump coordinates are the coordinates of the first bump on the wafer. Since the first bump is formed after electroplating, the heat here is higher than the heat in other areas, so the bump coordinates can be analyzed based on the infrared scanning spectrum.

[0121] Step 302: Determine a second convex point printing position based on the convex point coordinates and a preset printing scheme.

[0122] The printing scheme is a scheme of the associated positions between the first bump and the second bump, for example: 3mm to the left of the first bump. The second bump printing position is the position where the second bump is printed on the back of the wafer. The determination method is the bump coordinates plus the moving distance formed by the printing scheme.

[0123] Step 303: In the DBG process, before attaching a dicing film to the back side of the wafer and with the back side of the wafer facing upward, laser print the second bump at the second bump printing position.

[0124] Reference Figure 5 , and also includes a method for modifying the convex point coordinates and the second convex point printing position, the method comprising:

[0125] Step 400: Analyze the crack region when the crack result is obtained for the first time, define the crack result as the first crack result, and define the crack region as the first crack region.

[0126] The purpose here is to determine the location of the crack.

[0127] Step 401: when the convex point coordinates and the second convex point printing position fall into the first crack area, a normal area is obtained based on the first crack area and a preset safety bandwidth.

[0128] The safety bandwidth is a safety value set by humans, that is, the position beyond this value will not be affected by the first convex point and the second convex point. The normal area is the area at least as far away from the first crack area as the safety bandwidth. The method here is to extend the safety bandwidth around any point in the first crack area.

[0129] Step 402: Determine the test convex point coordinates and the test second convex point printing position based on the normal area and the convex point coordinates.

[0130] The determination method is to search in the normal area for each first convex point and the second convex point to fall within the normal area. The test convex point coordinates are the convex point coordinates falling within the normal area. The test second convex point printing position is the second convex point printing position falling within the normal area.

[0131] Step 403: After testing according to the test convex point coordinates and the test second convex point printing position, the crack result is obtained again and the crack area is analyzed, and the crack area is defined as the test crack area.

[0132] The steps here are the same as step 400.

[0133] Step 404: outputting an abnormal electroplating step or an abnormal printing step when the test bump coordinates and the test second bump printing position fall into the test crack area.

[0134] If it still falls in, it means that the crack here moves with the position of the first bump plating and the second bump printing. There is a problem with the plating and printing steps here, so the abnormal plating step or abnormal printing step is output.

[0135] Step 405: When the test convex point coordinates and the test second convex point printing position do not fall into the test crack area, the convex point coordinates and the second convex point printing position are updated according to the test convex point coordinates and the test second convex point printing position respectively, and the obtained crack result is redefined as the first crack result.

[0136] When it does not fall into the test, the test convex point coordinates and the test second convex point printing position do not affect the cracks and will not generate cracks, so they can be output as actual convex point coordinates and the second convex point printing position.

[0137] Reference Figure 6 , the method for determining crack results and outputting them based on the comprehensive crack scanning map includes:

[0138] Step 500: When the crack result is an existence crack result, the comprehensive crack scanning map is disassembled into a back crack scanning map and a front crack scanning map.

[0139] The crack existence result is the result of the existence of cracks. In order to further analyze the process, the spectrum can be re-analyzed to find the cause of the crack. The comprehensive crack scanning spectrum can be disassembled or the original spectrum can be recalled.

[0140] It should be noted that if no steps need to be changed here, no implementation processing is required.

[0141] Step 501: Analyze the back crack scanning map and the front crack scanning map separately to obtain a map where the crack is located, and define the map as the crack location map.

[0142] Step 502: Accumulate the number of anomalies in each of the crack maps and calculate the percentage.

[0143] The number of abnormalities is the number of maps where the crack is located. The percentage is the percentage of the map where the crack is located in all maps. Here, the denominator includes not only the number of maps with cracks on the back and the number of maps with cracks on the front, but also the number of maps without cracks. The calculation method is to divide the number of abnormalities by the total number.

[0144] Step 503: When the percentage is greater than a preset average qualified rate, the crack location map is screened out and the crack area is analyzed based on the crack location map.

[0145] The average qualified rate is a manually set value. When it is greater than this value, it means that the cracks are not accidental, and the cause needs to be carefully investigated. In order to reduce the percentage of a small number, it is not a reference, so this step will be performed only after the total number is greater than a certain number.

[0146] Step 504: Find the corresponding abnormal process step from a preset process database based on the crack area and the crack map.

[0147] Abnormal process steps are process steps that may cause cracks on the wafer due to operating errors or improper operations. The database stores the mapping relationship between the crack area, the crack location map and the abnormal process steps, which is obtained by the staff in this field based on previous experience and experiments, that is, inaccurate data or improper operation are used in different steps. When cracks occur on the back or front of the wafer, the crack area and the back or front where it is located are recorded. When the system receives the corresponding crack area and the crack location map, it automatically finds the corresponding abnormal process step from the database and outputs it.

[0148] Step 505: Output the crack results and the abnormal process steps at the same time.

[0149] The purpose of the output here is to alert the staff and check and verify the staff, equipment and operating methods corresponding to the abnormal process steps.

[0150] Reference Figure 7 The method of outputting the crack results and abnormal process steps at the same time includes:

[0151] Step 600: Determine the number of abnormal process steps, and define the number as an abnormal number.

[0152] The method of determination is by counting.

[0153] Step 601: When the number of abnormalities is one, the crack result is output and the abnormal process step is output at the same time.

[0154] When there is only one, there is no need to divide it. If there is only one corresponding step, then there must be a problem with this step, so you only need to output this step.

[0155] Step 602: When the number of abnormal process steps is greater than or equal to two, scan in the time period between two adjacent abnormal process steps to obtain an intermediate crack scanning map and an intermediate crack scanning map number.

[0156] When there are more than or equal to two, it is necessary to analyze which step is the cause. Therefore, in order to determine which step is the cause, one by one can be analyzed. Here, the step of analyzing one by one is performed in an operation after observing that the percentage is greater than the average qualified rate. The intermediate crack scanning map is obtained after the previous abnormal process step is performed, and the purpose is to detect whether the previous abnormal process step will produce cracks.

[0157] Step 603: Analyze the intermediate crack scanning map and obtain the intermediate crack result, forming a mapping relationship between the intermediate crack result and the intermediate crack scanning map number.

[0158] The middle crack result is the result of the middle crack scanning spectrum. The purpose of forming a mapping relationship is to facilitate the search for the corresponding spectrum and the spectrum number.

[0159] Step 604: Analyze two adjacent middle crack scanning maps and obtain a phase difference crack result, forming a mapping relationship between the phase difference crack result and the middle crack scanning map number.

[0160] The phase difference crack result is the difference between the two intermediate crack results, that is, whether some new cracks are added after the previous process step. The purpose of formation is also to facilitate searching.

[0161] Step 605: Analyze the intermediate crack results and the phase difference crack results according to the intermediate crack scanning atlas number.

[0162] The method of analysis here is to determine the area where the crack is located and its size.

[0163] Step 606: When the intermediate crack result first shows an existing crack result, define the intermediate crack scanning map number as the first abnormal map number.

[0164] When it appears, it means that cracks have begun to appear at this step.

[0165] Step 607: When a crack result exists in the phase difference crack result, define the corresponding intermediate crack scanning map number as the subsequent abnormal map number.

[0166] When the phase difference crack result shows a crack existence result, it means that a new crack is added on the basis of the original crack, which means that the corresponding step may also lead to the generation of the new crack.

[0167] Step 608: Determine the actual abnormal process step based on the first abnormal map number and the subsequent abnormal map number, and define the abnormal process step as the actual abnormal process step.

[0168] Here, since the corresponding mapping relationship has been formed before, the abnormal process steps corresponding to the first abnormal graph number and the subsequent abnormal graph number can be found through the mapping relationship and output.

[0169] Step 609: while outputting the crack results, the actual abnormal process steps are outputted in sequence.

[0170] Reference Figure 8 The method of outputting crack results and outputting actual abnormal process steps in sequence includes:

[0171] Step 700: Based on the actual abnormal process steps, the influence degree and influence mode between any two actual abnormal process steps are searched from a preset association database.

[0172] The degree of influence is the degree of influence between two actual abnormal process steps, which can be expressed as a percentage here. The mode of influence is the way the former affects the latter, for example: if the former extends 1 cm more, the latter will extend 1 cm more. The database stores the mapping relationship between any two actual abnormal process steps, the degree of influence and the mode of influence. The staff in this field observes the phenomena when the influence occurs according to the actual situation and combines their own cognition to record and store it in the database. When the system receives the corresponding two actual abnormal process steps, it automatically finds the corresponding degree of influence and mode of influence from the database and outputs them.

[0173] Step 701: When the degree of influence is greater than the preset close correlation degree, the actual abnormal process step performed first is defined as the front process step, and the intermediate crack scanning map corresponding to the front process step is defined as the front crack scanning map, the actual abnormal process step performed later is defined as the post-process step, and the intermediate crack scanning map corresponding to the post-process step is defined as the post-crack scanning map.

[0174] The degree of close correlation is the degree to which a problem in the former step will inevitably affect the latter step. When it is greater than, it means that the two steps will affect each other. Here, the two steps are steps acting on the same crack area.

[0175] Step 702: Analyze the front crack scanning map to obtain the front crack area.

[0176] The front crack region is the crack region obtained after the front process step is performed.

[0177] Step 703: Obtain the predicted crack area based on the previous crack area and the impact mode.

[0178] The expected crack area is the crack area after the later process step if the equipment or method corresponding to the later process step is installed or operated correctly in theory. Here, the front crack area is extended according to the impact mode. For example, the front crack area is a crack with a width of 1mm and a length of 2mm. When an impact occurs, it may be a crack with a width of 1mm and a length of 4mm.

[0179] Step 704: Analyze the post-crack scanning map to obtain the post-crack area.

[0180] The post-crack region is the crack region obtained after the post-process steps are performed.

[0181] Step 705: Analyze the predicted crack region and the post-crack region to obtain the degree of similarity.

[0182] The degree of similarity refers to the degree of similarity between the predicted crack area and the post-crack area, where the percentage of similarities between the two is used as the similarity.

[0183] Step 706: When the similarity level is greater than a preset critical similarity level, the subsequent process steps are deleted from the actual abnormal process steps.

[0184] The critical similarity is an artificially set value, that is, when it is greater than this value, it means that the two are basically the same, which means that the subsequent process step alone does not produce cracks, and cracks are only caused by the previous process step. Therefore, the subsequent process step should be deleted from the actual abnormal process steps.

[0185] Step 707: When the similarity level is less than the critical similarity level, the preceding process step and the succeeding process step are still outputted.

[0186] If it is less than, it means that the post-process step is also different from the theoretically normal process step, and the pre-process step and post-process step need to be output.

[0187] Based on the same inventive concept, an embodiment of the present invention provides a chip crack detection system.

[0188] Reference Fig. 9 , a chip crack detection system, comprising:

[0189] An acquisition module is used to acquire a back crack scanning map, a front crack scanning map, a wafer transmittance and an infrared scanning map;

[0190] A memory for storing a program of a control method for a chip crack detection method;

[0191] The program in the memory can be loaded and executed by the processor to implement a control method for a chip crack detection method.

[0192] Those skilled in the art can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional modules is used as an example. In actual applications, the above-mentioned functions can be assigned to different functional modules as needed, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above. The specific working process of the system, device and unit described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.

[0193] An embodiment of the present invention provides a computer-readable storage medium storing a computer program that can be loaded by a processor and executed by a chip crack detection method.

[0194] Computer storage media include, for example, various media that can store program codes, such as USB flash drives, mobile hard disks, read-only memories (ROM), random access memories (RAM), magnetic disks or optical disks.

[0195] Based on the same inventive concept, an embodiment of the present invention provides an intelligent terminal, including a memory and a processor, wherein the memory stores a computer program that can be loaded by the processor and execute a chip crack detection method.

[0196] The above are all preferred embodiments of the present application, and are not intended to limit the protection scope of the present application. Any feature disclosed in this specification (including the abstract and drawings), unless otherwise stated, can be replaced by other equivalent or alternative features with similar purposes. That is, unless otherwise stated, each feature is only an example of a series of equivalent or similar features.

Claims

1. A chip crack detection method, characterized in that: include: sputtering a barrier layer and a seed layer on the surface of a wafer before a DBG process, wherein a substrate and a passivation layer are provided on the wafer; Setting marks on the wafer; In the DBG process, before the wafer backside is attached with a dicing film and the backside of the wafer faces upward, a scan is performed to form a backside crack scan map; mirroring the back crack scan map to form a mirrored back crack scan map; After the DBG process is completed, the front side of the wafer is scanned to form a front crack scanning map; Based on the mark, the back crack scanning map and the front crack scanning map of the mirror image are integrated to form a comprehensive crack scanning map; Determine crack results based on comprehensive crack scanning maps and output them; Among them, the method for determining crack results based on the comprehensive crack scanning spectrum and outputting them includes: When the crack result is a crack result, the comprehensive crack scanning map is disassembled into the back crack scanning map and the front crack scanning map; the back crack scanning map and the front crack scanning map are analyzed separately to obtain the map where the crack is located, and the map is defined as the crack location map; the number of abnormalities of each as the crack location map is accumulated and the percentage is calculated; when the percentage is greater than the preset average qualified rate, the crack location map is screened out and the crack area is analyzed based on the crack location map; based on the crack area and the crack location map, the corresponding abnormal process step is found from the preset process database; the abnormal process step is output while the crack result is output; The method for outputting the abnormal process steps while outputting the crack results includes: determining the number of abnormal process steps and defining the number as the abnormal number; outputting the abnormal process steps while outputting the crack results when the abnormal number is one; scanning in the time period between two adjacent abnormal process steps when the number of abnormal process steps is greater than or equal to two to obtain an intermediate crack scanning map and an intermediate crack scanning map number; analyzing the intermediate crack scanning map and obtaining the intermediate crack results, forming a mapping relationship between the intermediate crack results and the intermediate crack scanning map number; analyzing two adjacent intermediate crack scanning maps and obtaining a phase difference crack result. , forming a mapping relationship between the phase difference crack result and the intermediate crack scanning atlas number; analyzing the intermediate crack result and the phase difference crack result according to the intermediate crack scanning atlas number; defining the intermediate crack scanning atlas number as the first abnormal atlas number when the intermediate crack result first shows an existing crack result; defining the corresponding intermediate crack scanning atlas number as the subsequent abnormal atlas number when the phase difference crack result shows an existing crack result; determining the actual abnormal process step based on the first abnormal atlas number and the subsequent abnormal atlas number, defining the abnormal process step as the actual abnormal process step; outputting the crack result and the actual abnormal process steps in sequence.

2. A chip crack detection method according to claim 1, characterized in that: Methods for setting tags include: Determine the light transmittance of the wafer; When the light transmittance of the wafer is strong, a first bump is electroplated on the passivation layer to serve as a mark; When the light transmittance of the wafer is weak or non-transparent, electroplating a first bump on the passivation layer; In the DBG process, before attaching a dicing film to the back side of the wafer and when the back side of the wafer faces upward, a second bump is laser printed on the back side, and a mapping relationship between the first bump and the second bump is formed as a mark.

3. A chip crack detection method according to claim 2, characterized in that: In the DBG process, before attaching a scribing film to the back side of a wafer and when the back side of the wafer faces upward, a method for laser printing a second bump on the back side includes: In the DBG process, an infrared scanning pattern is formed before the dicing film is attached to the back of the wafer and the back of the wafer faces upward; Determine the convex point coordinates of the first convex point based on the infrared scanning spectrum; Determining a second convex point printing position based on the convex point coordinates and a preset printing scheme; In the DBG process, before attaching a dicing film to the back side of the wafer and with the back side of the wafer facing upward, a second bump is laser printed at the second bump printing position.

4. A chip crack detection method according to claim 3, characterized in that: Also included is a method for modifying the convex point coordinates and the second convex point printing position, the method comprising: When a crack result is obtained for the first time, the crack region is analyzed, the crack result is defined as the first crack result, and the crack region is defined as the first crack region; When the convex point coordinates and the second convex point printing position fall into the first crack area, a normal area is obtained based on the first crack area and a preset safety bandwidth; Determine the test convex point coordinates and the test second convex point printing position based on the normal area and the convex point coordinates; After testing according to the test convex point coordinates and the test second convex point printing position, the crack result is re-obtained and the crack area is analyzed, and the crack area is defined as the test crack area; Outputting an abnormal electroplating step or an abnormal printing step when the test bump coordinates and the test second bump printing position fall into the test crack area; When the test convex point coordinates and the test second convex point printing position do not fall into the test crack area, the convex point coordinates and the second convex point printing position are updated according to the test convex point coordinates and the test second convex point printing position respectively, and the obtained crack result is redefined as the first crack result.

5. A chip crack detection method according to claim 1, characterized in that: The method of outputting crack results and outputting actual abnormal process steps in sequence includes: Based on the actual abnormal process steps, the influence degree and influence mode between any two actual abnormal process steps are found from a preset association database; When the influence degree is greater than the preset close correlation degree, the actual abnormal process step carried out first is defined as the front process step, and the intermediate crack scanning map corresponding to the front process step is defined as the front crack scanning map, the actual abnormal process step carried out later is defined as the back process step, and the intermediate crack scanning map corresponding to the back process step is defined as the back crack scanning map; Analyze the front crack scanning map to obtain the front crack area; The predicted crack area is obtained based on the previous crack area and the impact mode; Analyze the post-crack scanning map to obtain the post-crack area; Analyze the predicted crack area and the post-crack area to obtain the degree of similarity; When the degree of similarity is greater than a preset critical degree of similarity, the subsequent process step is deleted from the actual abnormal process steps; When the similarity level is less than the critical sameness level, the preceding process step and the following process step are still output.

6. A chip crack detection system, characterized in that: include: An acquisition module is used to acquire a back crack scanning map, a front crack scanning map, a wafer transmittance and an infrared scanning map; A memory for storing a program of a control method for a chip crack detection method according to any one of claims 1 to 5; The program in the memory can be loaded and executed by the processor and implement a control method for a chip crack detection method as described in any one of claims 1 to 5.

7. Intelligent terminal, characterized in that: The invention comprises a memory and a processor, wherein the memory stores a computer program which can be loaded by the processor and executes a chip crack detection method as claimed in any one of claims 1 to 5.

8. A computer-readable storage medium, characterized in that A computer program capable of being loaded by a processor and executing a chip crack detection method according to any one of claims 1 to 5 is stored.

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