Direct type electron probe

Abstract

The application provides a direct electronic detector, which comprises a semiconductor laminated structure and a peripheral signal measurement circuit; the semiconductor laminated structure comprises, from bottom to top, a semiconductor base, a U-shaped cross-section semiconductor resistance layer, a first semiconductor layer, a second semiconductor layer, an insulating layer, a metal layer, an intrinsic layer and a third semiconductor layer; the first semiconductor layer is formed in a groove of the resistance layer, the second semiconductor layer is formed on the first semiconductor layer, the insulating layer is formed on the outside of the second semiconductor layer, and the metal layer is formed on the outside of the insulating layer; the resistance layer and the first semiconductor layer are of a first doping type, the second semiconductor layer and the third semiconductor layer are of a second doping type, the third semiconductor layer and the intrinsic layer form an electron absorption zone, and the first semiconductor layer and the second semiconductor layer form an avalanche zone; the peripheral signal measurement circuit comprises a counter; and the semiconductor laminated structure is electrically connected with the peripheral signal measurement circuit. The structure can effectively improve the sensitivity and response speed of the detector.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor integrated circuit design and manufacturing technology, in particular to a direct electron detector. BACKGROUND

[0002] The direct electron detector is a digital imaging system made of a complementary metal-oxide-semiconductor (CMOS) process. It does not need to convert the electron signal into a photon signal through a fluorescent body and then couple the indirect detection mode. It can directly detect the electron signal, directly incident various energy electrons into the electron detector, generate collision ionization through the energy of the incident electrons, cause the conductivity of the incident material to change, and form electron-hole pairs. Compared with the indirect electron detector, it can improve the spatial resolution and detection efficiency of the cryo-electron microscopy technology for analyzing the structure of biological samples. It is commonly used in characterization tests based on electron detection, such as scanning electron microscopy (SEM), transmission electron microscopy (TEM), scanning transmission electron microscopy (STEM), and cryo-electron microscopy, for collecting electron signals.

[0003] At present, the direct electron detector mostly uses a PIN structure to collect the electron signal. The PIN structure only detects, and does not amplify the electron signal, so the sensitivity is low. In addition, the general direct electron detector needs to make the thickness of the absorption layer reach several hundred microns, such as 300 μm-600 μm, so as to obtain the smallest possible device capacitance in the full depletion state, thereby increasing the response speed of the detector. However, the thicker absorption layer increases the movement distance of the carriers under the action of the electric field, which in turn reduces the response speed of the detector. SUMMARY

[0004] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a direct electron detector to solve the problems of low sensitivity and low response speed of the direct electron detector in the prior art.

[0005] To achieve the above-mentioned purpose and other related purposes, the present application provides a direct electron detector, which comprises a semiconductor laminated structure and a peripheral signal measurement circuit.

[0006] The semiconductor stack structure comprises, from bottom to top, a semiconductor substrate, a U-shaped cross-section semiconductor resistance layer, a first semiconductor layer, a second semiconductor layer, an insulating layer, a metal layer, an intrinsic layer and a third semiconductor layer; wherein the U-shaped cross-section semiconductor resistance layer extends inward from the surface of the semiconductor substrate, the first semiconductor layer is formed in the groove of the U-shaped cross-section semiconductor resistance layer, the second semiconductor layer is formed on the first semiconductor layer, the insulating layer is formed outside the second semiconductor layer, and the metal layer is formed outside the insulating layer and in contact with the U-shaped cross-section semiconductor resistance layer; the U-shaped cross-section semiconductor resistance layer and the first semiconductor layer are of a first doping type, the second semiconductor layer and the third semiconductor layer are of a second doping type, the third semiconductor layer and the intrinsic layer form an electron absorption zone, and the first semiconductor layer and the second semiconductor layer form an avalanche zone.

[0007] The peripheral signal measurement circuit comprises a counter.

[0008] The semiconductor stack structure and the peripheral signal measurement circuit are electrically connected together, wherein the metal layer on the U-shaped cross-section semiconductor resistance layer is electrically connected to the counter to realize the counting measurement of the peripheral signal measurement circuit on the electrical signal.

[0009] Optionally, the peripheral signal measurement circuit further comprises an operational amplifier circuit, and the operational amplifier circuit is electrically connected to the metal layer and the counter, respectively.

[0010] Optionally, the operational amplifier circuit comprises an operational amplifier.

[0011] Optionally, the first doping type is N type and the second doping type is P type, or the first doping type is P type and the second doping type is N type.

[0012] Further, the first doping type is N type and the second doping type is P type; the thickness of the U-shaped cross-section semiconductor resistance layer is between 5 μm and 50 μm, the doping concentration is between 1E15 / cm 3 and 1E21 / cm 3 ; the thickness of the first semiconductor layer is between 0.1 μm and 10 μm, the doping concentration is between 1E17 / cm 3 and 1E22 / cm 3 ; the thickness of the second semiconductor layer is between 0.1 μm and 10 μm, the doping concentration is between 1E17 / cm 3 and 1E22 / cm 3 ; and the thickness of the intrinsic layer is between 10 μm and 60 μm, the doping concentration is between 0 and 1E15 / cm 3between 0.1 μm and 10 μm, and a doping concentration between 1E17 / cm 3 and 1E22 / cm 3 .

[0013] Optionally, the semiconductor stack structure further comprises a peripheral protection ring, which is arranged at the periphery of the third semiconductor layer and extends from the top to the inside of the intrinsic layer.

[0014] Optionally, the third semiconductor layer is in an inverted U shape and extends inward from the surface of the intrinsic layer.

[0015] Optionally, the semiconductor material of the semiconductor stack structure is silicon; the material of the insulating layer is silicon oxide; and the metal layer is one of an aluminum layer, a titanium layer, a tungsten layer and a gold layer, or a single layer or a stack of two or more layers.

[0016] Optionally, two or more avalanche regions are formed in the semiconductor stack structure, and adjacent two avalanche regions are separated by the semiconductor substrate, and adjacent two metal layers are separated by the insulating layer.

[0017] Optionally, the peripheral signal measurement circuit is arranged on a PCB board and is wire-bonded to the semiconductor stack structure through a pad on the PCB board, or the peripheral signal measurement circuit is integrated in an ASIC and is wire-bonded to the semiconductor stack structure through a pad on the ASIC.

[0018] As described above, the direct electron detector of the present application can effectively realize avalanche multiplication of incident electrons by arranging the avalanche region, improve the detection sensitivity; in addition, the thickness of the intrinsic layer can be reduced, such as to 30 μm, to meet the electron absorption capacity with 50 keV energy, and other intrinsic layer thicknesses can also be arranged according to the energy of the electrons to be detected; the reduction of the intrinsic layer thickness shortens the electron migration path and reduces the electron transit time, thereby improving the signal reading speed of the detector. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 FIG. 1 shows a structure schematic diagram of an example of a semiconductor stack structure in a direct electron detector of the present application.

[0020] Figure 2 FIG. 2 shows a structure schematic diagram of another example of a semiconductor stack structure in a direct electron detector of the present application.

[0021] Figure 3 FIG. 3 shows a structure schematic diagram of an example of a peripheral signal measurement circuit in a direct electron detector of the present application.

[0022] Figure 4A structural diagram showing another example of a peripheral signal measuring circuit in a direct type electron detector according to the present application.

[0023] Figure 5 A physical principle diagram showing a semiconductor laminated structure in a direct type electron detector according to the present application.

[0024] Figure 6 An equivalent circuit diagram showing a direct type electron detector according to the present application, in which two or more avalanche regions are included in the semiconductor laminated structure.

[0025] Figure 7 An equivalent circuit diagram showing a direct type electron detector according to the present application, in which only one avalanche region is included in the semiconductor laminated structure.

[0026] Figures 8 to 10 Cross-sectional structural diagrams showing each step in the process of preparing a semiconductor laminated structure in a direct type electron detector according to the present application.

[0027] Figure 11 A graph showing the internal potential distribution in a semiconductor laminated structure in a direct type electron detector according to the present application in the absence of incident electrons, in which the horizontal axis represents the depth of the semiconductor laminated structure and the vertical axis represents the voltage.

[0028] Figure 12 A graph showing the internal electric field distribution in a semiconductor laminated structure in a direct type electron detector according to the present application in the absence of incident electrons, in which the horizontal axis represents the depth of the semiconductor laminated structure and the vertical axis represents the electric field intensity.

[0029] Figure 13 A graph showing the current distribution and response of a device in a direct type electron detector according to the present application when avalanche breakdown occurs, in which the horizontal axis represents the transient time, the left vertical axis represents the current of incident electrons, and the right vertical axis represents the current inside the device.

[0030] Explanation of element reference numerals

[0031] 100 semiconductor laminated structure

[0032] 101 semiconductor substrate

[0033] 102 semiconductor resistance layer having a U-shaped cross section

[0034] 103 first semiconductor layer

[0035] 104 second semiconductor layer

[0036] 105 insulating layer

[0037] 106 metal layer

[0038] 107 intrinsic layer

[0039] 108 third semiconductor layer

[0040] 109 electron absorption region

[0041] 110 avalanche region

[0042] 111 peripheral guard ring

[0043] 200 peripheral signal measurement circuit

[0044] 201 counter

[0045] 202 operational amplifier circuit

[0046] 203 operational amplifier

[0047] 204 PCB board

[0048] 205 solder pad

[0049] 206 ASIC DETAILED DESCRIPTION

[0050] The present application is herein described, by way of example only, with the assistance of specific details to facilitate a comprehensive understanding of the application. Other advantages and utilities of the present application can be readily ascertained by those skilled in the art based on the preceding description. The present application can be practiced according to the claims without resorting to the following detailed description.

[0051] Reference will now be made to the drawings, wherein: Figures 1 to 13 It is to be understood that the drawings are to be used only for illustrative purposes and the present application can be practiced in a variety of ways beyond the specific embodiments illustrated herein. The present application is not limited in scope to the exact details shown and described herein.

[0052] As shown in Figures 1 to 4 , the present application provides a direct type electron detector, which comprises a semiconductor stack structure 100 (as shown in Figure 1 and Figure 2 ) and a peripheral signal measurement circuit 200 (as shown in Figure 3 and Figure 4 );

[0053] The semiconductor stack structure 100 comprises, from bottom to top, a semiconductor substrate 101, a U-shaped cross-section semiconductor resistance layer 102, a first semiconductor layer 103, a second semiconductor layer 104, an insulating layer 105, a metal layer 106, an intrinsic layer 107 and a third semiconductor layer 108; wherein the U-shaped cross-section semiconductor resistance layer 102 extends inward from the surface of the semiconductor substrate 101, the first semiconductor layer 103 is formed in the groove of the U-shaped cross-section semiconductor resistance layer 102, the second semiconductor layer 104 is formed on the first semiconductor layer 103, the insulating layer 105 is formed outside the second semiconductor layer 104, and the metal layer 106 is formed outside the insulating layer 105 and in contact with the U-shaped cross-section semiconductor resistance layer 102; the U-shaped cross-section semiconductor resistance layer 102 and the first semiconductor layer 103 are of a first doping type, the second semiconductor layer 104 and the third semiconductor layer 108 are of a second doping type, the third semiconductor layer 108 and the intrinsic layer 107 form an electron absorption zone 109, and the first semiconductor layer 103 and the second semiconductor layer 104 form an avalanche zone 110; the intrinsic layer 107 can be a non-intentionally doped material layer, i.e. a high-resistance semiconductor material, or a lightly doped layer of the second doping type.

[0054] The peripheral signal measurement circuit 200 comprises a counter 201;

[0055] The semiconductor stack structure 100 and the peripheral signal measurement circuit 200 are electrically connected together, wherein the metal layer 106 on the U-shaped cross-section semiconductor resistance layer 102 is electrically connected to the counter 201, so as to realize the counting measurement of the electric signal by the peripheral signal measurement circuit 200.

[0056] It is to be noted that the first doping type is opposite to the second doping type. That is, if the first doping type is N type, the second doping type is P type; if the first doping type is P type, the second doping type is N type.

[0057] Here, the first doping type is N type and the second doping type is P type, and the direct-type electron detector of the present application is described as follows. Figures 5 to 7As shown, the electrons from the third semiconductor layer 108 into the semiconductor stack structure 100 of the electron absorption zone 109, under the action of electric field, the electron flow drift into the semiconductor stack structure 100 of the avalanche zone 110, avalanche zone PN junction (formed by the first semiconductor layer 103 and the second semiconductor layer 104 PN junction) both ends voltage slightly greater than the breakdown voltage of the PN junction, avalanche phenomenon; after the formation of avalanche avalanche zone 110 PN junction conduction, current flow through the semiconductor stack structure 100 in the U-shaped cross section of the semiconductor resistance layer 102, the signal is detected; at this time, the PN junction both ends of the avalanche zone 110 bias voltage drop, avalanche cut-off, U-shaped cross section of the semiconductor resistance layer 102 on the current disappears, the PN junction both ends of the avalanche zone 110 reverse voltage rises to the original level, waiting to receive the next electron incidence to form avalanche effect; the detected signal is transmitted to the peripheral signal measurement circuit 200 in the counter 201 for counting measurement. The direct type electron detector of the present application can effectively realize the avalanche multiplication of the incident electrons by setting the avalanche zone, improve the detection sensitivity; in addition, the thickness of the intrinsic layer can be reduced, such as to 30 μm, meet the electron absorption capacity with 50 keV energy, also can be set to other intrinsic layer thickness according to the energy of the electron to be detected; the intrinsic layer thickness is reduced, the electron migration path is shortened, the electron transit time is reduced, and the signal reading speed of the detector is improved.

[0058] As an example, any suitable semiconductor material can be selected to prepare the semiconductor stack structure 100, such as silicon material, germanium material, gallium arsenide material, three-five compound material, silicon carbide material, etc. In the present embodiment, silicon material is preferably used. The material of the insulating layer 105 can also be selected from any suitable insulating material, such as silicon oxide, silicon nitride, etc. In the present embodiment, silicon oxide material is preferably used. The metal layer 106 as electrode lead-out material can be selected from any suitable material for electrode preparation, such as any one of aluminum layer, titanium layer, tungsten layer and gold layer, or a two-layer or more stack structure.

[0059] As a preferred example, when the first doping type is N type and the second doping type is P type, the thickness of the U-shaped cross section of the semiconductor resistance layer 102 is between 5 μm and 50 μm, and the doping concentration is between 1E15 / cm 3 ~ 1E21 / cm 3 ; the thickness of the first semiconductor layer 103 is between 0.1 μm and 10 μm, and the doping concentration is between 1E17 / cm 3 ~ 1E22 / cm 3 ; the thickness of the second semiconductor layer 104 is between 0.1 μm and 10 μm, and the doping concentration is between 1E17 / cm 3 ~ 1E22 / cm 3between 0 and 1E15 / cm 3 between 0.1 μm and 10 μm, and a doping concentration between 1E17 / cm 3 and 1E22 / cm 3 It should be noted that when the doping concentration of the intrinsic layer 107 is not 0, the doping type is the second doping type, i.e. P type here.

[0060] As an example, the thickness of the metal layer 106 is between 0.5 μm and 10 μm.

[0061] As a preferred example, the semiconductor stack structure 100 further comprises a peripheral protection ring 111, which is arranged at the outer periphery of the third semiconductor layer 108 and extends downward to the inside of the intrinsic layer 107. The specific shape, size, doping concentration and other parameters of the peripheral protection ring 111 can be set according to actual needs, as long as it can prevent the structure arranged inside from being broken down.

[0062] As shown in Figure 2 , as a preferred example, the third semiconductor layer 108 is in an inverted U shape and extends inward from the surface of the intrinsic layer 107. By deepening the depth of ion implantation at the edge of the third semiconductor layer 108 to form a U shape, the potential distribution at the edge can be changed, the electric field strength at the edge can be reduced, and thus the breakdown voltage of the device can be improved and the risk of breakdown can be reduced.

[0063] As shown in Figure 1 , Figure 2 and Figure 6 , according to actual needs, two or more avalanche regions 110 can be formed in the semiconductor stack structure 100, and the two adjacent avalanche regions 110 are isolated by the semiconductor substrate 101. At this time, the two metal layers 106 on the semiconductor resistance layer 102 of the two adjacent U-shaped sections are isolated by the insulating layer 105, and each avalanche region 110 is electrically connected to a corresponding U-shaped semiconductor resistance layer 102 and a counter 201. This structure is equivalent to a plurality of avalanche structures connected in parallel, and the signals measured by a plurality of U-shaped semiconductor resistance layers 102 are counted and measured by a plurality of counters 201, and the data counted and measured by the plurality of counters 201 are input into a microprocessor (MPU) for further processing, and the sum is the final signal value. The number and arrangement of the avalanche regions 110 are set according to actual needs, and are not limited here. Preferably, all the avalanche regions 110 can be arranged in an array.

[0064] As shown in Figures 8 to 10As shown, as a specific example, the preparation method of the semiconductor stack structure 100 is described with the first doping type being N type and the second doping type being P type, which includes: as shown Figure 8 As shown, first, a semiconductor substrate 101 is provided; then N type ion doping is performed from the surface of the semiconductor substrate 101 inwardly to form N type ion doping regions, and the number, size, depth and arrangement of the N type ion doping regions can be set according to actual needs; then N type ion doping is performed from the surface of the region where the N type ion doping regions are located inwardly to form a first semiconductor layer 103, and the remaining N type ion doping regions form a semiconductor resistance layer 102 with a U-shaped cross section; as shown Figure 9 As shown, an insulating material layer is formed on the surface of the obtained structure, and the insulating material layer is patterned and etched to form an insulating layer 105, which exposes the surface of the first semiconductor layer 103; then a metal material layer is deposited, and the metal material layer is patterned and etched to form a metal layer 106, which is formed on the outer side of the insulating layer 105 and contacts the semiconductor resistance layer 102 with a U-shaped cross section, so as to realize the electrical lead-out of the semiconductor resistance layer 102 with a U-shaped cross section through the metal layer 106 later; as shown Figure 10 As shown, then, a second semiconductor layer 104 is formed on the surface of the obtained structure, which is formed on the first semiconductor layer 103 exposed by the insulating layer 105; as shown Figure 1 and Figure 2 As shown, then, an intrinsic material layer is deposited on the surface of the obtained structure as an intrinsic material region; finally, P type ion re-doping is performed from the surface of the intrinsic material region inwardly to form a third semiconductor layer 108, and the remaining intrinsic material region forms an intrinsic layer 107. After the semiconductor stack structure is formed, it can be packaged to form a semiconductor chip, and then connected to the peripheral signal measurement circuit through wire bonding according to the position of the lead electrode.

[0065] As an example, the peripheral signal measurement circuit 200 further includes an operational amplifier circuit 202, and the operational amplifier circuit 202 is arranged between the semiconductor resistance layer 102 with a U-shaped cross section and the counter 201 to realize amplification of the measurement signal. As shown Figure 7 As a specific example, the operational amplifier circuit 202 includes an operational amplifier 203, which is connected in parallel with a capacitor and a resistor, respectively.

[0066] As an example, the peripheral signal measurement circuit 200 can be realized by using existing common circuit structures, as shown Figure 3As shown, it can be disposed on PCB board 204 and connected to the semiconductor stack-up structure 100 via solder pads 205 on PCB board 204. This packaging method has mature technology, is easy to implement, and has good packaging efficiency and quality; Figure 4 As shown, it can also be integrated into ASIC 206 and wire-connected to the semiconductor stack structure 100 via pad 205.

[0067] This embodiment performs simulation verification on the specific parameters of the following semiconductor stacked structure 100, as shown in Table 1.

[0068] Table 1

[0069]

[0070] The simulation results show that, Figure 11 As shown, the first part A of the curve corresponds to the voltage of the electron absorption region. The bias electric field of the electron absorption region provides the conditions for the generation of the initial electrical signal. The second part B of the curve corresponds to the PN junction voltage. The PN junction bias voltage is relatively large, providing the conditions for the avalanche effect. Figure 12 As shown, in the electric field intensity distribution of the entire semiconductor stacked structure, the electric field intensity of the PN junction is relatively large. Figure 13 As shown, curve A is the current change over time of the metal layer electrode of the device when avalanche breakdown occurs, and curve B is the current change over time of the incident electron current. The signal rise time is 0.88 ps, which can significantly improve the response speed, and the signal current intensity is at the 3 mA level.

[0071] In summary, this invention provides a direct electron detector that, by setting an avalanche region, effectively achieves avalanche multiplication of incident electrons, thereby improving detection sensitivity. Furthermore, the avalanche multiplication effect of the avalanche region can reduce the thickness of the intrinsic layer, such as reaching 30 μm, to meet the absorption capacity for electrons with 50 keV energy. Other intrinsic layer thicknesses can also be set according to the energy of the electrons to be detected. The reduced intrinsic layer thickness shortens the electron migration path and reduces the electron transit time, thus improving the detector's signal readout speed. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and has high industrial applicability.

[0072] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A direct type electron detector, characterized by, The direct type electron detector comprises a semiconductor laminated structure and a peripheral signal measurement circuit; The semiconductor laminated structure comprises, from bottom to top, a semiconductor substrate, a U-shaped cross-section semiconductor resistance layer, a first semiconductor layer, a second semiconductor layer, an insulating layer, a metal layer, an intrinsic layer and a third semiconductor layer; the U-shaped cross-section semiconductor resistance layer extends inward from the surface of the semiconductor substrate, the first semiconductor layer is formed in the groove of the U-shaped cross-section semiconductor resistance layer, the second semiconductor layer is formed on the first semiconductor layer, the insulating layer is formed outside the second semiconductor layer, and the metal layer is formed outside the insulating layer and in contact with the U-shaped cross-section semiconductor resistance layer; the U-shaped cross-section semiconductor resistance layer and the first semiconductor layer are of a first doping type, the second semiconductor layer and the third semiconductor layer are of a second doping type, the third semiconductor layer and the intrinsic layer form an electron absorption zone, and the first semiconductor layer and the second semiconductor layer form an avalanche zone; The peripheral signal measurement circuit comprises a counter; The semiconductor laminated structure and the peripheral signal measurement circuit are electrically connected together, wherein the metal layer on the U-shaped cross-section semiconductor resistance layer is electrically connected to the counter to realize the counting measurement of the peripheral signal measurement circuit on the electric signal.

2. The direct electron detector of claim 1, wherein: The peripheral signal measurement circuit further comprises an operational amplifier circuit, and the operational amplifier circuit is electrically connected to the metal layer and the counter respectively.

3. The direct electron detector of claim 2, wherein: The operational amplifier circuit comprises an operational amplifier.

4. The direct electron detector of claim 1, wherein: The first doping type is N type and the second doping type is P type, or the first doping type is P type and the second doping type is N type.

5. The direct electron detector of claim 4, wherein: The first doping type is N type and the second doping type is P type; the semiconductor resistance layer with U-shaped cross section has a thickness of 5-50 μm and a doping concentration of 1E15 / cm 3 1E21 / cm 3 ; the first semiconductor layer has a thickness of 0.1-10 μm and a doping concentration of 1E17 / cm 3 1E22 / cm 3 ; the second semiconductor layer has a thickness of 0.1-10 μm and a doping concentration of 1E17 / cm 3 1E22 / cm 3 ; the intrinsic layer has a thickness of 10-60 μm and a doping concentration of 0-1E15 / cm 3 ; and the third semiconductor layer has a thickness of 0.1-10 μm and a doping concentration of 1E17 / cm 3 1E22 / cm 3 .

6. The direct electron detector of claim 1, wherein: The semiconductor laminated structure further comprises a peripheral protection ring, which is arranged at the outer periphery of the third semiconductor layer and extends downward from the top to the inside of the intrinsic layer.

7. The direct electron detector of claim 1, wherein: The third semiconductor layer is in an inverted U shape and extends inward from the surface of the intrinsic layer.

8. The direct electron detector of claim 1, wherein: The semiconductor material of the semiconductor laminated structure is silicon, the material of the insulating layer is silicon oxide, and the metal layer is one layer of aluminum layer, titanium layer, tungsten layer and gold layer or a stack of two or more layers.

9. The direct electron detector of claim 1, wherein: Two or more avalanche zones are formed in the semiconductor laminated structure, adjacent two avalanche zones are isolated by the semiconductor substrate, and adjacent two metal layers are isolated by the insulating layer.

10. The direct electron detector of claim 1, wherein: The peripheral signal measurement circuit is arranged on a PCB and connected to the semiconductor laminated structure by wire bonding through the pads on the PCB; or the peripheral signal measurement circuit is integrated in an ASIC and connected to the semiconductor laminated structure by wire bonding through the pads on the ASIC.

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