Method and system for calibrating linearity of analog-to-digital converter, storage medium

Abstract

The application discloses a linearity calibration method and system of an analog-to-digital converter and a storage medium, and relates to the technical field of analog-to-digital converters. The method comprises the following steps: a pseudo-random sequence generator generates a pseudo-random sequence and sends the pseudo-random sequence to a signal modulator; the signal modulator adjusts the signal amplitude of the pseudo-random sequence, modulates an input signal according to the adjusted pseudo-random sequence, obtains a first signal, and sends the first signal to a signal buffer; the signal buffer buffers the first signal and sends the buffered first signal to an analog-to-digital converter; the analog-to-digital converter samples and quantizes the buffered first signal, obtains a second signal, and sends the second signal to a digital calibration circuit; and the digital calibration circuit calibrates the second signal, removes the information of the pseudo-random sequence in the second signal, and outputs a calibrated digital signal. According to the linearity calibration method of the analog-to-digital converter, the linearity of the analog-to-digital converter can be improved.

Description

Technical Field

[0001] This invention relates to the field of analog-to-digital converter technology, and in particular to a linearity calibration method and system for analog-to-digital converters, as well as a storage medium. Background Technology

[0002] Modern phased array applications, such as radar systems, require numerous parallel, medium-resolution, high-speed analog-to-digital converters (ADCs). The current trend is to design these ADCs for low cost and high efficiency, aiming to directly sample signals from the intermediate frequency (IF) and down-convert them to baseband, thereby reducing the overall component count and system cost without the need for additional analog mixers. However, achieving high linearity at the IF with a small-area, low-power ADC is a challenging design task. The ADC's input buffer, sample-and-hold circuitry, and other front-end static nonlinear sources collectively contribute to input buffer distortion, thus limiting the overall linearity of the ADC. Summary of the Invention

[0003] This invention aims to at least solve one of the technical problems existing in the prior art. To this end, this invention proposes a linearity calibration method and system for analog-to-digital converters, as well as a storage medium, which can improve the linearity of analog-to-digital converters.

[0004] On one hand, the linearity calibration method for an analog-to-digital converter according to an embodiment of the present invention includes the following steps:

[0005] A pseudo-random sequence generator generates a pseudo-random sequence and sends the pseudo-random sequence to a signal modulator;

[0006] After adjusting the signal amplitude of the pseudo-random sequence, the signal modulator modulates the input signal according to the adjusted pseudo-random sequence to obtain a first signal, and sends the first signal to the signal buffer.

[0007] The signal buffer buffers the first signal and then sends it to the analog-to-digital converter.

[0008] The analog-to-digital converter samples and quantizes the buffered first signal to obtain a second signal, and sends the second signal to the digital calibration circuit.

[0009] After calibrating the second signal, the digital calibration circuit removes the pseudo-random sequence information from the second signal and outputs the calibrated digital signal.

[0010] According to some embodiments of the present invention, the digital calibration circuit includes a calibration core module, a pseudo-random sequence demodulation module, a reference point scanning module, and a coefficient iteration module; the step of the digital calibration circuit calibrating the second signal, removing the pseudo-random sequence information from the second signal, and outputting the calibrated digital signal specifically includes:

[0011] After calibrating the second signal according to the calibration coefficient, the calibration core module sends the calibrated second signal to the pseudo-random sequence demodulation module.

[0012] After removing the pseudo-random sequence information from the second signal, the pseudo-random sequence demodulation module outputs a calibrated digital signal.

[0013] The reference point scanning module generates multiple reference points, scans the multiple reference points according to the calibrated digital signal, obtains the optimal reference point, and sends the optimal reference point to the coefficient iteration module.

[0014] The coefficient iteration module performs iterative calculations on the calibration coefficients based on the optimal reference point to obtain new calibration coefficients, and sends the new calibration coefficients to the calibration core module.

[0015] The calibration core module calibrates the second signal according to the new calibration coefficient.

[0016] According to some embodiments of the present invention, the step of the reference point scanning module generating multiple reference points, scanning the multiple reference points according to the calibrated digital signal to obtain an optimal reference point, and sending the optimal reference point to the coefficient iteration module specifically includes:

[0017] The reference point scanning module generates multiple reference points; the code values ​​of the multiple reference points are uniformly distributed from 0 to the maximum output value of the analog-to-digital converter.

[0018] The code value of each reference point is compared with the calibrated digital signal, and the comparison result is correlated with the pseudo-random sequence. The results of the correlation calculation are then accumulated to obtain the accumulated result corresponding to each reference point.

[0019] The reference point with the largest cumulative result is taken as the optimal reference point, and the optimal reference point is sent to the coefficient iteration module.

[0020] According to some embodiments of the present invention, the step of the coefficient iteration module iteratively calculating the calibration coefficients based on the optimal reference point to obtain new calibration coefficients, and sending the new calibration coefficients to the calibration core module, specifically includes:

[0021] The calibrated digital signal is compared with the code value of the optimal reference point to obtain the comparison result;

[0022] The correlation between the comparison result and the pseudo-random sequence is calculated, and the results of the correlation calculation are accumulated to obtain the accumulated result;

[0023] Based on the accumulated results, the calibration coefficients are iteratively calculated using the least mean square root approximation method to obtain new calibration coefficients, and the new calibration coefficients are sent to the calibration core module.

[0024] According to some embodiments of the present invention, the step of the pseudo-random sequence generator generating a pseudo-random sequence and sending the pseudo-random sequence to the signal modulator specifically includes:

[0025] The pseudo-random sequence generator generates 0 / 1 pseudo-random sequences; where 0 corresponds to the circuit ground voltage and 1 corresponds to the circuit operating voltage.

[0026] The pseudo-random sequence is sent to the signal modulator.

[0027] According to some embodiments of the present invention, the value of the pseudo-random sequence changes in each master clock cycle and remains stable at the falling edge of the sampling clock.

[0028] On the other hand, the linearity calibration system for an analog-to-digital converter according to an embodiment of the present invention includes:

[0029] A pseudo-random sequence generator, used to generate pseudo-random sequences;

[0030] A signal modulator is used to adjust the signal amplitude of the pseudo-random sequence and modulate the input signal according to the adjusted pseudo-random sequence to obtain a first signal.

[0031] A signal buffer is used to buffer the first signal;

[0032] An analog-to-digital converter is used to sample and quantize the buffered first signal to obtain a second signal;

[0033] A digital calibration circuit is used to calibrate the second signal, remove the pseudo-random sequence information from the second signal, and output the calibrated digital signal.

[0034] According to some embodiments of the present invention, the digital calibration circuit includes:

[0035] The calibration core module is used to calibrate the second signal according to the calibration coefficient;

[0036] The pseudo-random sequence demodulation module is used to remove the information of the pseudo-random sequence from the second signal and output the calibrated digital signal.

[0037] The reference point scanning module is used to generate multiple reference points and scan the multiple reference points according to the calibrated digital signal to obtain the optimal reference point;

[0038] The coefficient iteration module is used to iteratively calculate the calibration coefficients based on the optimal reference point, obtain new calibration coefficients, and send the new calibration coefficients to the calibration core module.

[0039] On the other hand, according to an embodiment of the present invention, the storage medium stores computer-executable instructions for causing a computer to perform the above-described linearity calibration method for an analog-to-digital converter.

[0040] The linearity calibration method, system, and storage medium for analog-to-digital converters proposed in this invention have at least the following beneficial effects: Unlike previous digital calibrations for dynamic distortion at the front end of analog-to-digital converters, where the injection of pseudo-random sequences could only be performed after the input buffer, this invention uses a signal modulator before the input buffer (i.e., the signal buffer) to pre-degrade the pseudo-random sequence to a reasonable value and modulate it with the input signal, thus enabling the signal buffer to be calibrated as well. The analog-to-digital converter sends the output result to a digital calibration circuit for calibration and removes the information from the pseudo-random sequence, thereby obtaining a calibrated digital signal and achieving calibration of the nonlinearity of the analog-to-digital converter.

[0041] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0042] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0043] Figure 1 This is a schematic diagram of the linearity calibration system for an analog-to-digital converter according to an embodiment of the present invention;

[0044] Figure 2 This is a timing diagram of the linearity calibration system for an analog-to-digital converter according to an embodiment of the present invention.

[0045] Figure 3 This is a schematic diagram of the structure of the digital calibration circuit according to an embodiment of the present invention;

[0046] Figure 4 This is a schematic diagram illustrating the working principle of the reference point scanning module in an embodiment of the present invention.

[0047] Figure 5 This is a schematic diagram illustrating the working principle of the coefficient iteration module in an embodiment of the present invention;

[0048] Figure 6 This is a flowchart illustrating the steps of the linearity calibration method for an analog-to-digital converter according to an embodiment of the present invention.

[0049] Figure label:

[0050] The system includes a pseudo-random sequence generator 100, a signal modulator 200, a signal buffer 300, an analog-to-digital converter 400, a digital calibration circuit 500, a calibration core module 510, a pseudo-random sequence demodulation module 520, a reference point scanning module 530, and a coefficient iteration module 540. Detailed Implementation

[0051] This section will describe in detail specific embodiments of the present invention. Preferred embodiments of the present invention are shown in the accompanying drawings. The purpose of the drawings is to supplement the textual description with graphics, so that people can intuitively and vividly understand each technical feature and overall technical solution of the present invention, but they should not be construed as limiting the scope of protection of the present invention.

[0052] In the description of this invention, unless otherwise explicitly defined, terms such as "setting," "installing," and "connecting" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this invention in conjunction with the specific content of the technical solution.

[0053] On the one hand, such as Figure 1 As shown in the figure, this embodiment of the invention proposes a linearity calibration system for an analog-to-digital converter, including a pseudo-random sequence generator 100, a signal modulator 200, a signal buffer 300, an analog-to-digital converter 400, and a digital calibration circuit 500. The pseudo-random sequence generator 100 is used to generate a pseudo-random sequence; the signal modulator 200 is used to adjust the signal amplitude of the pseudo-random sequence and modulate the input signal according to the adjusted pseudo-random sequence to obtain a first signal; the signal buffer 300 is used to buffer the first signal; the analog-to-digital converter 400 is used to sample and quantize the buffered first signal to obtain a second signal; the digital calibration circuit 500 is used to calibrate the second signal, remove the pseudo-random sequence information from the second signal, and output a calibrated digital signal.

[0054] The specific structure of the analog-to-digital converter 400 is well known to those skilled in the art, and therefore will not be described in detail here. The specific working principle of the system is as follows:

[0055] The pseudo-random sequence generator 100 generates a 0 / 1 pseudo-random sequence and sends it to the signal modulator 200; where 0 corresponds to the circuit ground voltage and 1 corresponds to the circuit operating voltage; for example... Figure 2As shown, the value of the pseudo-random sequence changes in each master clock cycle and remains stable on the falling edge of the sampling clock, enabling the sample-and-hold circuit of the analog-to-digital converter 400 to sample the correct value.

[0056] After receiving the pseudo-random sequence, the signal modulator 200 first uses capacitors, resistors, or other methods to reduce the signal amplitude of the pseudo-random sequence to a suitable initial value, and then injects it into the input signal to modulate the input signal and obtain the modulated input signal (i.e., the first signal). This initial value ensures that after the pseudo-random sequence is injected into the input signal, the amplitude of the injected signal will not saturate the analog-to-digital converter 400.

[0057] The signal modulator 200 sends the first signal to the signal buffer 300 for buffering, so that the pseudo-random sequence and the original input signal are simultaneously affected by the nonlinearity of the signal buffer 300; the analog-to-digital converter 400 samples and quantizes the first signal buffered by the signal buffer 300, and outputs the digital signal before calibration (i.e., the second signal); the digital calibration circuit 500 calibrates the second signal and removes the pseudo-random sequence information from the second signal, and outputs the calibrated digital signal.

[0058] Specifically, such as Figure 3 As shown, in some embodiments of the present invention, the digital calibration circuit 500 includes a calibration core module 510, a pseudo-random sequence demodulation module 520, a reference point scanning module 530, and a coefficient iteration module 540. The calibration core module 510 is used to calibrate the second signal according to the calibration coefficients. The pseudo-random sequence demodulation module 520 is used to remove the pseudo-random sequence information from the second signal and output the calibrated digital signal. The reference point scanning module 530 is used to generate multiple reference points and scan the multiple reference points according to the calibrated digital signal to obtain the optimal reference point. The coefficient iteration module 540 is used to iteratively calculate the calibration coefficients according to the optimal reference point to obtain new calibration coefficients and send the new calibration coefficients to the calibration core module 510. The calibration core module 510 further calibrates the second signal according to the new calibration coefficients.

[0059] First, the calibration core module 510 calibrates the second signal output from the analog-to-digital converter 400, then sends the signal to the pseudo-random sequence demodulation module 520. The pseudo-random sequence demodulation module 520 removes the pseudo-random sequence information from the signal and outputs the calibrated digital signal. To obtain and update the calibration coefficients in the calibration core module 510, the calibrated digital signal also needs to be input to the reference point scanning module 530 and the coefficient iteration module 540. For example... Figure 4As shown, the reference point scanning module 530 first generates multiple reference points, whose code values ​​are uniformly distributed from 0 to the maximum output value of the analog-to-digital converter 400. In the first stage, the code value of the first reference point is compared with the calibrated digital signal, and the comparison result is correlated with a pseudo-random sequence. The correlation calculation result is accumulated in an accumulator to obtain the corresponding accumulation result. In the second stage, a second reference point is selected, and the same operation as in the first stage is performed to obtain the accumulation result corresponding to the second reference point. This process is repeated multiple times until the accumulation results corresponding to all reference points are obtained. Finally, the reference point with the largest accumulation result is selected as the optimal reference point. Figure 5 As shown, after obtaining the optimal reference point, the coefficient iteration module 540 compares the calibrated digital signal with the code value of the optimal reference point to obtain the comparison result. Then, it performs correlation calculation on the comparison result and the pseudo-random sequence, and accumulates the correlation calculation results to obtain the accumulated result. Finally, based on the accumulated result, it iteratively calculates the calibration coefficients using the least mean square approximation method to obtain new calibration coefficients, and sends the new calibration coefficients to the calibration core module 510 for further calibration.

[0060] The linearity calibration system for an analog-to-digital converter (ADC) according to an embodiment of the present invention differs from conventional digital calibration for dynamic distortion at the front end of the ADC. Previously, the injection of pseudo-random sequences could only be performed after the input buffer. However, this invention injects the pseudo-random sequence before the input buffer (i.e., signal buffer 300) using a signal modulator 200, reducing the pseudo-random sequence to a reasonable value and modulating it with the input signal, thus enabling the signal buffer 300 to be calibrated as well. After the ADC 400 sends its output to the digital calibration circuit 500 for calibration, to obtain new calibration coefficients, this invention adds a reference point scanning module 530 and a coefficient iteration module 540 to the digital calibration circuit 500. The purpose is to adaptively calculate the optimal reference point for coefficient iteration without manual selection. The optimal coefficients obtained through coefficient iteration are used for digital calibration, thereby achieving calibration of the nonlinearity of the ADC 400. This linearity calibration system for an ADC, while achieving high linearity of the ADC 400, also reduces the design difficulty and power supply voltage requirements of the signal buffer 300, and reduces the overall power consumption of the circuit. The analog-to-digital converter of this invention calibrates the harmonic distortion caused by the signal buffer 300 to below the noise floor based on the result of the fast Fourier transform. At the 28nm CMOS process node, the signal buffer 300 requires a power supply voltage of only 1.1 volts.

[0061] On the other hand, such as Figure 6As shown, corresponding to the linearity calibration system for analog-to-digital converters described above, this embodiment of the invention also proposes a linearity calibration method for analog-to-digital converters, which includes the following steps:

[0062] Step S100: The pseudo-random sequence generator 100 generates a pseudo-random sequence and sends the pseudo-random sequence to the signal modulator 200;

[0063] Step S200: After adjusting the signal amplitude of the pseudo-random sequence, the signal modulator 200 modulates the input signal according to the adjusted pseudo-random sequence to obtain a first signal, and sends the first signal to the signal buffer 300.

[0064] Step S300: After the signal buffer 300 buffers the first signal, it is sent to the analog-to-digital converter 400;

[0065] Step S400: The analog-to-digital converter 400 samples and quantizes the buffered first signal to obtain the second signal, and sends the second signal to the digital calibration circuit 500;

[0066] Step S500: After calibrating the second signal, the digital calibration circuit 500 removes the pseudo-random sequence information from the second signal and outputs the calibrated digital signal.

[0067] Specifically, first, the pseudo-random sequence generator 100 generates a 0 / 1 pseudo-random sequence and sends it to the signal modulator 200; where 0 corresponds to the circuit ground voltage and 1 corresponds to the circuit operating voltage; for example... Figure 2 As shown, the value of the pseudo-random sequence changes in each master clock cycle and remains stable at the falling edge of the sampling clock, enabling the sample-and-hold circuit of the analog-to-digital converter 400 to sample the correct value. After receiving the pseudo-random sequence, the signal modulator 200 first uses capacitors, resistors, or other methods to reduce the signal amplitude of the pseudo-random sequence to a suitable initial value before injecting it into the input signal to modulate the input signal, obtaining the modulated input signal (i.e., the first signal). This initial value ensures that the amplitude of the injected signal will not saturate the analog-to-digital converter 400 after the pseudo-random sequence is injected into the input signal. The signal modulator 200 sends the first signal to the signal buffer 300 for buffering, so that both the pseudo-random sequence and the original input signal are simultaneously affected by the nonlinearity of the signal buffer 300. The analog-to-digital converter 400 samples and quantizes the first signal buffered by the signal buffer 300, outputting the digital signal before calibration (i.e., the second signal). The digital calibration circuit 500 calibrates the second signal and removes the pseudo-random sequence information from the second signal, outputting the calibrated digital signal.

[0068] The digital calibration circuit 500 includes a calibration core module 510, a pseudo-random sequence demodulation module 520, a reference point scanning module 530, and a coefficient iteration module 540. Step S500 further includes the following steps:

[0069] Step S501: After calibrating the second signal according to the calibration coefficient, the calibration core module 510 sends the calibrated second signal to the pseudo-random sequence demodulation module 520.

[0070] Step S502: After removing the pseudo-random sequence information from the second signal, the pseudo-random sequence demodulation module 520 outputs the calibrated digital signal;

[0071] Step S503: The reference point scanning module 530 generates multiple reference points and scans the multiple reference points according to the calibrated digital signal to obtain the optimal reference point, and sends the optimal reference point to the coefficient iteration module 540;

[0072] Step S504: The coefficient iteration module 540 iterates the calibration coefficients according to the optimal reference point to obtain new calibration coefficients, and sends the new calibration coefficients to the calibration core module 510.

[0073] Step S504: The calibration core module 510 calibrates the second signal according to the new calibration coefficient.

[0074] First, the calibration core module 510 calibrates the second signal output from the analog-to-digital converter 400, then sends the signal to the pseudo-random sequence demodulation module 520. The pseudo-random sequence demodulation module 520 removes the pseudo-random sequence information from the signal and outputs the calibrated digital signal. To obtain and update the calibration coefficients in the calibration core module 510, the calibrated digital signal also needs to be input to the reference point scanning module 530 and the coefficient iteration module 540. For example... Figure 4 As shown, the reference point scanning module 530 first generates multiple reference points, whose code values ​​are uniformly distributed from 0 to the maximum output value of the analog-to-digital converter 400. In the first stage, the code value of the first reference point is compared with the calibrated digital signal, and the comparison result is correlated with a pseudo-random sequence. The correlation calculation result is accumulated in an accumulator to obtain the corresponding accumulation result. In the second stage, a second reference point is selected, and the same operation as in the first stage is performed to obtain the accumulation result corresponding to the second reference point. This process is repeated multiple times until the accumulation results corresponding to all reference points are obtained. Finally, the reference point with the largest accumulation result is selected as the optimal reference point. Figure 5As shown, after obtaining the optimal reference point, the coefficient iteration module 540 compares the calibrated digital signal with the code value of the optimal reference point to obtain the comparison result. Then, it performs correlation calculation on the comparison result and the pseudo-random sequence, and accumulates the correlation calculation results to obtain the accumulated result. Finally, based on the accumulated result, it iteratively calculates the calibration coefficients using the least mean square approximation method to obtain new calibration coefficients, and sends the new calibration coefficients to the calibration core module 510 for further calibration.

[0075] The linearity calibration method for an analog-to-digital converter (ADC) according to an embodiment of the present invention differs from previous digital calibration methods for dynamic distortion at the front end of the ADC. Previously, the injection of pseudo-random sequences could only be performed after the input buffer. However, this invention injects the pseudo-random sequence before the input buffer (i.e., signal buffer 300) using a signal modulator 200, reducing the pseudo-random sequence to a reasonable value and modulating it with the input signal, thus enabling the signal buffer 300 to be calibrated as well. After the ADC 400 sends its output to the digital calibration circuit 500 for calibration, to obtain new calibration coefficients, this invention adds a reference point scanning module 530 and a coefficient iteration module 540 to the digital calibration circuit 500. The purpose is to adaptively calculate the optimal reference point for coefficient iteration without manual selection. The optimal coefficients obtained through coefficient iteration are used for digital calibration, thereby achieving calibration of the nonlinearity of the ADC 400. The linearity calibration system for the ADC according to this embodiment of the present invention achieves high linearity of the ADC 400 while reducing the design difficulty and power supply voltage requirements of the signal buffer 300, and also reduces the overall power loss of the circuit. The analog-to-digital converter of this invention calibrates the harmonic distortion caused by the signal buffer 300 to below the noise floor based on the result of the fast Fourier transform. At the 28nm CMOS process node, the signal buffer 300 requires a power supply voltage of only 1.1 volts.

[0076] On the other hand, in some embodiments of the present invention, a storage medium is also provided that stores computer-executable instructions for causing a computer to perform the above-described linearity calibration method for an analog-to-digital converter.

[0077] Although specific embodiments are described herein, those skilled in the art will recognize that many other modifications or alternative embodiments are also within the scope of this disclosure. For example, any of the functions and / or processing capabilities described in connection with a particular device or component can be performed by any other device or component. Furthermore, while various exemplary embodiments and architectures have been described according to embodiments of this disclosure, those skilled in the art will recognize that many other modifications to the exemplary embodiments and architectures described herein are also within the scope of this disclosure.

[0078] The foregoing description, with reference to block diagrams and flowcharts of systems, methods, systems, and / or computer program products according to exemplary embodiments, has described certain aspects of this disclosure. It should be understood that one or more blocks in the block diagrams and flowcharts, as well as combinations of blocks in the block diagrams and flowcharts, can be implemented by executing computer-executable program instructions, respectively. Similarly, according to some embodiments, some blocks in the block diagrams and flowcharts may not need to be executed in the order shown, or may not all need to be executed. Furthermore, additional components and / or operations beyond those shown in the blocks in the block diagrams and flowcharts may exist in some embodiments.

[0079] Therefore, blocks in block diagrams and flowcharts support combinations of means for performing a specified function, combinations of elements or steps for performing a specified function, and program instruction means for performing a specified function. It should also be understood that each block in a block diagram and flowchart, and combinations of blocks in block diagrams and flowcharts, can be implemented by a dedicated hardware computer system or a combination of dedicated hardware and computer instructions that performs a specific function, element, or step.

[0080] The program modules, applications, etc., described herein may include one or more software components, including, for example, software objects, methods, data structures, etc. Each such software component may include computer-executable instructions that, in response to execution, cause at least a portion of the functionality described herein (e.g., one or more operations of the exemplary methods described herein) to be performed.

[0081] Software components can be coded using any of a variety of programming languages. An exemplary programming language could be a low-level programming language, such as assembly language associated with a specific hardware architecture and / or operating system platform. Software components including assembly language instructions may need to be converted into executable machine code by an assembler before being executed by the hardware architecture and / or platform. Another exemplary programming language could be a higher-level programming language that is portable across multiple architectures. Software components including higher-level programming languages ​​may need to be converted into an intermediate representation by an interpreter or compiler before execution. Other examples of programming languages ​​include, but are not limited to, macro languages, shell or command languages, job control languages, scripting languages, database query or search languages, or report writing languages. In one or more exemplary embodiments, a software component containing instructions from one of the above-described programming language examples can be executed directly by the operating system or other software components without first being converted into another form.

[0082] Software components can be stored as files or other data storage structures. Software components of similar type or related function can be stored together in a specific directory, folder, or library. Software components can be static (e.g., pre-defined or fixed) or dynamic (e.g., created or modified at runtime).

[0083] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of the present invention.

Claims

1. A method for calibrating the linearity of an analog-to-digital converter, characterized in that, Includes the following steps: A pseudo-random sequence generator generates a pseudo-random sequence and sends the pseudo-random sequence to a signal modulator; After adjusting the signal amplitude of the pseudo-random sequence, the signal modulator modulates the input signal according to the adjusted pseudo-random sequence to obtain a first signal, and sends the first signal to the signal buffer. The signal buffer buffers the first signal and then sends it to the analog-to-digital converter. The analog-to-digital converter samples and quantizes the buffered first signal to obtain a second signal, and sends the second signal to the digital calibration circuit. After calibrating the second signal, the digital calibration circuit removes the pseudo-random sequence information from the second signal and outputs the calibrated digital signal. The digital calibration circuit includes a calibration core module, a pseudo-random sequence demodulation module, a reference point scanning module, and a coefficient iteration module; The step of the digital calibration circuit calibrating the second signal, removing the pseudo-random sequence information from the second signal, and outputting the calibrated digital signal specifically includes: After calibrating the second signal according to the calibration coefficient, the calibration core module sends the calibrated second signal to the pseudo-random sequence demodulation module. After removing the pseudo-random sequence information from the second signal, the pseudo-random sequence demodulation module outputs a calibrated digital signal. The reference point scanning module generates multiple reference points, scans the multiple reference points according to the calibrated digital signal, obtains the optimal reference point, and sends the optimal reference point to the coefficient iteration module. The coefficient iteration module performs iterative calculations on the calibration coefficients based on the optimal reference point to obtain new calibration coefficients, and sends the new calibration coefficients to the calibration core module. The calibration core module calibrates the second signal according to the new calibration coefficient.

2. The linearity calibration method for an analog-to-digital converter according to claim 1, characterized in that, The step of generating multiple reference points by the reference point scanning module, scanning the multiple reference points according to the calibrated digital signal to obtain the optimal reference point, and sending the optimal reference point to the coefficient iteration module specifically includes: The reference point scanning module generates multiple reference points; the code values ​​of the multiple reference points are uniformly distributed from 0 to the maximum output value of the analog-to-digital converter. The code value of each reference point is compared with the calibrated digital signal, and the comparison result is correlated with the pseudo-random sequence. The results of the correlation calculation are then accumulated to obtain the accumulated result corresponding to each reference point. The reference point with the largest cumulative result is taken as the optimal reference point, and the optimal reference point is sent to the coefficient iteration module.

3. The linearity calibration method for an analog-to-digital converter according to claim 1, characterized in that, The step of the coefficient iteration module iteratively calculating the calibration coefficients based on the optimal reference point to obtain new calibration coefficients, and sending the new calibration coefficients to the calibration core module, specifically includes: The calibrated digital signal is compared with the code value of the optimal reference point to obtain the comparison result; The correlation between the comparison result and the pseudo-random sequence is calculated, and the results of the correlation calculation are accumulated to obtain the accumulated result; Based on the accumulated results, the calibration coefficients are iteratively calculated using the least mean square root approximation method to obtain new calibration coefficients, and the new calibration coefficients are sent to the calibration core module.

4. The linearity calibration method for an analog-to-digital converter according to claim 1, characterized in that, The step of generating a pseudo-random sequence using a pseudo-random sequence generator and sending the pseudo-random sequence to a signal modulator specifically includes: The pseudo-random sequence generator generates 0 / 1 pseudo-random sequences; where 0 corresponds to the circuit ground voltage and 1 corresponds to the circuit operating voltage. The pseudo-random sequence is sent to the signal modulator.

5. The linearity calibration method for an analog-to-digital converter according to claim 1 or 4, characterized in that, The value of the pseudo-random sequence changes in each master clock cycle and remains stable at the falling edge of the sampling clock.

6. A linearity calibration system for an analog-to-digital converter, characterized in that, include: A pseudo-random sequence generator, used to generate pseudo-random sequences; A signal modulator is used to adjust the signal amplitude of the pseudo-random sequence and modulate the input signal according to the adjusted pseudo-random sequence to obtain a first signal. A signal buffer is used to buffer the first signal; An analog-to-digital converter is used to sample and quantize the buffered first signal to obtain a second signal; A digital calibration circuit is used to calibrate the second signal, remove the pseudo-random sequence information from the second signal, and output the calibrated digital signal. The digital calibration circuit includes: The calibration core module is used to calibrate the second signal according to the calibration coefficient; The pseudo-random sequence demodulation module is used to remove the information of the pseudo-random sequence from the second signal and output the calibrated digital signal. The reference point scanning module is used to generate multiple reference points and scan the multiple reference points according to the calibrated digital signal to obtain the optimal reference point; The coefficient iteration module is used to iteratively calculate the calibration coefficients based on the optimal reference point, obtain new calibration coefficients, and send the new calibration coefficients to the calibration core module.

7. A storage medium, characterized in that, The storage medium stores computer-executable instructions for causing a computer to perform the linearity calibration method for the analog-to-digital converter according to any one of claims 1-5.

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